Bringing the Best Together
Lattice Solutions
2
Bringing the
Best Together
Today’s leading-edge system designers have to satisfy multiple and often competing
goals. Designers must balance speed, low power consumption, high functionality,
board-space savings, cost, and fast time-to-market.
Lattice Semiconductor brings together a variety of technologies and features to provide
innovative solutions that address the real needs of designers. This approach has been
adopted across the range of products that Lattice supplies. In silicon products this
spans logic, interface, and analog. In design tools it covers design entry, intellectual
property and development tools.
Lattice’s product portfolio includes the world’s fastest programmable logic devices
(2.3 ns pin-to-pin delay), the lowest power consumption (20 µA static ICC), the world’s
only non-volatile, infinitely reconfigurable FPGAs (Field Programmable Gate Arrays),
the fastest programmable SERDES (3.7 Gbps per channel),
and programmable mixed signal devices. Lattice
consistently brings the best together to
deliver innovative, high-performance,
programmable solutions.
Performance Leadership
Lattice delivers the world’s highest
performance programmable logic
devices.
■ispMACH 4000 – 2.5 ns / 400 MHz
■ispGAL®22V10 – 2.3 ns / 455 MHz
ispXPGA™
Non-volatile + Reconfigurable
ispXPLD™
CPLD + Memory
ispMACH™
Lowest Power + Speed
Power Manager
ISP Analog + Logic
ispPAC®
ISP + Analog
FPSC
FPGA + ASSP
200
Number of Macrocells
fMAX (MHz)
100
400
300
512256 1024768
Altera
Xilinx
Lattice
Lattice
S
p
ee
d
Leadership
p
dh
Superior SERDES
Solutions
Lattice sysHSI™ (system high-speed
interface) serializer/deserializer (SERDES)
technology leads the programmable logic
industry in terms of maximum bit rate
and low jitter. The following actual eye
diagram illustrates the outstanding
characteristics of Lattice’s sysHSI SERDES
technology.
ORT82G5 RX Eye Diagram over 26 inches
(65 centimeters) of FR4 at 3.7 Gbps
Technology Leadership
Through the development of products
utilizing advanced manufacturing processes,
Lattice delivers higher speed and lower cost
solutions to the marketplace. Current
developments are focused on 0.13 µm and
90 nm technology.
Lattice Exceeding
Design Requirements
Highest Speed Logic
Highest Performance I/Os
Complex Functions
Lowest Power Dissipation
Smallest Footprint
Mixed Signal Capability
Lower Cost
Faster Time-to-Market
0.2
0.1
Year of Introduction
Dimension (µm)
0
.
3
20001998
256 Macrocell
CPLD Evolution
20042002
12 n
s
1.0X
0.4X
0.25X
5 ns
3ns
3
ns
ns
3
Ultra Low Power
Lattice delivers the world’s lowest power
programmable logic devices.
■ispMACH 4000Z – 20 µA (max.)
■ORCA® FPSC – 225 mW per
SERDES Channel @ 3.125 Gbps
80
Competitive
Device
Lattice
ispMACH 4032Z
60
40
20
100
120
2
0
µ
A
Static ICC (µA)
< 100 µA
80%
Powe
r
R
educ
ti
on
Advanced Packaging
Lattice utilizes a variety of advanced
packaging technologies that allow
designers to increase functional density.
Lattice offers TQFP, caBGA (0.8 mm), and
fpBGA (1.0 mm) packaging – including
thermally enhanced options. Current
developments include packages ranging
from the space-saving QFN to 1000+ ball
BGA packages.
Programmable Analog
Today’s system designs contain analog
signals which must be monitored and
processed. Lattice’s innovative ispPAC
family of programmable analog devices
offers an excellent solution for signal
conditioning, filtering and control loop
applications. The ispPAC Power Manager
combines programmable analog and
digital providing an optimized power
sequencing and monitoring solution.
Lattice Products
Faster Time to Market
Programmable devices provide fast time-
to-market. Lattice facilitates the design
process by supporting users with easy-to-
use ispLEVER™ tools, IP cores, on-time
delivery, a global network of field
applications engineers, and over 20 years
of experience in
programmable
products.
Logic Devices Page
ORCA Series 4 4
SRAM-based FPGAs
ispXPGA 5
Non-volatile, reconfigurable FPGAs
ispXPLD 5000MX 8
High-density CPLD plus memory
ispMACH 4000 9
Highest speed, lowest power CPLDs
ispPAC Power Manager 10
Programmable analog + logic
SERDES Interface Devices
ORT82G5 6
8 x 3.7 Gbps SERDES + FPGA
ORT42G5 6
4 x 3.7 Gbps SERDES + FPGA
ORSO82G5 6
8 x 2.7 Gbps SERDES + SONET + FPGA
ORSO42G5 6
4 x 2.7 Gbps SERDES + SONET + FPGA
ORT8850H/L 6
8 x 850 Mbps SERDES + SONET + FPGA
ispGDX2 7
Programmable SERDES + interconnect
Source Synchronous
Interface Devices
ORLI10G 6
10 Gbps line interface + FPGA
Programmable Analog
ispPAC 10
Programmable analog
ispPAC Power Manager 10
Programmable analog + logic
Design Entry
ispLEVER 11
Digital design
PAC-Designer®10
Analog + mixed signal design
Intellectual Property
IP Cores 11
Reference Designs 11
Development Tools
Evaluation Boards 11
Programming Hardware 11
Programming Software 11
Prog.
Voltage
Monitor
CPLD
Timers
High Voltage
Driver
Logic Driver
Input
Power Supply 5V
5V
2.5V
1.2V
Other
Board
Circuitry
LDO
Brick
ispPAC Power-1208
49-Ball caBGA
7 x 7 mm
32-Pin QFN
5 x 5 mm
900-Ball fine pitch BGA
31 x 31 mm
Packages shown actual size.
4
System EBR RAM EBR RAM Distributed
Device Gates LUT-4 Total Registers Blocks Bits RAM Bits PLLs User I/O
OR4E02
397k 5.0k 6.8k 8 74k 80k 8 405
OR4E04
643k 10.4k 13.4k 12 111k 166k 8 466
OR4E06
899k 16.2k 20.4k 16 148k 259k 8 466
ORCA Series 4 Family of FPGAs
FPGA Products
Lattice Field Programmable Gate Arrays
The ispXPGA (in system programmable eXpanded field
Programmable Gate Array) family of devices allows the creation of
high-performance logic designs that are both non-volatile and
infinitely reconfigurable. Other FPGA solutions force a compromise,
being either re-programmable, or reconfigurable, or non-volatile.
Lattice’s ispXPGA family offers all these capabilities with a
mainstream architecture containing the features required for today’s
system-level design.
ORCA Series 4 FPGAs by Lattice Semiconductor are built on the familiar Optimized Reconfigurable
Cell Array (ORCA) architecture. This FPGA device family offers many new features and architectural
enhancements not available in any earlier FPGA generations. Bringing together highly flexible SRAM-
based programmable logic, powerful system features, a rich hierarchy of routing and interconnect
resources, and meeting multiple interface standards, the ORCA family of FPGAs accommodates
the most complex and high-performance design challenges.
Bringing the Best Together
ORCA Series 4 Family
■High Performance FPGA
–Up to 900k system gates
–Up to 466 user I/Os
–Up to 148k embedded memory
–250 MHz performance
■Flexible Programmable Logic Cells
(PLCs)
■sysIO™ Capability for High
Performance Interfacing
■Block and Distributed Memory
■sysCLOCK™ PLLs for Clock
Management
–6 general purpose PLLs
–2 communication specific PLLs
■System-level Design Features
–Embedded Microprocessor Interface
(MPI)
–Embedded system bus (ARM AHB bus)
Clock
Pins
(all 4 sides)
Programmable I/O Cells (PICs)
• Separate Input, Output, and OE Registers
• DDR Support
• Programmable Input Options
• Programmable Output Skew
sysMEM™ Blocks
• Up to 148k Of Dedicated Memory
• Configurable as Dual-port, FIFO, Single-port,
ROM, CAM, or Multiplier
• 256x36, 512x18, and 1kx9 Modes
sysCLOCK PLLs
• Clock Multiplication and Division
• Phase Shifting
• 2.5 MHz to 420 MHz
• Supports DS-1/E-1 & STS3 /STM-1
Microprocessor Interface (MPI)
and Associated System Bus
• 32-/16-/8-bit External Interface
• 32-bit Internal Interface With
Automatic Width Conversion
• Embedded System Multi-Master Bus
• Configuration / Readback / Control /
Status Modes
sysIO Buffers
• High Speed Memory Support: SSTL, HSTL
• Bus Support: PCI, GTL+
• Differential Support: LVDS, LVPECL
• On-chip Differential Termination
• Standard Logic Support: LVTTL,
LVCMOS 3.3, 2.5 and 1.8
Programmable Logic Cells (PLCs)
• 8 LUT-4s Per PLC
• 9 Flip-flops Per PLC
- One Flip-flop Per LUT
- Additional Flip-flop For Pipelining
• Distributed Memory
• Up to 250 MHz Operation
ORCA Series 4 Block Diagram
Time
System Gates
is
p
XPG
A
O
R
C
A
4
O
R
C
A 3
O
R
C
A
2
O
R
CA
FP
SC
5
ispXPGA Family
■ispXP™ Programming Technology Provides Non-volatility and
Infinite Reconfigurability
–Instant availability of logic at power-up
–Single chip solution
–Secure
■High-Performance FPGAs
–Up to 1.25M system gates
–Up to 496 I/Os
–Up to 414k embedded memory
■High Performance Logic Blocks (PFUs)
■Block and Distributed Memory
■sysCLOCK PLLs for Clock Management
■sysIO Capability for High Performance
Interfacing
–Hot socketing support
–Leave alone I/O – holds pin state during programming
■sysHSI for 850 Mbps Serial Communication
Programmable
Function Units (PFUs)
sysCLOCK PLL
• 8 Phase Locked Loops
• 10 MHz to 320 MHz
• Clock Multiplication
and Division
• Phase Adjustment
• Shift Clocks in 325 ps Steps
• Up to 3,844 High Speed
Logic Blocks
• Four LUT-4 per PFU
• Dual Flip-Flops per LUT-4
for Extensive Pipelining
• Dedicated Logic for Adders
Multipliers, Multiplexers,
and Counters
• Distributed Memory
sysIO Buffers
Programmable I/O Cells (PICs)
sysMEM Blocks
• Up to 414k of Dedicated
Memory per ispXPGA
• Configurable as Single- or
Dual-Port, FIFO, or ROM
• 512 x 9 Bits or 256 x 18 Bits
• Cascadable Width and Depth
• High Speed Memory
Support: SSTL and HSTL
• Bus Support: PCI, GTL+,
LVDS and LVPECL
• Standard Logic Support:
LVTTL, LVCMOS 3.3, 2.5
and 1.8
sysHSI Blocks
• Cost Effective SERDES
• Up to 850 Mbps Performance
• Clock Data Recovery
• Up to 20 Channels per
Device
• Separate Input, Output, and OE Registers
• Flexible Set, Reset, Clock Enable and Polarity
• Input Register Offers Delay Option for Zero tHOLD
• Programmable Output Slew Rate
ispXPGA Block Diagram
SERDES
System Total EBR RAM EBR RAM Distributed Channels User
Family Member Gates LUT-4 Registers Blocks Bits RAM Bits (850Mbps) PLLs I/O
ispXPGA 125 139k 1.9k 4.4k 20 92k 30k 4 8 176
ispXPGA 200 210k 2.7k 6.0k 24 111k 43k 8 8 208
ispXPGA 500 476k 7.0k 15.1k 40 184k 112k 12 8 336
ispXPGA 1200 1.25M 15.3k 32.2k 90 414k 246k 20 8 496
ispXPGA Family of FPGAs
ispXP Offers Unique Set of
Advantages
New ispXPGA and ispXPLD Families
are Infinitely Reconfigurable and Non-
volatile
Lattice offers an innovative new
programming technology referred to as ispXP,
for In-System Programmable eXpanded
Programming. Previous programmable logic
technologies have typically been either non-
volatile EEPROM based or reconfigurable
SRAM based. Because both these technologies
provide unique benefits, Lattice decided to
combine them in ispXP. This provides users,
for the first time, with the benefits of non-
volatility, including instant-on, single chip
solutions, and high-security, with the infinite
reconfigurability of SRAM technology.
■Single chip solution
■Instant-on – PLD logic available within
microseconds of power-up (less than
200 µS)
■ispXP devices include security bits to
prevent unauthorized readback
■No external bitstream
6
FPSC Interface Devices
Interface Product
Lattice Field Programmable System Chips
and ispGDX2 Products
Lattice offers the world’s fastest programmable interface products.
Lattice Semiconductor pioneered the approach of putting ASIC
macrocells and FPGA gates on the same silicon die. We call this a
Field Programmable System Chip (FPSC). The embedded macrocells
hold industry-standard Intellectual Property - bus interface, high-
speed line interface, and high-speed transceiver cores. When these
macrocells are combined with hundreds of thousands of
programmable gates they can be used in a variety of advanced system
designs.
In addition to the innovative FPSC products, Lattice delivers the high-speed line of ispGDX2 (in-
system programmable Generic Digital Crosspoint) bus switching and interface products. These
flexible devices offer low-cost SERDES solutions and high-performance bus switching.
Bringing the Best Together
Lattice FPSC Families
■High Performance ORCA Series 4 based Field
Programmable System Chips
■FPSC Functions
–High-speed line interface
–Programmable backplane transceiver
–Serial backplane driver
–SONET backplane transceiver
■sysCLOCK PLLs for Clock Management
■sysIO Capability for High Performance Interfacing
–On-chip differential termination
■MPI and System Bus for Easy Connection to
Microprocessor
ORCA
Series 4
FPGA
Gates
I/O
I
/
O
Configurable I/O
Flexible s
y
sIO
Ca
p
abilit
y
Single-ended
(
GTL+,
HSTL, SSTL, etc.
)
,
Differential
(
LVDS,
LVPECL
)
, DD
R
O
ASIC Gate
s
ORT82G5
/
ORT42G5: 8b/10b encodin
g
/decodin
g
, multi-channel ali
g
nment lo
g
ic,
XA
U
I
&
Fibre
C
hannel state machine
s
SONET framing, SONET scrambling, pa
y
load processo
r
O
RT
8850
: SONET framin
g
, SONET scramblin
g
ORLI10G: High-speed MUX/deMU
X
ASIC Gates
Provide
cost effective,
high-speed,
p
re-desi
g
ne
d
su
pp
ort lo
g
i
c
FPSC Block Diagram
O
RT8850
L
H
ORT8850H
Programmable Logic Gates
Aggregate Bandwidth
is
p
GDX
2
O
RT82
G5
O
R
SO
82
G5
O
RT42
G5
O
R
SO
42
G5
O
RLI10
G
FPSC Data Rate SERDES Encoding Standards FPSC FPGA
Device per Channel Channels Support Support Functionality Core
ORT82G5 / 3.7 – 0.6 Gbps 8 / 4 8b/10b XAUI 8b/10b encoding XAUI & Fibre 10,368 LUTS
ORT42G5 Fibre Channel, channel link state machines, 643K Gates
Gigabit Ethernet multi-channel alignment 372 / 204 I/O
ORSO82G5 / 2.7 – 0.6 Gbps 8 / 4 SONET SONET-based Pseudo-SONET framing, 10,368 LUTS
ORSO42G5 SERDES Links TOH insertion/extraction, 643K Gates
multi-channel alignment, 372 / 204 I/O
payload cell processor
ORT8850H 850 – 126 Mbps 8 SONET SONET-based Pseudo-SONET framing, 16,192 LUTS
SERDES Links TOH insertion/extraction, 899K Gates
multi-channel alignment, 297 I/O
pointer mover
ORT8850L 850 – 126 Mbps 8 SONET SONET-based Pseudo-SONET framing, 4,992 LUTS
SERDES Links TOH insertion/extraction, 397K Gates
multi-channel alignment, 278 I/O
pointer mover
ORLI10G 850 – 622 Mbps – OIF XSBI, OIF SFI-4 High speed MUX/deMUX 10,368 LUTS
643K Gates
316 I/O
7
ts
ispGDX2 Features & Benefits
■High Performance Bus Switching
–13.6 Gbps (SERDES), 38 Gbps (without SERDES)*
–Up to 16 (15x10) FIFOs for data buffering
–I/O intensive: 64 to 256 I/Os
■sysCLOCK PLLs for Clock Management
–Frequency synthesis and skew management
–Clock shifting, multiply and divide capability
–Jitter as low as 150 ps
■sysIO Capability for High Performance Interfacing
–Hot socketing support
–Leave alone I/O – holds pin state during programming
■Up to 16 Channels of 850 Mbps sysHSI SERDES
–Serializer/de-serializer (SERDES) included
–Built-in Clock Data Recovery (CDR)
–10b/12b and 8b/10b support
■Flexible Programming & Testing
ispGDX2 Block Diagram
ispGDX2 Families
sysHSI
Block
S
ERDE
S
S
ERDE
S
FIF
O
FIF
O
G
DX Bloc
k
G
DX Bloc
k
PLL
PLL
Global Routin
g
Poo
l
S
ERDE
S
SERDES
FIF
O
FIFO
GDX Block
GDX Block
sysIO Block sysIO Block
sysIO Bloc
k
sysIO Bloc
k
for
s
u
pp
ort
:
SSTL, HSTL, PCI, GTL+,
LVCMOS 3.3, 2.5 and
1.
8
s
y
sHSI Block
p
rovides 2
du
p
lex 850Mb
p
s SERDE
S
s
y
sCLOCK PLL
s
FIFOs for bufferin
g
data
streams
(
15x10 bits
)
G
DX Bl
oc
kincludes
control lo
g
ic and data
multi
p
lexer
s
Flexible routin
g
o
p
timized for bus
switchin
g
sysIO Block
sysIO Block
sysIO Block
GDX
GDX
sIO
sIO
sIO
s
s
s
O
O
O
* Bandwidth assumes 50% of I/Os are inputs and 50% are outputs.
ORSO82G5 and ORSO42G5
The ORSO82G5 includes eight 2.7 Gbps
SERDES coupled with on-chip SONET
framing. The ORSO82G5 provides an
excellent SONET-based solution for chip-
to-chip or backplane applications. The
ORSO42G5 offers four SERDES channels
instead of eight.
ORT82G5 and ORT42G5
The ORT82G5 provides eight 3.7 Gbps
SERDES. Standard compliance and on-
chip link state machines make it ideal for
implementing XAUI, 10 Gbps Ethernet
and Fibre Channel links in chip-to-chip
or backplane applications. The ORT42G5
offers four SERDES channels instead of
eight.
ORT8850
The ORT8850 includes eight 850 Mbps
SERDES channels plus on-chip SONET
framing. The ORT8850 provides an
alternative to Ethernet technology for
implementing chip-to-chip or backplane
applications.
ORLI10G
The ORLI10G provides a high-speed line
interface with a flexible FPGA logic core.
The ORLI10G can be used as the interface
in a variety of emerging networks,
including 10 Gbps SONET/SDH (OC-
192/STM-48), 10 Gbps optical transport
networks (OTN) using digital wrapper
and strong FEC, or 10 Gbps Ethernet.
ispGDX2 Family of Digital Cross Point Switches
Superior SERDES
Performance
Lattice sysHSI SERDES technology leads
the programmable logic industry in terms
of maximum bit rate and low jitter. The
following eye diagram illustrates the
outstanding characteristics of Lattice’s
sysHSI SERDES technology.
Lattice FPSC Devices
ORT82G5 RX Eye Diagram over 40 inches
(100 centimeters) of FR4 at 3.125 Gbps
SERDES
GDX Bandwidth Bandwidth Data Rate Bus LVDS Channels
Family Member I/Os Blocks Fmax (SERDES) (without SERDES) Per Channel (Pairs) (850Mbps) PLLs
ispGDX2-64
64 4 330 MHz 3.5 Gbps 11 Gbps 400–850 32 4 2
ispGDX2-128
128 8 330 MHz 7.0 Gbps 21 Gbps 400–850 64 8 2
ispGDX2-256
256 16 300 MHz 13.6 Gbps 38 Gbps 400–850 128 16 4
8
CPLD Products
Bringing the Best Together
ispXPLD 5000MX Block DiagramispXPLD 5000MX Features and Benefits
■Flexible MFB Architecture
–SuperWIDE logic, SuperBIG density
–Arithmetic support
–Single- or Dual-Port RAM
–Asynchronous FIFO
–Ternary CAM
■sysCLOCK PLLs for Clock Management
■sysIO Capability for High Performance Interfacing
–Leave alone I/O – holds pin state during
programming
–5V tolerant inputs & I/Os
■In-system eXpanded Programming (ispXP)
–Instant-on capability
–Single chip convenience
–ISP via IEEE 1532 Interface
–Infinitely reconfigurable via IEEE 1532 or
sysCONFIG™ interface
■High Performance
–4.0 ns tPD pin-to-pin delays
–285 MHz fMAX
■Low Power Consumption
–Static power as low as 20 mA
■Ease of Design
–3.3, 2.5 and 1.8V power supply operation
G
loba
l
Routin
g
Poo
l
I
/
O Bank
0
I/O Bank 1 I/O Bank 2
I/O Bank 3
MFB
sysIO
sysI
O
MFB
MFB
sysI
O
sysIO MFB
sysCLOCK PLL
sysCLOCK PLL
sysIO
sysIO
MFB
MFB
sysIO
sysIO
MFB
MFB
I
S
P Por
t
s
y
sy
s
s
M
M
M
Multi-Function Blocks
(
MFBs
)
are independentl
y
programmable
as logic, single- or dual-port memor
y
, FIFO, or CA
M
sysIO Interfaces for ultra hi
gh
s
p
eed I/Os. Su
pp
orts SSTL
,
HSTL
,
PCI
,
GTL+
,
LVDS
,
LVPECL
,
LVTTL
,
& LVCMOS
.
sysCLOCK PLLs
Global Routing Pool
(
GRP
)
p
rovides flexible,
deterministic routin
g
I
S
P Por
t
offers non-volatile, In-s
y
stem programmabilit
y
,
and reconfigurabilit
y
via s
y
sCONFIG interface
Lattice ispXPLD and ispMACH CPLDs
Through its optimized portfolio of CPLDs, Lattice provides products
a generation ahead of other CPLD solutions. These architectures are
optimized to fit a variety of CPLD design challenges. This contrasts to
the "one size fits all" approach of other CPLD vendors.
■SuperFAST™ Performance Leadership - Up to 400 MHz
■Zero Power CPLD - As low as 20 µA Standby Current
■SuperBIG™ Density Leadership - Up to 1024 macrocells
■SuperWIDE™ Logic - 68-input logic blocks
■Multi-Function Block (MFB) Architecture combines memory,
CAM and FIFO with logic
Lattice pioneered the ispMACH 5000 architecture delivering SuperWIDE performance with 68 logic inputs and
easy implementation of complex logic functions in a single level of logic. The new ispXPLD 5000MX family
combines memory with Lattice’s SuperWIDE architecture and SuperBIG density. The ispXPLD 5000MX family
represents a new class of devices called eXpanded Programmable Logic Devices (XPLDs). These devices are built
around a new building block, the Multi-Function Block (MFB). MFBs can be individually configured as
SuperWIDE (136-input) logic, single- or dual-port memory, FIFO, or CAM depending on the application. This
architecture delivers the ultimate PLD flexibility through ispXP.
Lattice’s ispMACH 4000 family is built on the industry’s most advanced non-volatile CMOS process and delivers
SuperFAST system performance for logic functions up to 36 inputs. The ispMACH 4000Z offers the industry’s
lowest power for handheld and other power-sensitive applications. Lattice’s ispMACH 4000 family brings
together high speed, low power and low cost to deliver the best solutions for a broad range of applications.
Lattice’s CPLD product portfolio offers commercial, industrial, automotive, and military grade devices.
Density
Functionality
is
p
XPL
D
5000
M
X
is
p
MAC
H
5000
is
p
MAC
H
4
000
9
ispMACH 4000 Features and Benefits
■SuperFAST Performance
–2.5 ns tPD pin-to-pin delay
–400 MHz system performance
■Industry’s Lowest Power Consumption
–1.8V core for low dynamic power
–Low static current
• 20 µA max. (1.8V ispMACH 4000Z)
• 1 - 3.5 mA (1.8V ispMACH 4000C)
■Ease of Design
–In-system programmable
• IEEE 1149.1, IEEE 1532 compliant
–Flexible I/O support
• 2 I/O banks with independent VCCO and GND
• Leave alone I/O – holds pin state during programming
• LVTTL, LVCMOS 1.8, 2.5, 3.3
• 5V tolerant inputs and I/Os
• Hot socketing support
■Automotive Temperature Devices
–Broadest density range: 32 to 256 macrocells
–Available for 3.3V (4000V) and 1.8V (4000Z) power supply
–7.5 ns tPD pin-to-pin delay
–168 MHz system performance
ispMACH 4000 Block Diagram
36
36
36
36
16
I/O
Bank
0
I
/O
Bank
1
G
loba
l
Routin
g
Poo
l
Generic
Logic
Block
16
I/O Block
I/O Block
Generic
Logic
Block
Output Routing Pool
Output Routing Pool
16
16
Output Routing Pool
Generic
Logic
Block
I/
O
Bloc
k
I/O Block
Output Routing Pool
Generic
Logic
Block
16
16 16
16
Global Routing Pool
(
GRP
)
provides flexible
,
deterministic routin
g
k
I/O Bank power suppl
y
can be 1.8V
,
2.5V or
3.3V. In
p
ut standard
su
pp
orted is
inde
p
endent of
V
CCO
.
1.8V
2.5V
3.3V
Power
Supply
5V
User I/O tPD f
MAX Logic Block Memory Standby
Family Macrocells Options (ns) (MHz) Inputs Kbits Current
ispXPLD 5000MC 256 - 1024 141 - 381 4.0 285 68 128–512 20 mA
ispMACH 4000C 32 - 512 30 - 208 2.5 400 36 — 1.8 mA
ispMACH 4000Z 32 - 128 32 - 92 3.5 265 36 — 20 µA (Max.)
ispXPLD 5000MB 256 - 1024 141 - 381 4.0 285 68 128–512 30 mA
ispMACH 5000B 128 - 512 92 - 256 3.0 275 68 — 83 mA
ispMACH 4000B 32 - 512 30 - 208 2.5 400 36 — 11.3 mA
ispXPLD 5000MV 256 - 1024 141 - 381 4.0 285 68 128–512 30 mA
ispLSI 5000VE 128 - 512 72 - 256 5.0 180 68 — 100 mA
ispMACH 4000V 32 - 512 30 - 208 2.5 400 36 — 11.3 mA
ispMACH 4A5 32 - 256 32 - 128 5.0 182 36 — 20 mA
XPLD and CPLD Device Families
ispMACH 5000 Features and
Benefits
■SuperWIDE Performance
–68 Inputs / 32 macrocells per logic block
–3.0 ns tPD pin-to-pin delay
–275 MHz system performance
■sysIO Capability for High Performance
interfacing
–Leave alone I/O – holds pin state
during programming
–5V tolerant inputs & I/Os
■Ease of Design
–In-system programmable
• IEEE 1149.1, IEEE 1532 compliant
–2.5V power supply operation
–Hot socketing support
Lattice Offers Ultra-Low
Power Consumption
80
Competitive
Device
Lattice
ispMACH 4032Z
60
40
20
100
120
2
0
µ
A
Static ICC (µA)
< 100 µA
80%
Powe
r
R
educ
ti
on
Lattice’s ispGAL22V10A device takes
board-space savings and speed to a
new level. This high performance
device brings together the best
features in one tiny package.
■2.3 ns / 455 MHz Speed
■150 µA Standby Current
■5 x 5 mm QFN Package
■In-System Programmable
World’s Fastest and
Smallest PLD
10
Analog Products
Bringing the Best Together
Programmable Analog & Mixed Signal Devices
Impossible was never so easy! Lattice delivers in-system programmable
analog ICs (ispPAC) and the new Programmable Mixed Signal devices
... ispPAC Power Manager.
Bringing the Best Together: Integrating in-system programmable
analog and digital components on a single chip, the ispPAC Power
Manager devices provide complete monitoring and sequencing control
of power supplies on your circuit board.
ispPAC Device Families
ispPAC10 ispPAC30
ispPAC20
Fully-Integrated,
All-in-One, ISP,
Fifth-Order
Low Pass Filter
ispPAC80/81
IA
IA OA
IA
IA OA
IA
IA OA
IA
IA OA
Analog Routing Pool
Auto-Cal
Reference
ISP Control
IA
IA OA
IA
IA OA
CP
CP
DAC
Analog Routing Pool
Auto-Cal
Reference
ISP Control
E
2
CMOS Mem
E
2
CMOS Mem
E
2
CMOS Cfg A
Ref & Auto-Cal ISP Control
E2CMOS Cfg B
IA OA
5th Order LPF
OA
OA
IA
IA
IA
JTAG/SPI
Interface Logic
& Configuration
Memory
Filter
Amplify
Integrate
Compare
Filter
Amplify
Integrate
Compare
2.5V Reference
Auto-Calibration
Summation Routing Pool
MDAC
Vref1
MDAC
Vref2
IA
Input/Output Routing Pool
ispPAC Device Block Diagrams
PAC-Designer software’s easy-to-use GUI
ispPAC Design Tools
Lattice provides a complete set of tools
for rapidly implementing analog and
mixed signal designs.
■PAC-Designer Software Allows
Intuitive Point & Click Design
entry
•Board power supply management
•Adaptive analog front ends
• Continuous-time filters from 5th
order down
•Flexible feedback control loops
■Simulation for Analog and Mixed
Signal Designs
■Evaluation Boards for Rapid
Prototyping
Simultaneousl
y
monito
r
u
p
to 12
p
ower su
pp
lie
s
without discrete
com
p
onent
s
Flexible Power suppl
y
sequencin
g
throu
gh
MOSFETS
,
Bricks
,
an
d
LD
Os
S
y
stem-level contro
l
for s
y
stem reset an
d
front
p
anel shut-dow
n
Supervisor
y
signa
l
g
eneration control
s
CPU_RESET
,
Power_Good
,
Suppl
y
_Interrupt, etc
.
Basic timin
g
g
eneration,
control sequence dela
y
,
and watchdo
g
time
r
Pro
g
rammable
Function
Di
g
ita
l
Out
p
u
t
Programmable
Power Supply Monito
r
CPLD
Char
g
e
Pum
p
e
d
FET Driv
e
with
Digital
Output
Internal Oscillator
&
Timers
Di
g
ital
S
i
g
na
l
Monito
r
r
r
ispPAC Power Manager Block Diagram
Power Manager and ispPAC Evaluation
boards enable fast prototyping.
Power Supply Supervisory FET Drivers/ Reprogrammable CPLD
Device Sense Inputs Outputs Digital Outputs Timers Macrocells
Power1208 12 4 4 4 16
Power604 6 4 — 2 8
Device Filters Control Loop Sensor Interface Data Acquisition
ispPAC10 — —
ispPAC20
ispPAC30 —
ispPAC80/81 — —
ispPAC Power Manager Devices
11
Bringing the Best Together
ispLEVER
Intellectual Property
Lattice offers an expanding range of IP
cores (ispLeverCORE™ IP modules) to
support easy integration of commonly
used complex functions for:
■Communications
–UTOPIA
– POS-PHY3
–Fast 10/100 Ethernet MAC
–Gigabit Ethernet MAC
–10 Gigabit PCS
■Bus Interface
–PCI Target
■Memory Control
–DDR SDRAM Controller
–Multi-channel DMA Controller
■Digital Signal Processing
–Reed Solomon Encoder
–Convolutional Encoder
Additional cores are in progress. Check
the Lattice website for details and
schedules.
Evaluation and
Programming Hardware
Evaluation boards are offered to allow
users to evaluate, test, and perform
design debug for a variety of Lattice
devices and include:
■EV Board
■Download Cable
■Board Schematics
■Gerber Files
■Users Manual
Lattice also offers a wide range of
programming cables, desktop
programmers, and adapters for
advanced packages:
■ispDOWNLOAD® Cables
–Parallel (1 x 8, 2 x 5, Flywire)
–USB (Flywire)
■Model 300 Desktop Programmer
and Adapters
CPLD
GDX/2 LeoSpec Synplify® ModelSim
Package Part Number FPGA FPSC SPLD Synthesis Synthesis Simulation
Starter Downloadable
Base LS-HDL-BASE-PC-N
Advanced LS-EXM-ADV-PC-F
LS-HDL-ADV-PC-N
LS-ADV-WS-F
Project Navigator
Constraints Editor
Floorplanner
Design
Tools
The Simple Machine for Complex Design
Lattice’s ispLEVER is an advanced programmable logic design tool
equipped to provide a complete system for FPGA, FPSC, CPLD,
XPLD, ispGDX®, and SPLD design. ispLEVER includes a fully
integrated, push-button design environment, and advanced features
for interactive design optimization and debug.
ispLEVER Design Tools Features
■Integrated ModelSim® RTL Simulator
■Integrated Mentor Graphics® and Synplicity® Synthesis
■VHDL, Verilog, and ABEL Language Support
■Module Generator / IP Manager
■Comprehensive Constraints / Pin Editor
■Floorplanner for FPGA / FPSC
■Static Timing Analyzer
■Integrated Timing and Functional Simulator
■HTML Reporting
■Integrated ispVM® Programming Software
■Automated ispUPDATE™ Utility
■PC and UNIX Versions
ispLEVER Design Tools
Copyright © 2003 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), E2CMOS, ISP,
ispDOWNLOAD, ispGAL, ispGDX, ispLEVER, ispLeverCORE, ispMACH, ispPAC, ispVM, ispXP, ispXPGA, ispXPLD, ORCA, PAC-Designer, SuperBIG, SuperFAST,
SuperWIDE, sysCLOCK, sysCONFIG, sysHSI, sysIO and sysMEM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United
States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Lattice Semiconductor Corporation
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Telephone: (503) 268-8000 • FAX: (503) 268-8556
Applications & Literature Hotline: 1-800-LATTICE
www.latticesemi.com
March 2003
Order #: I0156
