CY62147GN/CY621472GN MoBL®
4-Mbit (256K words × 16 bit) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-10624 Rev. *D Revised December 21, 2017
4-Mbit (256K words × 16 bit) Static RA M
Features
■High speed: 45 ns/55 ns
■Ultra-low standby power
❐Typical standby current: 3.5 A
❐Maximum standby current: 8.7 A
■Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V , 4.5 V to 5.5 V
■1.0-V data retention
■TTL-compatible inputs and outputs
■Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY62147GN and CY621472GN are high-performance CMOS
low-power (MoBL) SRAM devices organized as 256K Words by
16-bits. Both devices are offered in single and dual chip enable
options and in multiple pin configur ations.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while provid ing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the require d address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual ch ip enable device), or
control signals are de-asserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
The logic block diagram is provided in page 2.
Product Portfolio
Product
Features and
Options
(see the Pin
Configurations
section)
Range VCC Range (V) Speed (ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2 (µA)
f = fmax
Typ[1] Max Typ[1] Max
CY62147GN18 Single or dual
Chip Enables Industrial 1.65 V–2.2 V 55 15 20 3.5 10
CY62147GN30
CY621472GN30 2.2 V–3.6 V 45 15 20 3.5 8.7
CY62147GN 4.5 V–5.5 V
Notes
1. Typical values are included for reference only and are not guar anteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC =3V (for V
CC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 002-10624 Rev. *D Page 2 of 20
CY62147GN/CY621472GN MoBL®
Logic Block Diagram – CY62147GN
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSE
AMPLIFIERS
A11
A12
A13
A14
A15
A16
A17
INPUTBUFFER
I/O0‐I/O7
I/O8‐I/O15
BHE
WE
OE
BLE
CE2
CE1
Document Number: 002-10624 Rev. *D Page 3 of 20
CY62147GN/CY621472GN MoBL®
Contents
Pin Configuration – CY62147GN .....................................4
Pin Configuration – CY621472GN ...................................5
Maximum Ratings .............................................................6
Operating Range ..................... .. .............. ... .............. ... ......6
DC Electrical Characteristics .. ... ... ................. .................6
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Loads and Waveforms .......................................8
Data Retention Characteristics .......................................9
Data Retention Waveform ................................................9
AC Switching Characterist ics ............. .. ... .............. ... ....10
Switching Waveforms ................. ... ... .............. .............. .11
Truth Table – CY6214 7GN/CY621472GN ......................15
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagrams ..........................................................17
Acronyms ........................................................................ 18
Document Conventions ..................... ... ... .............. ... .....18
Units of Measure .............................. ... ... .............. .. ...18
Document History Page .......... ... .. ............... .. .............. ...19
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products .................................................................... 20
PSoC® Solutions ......................................................20
Cypress Developer Community ...................... ... ........20
Technical Support .....................................................20
Document Number: 002-10624 Rev. *D Page 4 of 20
CY62147GN/CY621472GN MoBL®
Pin Configuration – CY62147GN
Figure 1. 48-ball VFBGA pinout (Dual Chip Enable),
CY62147GN[2] Figure 2. 48-ball VFBGA pinout (Single Chip Enable),
CY62147GN[2]
Figure 3. 44-pin TSOP II Pinout (Single Chip Enable), CY62147GN[2]
WE
A11
A10
A6
A0
CE1
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
Vss
A7
I/O0
BHE
CE2
A17
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
NC
VCC
A1A2
A3
WE
A11
A10
A6
A0
CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
Vss
A7
I/O0
BHE
NC
A17
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
NC
VCC
A1A2
A3
44-TSOP-II
A6A3 243
A7A2 342
/OEA1 441
I/O15I/O0 738
/BLE
639
/CE
I/O13I/O2 936
I/O12I/O3 10 35 VSSVCC 11 34 VCCVSS 12 33 I/O11I/O4 13 32 I/O10
I/O5 14 31 I/O9I/O6 15 30 I/O8I/O7 16 29 NC/WE 17 28 A8
A17 18 27 A9
A16 19 26 A10
A15 20 25 A11A14 21 24
A13 22 23
A5A4 144
I/O14I/O1 837
/BHEA0 540
A12
Notes
2. NC pins are not connected internally to the die and are typicall y used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 002-10624 Rev. *D Page 5 of 20
CY62147GN/CY621472GN MoBL®
Pin Configuration – CY621472GN
Figure 4. 44-pin TSOP II pinout (Dual Chip Enable), CY621472GN
44-TSOP-II
A6A3 243
A7A2 342
/OEA1 441
I/O15I/O0 738
/BLE
639
/CE1
I/O13I/O2 936
I/O12I/O3 10 35 VSSVCC 11 34 VCCVSS 12 33 I/O11I/O4 13 32 I/O10
I/O5 14 31 I/O9I/O6 15 30 I/O8I/O7 16 29 CE2
/WE 17 28 A8
A17 18 27 A9
A16 19 26 A10
A15 20 25 A11A14 21 24
A13 22 23
A5A4 144
I/O14I/O1 837
/BHEA0 540
A12
Document Number: 002-10624 Rev. *D Page 6 of 20
CY62147GN/CY621472GN MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage temperature ...............................–65 °C to + 150 °C
Ambient temperature
with power applied ......................... ... ... ...–55 °C to + 125 °C
Supply voltage
to ground potential[3] ...................... .....–0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z state [3]...................... .............. ..–0.5 V to VCC + 0.5 V
DC input voltage[3] ...................... ........–0.5 V to VCC + 0.5 V
Output current into outputs (in low state) ....................20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current .....................................................>140 mA
Operating Range
Grade Ambient Temperature VCC
Industrial –40 C to +85 C1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 45/55 ns Unit
Min Typ Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – –
V
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2 – –
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5[4] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2
V
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4
VIH Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2[3]
V
2.2 V to 2.7 V – 1.8 – VCC + 0.3[3]
2.7 V to 3.6 V – 2 – VCC + 0.3[3]
4.5 V to 5.5 V – 2.2 – VCC + 0.5[3]
VIL Input LOW
voltage
1.65 V to 2.2 V – –0.2[3] –0.4
V
2.2 V to 2.7 V – –0.3[3] –0.6
2.7 V to 3.6 V – –0.3[3] –0.8
4.5 V to 5.5 V – –0.5[3] –0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC,
Output disabled –1 – +1 A
ICC VCC operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f =
22.22 MHz
(45 ns) –1520mA
f =
18.18 MHz
(55 ns) –1520mA
f = 1 MHz – 3.5 6 mA
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of les s than 20 ns.
4. This parameter is guaranteed by design and not tested.
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CY62147GN/CY621472GN MoBL®
ISB1[5]
Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and 4.5 V to
5.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
–3.58.7
A
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V ––10
ISB2[5]
Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and 4.5 V to
5.5 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V or
(BHE and BLE) >
VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
25 °C[6] –3.53.7
A
40 °C[6] ––4.8
70 °C[6] ––7
85 °C – – 8.7
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2V or
CE2 < 0.2 V or
(BHE and BLE) >
VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
25 °C[6] –3.54.3
40 °C[6] ––5
70 °C[6] ––7.5
85 °C – – 10
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 45/55 ns Unit
Min Typ Max
Notes
5. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
6. T h e I SB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guarant eed by design and n ot 100% tested.
Document Number: 002-10624 Rev. *D Page 8 of 20
CY62147GN/CY621472GN MoBL®
Capacitance
Parameter[7] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = V CC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter[7] Description Test Conditions 48-ball VFBGA 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient) Still air, sold ered on a 3 × 4.5 inch, four
layer printed circuit board
31.35 68.85 °C/W
JC Thermal resistance
(junction to case) 14.74 15.97 °C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms[8]
V
HIGH
V
CC
OUTPUT
R2
30 pF*
*Including
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
jig and sope
Parameters 1.8 V 2.5 V 3.0 V 5.0 V Unit
R1 13500 16667 1103 1800
R2 10800 15385 1554 990
RTH 6000 8000 645 639
VTH 0.80 1.20 1.75 1.77 V
Notes
7. Tested init ially and after any design or process changes that may affect these parameters.
8. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 002-10624 Rev. *D Page 9 of 20
CY62147GN/CY621472GN MoBL®
Data Retention Characteristics
Over the Operating range
Parameter Description Conditions Min Typ[9] Max Unit
VDR VCC for data retention 1 – – V
ICCDR[10, 11] Data retention current
Vcc = 1.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
–13A
tCDR[12] Chip deselect to data retention
time 0––ns
tR[13] Operation recovery time 45/55 – – ns
Data Retention Waveform Figure 6. Data Retention Waveform[14]
Notes
9. T ypical values are included only for reference a nd are not guaranteed or tested. T ypical values are measured at VCC = 1.8 V (for VCC ra nge of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
10.Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the I SB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
12.These par ameters are guaranteed by design.
13.Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14.BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 002-10624 Rev. *D Page 10 of 20
CY62147GN/CY621472GN MoBL®
AC Switching Characteristics
Parameter[15, 16] Description 45 ns 55 ns Unit
Min Max Min Max
READ CYCLE
tRC Read cycle time 45 –55 –ns
tAA Address to data valid –45 –55 ns
tOHA Data hold from address change 10 –10 –ns
tACE CE1 LOW and CE2 HIGH to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to Low impedance[17] 5 – 5 – ns
tHZOE OE HIGH to HI-Z[17, 18] –18 –18 ns
tLZCE CE1 LOW and CE2 HIGH to Low impedance[17] 10 –10 –ns
tHZCE CE1 HIGH and CE2 LOW to HI-Z[17, 18] –18 –18 ns
tPU CE1 LOW and CE2 HIGH to power-up 0 – 0 – ns
tPD CE1 HIGH and CE2 LOW to power-down –45 –55 ns
tDBE BLE / BHE LOW to data valid –45 –55 ns
tLZBE BLE / BHE LOW to Low impedance[17] 5 – 5 – ns
tHZBE BLE / BHE HIGH to HI-Z[17, 18] –18 –18 ns
WRITE CYCLE[19, 20]
tWC Write cycle time 45 –55 –ns
tSCE CE1 LOW and CE2 HIGH to write end 35 –45 –ns
tAW Address setup to write end 35 –45 –ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tBW BLE / BHE LOW to write end 35 –45 –ns
tSD Data setup to write end 25 –25 –ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to HI-Z[17, 18] –18 –20 ns
tLZWE WE HIGH to Low impedance[17] 10 –10 –ns
Notes
15.Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the r ead cycle use output lo ading shown in AC Test Loads and W aveforms sectio n, unless
specified otherwise.
16.T hese parameters are guaranteed by design.
17.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is l ess than tLZWE for any device.
18.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output s enter a high-impedance state.
19.T he internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to t he edge of the signal that
terminates the write.
20.The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
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CY62147GN/CY621472GN MoBL®
Switching Waveforms
Figure 7. Read Cycle No. 1 of CY62147GN (Address Transition Controlled)[21, 22]
Figure 8. Read Cycle No. 2 (OE Controlled)[21, 22, 23, 24]
ADDRESS
DATA I / O
VALID DATAOUT
VALID
tRC
tOHA
tAA
PREVIOUS DATAOUT
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IM PEDANCE DATAOUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DATA I /O
tHZOE
tHZBE
ISB
CC
V
SUPPLY
CURRENT
Notes
21.The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
22.WE is HIGH for Read cycle.
23.Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/ or BLE = VIH.
24.Ad dress valid prior to or coincident with CE LOW transition.
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CY62147GN/CY621472GN MoBL®
Figure 9. Write Cycle No. 1 (WE Controlled)[25, 26, 27]
Switching Waveforms (continued)
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Notes
25.For all dual chip enable devices, CE is the logical combinatio n of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW ; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
26.The internal write time of the memory is d efined by the o verlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signa ls must be ACTIVE to initiate
a write and any of these signals can termi nate a write by going INACTIVE. The data input setup and hol d timing must refer to th e edge of the signal that terminat es the
write.
27.Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
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CY62147GN/CY621472GN MoBL®
Figure 10. Write Cycle No. 2 (CE Controlled)[28, 29, 30]
Figure 11. Write Cycle N o. 3 (WE Controlled, OE LOW)[28, 29, 30, 31]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE tHA
tBW
tHD
tHZOE
DATAIN VALID
tSD
ADDRESS
CE
DATA I /O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Notes
28.For all dual chip enable devices, CE is the logica l combinat ion of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29.The i nternal write t ime of the memory is defined by t he overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The da ta input setup and h old timing must refer t o the edge of th e signal that terminates the
write.
30.Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
31.The minimum write pulse widt h for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
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CY62147GN/CY621472GN MoBL®
Figure 12. Write Cycle No. 4 (BHE/BLE Controlled)[32, 33, 34]
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA tBW tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
Notes
32.For all dual chip enable devices, CE is the logica l combinat ion of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33.The i nternal write t ime of the memory is defined by t he overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The da ta input setup and h old timing must refer t o the edge of th e signal that terminates the
write.
34.Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BL E = VIH.
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CY62147GN/CY621472GN MoBL®
Truth Table – CY62147GN/CY621472GN
CE1/CE[35] CE2[35] WE OE BHE BLE Inputs/Outputs Mode Power
HX
[36] X X X X HI-Z Deselect/Power-down Standby (ISB)
X L X X X X HI-Z Deselect/Power-down Standby (ISB)
X X X X H H HI-Z Deselect/Power-down Standby (ISB)
L H H L L L Data Out (I/O0–I/O15) Read Active (ICC)
LHHLHL
Data Out (I/O0–I/O7);
HI-Z (I/O8–I/O15)Read Active (ICC)
LHHLLH
HI-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)Read Active (ICC)
L H H H L H HI-Z Output disabled Active (ICC)
L H H H H L HI-Z Output disabled Active (ICC)
L H H H L L HI-Z Output disabled Active (ICC)
L H L X L L Data In (I/O0–I/O15) Write Active (ICC)
LHLXHL
Data In (I/O0–I/O7);
HI-Z (I/O8–I/O15)Write Active (ICC)
LHLXLH
HI-Z (I/O0–I/O7);
Data In (I/O8–I/O15)Write Active (ICC)
Notes
35.For all dual chip enable devices, CE is the logical combinat ion of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW ; when CE1 is HIGH or CE2 is LOW ,
CE is HIGH
36.The ‘X’ (Don’t care) state f or the chip enables refer to the l ogic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 002-10624 Rev. *D Page 16 of 20
CY62147GN/CY621472GN MoBL®
Ordering Code Definitions
Ordering Information
Speed
(ns) Voltage
Range Ordering Code Package
Diagram Package Type Operating
Range
45 2.2 V–3.6 V
CY62147GN30-45 BVXI 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Dual Chip Enable
Industrial
CY62147GN30-45BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Dual Chip Enable, Tape
and Reel
CY62147GN30-45ZSXI 51-85087 44-pin TSOP II, Single Chip Enable
CY62147GN30-45ZSXIT 51-85087 44-pin TSOP II, Single Chip Enable, Tape and Reel
CY62147GN30-45 B2XI 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
CY62147GN30-45B2XIT 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable, Tape
and Reel
CY621472GN30-45ZSXI 51-85087 44-pin TSOP II, Dual Chip Enable
CY621472GN30-45ZSXIT 51-85087 44-pin TSOP II, Dual Chip Enable, Tape and Reel
55 1.65 V–2.2 V CY62147GN18-55 BVXI 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
CY62147GN18-55BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable, Tape
and Reel
X: T = Tape and Reel; Blank = Bulk
Temperature Grade: X = I; I = Industrial
Pb-free
Package Type: XX = BV, B2 or ZS
BV = 48-ball VFBGA (Dual Chip Enable);
B2 = 48-ball VFBGA (Single Chip Enable)
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
Voltage Range: 30 = 3 V typ
Process Technology: GN = 65 nm
Chip Enable: X = blank or 2
blank = Single Chip Enable; 2 = Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 47GN X
-
XX X
XX
Document Number: 002-10624 Rev. *D Page 17 of 20
CY62147GN/CY621472GN MoBL®
Package Diagrams
Figure 13. 44-pin TSOP II (Z44) Package Outline , 51-85087
Figure 14. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85087 *E
51-85150 *H
Document Number: 002-10624 Rev. *D Page 18 of 20
CY62147GN/CY621472GN MoBL®
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine-pitch ball grid array
WE write enable
Table 2. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
MHz megahertz
Amicroamperes
smicroseconds
mA milliamperes
mm millimeters
ns nanoseconds
ohms
%percent
pF picofarads
Vvolts
Wwatts
Document Number: 002-10624 Rev. *D Page 19 of 20
CY62147GN/CY621472GN MoBL®
Document History Page
Document Title: CY62147GN/CY621472GN MoBL®, 4-Mbit (256K words × 16 bit) Static RAM
Document Number: 002-10624
Rev. ECN No. Orig. of
Change Submission
Date Descriptio n of Change
** 5076421 NILE 01/07/2016 New data sheet.
*A 5084145 NILE 01/13/2016 Updated Logic Block Diagram – CY62147GN.
*B 5329364 VINI 06/29/2016 Updated Ordering Information:
Updated part numbers.
Updated to new te mplate.
*C 5429186 NILE 09/07/2016
Updated DC Electrical Characteristics: Enhanced VIH of 2.2V - 2.7V operating
range from 2.0V to 1.8V. Enhanced VOH of 2.7V - 3.6V operating range from
2.2V to 2.4V.
Updated Ordering Information: Updated part numbers.
Updated Note 3.
Updated Copyright and Disclaimer.
*D 6002285 AESATP12 12/21/2017 Updated logo and copyright.
Document Number: 002-10624 Rev. *D Revised December 21, 2017 Page 20 of 20
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CY62147GN/CY621472GN MoBL®
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