©2013 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSB70325 Rev. 1.2
FSB70325 Motion SPM® 7 Series
December 2015
FSB70325
Motion SPM® 7 Series
Features
• UL Certified No. E209204 (UL1557)
• High Performance PQFN Package
• 250 V RDS(on) = 1.4 Max FRFET MOSFET 3-Phase
Inverter with Gate Drivers and Protection
• Separate Open-Source Pins from Low-Side MOSFETs
for Three-Phase Current-Sensing
• Active-HIGH Interface, Works with 3.3 / 5 V Logic,
Schmitt-trigger Input
• Optimized for Low Electromagnetic Interference
• HVIC Temperature-Sensing Built-In for Temperature
Monitoring
• HVIC for Gate Driving with Under-Voltage Protection
and Interlock Function
• Isolation Rating: 1500 Vrms / min.
• Moisture Sensitive Level (MSL) 3
• RoHS Compliant
Application
• 3-Phase Inverter Driver for Small Power AC Motor
Drives
Related Source
• AN-9077 - Motion SPM® 7 Series User’s Guide
• AN-9078 - Surface Mount Guidelines for Motion
SPM® 7 Series
General Description
The FSB70325 is an advanced Motion SPM® 7 module
providing a fully-featured, high-performance inverter
output stage for AC Induction, BLDC a nd PMSM motors.
These modules integrate optimized gate drive of
the built-in MOSF ETs (FRFET® technology) to minimize
EMI and losses, while also providing multiple on-module
protection features including under-voltage lockouts,
thermal monitoring, fault reporting and interlock function.
The built-in one HVIC translates the in coming logic-level
gate inputs to the high-voltage, high-current drive signals
required to properly drive the module's internal
MOSFETs. Separate open-souce MOSFET terminals
are available for each phase to support the widest
variety of control algorithms.
3D Package Drawing (Click to Activate 3D Content)
Package Marking & Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FSB70325 FSB70325 PQFN27A 13’’ 24 mm 1000 units
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 2www.fairchildsemi.com
FSB70325 Rev. 1.2
Absolute Maximum Ratings
Inverter Part (each MOSFET unless otherwise specified.)
Control Part (each HVIC unless otherwise specified.)
Total System
1st Notes:
1. TCB is pad temperature of case bottom.
2. Marking “ * ” is calculation value or design factor.
Symbol Parameter Conditions Rating Unit
VDSS Drain-Source Voltage of Each MOSFET 250 V
*ID 25 Each MOSFET Drain Current, Continuous TCB = 25°C (1st Notes 1) 4.1 A
*ID 80 Each MOSFET Drain Current, Continuous TCB = 80°C 3.1 A
*IDP Each MOSFET Drain Current, Peak TCB = 25°C, PW < 100 s 8.2 A
*PDMaximum Power Dissipation TCB = 25°C, For Each MOSFET 49 W
Symbol Parameter Conditions Rating Unit
VDD Control Supply Voltage Applied Between VDD and COM 20 V
VBS High-side Bias Voltage Applied Between VB and VS20 V
VIN Input Signal Voltage Applied Between IN and COM -0.3 ~ VDD + 0.3 V
VFO Fault Output Supply Voltage Applied Between FO and COM -0.3 ~ VDD + 0.3 V
IFO Fault Output Current Sink Current FO Pin 5 mA
VCSC Current Sensing Input Voltage Applied Between Csc and COM -0.3 ~ VDD + 0.3 V
Symbol Parameter Conditions Rating Unit
TJOperating Junction Temperature -40 ~ 150 °C
TSTG Storage Temperature -40 ~ 125 °C
VISO Isolation Voltage 60 Hz, Sinusoidal, 1 Minute, Con-
nection Pins to Heat Sink Plate 1500 Vrms
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 3www.fairchildsemi.com
FSB70325 Rev. 1.2
Pin descriptions
Figure 1. Pin Configuration and Internal Block Diagram
1st Notes:
4. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM® 7 product. External connections should be made as
indicated in Figure 2.
5. The suffix -a pad is connected with same number pin. ex) 8 and 8a is connected inside.
Pin Number Pin Name Pin Description
1 /FO Fault Output
2V
TS Voltage Output of HVIC Temperature
3 Cfod Capacitor for Duration of Fault Output
4 Csc Capacitor (Low-pass Filter) for Short-circuit Current Detection Input
5V
DD Supply Bias Voltage for IC and MOSFETs Driving
6 IN_UH Signal Input for High-side U Phase
7 IN_VH Signal Input for High-side V Phase
8 (8a) COM Common Supply Ground
9 IN_WH Signal Input for High-side W Phase
10 IN_UL Signal Input for Low-side U Phase
11 IN_VL Signal Input for Low-side V Phase
12 IN_WL Signal Input for Low-side W Phase
13 Nu Negative DC-Link Input for U Phase
14 U Output for U Phase
15 Nv Negative DC-Link Input for V Phase
16 V Output for V Phase
17 W Output for W Phase
18 Nw Negative DC-Link Input for W Phase
19 VS(W) High-side Bias Vo ltage Ground for W phase Mosfet driving
20 PWPositive DC-Link Input for W Phase
21 PVPositive DC-Link Input for V Phase
22 PUPositive DC-Link Input for U Phase
23 (23a) VS(V) High-side Bias Voltage Ground for V phase Mosfet driving
24 (24a) VS(U) High-side Bias Voltage Ground for U phase Mosfet driving
25 VB(U) High-side Bias Voltage for U phase Mosfet driving
26 VB(V) High-side Bias Voltage for V phase Mosfet driving
27 VB(W) High-side Bias Vo ltage for W phase Mosfet driving
WH
VH
UH
OUT(WL)
OUT(VL)
OUT(UL)
(13) Nu
(17) W
(16) V
(14) U
(21) Pv
(19) VS(W)
(23), (23a ) V S(V)
(6) IN_UH
(7) IN _ VH
(9) IN_WH
COM
(24), (24a) VS(U)
OUT(UH)
VDD
OUT(VH)
OUT(WH)
VS(U)
VS(V)
VS(W)
(5) VDD
(8),(8a) C O M
UL
(10) IN _ U L VL
(11) IN _ V L WL
(12) IN_WL /Fo
(1) /F o
(2) VTS VTS
Cfod
(3) C fod Csc
(4) Csc
(25) VB(U)
(26) VB(V)
VB(U)
(27) VB(W)
VB(V)
VB(W)
(15) Nv
(18) Nw
(22) Pu
(20) Pw
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 4www.fairchildsemi.com
FSB70325 Rev. 1.2
Electrical Characteristics (TJ = 25°C, VDD = VBS = 15 V unless otherwise specified.)
Inverter Part (each MOSFET unless otherwise specified.)
Control Part (each HVIC unless otherwise specified.)
2nd Notes:
1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM® 7 product. VPN shou ld be sufficiently less than this
value consideri ng the ef f ect of the str ay inductance so that VPN should not exceed BVDSS in any case.
2. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field
applications due to the effect of different printed circuit boards and wirings. Please see Figure 3 for the switching time definition with the switching test circuit of Figure 4.
3. VTS is only for sensing-temperature of modu le and cann ot shutdown MOSFETs automatically.
4. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 24 x 10-6 x tFOD [F]
Symbol Parameter Conditions Min Typ Max Unit
BVDSS Drain - Source
Breakdown Voltage VIN = 0 V, ID = 1 mA (2nd Notes 1) 250 - - V
IDSS Zero Gate Voltage
Drain Current VIN = 0 V, VDS = 250 V - - 1 mA
RDS(on) Static Drain - Source
Turn-On Resistance VDD = VBS = 15 V, VIN = 5 V, ID = 1.0 A - 1.1 1.4
VSD Drain - Source Diode
Forward Voltage VDD = VBS = 15V, VIN = 0 V, ID = -1.0 A - 0.9 1.2 V
tON
Switching Times
VPN = 150 V, VDD = V BS = 15 V, ID = 1.0 A
VIN = 0 V 5 V, Inductive Load L = 3 mH
Low-Side MOSFET Switching
(2nd Notes 2)
- 460 - ns
tD(ON) - 405 - ns
tOFF - 340 - ns
tD(OFF) - 280 - ns
Irr -1.3- A
trr -72- ns
EON -25- J
EOFF -22- J
Symbol Parameter Conditions Min Typ Max Units
IQDD Quiescent VDD Current VDD=15V, VIN=0V VDD - COM - 1.7 3.0 mA
IQBS Quiescent VBS Current VBS=15V, VIN=0V VB(X)-VS(X),VB(V)-VS(V),
VB(W)-VS(W) -4570A
IPDD Operating VDD Current VDD=15V,FPWM=20kHz,
duty=50%, PWM signal
input for Low side VDD - COM - 1.9 3.2 mA
IPBS Operating VBS Current VBS=15V,FPWM=20kHz,
duty=50%, PWM signal
input for High side
VB(U)-VS(U),VB(V)-VS(V),
VB(W)-VS(W) - 300 400 A
UVDDD Low-side Undervoltage
Protection (Figure 6) VDD Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVDDR VDD Undervoltage Protection Reset Level 8.0 8.9 9.8 V
UVBSD High-side Undervoltage
Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V
VTS HVIC Temperature sens-
ing voltage output VDD=15V, THVIC=25°C (2nd Notes 3) 580 675 770 mV
VIH ON Threshold Voltage Logic High Level IN - COM --2.4V
VIL OFF Threshold Voltage Logic Low Level 0.8 - - V
VSC(ref) SC Current Trip Level V DD=15V CSC - COM 0.45 0.5 0.55 V
tFOD Fault-out Pulse Width CFOD=33nF (2nd Notes 4) 1.0 1.4 1.8 ms
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 5www.fairchildsemi.com
FSB70325 Rev. 1.2
Recommended Operating Condition
Thermal Resistance
Figure 2. Recommended MCU Interface and Bootstrap Circuit with Parameters
3rd Notes:
1. RJCB is simulation value with application board layout. (Please refer user’s guide SPM7 series)
2. Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
3. RC coupling (R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM® is compatible with
standard CMOS or LSTTL outptus.
4. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage.
Symbol Parameter Conditions Min. Typ. Max. Unit
VPN Supply Voltage Applied Between P and N - 150 200 V
VDD Control Supply Voltage Applied Between VDD and COM 13.5 15.0 16.5 V
VBS High-Side Bias Voltage Applied Between VB and VS13.5 15.0 16.5 V
dVDD/dt,
dVBS/dt Control Supply Variation -1.0 - 1.0 V/s
tdead Blanking Time for Preventing
Arm-Short VDD = VBS = 13.5 ~ 16.5 V, TJ 150°C 500 - - ns
fPWM PWM Switching Frequency TJ 150°C - 15 - kHz
Symbol Parameter Conditions Min. Typ. Max. Unit
RJCB Junction to Case Bottom
Thermal Resistance Single MOSFET Operating Condition
(3rd Notes 1) -2.0-°C/W
/Fo
VDD
LIN
HIN
VB
HO
VS
LO
P
NR3
Inverter
Output
C1
Micom
15-V
Line
10F
One-Leg Diagram of SPM
These values depend on PWM
control algorithm
R5
C5
VPN
C2
VTS
C4
* Example of bootstrap paramters:
C1 = C2 = 1F ceramic ca p a citor,
COM
5-V
Line
C3
CSC
C6
R2
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 6www.fairchildsemi.com
FSB70325 Rev. 1.2
Figure 3. Switching Time Definition
Figure 4. Switching Test Circuit (Low-side)
Figure 5. Under Voltage Protection
VDS ID
VIN
tON
tD(ON)
VIN (O N ) 10% ID90% ID
100% ID
trr
120% ID
0
VDS
ID
VIN
tOFF
tD(OFF)
VIN (O F F ) 10% ID
(a) Turn-on (b) Turn-off
Irr
90% ID
15-V
Line
5-V
Line
/Fo
VDD
LIN
HIN
VB
HO
VS
LO
VTS
COM
ID
LV
DC
+
VDS
-
UVBSD(DDD)
UVBSR(DDR)
Input Signal
UV P rotection
Status
High-side/Low-side
MO S FE T Drain Current
RESET DETECTION RESET
Fault Output
(Only Low-side UV protection)
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 7www.fairchildsemi.com
FSB70325 Rev. 1.2
Figure 6. Short-Circuit Current Protection
(with the external shunt resistance and CR connection)
c1 : Normal operation: MOSFET ON and car rying current.
c2 : Short circuit current detection (SC trigger).
c3 : Hard MOSFET gate interrupt.
c4 : MOSFET turns OFF.
c5 : Fault output timer operation start : Fault-out width (tFOD)
c6 : Input “L” : MOSFET OFF state.
c7 : Input “H”: MOSFET ON state, but during the active period of fault output the MOSFET doesn’t turn ON.
c8 : MOSFET OFF state
Figure 7. Timing Chart of Interlock Function
Control input
Output Current
Sensing Voltage
of the shunt
resistance
Fault Output S ignal
SC Reference Voltage
CR c ircuit time
constant delay
SC
Protection
Circuit state SET RESET
c6 c7
c3
c2
c1
c8
c4
c5
Internal M O SFE T
Gate-S ource Voltage
Hin
Lin
Ho
Lo
FSB70325 Motion SPM® 7 Series
©2013 Fairchild Semiconductor Corporation 8www.fairchildsemi.com
FSB70325 Rev. 1.2
Figure 8. Temperature profile VTS vs. THVIC
Figure 9. Example of Application Circuit
4th Notes:
1. RC-coupling (R5 and C5, R2 and C6) and C1, C5, C7, C8 at each input of Motion SPM® 7 product and MCU are useful to prevent improper input signal caused by surge-noise.
2. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC.
3. All the filter capacitors should be connected close to Motion SPM 7 product, and they should have good characteristics for rejecting high-frequency ripple current.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 25 50 75 100 125 150 175
Typ. 2.57V@125°Ｃ
Typ. 2.10V@100°Ｃ
Typ. 1.15V@50°Ｃ
100±5°Ｃ
125±5°Ｃ
50±5°Ｃ
HVIC Temperature, THVIC [°Ｃ]
Temperature Sensing Voltage, VTS [V]
Min.
Typ.
Max.
WH
VH
UH
OUT(WL)
OUT(VL)
OUT(UL) Nu
W
V
U
P
VS(W)
VS(V)
IN_UH
IN_VH
IN_WH
COM
VS(U)
OUT(UH)
VDD
OUT(VH)
OUT(WH)
VS(U)
VS(V)
VS(W)
VDD
COM
UL
IN_UL
VL
IN_VL
WL
IN_WL
/Fo
/Fo
VTS Vts
Cfod
Cfod
Csc
Csc
VB(U)
VB(V) VB(U)
VB(W) VB(V)
VB(W)
Nv
Nw
5V
15V
M
MCU
C3VDC
R3
R2
C6
C2
C4C7
R5
C8
C1
C5
0.10 C A B
0.65
(1.50)
1.10
(1.60)
(1.15)
13.00
12.80
C
L
PKG
L
C
PKG
13.00
12.80
27
PIN 1
QUADRANT
1 13
18
17
14
TOP VIEW
A
B
20
1.40
1.20
C
0.08 C
SEATING
PLANE
0.10 C
0.05
0.00
0.30
0.20
SCALE: 2:1
SEE DETAIL 'A'
FRONT VIEW
1.40
1.20
0.10 C
BOTTOM VIEW
SCALE: 2:1
2 3 4 5 6 7 8 9 10 1112
15
16
16
1819
2122
22
22
22
23
24
25
26
17
23a
24a
8a
8a
24a
23a
0.00
0.00
0.65
13
1
14
16
17
20 18
22
12
15
27
2345 6 78 9 10 11
16
17
1819
2122
22
22
23
24
25
26
0.75
0.55(9X)
0.40
0.20(26X)
1.65
1.45
5.07
0.35
0.15(6X)
0.40
1.00
1.20
2.50
3.20
3.80
1.70
0.35
0.15
(4X)
6.10
6.45
2.75
3.25
4.53
6.45
6.10
5.60
4.90
4.45
4.05
2.65
2.25
1.20
0.80
1.00
0.60
2.05
2.25
2.85
3.90
4.75
5.80
0.45
1.15
1.55
1.85
4.50
5.05
5.60
5.85
6.45
4.60
5.80
6.45
0.25
1.35
4.75
5.28
5.55
0.15
0.20
0.30
2.50
2.75
2.90
4.40
5.95
21 20
4.70
20
21
5.80
6.08
LAND PATTERN
RECOMMENDATION
0.35
0.30
0.65
TYP
1.11 (9X)
0.35
0.35
TYP
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE IS NOT PRESENTLY
REGISTERED TO ANY STANDARD
COMMITTEE.
B) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING CONFORMS TO ASME Y14.5M-1994.
E) LAND PATTERN REFERENCE:
QFN65P1290X1290X140-40N-40N
F) DRAWING FILE NAME: MKT-PQFN27AREV3.
G) IT IS NOT NECESSARY TO SOLDER 23a AND
24a, AND CAN BE OMITTED FROM THE
FOOTPRINT
H) FAIRCHILD SEMICONDUCTOR
SCALE: 2:1
8a
27
22
20 18
17
16
15
14
1 1312
2122
22
22
23
24
25
26
1819
17
16
2 3 4 5 6 7 8 9 10 11
0.55
0.00
0.00
0.60
1.03
2.03
2.23
2.88
3.42
3.88
4.78
5.58
5.78
6.23
6.88
2.23
2.65
4.05
4.48
4.88
5.58
6.13
6.88
6.10
5.80
5.25
2.70
2.73
0.28
0.10
5.78
1.33
5.85
5.08
4.50
1.15
1.53
1.85
0.20
2.48
2.73
4.40
6.13
2.50
3.22
3.77
5.07
6.12
6.88
1.73
4.50
6.10
6.13
6.88
3.00
4.78
1.55
0.42
0.97
1.05
21 20
24a
23a
0.48
0.98 0.80
1.23
4.63
4.72
1.05
1.55 1.65
0.70
0.65
2.03
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changes at any time without notice to improve the design.
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Rev. I77
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