© Semiconductor Components Industries, LLC, 2017
October, 2018 − Rev. 1
1Publication Order Number:
FSA646/D
FSA646
2:1 MIPI D-PHY (2.5Gbps)
4-Data Lane & C-PHY
(2.5Gsps) 3-Data Lane
Switch
Description
The FSA646 is a four−data−lane D−PHY or three−data−lane
C−PHY, MIPI switch. This single−pole, double−throw (SPDT) switch
is optimized for switching between two high−speed or low−power
MIPI sources. The FSA646 is designed for the MIPI specification and
allows connection to a SCI or DSI module.
Features
•Switch Type: SPDT (10x)
•Signal Types:
♦MIPI, D−PHY & C−PHY
•VCC: 1.5 to 5.0 V
•Input Signals: 0 to 1.3 V
•RON:
♦6 W Typical HS MIPI
♦6 W Typical LP MIPI
•DRON: 0.1 W Typical LP & HS MIPI
•DRON_FLAT: 0.9 W Typical LP & HS MIPI
•ICCZ: 1 mA Maximum
•ICC: 32 mA Typical
•OIRR: −24 dB Typical
•Bandwidth: 4.1 GHz Typical
•Xtalk: −30 dB Typical
•CON: 1.5 pF Typical
•Skew (P), Skew (O): 6 ps Typical
•This is a Pb−Free Device
Applications
•Cellular Phones, Smart Phones
•Tablets
•Laptops
•Displays
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WLCSP36, 2.43x2.43x0.4
CASE 567WJ
See detailed ordering and shipping information on page 7 of
this data sheet.
ORDERING INFORMATION
MARKING DIAGRAM
GS = Specific Device Code
KK = Assembly Lot
X = Year
Y = Work Week
Z = Assembly Location
(Bottom View)
GSKK
XYZ
FSA646
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4
Table 1. BALL−TO−PIN MAPPINGS
Ball Pin Name Ball Pin Name Ball Pin Name
A1 VCC C1 DB3N E1 DB1N
A2 GND C2 DB3P E2 DB1P
A3 DA4N C3 NC E3 DA1N
A4 DA4P C4 NC E4 DA1P
A5 /OE C5 D3N E5 D1N
A6 SEL C6 D3P E6 D1P
B1 DB4N D1 DB2N F1 CLKBN
B2 DB4P D2 DB2P F2 CLKBP
B3 DA3N D3 DA2N F3 CLKAN
B4 DA3P D4 DA2P F4 CLKAP
B5 D4N D5 D2N F5 CLKN
B6 D4P D6 D2P F6 CLKP
TRUTH TABLE
SEL /OE Function
LOW LOW CLKP = CLKAP
, CLKN = CLKAN, Dn(P/N) = DAn(P/N)
HIGH LOW CLKP = CLKBP
, CLKN = CLKBN, Dn(P/N) = DBn(P/N)
X HIGH Clock and Data Ports High Impedance
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min. Max. Unit
VCC Supply Voltage −0.5 6.0 V
VCNTRL DC Input Voltage (/OE, SEL) (Note 1) −0.5 VCC V
VSW DC Switch I/O Voltage (Note 1,2) −0.3 1.8 V
IIK DC Input Diode Current −50 mA
IOUT DC Output Current 25 mA
TSTG Storage Temperature −65 +150 °C
ESD Human Body Model, JEDEC: JESD22−A114 All Pins 2.0 kV
Charged Device Model, JEDEC: JESD22−C101 1.0
IEC 61000−4−2 System Contact 8.0
Air Gap 15.0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.
2. VSW refers to analog data switch paths.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 1.5 5.0 V
VCNTRL Control Input Voltage (SEL, /OE) (Note 3) 0 VCC V
VSW Switch I/O Voltage
(CLKn, Dn, CLKAn, CLKBn, Dan, DBn)
−HS Mode 0 0.3 V
−LS Mode 0 1.3 V
TAOperating Temperature −40 +85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. The control inputs must be held HIGH or LOW; they must no float.
FSA646
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5
DC AND TRANSIENT CHARACTERISTICS (TA = 25°C unless otherwise specified)
Symbol Parameter Conditions VCC (V)
TA = −40 to +855C
Unit
Min. Typ. Max.
VIK Clamp Diode Voltage
(/OE, SEL)
IIN = −18 mA 1.5 −1.2 −0.6 V
VIH Input Voltage High SEL, /OE 1.5 to 5 1.3 V
VIL Input Voltage Low SEL, /OE 1.5 to 5 0.5 V
IIN Control Input Leakage
(/OE, SEL)
VCNTRL = 0 to VCC 5−0.5 0.5 mA
INO(OFF)
INC(OFF)
Off Leakage Current of
Port CLKAn, Dan, CLKBn
and DBn
VSW = 0.0 ≤DATA ≤ 1.3 V 5−0.5 0.5 mA
IA(ON) ON Leakage Current of
Common Ports (CLKn,
Dn)
VSW = 0.0 ≤DATA ≤ 1.3 V 5−0.5 0.5 mA
IOFF Power−Off Leakage
Current (All I/O Ports)
VSW = 0.0 or 1.3 V 0−0.5 0.5 mA
IOZ Off−State Leakage VSW = 0.0 ≤DATA ≤ 1.3 V
/OE = High
5−0.5 0.5 mA
RON_MIPI_HS Switch On Resistance for
HS MIPI Applications
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 0.2 V
1.5 6W
2.5
3.3
5
RON_MIPI_LP Switch On Resistance for
LP MIPI Applications
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 1.2 V
1.5 6W
2.5
3.3
5
DRON_MIPI_HS On Resistance Matching
Between HS MIPI
Channels
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 0.2 V
1.5 0.1 W
2.5
3.3
5
DRON_MIPI_LP On Resistance Matching
Between LP MIPI
Channels
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 1.2 V
1.5 0.1 W
2.5
3.3
5
RON_FLAT_MIPI_HS On Resistance Flatness
for HS MIPI Signals
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 0 to
0.3 V
1.5 0.9 W
2.5
3.3
5
RON_FLAT_MIPI_LP On Resistance Flatness
for LP MIPI Signals
(Note 4)
ION = −8 mA, /OE = 0 V,
SEL = VCC or 0 V, CLKA,
CLKB, DBN or DAN = 0 to
1.3 V
1.5 0.9 W
2.5
3.3
5
ICC Quiescent Supply Current
(Includes Change Pump)
VSEL = 0 or VCC, IOUT = 0,
/OE = 0 V
5 30 mA
FSA646
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DC AND TRANSIENT CHARACTERISTICS (TA = 25°C unless otherwise specified) (continued)
Symbol Unit
TA = −40 to +855C
VCC (V)ConditionsParameterSymbol Unit
Max.Typ.Min.
VCC (V)ConditionsParameter
ICCZ Quiescent Supply Current
(High Impedance)
VSEL = 0 or VCC, IOUT = 0,
/OE = 0 V
5 1 mA
ICCT Increase in ICC Current
Per Control Voltage and
VCC
VSEL = 0 or VCC, /OE = 1.5 V 5 1 mA
4. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltage on the two (A or B ports).
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3 V and TA = 25°C unless otherwise specified)
Symbol Parameter Conditions VCC (V)
TA = −40 to +855C
Unit
Min. Typ. Max.
tINIT Initialization Time VCC to
Output
(Note 5)
RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 60 ms
tEN Enable Time
/OE to Output
RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 60 150 ms
tDIS Disable Time
/OE to Output
RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 35 250 ns
tON Turn−On Time
SEL to Output
RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 350 1100 ns
tOFF Turn−Off Time
SEL to Output
RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 125 800 ns
tBBM Break−Before−Make Time RL = 50 W, CL = 0 pF,
VSW = 0.6 V
1.5 to 5 50 450 ns
tPD Propagation Delay
(Note 5)
CL = 0 pF, RL = 50 W1.5 to 5 30 67 100 ps
OIRR Off Isolation for MIPI
(Note 5)
RL = 50 W, f = 1250 MHz,
/OE = HIGH, VSW = 0.2 VPP
1.5 to 5 −24 dB
XTALK Crosstalk for MIPI
(Note 5)
RL = 50 W, f = 1250 MHz,
SEL = High, VSW = 0.2 VPP
1.5 to 5 −30 −25 dB
RL = 50 W, f = 1250 MHz,
SEL = Low, VSW = 0.2 VPP
−30 −25
BW −3 db Bandwidth (Note 5) RL = 50 W, CL = 0 pF,
VSW = 0.2 VPP
1.5 to 5 2.5 4.1 GHz
IL Insertion Loss at 750 MHz
(Note 5)
RL = 50 W, CL = 0 pF,
VSW = 0.2 VPP
1.5 to 5 −0.7 dB
5. Guaranteed by characterization.
HIGH−SPEED−RELATED AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions VCC (V)
TA = −40 to +855C
Unit
Min. Typ. Max.
tSK(P) HS Mode Skew of Oppo-
site Transitions of the
Same Output
(Note 6)
RL = 50 W, CL = 0 pF,
VSW = 0.3 V
1.5 to 5 6 ps
tSK(O) HS Mode Skew of
Channel−to−Channel
Single−Ended Skew
(Note 6)
RL = 50 W, CL = 0 pF,
VSW = 0.3 V
1.5 to 5 6 ps
6. Guaranteed by characterization.
FSA646
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CAPACITANCE
Symbol Parameter Conditions
TA = −40 to +855C
Unit
Min. Typ. Max.
CIN Control Pin Input
Capacitance (Note 7)
VCC = 0 V, f = 1 MHz 2.1 pF
CON On Capacitance (Note 7) VCC = 3.3 V, /OE = 0 V, f = 1250 MHz (in
HS common value)
1.5
COFF On Capacitance (Note 7) VCC and /OE = 3.3 V, f = 1250 MHz (both
sides in HS common value)
0.9
7. Guaranteed by characterization.
The table below pertains to the Packaging information on
the following page.
ORDERING INFORMATION
Part Number Top Marking Package Top Mark
FSA646UCX −40 to +85°C36−Ball WLCSP, Non−JEDEC
2.43 x 2.43 mm, 0.4 mm Pitch
GS
WLCSP36 2.43x2.43x0.488
CASE 567WJ
ISSUE A
DATE 03 OCT 2018
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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WLCSP36 2.43x2.43x0.488
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