Fiber Channel/Ethernet Clock Generator IC, 7 Clock Outputs AD9572 FEATURES Fully integrated dual VCO/PLL cores 0.228ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz 0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.428ps rms jitter from 12 kHz to 20 MHz at 125 MHz www.analog.com Fax: 781.461.3113 (c)2009-2011 Analog Devices, Inc. All rights reserved. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 AD9572* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. * AD9572 Material Declaration * PCN-PDN Information EVALUATION KITS * Quality And Reliability * AD9572 Evaluation Board * Symbols and Footprints DOCUMENTATION DISCUSSIONS Data Sheet View all AD9572 EngineerZone Discussions. * AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs Data Sheet SAMPLE AND BUY TOOLS AND SIMULATIONS * AD9571/AD9572 IBIS Model Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD9572 TABLE OF CONTENTS REVISION HISTORY /11--Rev. A to Rev. B 11/10--Rev. 0 to Rev. A 7/09--Revision 0: Initial Version Rev. B | Page 2 of 20 AD9572 SPECIFICATIONS PLL CHARACTERISTICS Table 1. Parameter PHASE NOISE CHARACTERISTICS PLL Noise (106.25 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (156.25 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (125 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (100 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (106.25 MHz LVPECL Output) At 1 kHz At 10 kHz Min Typ Max Unit Test Conditions/Comments -123 -127 -129 -150 -152 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -118 -125 -126 -145 -151 -151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -119 -127 -128 -147 -151 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -121 -128 -130 -147 -150 -150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -121 dBc/Hz At 30ID 12.4MCID 9/MCID 18 5. ( )Tj E1 33.33 MHz output disabled Rev. B | Page 3 of 20 AD9572 Parameter PLL Noise (125 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (100 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (33.33 MHz CMOS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz Phase Noise (25 MHz CMOS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz Spurious Content 1 PLL Figure of Merit 1 Min Typ Max Unit Test Conditions/Comments -122 -127 -128 -148 -152 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -122 -128 -130 -148 -150 -151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -130 -138 -139 -152 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -133 -142 -148 -148 -148 -70 -217.5 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc/Hz Dominant amplitude, all outputs active When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case -50 dBc spurious content might be presented on Pin 21 and Pin 22 only. LVDS CLOCK OUTPUT JITTER Table 2. Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz 100 MHz 0.51 106.25 MHz 0.44 125 MHz 33M = Off/On 1 0.42/0.88 1.875 MHz to 20 MHz 637 kHz to 10 MHz 200 kHz to 10 MHz 12 kHz to 35 MHz 1 156.25 MHz 0.42 Unit ps rms 0.19 ps rms 0.22 0.32 ps rms 0.25/0.78 ps rms 0.50 (off only) ps rms The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted. Rev. B | Page 4 of 20 Test Conditions/Comments LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 2 x 125 MHz, 2 x 106.25 MHz AD9572 LVPECL CLOCK OUTPUT JITTER Table 3. Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz (Typ) 100 MHz 0.61 106.25 MHz 0.45 12 kHz to 20 MHz (Max) 0.87 0.81 125 MHz 33M = Off/On 0.44/2.2 0.56 (off only) 1.875 MHz to 20 MHz (Typ) 637 kHz to 10 MHz (Typ) 200 kHz to 10 MHz (Typ) 0.23 0.38 12 kHz to 35 MHz (Typ) 12 kHz to 35 MHz (Max) 156.25 MHz 0.46 Unit ps rms 0.56 ps rms 0.28 ps rms ps rms 0.24/2.2 ps rms 0.52 (off only) 0.66 (off only) ps rms ps rms Test Conditions/Comments LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 156.25 MHz unterminated, 2 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 156.25 MHz unterminated, 2 x 125 MHz, 2 x 106.25 MHz CMOS CLOCK OUTPUT JITTER Table 4. Jitter Integration Bandwidth 12 kHz to 5 MHz (Typ) 12 kHz to 5 MHz (Max) 200 kHz to 5 MHz (Typ) 200 kHz to 5 MHz (Max) 25 MHz 0.78 1.1 0.76 1.0 33.3 MHz 0.41 N/A 0.52 N/A Unit ps rms ps rms ps rms ps rms Test Conditions/Comments Unit Test Conditions/Comments REFERENCE INPUT Table 5. Parameter CLOCK INPUT (REFCLK) Input Frequency Input High Voltage Input Low Voltage Input Current Input Capacitance Min Typ Max 25 2.0 0.8 +1.0 -1.0 2 Rev. B | Page 5 of 20 MHz V V A pF AD9572 CLOCK OUTPUTS Table 6. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) Duty Cycle LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Duty Cycle CMOS CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Duty Cycle Min Typ Max Unit VS - 1.24 VS - 2.07 700 45 VS - 1.05 VS - 1.87 825 156.25 VS - 0.83 VS - 1.62 950 55 MHz V V mV % 250 350 1.125 1.25 156.25 475 25 1.375 25 24 55 MHz mV mV V mV mA % 33.33 0.1 58 MHz V V % 14 45 VS - 0.1 42 Test Conditions/Comments Output shorted to GND Sourcing 1.0 mA current Sinking 1.0 mA current TIMING CHARACTERISTICS Table 7. Parameter LVPECL Min Typ Max Unit Output Rise Time, tRP Output Fall Time, tFP LVDS 480 480 625 625 810 810 ps ps Output Rise Time, tRL Output Fall Time, tFL CMOS Output Rise Time, tRC 160 160 350 350 540 540 ps ps 0.25 0.50 2.5 ns Output Fall Time, tFC 0.25 0.70 2.5 ns Output Rise Time, tRC2 1.3 2.1 2.6 ns Output Fall Time, tFC2 1.4 2.3 3.0 ns Rev. B | Page 6 of 20 Test Conditions/Comments Termination = 200 to 0 V; CLOAD = 0 pF; CAC = 100 nF; oscilloscope set to 50 termination 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 100 differential; CLOAD = 0 pF; CAC = 100 nF; oscilloscope set to 50 termination 20% to 80%, measured differentially 80% to 20%, measured differentially 20% to 80%; termination = 50 to 0 V; CLOAD = 5 pF; CAC = 100 nF 80% to 20%; termination = 50 to 0 V; CLOAD = 5 pF; CAC = 100 nF 20% to 80%; active probe measurement, Cprobe = 1 pF, Rprobe=20 k, CLOAD = 3.9 pF 80% to 20%; active probe measurement, Cprobe = 1 pF, Rprobe=20 k, CLOAD = 3.9 pF AD9572 CONTROL PINS Table 8. Parameter INPUT CHARACTERISTICS REFSEL Pin Logic 1 Voltage Logic 0 Voltage Min Typ Max Unit Test Conditions/Comments REFSEL has a 30 k pull-up resistor. 2.0 V 0.8 Rev. B | Page 7 of 20 AD9572 TIMING DIAGRAMS DIFFERENTIAL SINGLE-ENDED 80% 80% VOD CMOS 5pF LOAD 0% 20% 20% tFP tRC Figure 3. LVPECL Timing, Differential DIFFERENTIAL 80% VOD 0% 20% tFL 07498-023 LVDS tRL tFC Figure 5. CMOS Timing, Single-Ended, 5 pF Load Figure 4. LVDS Timing, Differential Rev. B | Page 8 of 20 07498-006 tRP 07498-022 LVPECL AD9572 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 11. Parameter VS to GND REFCLK to GND BYPASSx to GND XO to GND FREQSEL, FORCE_LOW, and REFSEL to GND 25M, 33M, 100M/125M, 106M, and 156M to GND Junction Temperature1 Storage Temperature Range 1 Rating -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V 150C -65C to +150C Table 12. Thermal Resistance Package Type 40-Lead LFCSP ESD CAUTION See Table 12 for JA. Rev. B | Page 9 of 20 JA 27.5 Unit C/W AD9572 40 39 38 37 36 35 34 33 32 31 VS VS * FORCE_LOW BYPASS1 VS GND VS 106M 106M PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9572 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 106M 106M VS FREQSEL VS VS VS 33M 100M/125M 100M/125M NOTES 1. * = SHORT TO PIN 36. 2. ** = SHORT TO PIN 14. 3. NC = NO CONNECT. 4. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND). 07498-007 VS ** ** BYPASS2 VS VS 156M 156M 100M/125M 100M/125M 11 12 13 14 15 16 17 18 19 20 GND 1 VS 2 NC 3 25M 4 VS 5 XO 6 XO 7 REFCLK 8 REFSEL 9 GND 10 Figure 6. Pin Configuration Table 13. Pin Function Descriptions 1 Pin No. 1, 10, 34 2 3 4 5 6, 7 8 9 11 12, 13 14, 36 15 16 17 18 19, 21 20, 22 Mnemonic GND VS NC 25M VS XO REFCLK REFSEL VS N/A BYPASS2, BYPASS1 VS VS 156M 156M 100M/125M 100M Description Ground. Includes external paddle (EPAD). Power Supply Connection for the 25M CMOS Buffer. No Connect. This pin should be left floating. CMOS 25 MHz Output. Power Supply Connection for the Crystal Oscillator. External 25 MHz Crystal. 25 MHz Reference Clock Input. Tie low when not in use. Logic Input. Used to select the reference source. Power Supply Connection for the GbE PLL. Short to Pin 14. These pins are for bypassing each LDO to ground with a 220 nF capacitor. Power Supply Connection for the GbE VCO. Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers. LVPECL/LVDS Output at 156.25 MHz. Complementary LVPECL/LVDS Output at 156.25 MHz. LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping. Rev. B | Page 10 of 20 AD9572 Pin No. 33 35 37 38 39 40 Description Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers. Power Supply Connection for the FC VCO. Forces the 33.33 MHz output into a low state. Short to Pin 36. Power Supply Connection for the FC PLL. Power Supply Connection for Miscellaneous Logic. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground (GND). 50 50 106M GND VS BYPASS1 FORCE_LOW CD RT = 100 106M 50 VS 106M 50 NC VS GND VS CD VS 0.22F CD VS 106M VS TEST VS CD VS VS VS CD = 100nF||10nF RT = 100 CD CD TO CMOS INPUT 50 VS CX = 22pF VS FREQSEL 25M VS VS CD CD AD9572 XO VS 25MHz XO VS CX = 22pF CD CD VS VS VS 50 REFCLK 33M REFSEL 100M/125M 50 GND 100M/125M 50 TO CMOS INPUT 100M/125M 100M/125M 50 50 VS RT = 100 RT = 100 Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 x 25 MHz, 1 x 156.25 MHz, 2 x 125 MHz, and 2 x 106.25 MHz Rev. B | Page 11 of 20 07498-024 VS 156M 0.22F VS 50 CD 156M VS VS CD 50 CD BYPASS2 TEST TEST RT = 100 VS 1 Mnemonic VS VS FORCE_LOW N/A VS VS AD9572 VS VS CD = 100nF||10nF CD VS VS VS 0.22F CD CD VS 127 127 83 83 50 CD 50 VS 106M 50 NC VS CD CD 50 VS CX = 22pF VS VS 127 127 83 83 FREQSEL 25M VS VS CD CD AD9572 XO VS 25MHz XO VS CX = 22pF CD CD 100M/125M 100M/125M VS CD 50 VS 50 VS VS VS TO CMOS INPUT 127 83 VS VS 127 83 VS 127 127 83 83 50 0.22F VS 156M 50 156M 100M/125M VS GND BYPASS2 50 TEST 100M/125M TEST REFSEL VS 33M CD VS 50 REFCLK CD VS 50 VS 83 127 83 127 VS Figure 8. Typical Application Schematic, LPECL Format Outputs, 1 x 25 MHz, 1 x 156.25 MHz, 2 x 125 MHz, and 2 x 106.25 MHz Rev. B | Page 12 of 20 07498-025 TO CMOS INPUT VS 106M 106M VS GND VS BYPASS1 106M GND VS FORCE_LOW TEST VS VS 50 AD9572 -100 -110 -110 PHASE NOISE (dBc/Hz) -100 -120 -130 -140 -160 1k -120 -130 -140 -150 10k 100k 1M FREQUENCY (Hz) 10M 100M Rev. B | Page 13 of 20 -160 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 07498-011 -150 07498-008 PHASE NOISE (dBc/Hz) TYPICAL PERFORMANCE CHARACTERISTICS 2ns/DIV 07498-027 200mV/DIV AD9572 Rev. B | Page 14 of 20 AD9572 TERMINOLOGY Phase Jitter Rev. B | Page 15 of 20 AD9572 THEORY OF OPERATION REFSEL BYPASS1 VS GND VS XTAL OSC REFCLK 1 0 DIVIDE BY 5 DIVIDE BY 4 DIVIDE BY 5 DIVIDE BY 3 AD9572 0 1 0 1 33.33MHz 33M CMOS FORCE_LOW Rev. B | Page 16 of 20 AD9572 Table 15. FREQSEL (Pin 27) Definition FREQSEL 0 1 NC Frequency Available from Pin 19 and Pin 20 (MHZ) 125 100 125 Frequency Available from Pin 21 and Pin 22 (MHZ) 125 100 100 3.5mA OUT 07498-014 0 OUTB 3.5mA Figure 18. LVDS Output Simplified Equivalent Circuit 3.3V OUT GND 07498-015 OUTB Figure 19. LVPECL Output Simplified Equivalent Circuit Table 16. FORCE_LOW (Pin 37) Definition FORCE_LOW 0 or NC 1 33.33 MHz Output (Pin 23) 33.33 MHz 0 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP Rev. B | Page 17 of 20 AD9572 VPULLUP = 3.3V CMOS 10 100 50 5pF 07498-018 100 Figure 21. CMOS Output with Far-End Termination LVPECL CLOCK DISTRIBUTION 3.3V 3.3V 127 127 3.3V 50 LVPECL SINGLE-ENDED (NOT COUPLED) LVPECL 50 83 83 07498-029 VT = VCC - 2.0V VCC = 3.3V Figure 22. LVPECL Far-End Termination 50 LVPECL LVPECL 50 50 50 07498-030 50 Rev. B | Page 18 of 20 AD9572 Table 17. REFSEL (Pin 9) Definition REFSEL 0 1 Reference Source REFCLK input Internal crystal oscillator POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION Rev. B | Page 19 of 20 AD9572 OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 4.60 SQ 4.50 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE *4.70 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 02-02-2010-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm x 6 mm Body, Very Very Thin Quad (CP-40-7) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD9572ACPZLVD AD9572ACPZLVD-RL Temperature Range -40C to +85C -40C to +85C AD9572ACPZLVD-R7 -40C to +85C AD9572ACPZPEC AD9572ACPZPEC-RL -40C to +85C -40C to +85C AD9572ACPZPEC-R7 -40C to +85C AD9572-EVALZ-LVD AD9572-EVALZ-PEC Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 13" Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape and Reel, 750 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 13" Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape and Reel, 750 Pieces Evaluation Board Evaluation Board 1 Z = RoHS Compliant Part. LVD indicates LVDS-compliant, differential clock outputs. 3 PEC indicates LVPECL-compliant, differential clock outputs. 2 (c)2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07498-0-4/11(B) Rev. B | Page 20 of 20 Package Option CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7