LTC3896
1
3896f
For more information www.linear.com/LTC3896
Typical applicaTion
FeaTures DescripTion
150V Low IQ, Synchronous
Inverting DC/DC Controller
The LT C
®
3896 is a high performance inverting DC/DC
switching regulator controller that drives an all N-channel
synchronous power MOSFET stage. It converts a wide-
ranging positive input voltage source to a regulated negative
output that can be as much as 60V below ground. The
input can operate from a voltage as low as 4V and as high
as 140V – |VOUT–|.
The LTC3896 contains true ground-referenced RUN, PLLIN
and PGOOD pins, eliminating the need for external discrete
level-shifting components to interface with the LTC3896.
A constant frequency current mode architecture allows a
phase-lockable frequency of up to 850kHz. The low 40μA
no-load quiescent current extends operating run time in
battery-powered systems. OPTI-LOOP
®
compensation
allows the transient response to be optimized over a
wide range of output capacitance and ESR values. The
LTC3896 features a precision 0.8V reference and power
good output indicator. The soft-start (SS) pin ramps the
output voltage during start-up.
High Efficiency 36V–72V to –48V/2A Inverting Regulator
applicaTions
n Wide VIN + |VOUT–| Range: 4V to 140V (150V Abs Max)
n Wide Output Voltage Range: –60V to –0.8V
n Ground-Referenced Control / Interface Pins
n Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
n Integrated Bootstrap Diode
n Low Operating IQ: 40μA (Shutdown = 10μA)
n Selectable Gate Drive UVLO Thresholds
n Onboard LDO or External NMOS LDO for DRVCC
n EXTVCC LDO Powers Drivers from Output
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode
®
Operation at Light Loads
n Adjustable Burst Clamp and Current Limit
n Power Good Output Voltage Monitor
n Programmable Input Overvoltage Lockout
n 38-Lead TSSOP High Voltage Package
n Automotive and Industrial Power Systems
n Telecommunications Power Supplies
n Distributed Power Systems
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,
6144194, 6177787, 6580258.
Efficiency and Power Loss
vs Load Current
0.1µF
4.7µF
10mΩ
0.1µF
0.1µF
4.99k
15nF
47µF
47µH
10k
590k
100k
301k
100pF
V
IN
INTV
CC
DRVSET
DRVUV
ITH
SS
V
OUT
–
LTC3896
TG
SW
BG
SENSE+
SENSE–
V
FB
BOOST
NDRV
DRV
CC
V
IN
36V to 72V
V
OUT
–
–48V
2A
RUN
PLLIN
0V
PGOOD
5V
0V
FREQ
GND
4.7µF
100V
2220
×4
0.1µF
×3
3896 TA01a
V
IN
= +48V
V
OUT
–
= –48V
EFFICIENCY
POWER LOSS
FIGURE 16 CIRCUIT
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
10
100
1k
10k
100k
EFFICIENCY (%)
POWER LOSS (mW)
3896 TA01b
LTC3896
2
3896f
For more information www.linear.com/LTC3896
pin conFiguraTionabsoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ....................... –0.3V to 150V
Top Side Driver Voltage BOOST .............. –0.3V to 150V
Switch Voltage (SW) ................................. –5V to 150V
DRVCC, (BOOST – SW) Voltages ................ –0.3V to 11V
BG, TG ............................................................... (Note 8)
GND Voltage .............................................. –0.3V to 65V
RUN Voltage................................... (GND–0.3V) to 150V
(PLLIN – GND) Voltage ................................ –0.3V to 6V
(PGOOD – GND) Voltage .............................. –0.3V to 6V
SENSE+, SENSE– Voltages ......................... –0.3V to 65V
MODE, DRVUV Voltages .............................. –0.3V to 6V
ILIM, VPRG, FREQ, PHASMD Voltages ........ –0.3V to 6V
DRVSET Voltage .......................................... –0.3V to 6V
NDRV ................................................................. (Note 9)
EXTVCC Voltage ......................................... –0.3V to 14V
ITH, VFB Voltages ........................................ –0.3V to 6V
SS, OVLO Voltages ..................................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3896E, LTC3896I ........................ –40°C to 125°C
LTC3896H ......................................... –40°C to 150°C
Storage Temperature Range ................. –65°C to 150°C
All pins with respect to VOUT– unless otherwise noted (Note 1).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
34
32
30
28
26
24
22
21
20
OVLO
VPRG
SENSE+
SENSE–
SS
VFB
ITH
MODE
VOUT–
VOUT–
CLKOUT
GND
PLLIN
PGOOD
VOUT–
NC
FREQ
DRVSET
DRVUV
INTVCC
ILIM
PHASMD
RUN
EXTVCC
VIN
NDRV
DRVCC
BG
BOOST
SW
TG
39
VOUT–
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 39) IS VOUT–, MUST BE SOLDERED TO PCB
FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3896EFE#PBF LTC3896EFE#TRPBF LTC3896FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3896IFE#PBF LTC3896IFE#TRPBF LTC3896FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3896HFE#PBF LTC3896HFE#TRPBF LTC3896FE 38-Lead Plastic TSSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
http://www.linear.com/product/LTC3896#orderinfo
LTC3896
3
3896f
For more information www.linear.com/LTC3896
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V with respect to GND, EXTVCC =
0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted. All pin voltages with respect to VOUT–, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range
(VIN + |VOUT–|)
(Note 10) DRVUV = VOUT–4 140 V
VOUT–Regulated Output Voltage Set Point VIN + |VOUT–| ≤ 140V –60 –0.8 V
VFB Regulated Feedback Voltage (Note 4); ITH Voltage = 1.2V
0°C to 85°C, VPRG = FLOAT
VPRG = FLOAT
VPRG = VOUT–
VPRG = INTVCC
l
l
l
0.792
0.788
3.220
4.875
0.800
0.800
3.300
5.000
0.808
0.812
3.380
5.125
V
V
V
V
IFB Feedback Current (Note 4)
VPRG = FLOAT
VPRG = VOUT– or INTVCC
–0.006
4
±0.050
6
µA
µA
Reference Voltage Line Regulation (Note 4) VIN = 4.5V to 150V 0.002 0.02 %/V
Output Voltage Load Regulation (Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
(Note 4) Measured in Servo Loop, ∆ITH
Voltage = 1.2V to 1.6V
l–0.01 –0.1 %
gmTransconductance Amplifier gm(Note 4) ITH = 1.2V, Sink/Source 5µA 2.2 mmho
IQInput DC Supply Current (Note 5) VDRVSET = VOUT–
Pulse-Skipping or Forced Continuous Mode VFB = 0.83V (No Load) 2.5 mA
Sleep Mode VFB = 0.83V (No Load) 40 55 µA
Shutdown RUN = 0V with Respect to GND 10 20 µA
UVLO Undervoltage Lockout DRVCC Ramping Up
DRVUV = VOUT–
DRVUV = INTVCC, DRVSET = INTVCC
l
l
4.0
7.5
4.2
7.8
V
V
DRVCC Ramping Down
DRVUV = VOUT–
DRVUV = INTVCC, DRVSET = INTVCC
l
l
3.6
6.4
3.8
6.7
4.0
7.0
V
V
VRUN ON RUN Pin ON Threshold VRUN Rising with Respect to GND l1.1 1.2 1.3 V
VRUN Hyst RUN Pin Hysteresis 80 mV
OVLO Overvoltage Lockout Threshold VOVLO Rising with Respect to VOUT–l1.1 1.2 1.3 V
OVLO Hyst OVLO Hysteresis 100 mV
OVLO Delay 1 µs
Feedback Overvoltage Protection Measured at VFB, Relative to Regulated VFB 7 10 13 %
ISENSE+SENSE+ Pin Current ±1 µA
ISENSE–SENSE– Pin Current SENSE– < VINTVCC – 0.5V
SENSE– > VINTVCC + 0.5V
850
±1 µA
µA
Maximum Duty Factor FREQ = VOUT–98 99 %
ISS Soft-Start Charge Current VSS = 0V 8 10 12 µA
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V
ILIM = FLOAT
ILIM = VOUT–
ILIM = INTVCC
l
l
l
66
43
90
75
50
100
84
57
109
mV
mV
mV
Gate Driver
TG Pull-Up On-Resistance
TG Pull-Down On-Resistance
VDRVSET = INTVCC 2.2
1.0
Ω
Ω
LTC3896
4
3896f
For more information www.linear.com/LTC3896
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V with respect to GND, EXTVCC =
0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted. All pin voltages with respect to VOUT–, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
BG Pull-Up On-Resistance
BG Pull-Down On-Resistance
VDRVSET = INTVCC 2.0
1.0
Ω
Ω
BOOST to DRVCC Switch On-Resistance VSW = 0V, VDRVSET = INTVCC 11 Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF each driver, VDRVSET = INTVCC 55 ns
Bottom Gate Off to Top Gate On Delay Top
Switch-On Delay Time
CLOAD = 3300pF each driver, VDRVSET = INTVCC 50 ns
tON(MIN) TG Minimum On-Time (Note 7) VDRVSET = INTVCC 80 ns
DRVCC LDO Regulator
DRVCC Voltage from NDRV LDO Regulator NDRV Driving External NFET, VEXTVCC = 0V
7V < VIN < 150V, DRVSET = VOUT–
11V < VIN < 150V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
DRVCC Load Regulation from NDRV LDO
Regulator
NDRV Driving External NFET
ICC = 0mA to 50mA, VEXTVCC = 0V
0
1.0
%
DRVCC Voltage from Internal VIN LDO NDRV = DRVCC (NDRV LDO Off), VEXTVCC = 0V
7V < VIN < 150V, DRVSET = VOUT–
11V < VIN < 150V, DRVSET = INTVCC
5.6
9.5
5.85
9.85
6.1
10.3
V
V
DRVCC Load Regulation from VIN LDO ICC = 0mA to 50mA, VEXTVCC = 0V
DRVSET = VOUT
DRVSET = INTVCC
1.4
0.9
2.5
2.0
%
%
DRVCC Voltage from Internal EXTVCC LDO 7V < VEXTVCC < 13V, DRVSET = VOUT–
11V < VEXTVCC < 13V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA
DRVSET = VOUT–, VEXTVCC = 8.5V
DRVSET = INTVCC, VEXTVCC = 13V
0.7
0.5
2.0
2.0
%
%
EXTVCC LDO Switchover Voltage EXTVCC Ramping Positive
DRVUV = VOUT–
DRVUV = INTVCC, DRVSET = INTVCC
4.5
7.4
4.7
7.7
4.9
8.0
V
V
EXTVCC Hysteresis 250 mV
Programmable DRVCC RDRVSET = 50kΩ, NDRV Driving External NFET,
VEXTVCC = 0V
5.0 V
Programmable DRVCC RDRVSET = 70kΩ, NDRV Driving External NFET,
VEXTVCC = 0V
6.4 7.0 7.6 V
Programmable DRVCC RDRVSET = 90kΩ, NDRV Driving External NFET,
VEXTVCC = 0V
9.0 V
INTVCC LDO Regulator
VINTVCC INTVCC Voltage ICC = 0mA to 2mA 4.7 5.0 5.2 V
Oscillator and Phase-Locked Loop
Programmable Frequency RFREQ = 25kΩ, PLLIN = DC Voltage 105 kHz
Programmable Frequency RFREQ = 65kΩ, PLLIN = DC Voltage 375 440 505 kHz
Programmable Frequency RFREQ = 105kΩ, PLLIN = DC Voltage 835 kHz
LTC3896
5
3896f
For more information www.linear.com/LTC3896
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Low Fixed Frequency VFREQ = VOUT–, PLLIN = DC Voltage 320 350 380 kHz
High Fixed Frequency VFREQ = INTVCC, PLLIN = DC Voltage 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN = External Clock l75 850 kHz
PLLIN Input High Level
PLLIN Input Low Level
PLLIN = External Clock with Respect to GND
PLLIN = External Clock with Respect to GND
l
l
2.8
0.5
V
V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA, VPGL with Respect to GND 0.02 0.04 V
IPGOOD PGOOD Leakage Current VPGOOD = 3.3V 10 µA
PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
Hysteresis
–13
–10
2.5
–7
%
%
VFB with Respect to Set Regulated Voltage
VFB Ramping Positive
Hysteresis
7
10
2.5
13
%
%
Delay for Reporting a Fault 40 µs
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V with respect to VOUT–, EXTVCC =
0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted. All pin voltages with respect to VOUT–, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3896 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3896E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3896I is guaranteed over the
–40°C to 125°C operating junction temperature range and the LTC3896H
is guaranteed over the –40°C to 150°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. High temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. The junction temperature (TJ, in °C) is calculated from the
ambient temperature (TA, in °C) and power dissipation (PD, in Watts)
according to the formula:
TJ = TA + (PD • θJA)
where θJA = 28°C/W for the TSSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3896 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB. The specification at 85°C
is not tested in production and is assured by design, characterization and
correlation to production testing at other temperatures (125°C for the
LTC3896E and LTC3896I, 150°C for the LTC3896H). For the LTC3896I
and LTC3896H, the specification at 0°C is note tested in production and is
assured by design, characterization and correlation to production testing
at –40°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 9: Do not apply a voltage or current source to the NDRV pin, other
than tying NDRV to DRVCC when not used. If used it must be connected
to capacitive loads only (see DRVCC Regulators (OPTI-DRIVE) in the
Applications Information section), otherwise permanent damage may
occur.
Note 10: The minimum input supply (VIN + |VOUT–|) operating range is
dependent on the DRVCC UVLO thresholds as determined by the DRVUV
pin setting.
LTC3896
6
3896f
For more information www.linear.com/LTC3896
Typical perForMance characTerisTics
Load Step Burst Mode Operation Load Step Pulse-Skipping Mode
Load Step Forced Continuous
Mode
Inductor Current at Light Load Soft Start-Up
Regulated Feedback Voltage vs
Temperature
Efficiency and Power Loss vs
Load Current Efficiency vs Load Current Efficiency vs Input Voltage
VIN and VOUT– with respect to GND. All other voltages with respect to VOUT–, unless otherwise noted.
BURST EFFICIENCY
V
IN
= +48V
V
OUT
–
= –48V
PS LOSS
PS EFFICIENCY
FCM LOSS
FCM EFFICIENCY
BURST LOSS
FIGURE 16 CIRCUIT
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
10
100
1k
10k
100k
EFFICIENCY (%)
POWER LOSS (mW)
3896 G01
V
OUT
–
= –48V
FIGURE 16 CIRCUIT
V
IN
= 36V
V
IN
= 48V
V
IN
= 72V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3896 G02
V
OUT
–
= –48V
I
LOAD
= 1.5A
FIGURE 16 CIRCUIT
INPUT VOLTAGE (V)
35
40
45
50
55
60
65
70
75
80
82
84
86
88
90
92
94
96
98
100
EFFICIENCY (%)
3896 G03
200µs/DIV
VOUT–
100mV/DIV
AC-COUPLED
IL
1A/DIV
3896 G04
VOUT– = –48V
LOAD STEP = 0A to 1A
FIGURE 16 CIRCUIT
200µs/DIV
VOUT– = –48V
LOAD STEP = 0A to 1A
FIGURE 16 CIRCUIT
VOUT–
100mV/DIV
AC-COUPLED
IL
1A/DIV
3896 G05
200µs/DIV
VOUT– = –48V
LOAD STEP = 0A to 1A
FIGURE 16 CIRCUIT
VOUT–
100mV/DIV
AC-COUPLED
IL
1A/DIV
3896 G06
10µs/DIV
VOUT– = –48V
ILOAD = 1mA
FIGURE 16 CIRCUIT
FORCED
CONTINUOUS
MODE
BURST MODE
OPERATION
2A/DIV
PULSE-
SKIPPING
MODE
3896 G07
1ms/DIV
VOUT– = –48V
FIGURE 16 CIRCUIT
GND
GND
3896 G08
RUN
2V/DIV
VOUT–
20V/DIV
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
792
794
796
798
800
802
804
806
808
REGULATED FEEDBACK VOLTAGE (V)
3896 G09
LTC3896
7
3896f
For more information www.linear.com/LTC3896
Typical perForMance characTerisTics
SENSE– Pins Input Current vs
VSENSE Voltage
SENSE– Pin Input Bias Current vs
Temperature
Undervoltage Lockout Threshold
vs Temperature
Foldback Current Limit
Maximum Current Sense
Threshold vs ITH Voltage RUN Threshold vs Temperature
DRVCC vs Load Current
EXTVCC Switchover and DRVCC
Voltages vs Temperature
EXTVCC Switchover and DRVCC
Voltages vs Temperature
VIN and VOUT– with respect to GND. All other voltages with respect to VOUT–, unless otherwise noted.
EXTV
CC
= 5V
V
IN
LDO (No NDRV FET),
EXTV
CC
= 0V
NDRV LDO (NDRV FET),
EXTVCC = 0V
EXTV
CC
= 8.5V
DRVUV = DRVSET = 0V
LOAD CURRENT (mA)
0
20
40
60
80
100
4.0
4.5
5.0
5.5
6.0
6.5
DRV
CC
VOLTAGE (V)
3896 G10
DRVUV = DRVSET = 0V
EXTV
CC
RISING
EXTV
CC
FALLING
EXTV
CC
= 8.5V
NDRV LDO (NDRV FET)
EXTV
CC
= 0V
V
IN
LDO (No NDRV FET)
EXTV
CC
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
4.0
4.5
5.0
5.5
6.0
6.5
DRV
CC
VOLTAGE (V)
3896 G11
DRVUV = DRVSET = INTV
CC
EXTV
CC
RISING
EXTV
CC
FALLING
EXTV
CC
= 8.5V
NDRV LDO (NDRV NFET)
EXTV
CC
= 0V
V
IN
LDO (No NDRV NFET)
EXTV
CC
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
DRV
CC
VOLTAGE (V)
3896 G12
V
SENSE
COMMON MODE VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
100
200
300
400
500
600
700
800
900
1000
SENSE
–
CURRENT (µA)
3896 G13
V
OUT
≥ INTV
CC
+ 0.5V
V
OUT
≤ INTV
CC
– 0.5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
SENSE
–
CURRENT (µA)
3896 G14
RISING
RISING
FALLING
FALLING
DRVUV = INTV
CC
DRVUV = 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
DRV
CC
VOLTAGE (V)
3896 G15
FEEDBACK VOLTAGE (mV)
0
100
200
300
400
500
600
700
800
0
10
20
30
40
50
60
70
80
90
100
MAXIMUM CURRENT SENSE VOLTAGE (mV)
3896 G16
ILIM = FLOAT
ILIM = GND
ILIM = INTVCC
5% DUTY CYCLE
PULSE–SKIPPING
Burst Mode
OPERATION
FORCED CONTINUOUS
V
ITH
(V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40
–20
0
20
40
60
80
100
CURRENT SENSE VOLTAGE (mV)
3896 G17
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
RUN RISING
RUN FALLING
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
RUN PIN VOLTAGE REFERENCED TO GND (V)
3896 G18
LTC3896
8
3896f
For more information www.linear.com/LTC3896
Typical perForMance characTerisTics
Quiescent Current vs Temperature
Oscillator Frequency vs
Temperature
SS Pull-Up Current vs
Temperature OVLO Threshold vs Temperature
DRVCC Line Regulation Shutdown Current vs Temperature
Shutdown Current vs Input
Voltage
VIN and VOUT– with respect to GND. All other voltages with respect to VOUT–, unless otherwise noted.
DRVSET = INTV
CC
DRVSET = 0V
No NDRV FET
EXTV
CC
= 0V
NDRV FET
INPUT VOLTAGE (V)
0
15
30
45
60
75
90
105
120
135
150
5
6
7
8
9
10
11
DRV
CC
VOLTAGE (V)
3896 G19
V
IN
= 12V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
18
20
SHUTDOWN CURRENT (µA)
3896 G20
V
IN
= 6.3V
INPUT VOLTAGE (V)
0
15
30
45
60
75
90
105
120
135
150
0
5
10
15
20
25
30
SHUTDOWN CURRENT (µA)
3896 G21
V
IN
– V
OUT
–
= 12V
Burst Mode OPERATION
DRVSET = 70kΩ
DRVSET = 0V
DRVSET = INTV
CC
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
70
80
90
100
QUIESCENT CURRENT (µA)
3896 G22
FREQ = 0V
FREQ = INTV
CC
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
300
350
400
450
500
550
600
FREQUENCY (kHz)
3896 G23
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
SS CURRENT (µA)
3896 G24
OVLO RISING
OVLO FALLING
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
OVLO PIN VOLTAGE REFERENCED TO V
OUT
-
(V)
3896 G25
LTC3896
9
3896f
For more information www.linear.com/LTC3896
pin FuncTions
OVLO (Pin 1): Overvoltage Lockout Input. A voltage on this
pin above 1.2V with respect to VOUT– disables switching
of the controller. The DRVCC and INTVCC supplies maintain
regulation during an OVLO event. Exceeding the OVLO
threshold triggers a soft-start reset. If the OVLO function
is not used, connect this pin to VOUT–.
VPRG (Pin 2): Output Voltage Control Pin. This pin sets
the regulator in adjustable output mode using external
feedback resistors or fixed –5V/–3.3V output mode.
Floating this pin allows the output to be programmed from
–0.8V to –60V with an external resistor divider on the VFB
pin, regulating VFB to 0.8V with respect to VOUT–. Tying
this pin to INTVCC or VOUT– programs the output to –5V or
–3.3V, respectively, through an internal resistor divider on
VFB. In fixed –5V/–3.3V output mode, VFB should connect
to GND, which is the positive terminal of the output.
SENSE+ (Pin 3): The (+) Input to the Differential Current
Comparator. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins in conjunction with
RSENSE set the current trip threshold.
SENSE– (Pin 4): The (–) Input to the Differential Current
Comparator. When SENSE– is greater than INTVCC, the
SENSE– pin supplies power to the current comparator.
SS (Pin 5): Soft-Start Input. The LTC3896 regulates the
VFB voltage with respect to VOUT– to the smaller of 0.8V or
the voltage on the SS pin. An internal 10μA pull-up current
source is connected to this pin. A capacitor to VOUT– at this
pin sets the ramp time to final regulated output voltage. The
SS pin is also used for the Regulator Shutdown (REGSD)
feature. A 5μA/1μA pull-down current can be connected
on SS depending on the state of the EXTVCC LDO and
the voltage on SS. See Regulator Shutdown (REGSD)
section in the Operation section for more information.
To defeat the REGSD feature, place a 330kΩ or smaller
resistor between INTVCC and SS. See Soft-Start Pin in the
Applications Information section for more information on
defeating REGSD.
VFB (Pin 6): Feedback Input. If the VPRG pin is floating,
the VFB pin receives the remotely sensed feedback voltage
from an external resistor divider across the output. If VPRG
is tied to VOUT– or INTVCC, the VFB pin should connect to
the GND pin.
ITH (Pin 7): Error Amplifier Output and Switching Regulator
Compensation Point. The current comparator trip point
increases with this control voltage.
MODE (Pin 8): Mode Select and Burst Clamp Adjust
Input. This input determines how the LTC3896 operates
at light loads. Pulling this pin to VOUT– selects Burst
Mode operation with the burst clamp level defaulting to
25% of VSENSE(MAX). Tying this pin to a voltage between
0.5V and 1.0V with respect to VOUT– selects Burst Mode
operation and adjusts the burst clamp between 10% and
60%. Tying this pin to INTVCC forces continuous inductor
current operation. Tying this pin to a voltage greater than
1.4V and less than INTVCC–1.3V (with respect to VOUT–)
selects pulse-skipping operation.
VOUT– (Pins 9, 15, Exposed Pin 39): Negative Terminal of
Output Voltage. This serves as a virtual ground return for
most of the LTC3896’s circuits. Most pins and components
are referenced to VOUT–, which can operate at up to 60V
(65V Abs Max) below the GND pin. The exposed pad must
be soldered to the PCB for rated electrical and thermal
performance.
VOUT– (Pin 10): This pin must be externally tied to the other
VOUT– pins (Pin 9, e.g.) but is not internally electrically
connected to them.
CLKOUT (Pin 11): Output Clock Signal. This signal is
available to daisy-chain other controller ICs for additional
MOSFET driver stages/phases. The output levels swing
from INTVCC to VOUT–.
GND (Pin 12): Ground. This pin should be externally tied
to the true ground (e.g., ground terminal of the positive
input supply connected to VIN). The RUN, PLLIN, and
PGOOD pins are referenced to this GND pin.
LTC3896
10
3896f
For more information www.linear.com/LTC3896
pin FuncTions
PLLIN (Pin 13): External Synchronization Input to Phase
Detector. When an external clock is applied to this pin,
the phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. If
the MODE pin is set to Forced Continuous Mode or Burst
Mode operation, then the regulator operates in Forced
Continuous Mode when synchronized. If the MODE pin is
set to pulse-skipping mode, then the regulator operates
in pulse-skipping mode when synchronized. The PLLIN
pin is referenced to the GND pin, allowing the LTC3896
to be used with a true ground-referenced external clock
source with no level shifters needed.
PGOOD (Pin 14): Open-Drain Logic Output. PGOOD is
pulled to GND when the voltage on the VFB pin is not within
±10% of its set point. PGOOD is referenced to GND to
allow it to interface with external true ground-referenced
components with no level shifters needed.
NC (Pin 16): No connect. Float this pin or connect to GND
or VOUT–.
FREQ (Pin 17): Frequency Control Pin for the Internal
VCO. Connecting the pin to VOUT– forces the VCO to
a fixed low frequency of 350kHz. Connecting the pin
to INTVCC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz
can be programmed by using a resistor between FREQ
and VOUT–. An internal 20µA pull-up current develops the
voltage to be used by the VCO to control the frequency.
DRVSET (Pin 18): DRVCC Regulation Program Pin. This
pin sets the regulated output voltage of the DRVCC linear
regulator. Tying this pin to VOUT– sets DRVCC to 6.0V.
Tying this pin to INTVCC sets DRVCC to 10V. Other voltages
between 5V and 10V can be programmed by placing a
resistor (50k to 100k) between the DRVSET pin and VOUT–.
An internal 20µA pull-up current develops the voltage to
be used as the reference to the DRVCC LDO.
DRVUV (Pin 19): DRVCC UVLO Program Pin. This
pin determines the higher or lower DRVCC UVLO and
EXTVCC switchover thresholds, as listed on the Electrical
Characteristics table. Connecting DRVUV to VOUT– chooses
the lower thresholds whereas tying DRVUV to INTVCC
chooses the higher thresholds. Do not float this pin.
TG (Pin 20): High Current Gate Drives for Top N-Channel
MOSFET. This is the output of floating high side driver
with a voltage swing equal to DRVCC superimposed on
the switch node voltage SW.
SW (Pin 21): Switch Node Connection to Inductor.
BOOST (Pin 22): Bootstrapped Supply to the Topside
Floating Driver. A capacitor is connected between the
BOOST and SW pins. Voltage swing at the BOOST pin is
from approximately DRVCC to (VIN + DRVCC).
BG (Pin 24): High Current Gate Drive for Bottom
(Synchronous) N-Channel MOSFET. Voltage swing at this
pin is from VOUT– to DRVCC.
DRVCC (Pin 26): Output of the Internal or External Low
Dropout Regulators. The gate drivers are powered from this
voltage source. The DRVCC voltage is set by the DRVSET
pin. Must be decoupled to VOUT– with a minimum of 4.7µF
ceramic or other low ESR capacitor, as close as possible
to the IC. Do not use the DRVCC pin for any other purpose.
NDRV (Pin 28): Drive Output for External Pass Device of
the NDRV LDO Linear Regulator for DRVCC. Connect this
pin to the gate of an external NMOS pass device. To disable
this external NDRV LDO, tie NDRV to DRVCC.
VIN (Pin 30): Main Supply Pin. A bypass capacitor should
be tied between this pin and the GND pin. An additional
bypass capacitor between the VIN and VOUT– pins is
recommended.
EXTVCC (Pin 32): External Power Input to an Internal LDO
linear regulator Connected to DRVCC. This LDO supplies
DRVCC power from EXTVCC, bypassing the internal LDO
powered from VIN or the external NDRV LDO whenever
EXTVCC is higher than its switchover threshold (4.7V or
7.7V referenced to VOUT– depending on the DRVUV pin).
See the EXTVCC Connection section in the Applications
Information section. Do not exceed 14V with respect to
VOUT– on this pin. Do not connect EXTVCC to a voltage
greater than VIN. Connect to VOUT– if not used.
LTC3896
11
3896f
For more information www.linear.com/LTC3896
pin FuncTions
RUN (Pin 34): Run Control Input. Forcing this pin below
1.12V (with respect to GND) shuts down the controller.
Forcing this pin below 0.7V shuts down the entire LTC3896,
reducing quiescent current to approximately 10µA. The
RUN pin is referenced to the GND pin, allowing the LTC3896
to be used with a true ground-referenced external signal
or logic with no level shifters needed. This pin can be tied
to VIN for always-on operation. Do not float this pin.
PHASMD (Pin 36): Control Input to Phase Selector. This
pin determines the CLKOUT phase relationships with
respect to TG. Pulling this pin to VOUT– forces CLKOUT to
be out of phase 90° with respect to TG. Connecting this
pin to INTVCC forces CLKOUT to be out-of-phase 120°
with respect to TG. Floating this pin forces CLKOUT to be
out of phase 180° with respect to TG.
ILIM (Pin 37): Current Comparator Sense Voltage Range
Input. Tying this pin to VOUT– or INTVCC or floating it sets
the maximum current sense threshold to one of three
different levels (50mV, 100mV, and 75mV, respectively).
INTVCC (Pin 38): Output of the Internal 5V (referenced to
VOUT–) Low Dropout Regulator. CLKOUT and many of the
low voltage analog and digital circuits are powered from
this voltage source. A low ESR 0.1µF ceramic bypass
capacitor should be connected between INTVCC and VOUT–,
as close as possible to the IC.
LTC3896
12
3896f
For more information www.linear.com/LTC3896
block DiagraM
20µA
10µA
3V
5µA/1µA
2mV
R2
4R
R
100k
15M
R1
R
A
R
B
C
C2
C
C1
R
C
CB
L
C
OUT
R
SENSE
C
SS
20µA
C
INB
C
INA
PGOOD
EA–
0.88V
0.72V
OVLO
RUN
GND + 1.2V
CLKOUT
PHASMD
VCO
FREQ
PFD
PLLIN
ILIM
DRVSET
V
IN
NDRV
DRV
CC
SS
ITH
V
FB
VPRG
SENSE
–
SENSE
+
BG
SW
TG
BOOST
CURRENT
LIMIT
SYNC
DET
CHARGE
PUMP
DRV
CC
LDO/UVLO
CONTROL
INTV
CC
EXTV
CC
DRVUV
INTV
CC
LDO
4.7V/
7.7V
MODE
NDRV LDO
V
IN
LDO
EXTV
CC
LDO
3.5V
DROPOUT
DETECT
SWITCH
LOGIC
DRV
CC
DRV
CC
TOP
BOT
BOT
TOP ON
Q
S
R
EA
ICMP
IR
SLEEP
0.88V
REGSD
CLK
SHDN
1.8V
0.425V
SLOPE COMP
BCLAMP
0.80V
SS
V
IN
V
IN
2.0V
1.2V
EN
EN
EN
EA–
VPRG
R1
R2
FLOAT
ADJUSTABLE
0
∞
–3.3V FIXED
625k
200k
200k
1.05M
–5V FIXED
INTV
CC
LVLSHFT
GND
LVLSHFT
V
OUT
–
INTV
CC
3896 BD
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
V
OUT–
+ 1.2V
V
OUT–
V
OUT–
V
OUT–
* ALL VOLTAGES WITH RESPECT TO V
OUT–
UNLESS OTHERWISE NOTED.
LTC3896
13
3896f
For more information www.linear.com/LTC3896
operaTion
Main Control Loop
The LTC3896 uses a constant frequency, current mode
control architecture. During normal operation, the external
top MOSFET is turned on when the clock sets the RS
latch, and is turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP trips and resets the latch is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier, EA. The error amplifier compares the output
voltage feedback signal at the VFB pin (which is generated
with an external resistor divider connected across ground
(GND) to the negative output voltage, VOUT–) to the internal
0.800V reference voltage (referenced to VOUT–). When the
load current increases, it causes a slight decrease in VFB
relative to the reference, which causes the EA to increase
the ITH voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 5V to 10V referenced to VOUT– by setting
the DRVSET pin. Two separate LDOs (low dropout linear
regulators) can provide power from VIN to DRVCC. The
internal VIN LDO uses an internal P-channel pass device
between the VIN and DRVCC pins. To prevent high on-chip
power dissipation in high input voltage applications, the
LTC3896 also includes an NDRV LDO that utilizes the NDRV
pin to supply power to DRVCC by driving the gate of an
external N-channel MOSFET acting as a linear regulator
with its source connected to DRVCC and drain connected
to VIN. The NDRV LDO includes an internal charge pump
that allows NDRV to be driven above VIN for low dropout
performance.
When the EXTVCC pin is tied to a voltage below its switchover
voltage (4.7V or 7.7V with respect to VOUT–, depending on
the DRVUV pin), the VIN and NDRV LDOs are enabled and
one of them supplies power from VIN to DRVCC. The VIN
LDO has a slightly lower regulation point than the NDRV
LDO. If the NDRV LDO is being used with an external
N-channel MOSFET, the gate of the MOSFET tied to the
NDRV pin is driven such that DRVCC regulates above the
VIN LDO regulation point, causing all DRVCC current to
flow through the external N-channel MOSFET, bypassing
the internal VIN LDO pass device. If the NDRV LDO is not
being used, all DRVCC current flows through the internal
P-channel pass device between the VIN and DRVCC pins.
If EXTVCC is taken above its switchover voltage, the VIN
and NDRV LDOs are turned off and an EXTVCC LDO is
turned on. Once enabled, the EXTVCC LDO supplies power
from EXTVCC to DRVCC. Using the EXTVCC pin allows the
DRVCC power to be derived from a high efficiency external
source such as the LTC3896 switching regulator output.
The top MOSFET driver is biased from the floating bootstrap
capacitor, CB, which normally recharges during each cycle
through an internal switch whenever SW goes low.
The INTVCC supply powers most of the other internal
circuits in the LTC3896. The INTVCC LDO regulates to a
fixed value of 5V (with respect to VOUT–) and its power is
derived from the DRVCC supply.
Shutdown and Start-Up (RUN, SS Pins)
The LTC3896 can be shut down using the RUN pin.
Connecting the RUN pin below 1.12V (with respect to GND)
shuts down the main control loop. Connecting the RUN
pin below 0.7V disables the controller and most internal
circuits, including the DRVCC and INTVCC LDOs. In this
state, the LTC3896 draws only 10μA of quiescent current.
The RUN pin has no internal pull-up current, so the pin
must be externally pulled up or driven directly by logic.
The RUN pin can tolerate up to 150V (with respect to
VOUT–), so it can be conveniently tied to VIN in always-on
applications where the controller is enabled continuously
and never shut down.
The start-up of the controller’s output voltage VOUT– is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 0.8V internal reference (with
respect to VOUT–), the LTC3896 regulates the VFB voltage
to the SS pin voltage instead of the 0.8V reference. This
allows the SS pin to be used to program a soft-start by
connecting an external capacitor from the SS pin to VOUT–.
LTC3896
14
3896f
For more information www.linear.com/LTC3896
operaTion
An internal 10μA pull-up current charges this capacitor
creating a voltage ramp on the SS pin. As the SS voltage
rises linearly from VOUT– to 0.8V above VOUT– (and beyond),
the output voltage VOUT– descends smoothly from zero to
its final negative value.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode) (MODE
Pin)
The LTC3896 can be enabled to enter high efficiency
Burst Mode operation, constant frequency pulse-skipping
mode, or forced continuous conduction mode at light load
currents. To select Burst Mode operation, tie the MODE pin
to VOUT– or a voltage between 0.5V and 1.0V (with respect
to VOUT–). To select forced continuous operation, tie the
MODE pin to INTVCC. To select pulse-skipping mode, tie
the MODE pin to a DC voltage greater than 1.4V and less
than INTVCC – 1.3V (with respect to VOUT–). This can be
done with a simple resistor divider between INTVCC and
VOUT–, with both resistors being 100kΩ.
When the controller is enabled for Burst Mode operation,
the minimum peak current in the inductor (burst clamp) is
adjustable and can be programmed by the voltage on the
MODE pin. Tying the MODE pin to VOUT– sets the default
burst clamp to approximately 25% of the maximum sense
voltage even when the voltage on the ITH pin indicates
a lower value. A voltage between 0.5V and 1.0V (with
respect to VOUT–) on the MODE pin programs the burst
clamp linearly between 10% and 60% of the maximum
sense voltage.
In Burst Mode operation, if the average inductor current
is higher than the load current, the error amplifier, EA,
will decrease the voltage on the ITH pin. When the ITH
voltage drops below 0.425V (with respect to VOUT–), the
internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3896 draws
to only 40μA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going positive. Thus, the
controller operates discontinuously.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
When the MODE pin is connected for pulse-skipping mode,
the LTC3896 operates in PWM pulse-skipping mode at
light loads. In this mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator, ICMP, may remain tripped for several cycles
and force the external top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor current
is not allowed to reverse (discontinuous operation). This
mode, like forced continuous operation, exhibits low output
ripple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation. At greater
|VOUT–| voltages, the efficiency in pulse-skipping mode is
comparable to forced continuous mode.
If the PLLIN pin is clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), then the LTC3896 operates
in forced continuous operation when the MODE pin is
set to forced continuous or Burst Mode operation. The
controller operates in pulse-skipping mode when clocked
by an external clock source with the MODE pin set to
pulse-skipping mode.
LTC3896
15
3896f
For more information www.linear.com/LTC3896
operaTion
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3896 can be selected
using the FREQ pin.
If the PLLIN pin is not being driven by an external clock
source, the FREQ pin can be tied to VOUT–, tied to INTVCC
or programmed through an external resistor to VOUT–.
Tying FREQ to VOUT– selects 350kHz while tying FREQ to
INTVCC selects 535kHz. Placing a resistor between FREQ
and VOUT– allows the frequency to be programmed between
50kHz and 900kHz, as shown in Figure 15.
A phase-locked loop (PLL) is available on the LTC3896
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN pin. The LTC3896’s
phase detector adjusts the voltage (through an internal
lowpass filter) of the VCO input to align the turn-on of the
external top MOSFET to the rising edge of the synchronizing
signal.
The VCO input voltage is prebiased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3896’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guarantee
to be between 75kHz and 850kHz. In other words, the
LTC3896’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
It is recommended that the external clock source swing
from GND (0V) to at least 2.8V.
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3896 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3896 in PolyPhase applications. The clock output
signal on the CLKOUT pin, which swings from VOUT– to
INTVCC, can be used to synchronize additional power
stages in a multiphase power supply solution feeding a
single, high current output or multiple separate outputs.
See the application circuit in Figure 17 for an example
of how to configure two LTC3896 ICs to produce a two-
phase inverting regulator. Pay particular attention to the
RUN, PLLIN and GND connections on the slave LTC3896.
The PHASMD pin is used to adjust the phase of the
CLKOUT signal. Pulling this pin to VOUT– forces CLKOUT
to be out-of-phase 90° with respect to TG. Connecting
this pin to INTVCC forces CLKOUT to be out of phase 120°
with respect to TG. Floating this pin forces CLKOUT to be
out-of-phase 180° with respect to TG.
VIN + |VOUT–| Overvoltage Lockout (OVLO Pin)
The LTC3896 implements a protection feature that inhibits
switching when the total voltage between input and output
(VIN + |VOUT–|) rises above a programmable operating
range. By using a resistor divider from the input supply to
VOUT–, the OVLO pin serves as a precise voltage monitor.
Switching is disabled when the OVLO pin rises above 1.2V
with respect to VOUT–, which can be configured to limit
switching to a specific range of total voltage applied to
the external MOSFETs.
When switching is disabled, the LTC3896 can safely sustain
VIN + |VOUT–| voltages up to the absolute maximum rating
of 150V. Overvoltage events trigger a soft-start reset,
which results in a graceful recovery from an input supply
transient.
Negative Output Overvoltage Protection
An overvoltage comparator guards against transient
overshoots as well as other more serious conditions that
may overvoltage (in the negative direction) the output.
When the VFB pin rises by more than 10% above its
regulation point of 0.800V with respect to VOUT–, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the negative overvoltage condition is cleared.
LTC3896
16
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Power Good Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET with its drain connected to GND. The
MOSFET turns on and pulls the PGOOD pin low when the
VFB pin voltage is not within ±10% of the 0.8V reference
voltage with respect to VOUT–. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the VFB pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V
with respect to GND. PGOOD is referenced to GND to allow
it to interface with other external true ground-referenced
components with no level shifters needed.
Foldback Current
When the output voltage (|VOUT–|) falls to less than 70%
of its nominal level, foldback current limiting is activated,
progressively lowering the peak current limit in proportion
to the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
SS voltage). Foldback current limiting is intended to limit
power dissipation during overcurrent and short-circuit fault
conditions. Note that the LTC3896 continuously monitors
the inductor current and prevents current runaway under
all conditions.
Regulator Shutdown (REGSD)
High input voltage applications typically require using the
EXTVCC LDO to keep power dissipation low. Fault conditions
where the EXTVCC LDO becomes disabled (EXTVCC below
the switchover threshold) for an extended period of time
could result in overheating of the IC (or overheating the
external N-channel MOSFET if the NDRV LDO is used). In
the cases where EXTVCC is powered from the output, this
event could happen during overload conditions such as a
VOUT– short to ground. The LTC3896 includes a regulator
shutdown (REGSD) feature that shuts down the regulator
to substantially reduce power dissipation and the risk of
overheating during such events.
The REGSD circuit monitors the EXTVCC LDO and the SS
pin to determine when to shut down the regulator. Refer
to the timing diagram in Figure 1. Whenever SS is above
2.2V with respect to VOUT– and the EXTVCC LDO is not
switched over (the EXTVCC pin is below the switchover
threshold), the internal 10μA pull-up current on SS turns
off and a 5μA pull-down current turns on, discharging SS.
Once SS discharges to 2.0V and the EXTVCC pin remains
below the EXTVCC switchover threshold, the pull-down
current reduces to 1μA and the regulator shuts down,
eliminating all DRVCC switching current. Switching stays
off until the SS pin discharges to approximately 200mV,
at which point the 10μA pull-up current turns back on
and the regulator re-enables switching. If the short-circuit
persists, the regulator cycles on and off at a low duty cycle
interval of about 12%.
Figure 1. Regulator Shutdown Operation
VOUT–
VOUT–
2.2V
SS
TG/BG
EXTVCC
2.0V
0.8V
0.2V
EXTVCC SWITCHOVER
THRESHOLD (FALLING)
ISS = –5µA
(SINK)
ISS = –1µA
(SINK)
ISS = 10µA
(SOURCE)
START-UP INTO
SHORT-CIRCUIT
ISS = 10µA
(SOURCE)
SHORT-CIRCUIT EVENT
SHORT REMOVED
FROM VOUT–
3896 F01
LTC3896
17
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The Typical Application on the first page is a basic LTC3896
application circuit. LTC3896 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs are selected. Finally, input and output
capacitors are selected.
Current Limit Programming
The ILIM pin is a three-state logic input which sets the
maximum current limit of the controller. When ILIM is tied
to VOUT–, the maximum current limit threshold voltage of
the current comparator is programmed to be 50mV. When
ILIM is floated, the maximum current limit threshold is
75mV. When ILIM is tied to INTVCC, the maximum current
limit threshold is set to 100mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparator. The common mode voltage range on these pins
is 0V to 65V with respect to VOUT– (absolute maximum),
enabling the LTC3896 to regulate output voltages down to
a nominal set point of –60V with respect to GND (allowing
margin for tolerances and transients). The SENSE+ pin
is high impedance over the full common mode range,
drawing at most ±1μA. This high impedance allows the
current comparators to be used with inductor DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V (with respect to VOUT–), a small current of
less than 1μA flows out of the pin. When SENSE– is above
INTVCC + 0.5V, a higher current (≈850μA) flows into the
pin. Between INTVCC – 0.5V and INTVCC + 0.5V, the current
transitions from the smaller current to the higher current.
Filter components mutual to the sense lines should be
placed close to the LTC3896, and the sense lines should
run close together to a Kelvin connection underneath
the current sense element (shown in Figure 2). Sensing
current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 4), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
Figure 2. Sense Lines Placement with Inductor or Sense Resistor
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 3. RSENSE is chosen based on the required output
current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the inductor
current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +ΔIL
2
Normally in high duty cycle conditions, the maximum
output current level will be reduced due to the internal
compensation required to meet stability criterion operating
at greater than 50% duty factor. The LTC3896, however,
uses a proprietary circuit to nullify the effect of slope
compensation on the current limit performance.
3896 F02
TO SENSE FILTER
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
CURRENT FLOW
COUT
LTC3896
18
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Inductor DCR Sensing
For applications requiring the highest possible efficiency at
high load currents, the LTC3896 is capable of sensing the
voltage drop across the inductor DCR, as shown in Figure 4.
The DCR of the inductor represents the small amount of
DC winding resistance of the copper, which can be less
than 1mΩ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD=
R
SENSE(EQUIV)
DCRMAX at T
L(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
The equivalent resistance R1|| R2 is scaled to the
temperature inductance and maximum DCR:
R1||R2 =
L
(DCR at 20°C) • C1
The values for R1 and R2 are:
R1=
R1||R2
RD
; R2 =
R1•R
D
1−RD
Figure 3. Using a Resistor to Sense Current
Figure 4. Using the Inductor DCR to Sense Current
LTC3896
BOOST
TG
VOUT–
V
IN
V
OUT
–
SW
BG
SENSE+
SENSE–
* PLACE C1 NEAR SENSE PINS
C1*
R
SENSE
3896 F03
LTC3896
BOOST
TG
VOUT–
V
IN
V
OUT
–
SW
BG
SENSE+
SENSE–
* PLACE C1 NEAR SENSE PINS
C1*
R2
R1**
INDUCTOR
DCR
L
(R1||R2)C1 = L/DCR
** PLACE R1 NEAR INDUCTOR
R
SENSE(EQ)
= DCR[R2/(R1+R2)]
3896 F04
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The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=V
IN(MAX) •|VOUT
–
|
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are
interrelated in that higher operating frequencies allow the
use of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, decreases with higher
inductance or higher frequency:
ΔIL=1
(f)(L) V
IN
|VOUT–|
V
IN +|VOUT–|
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage.
The inductor value also has secondary effects. The
transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
the burst clamp, which can be programmed between
10% and 60% of the current limit determined by RSENSE.
(For more information see the Burst Clamp Programming
section.) Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC3896 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak drive levels are set by the DRVCC voltage.
This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-
level and standard-level threshold MOSFETs can be used
in most applications depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
The LTC3896’s ability to adjust the gate drive level between
5V to 10V (OPTI-DRIVE) allows an application circuit to
be precisely optimized for efficiency. When adjusting the
gate drive level, the final arbiter is the total input current
for the regulator. If a change is made and the input
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current decreases, then the efficiency has improved. If
there is no change in input current, then there is no change
in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
|V
OUT
–|
V
IN+|VOUT–|
Synchronous Switch Duty Cycle =V
IN
V
IN
+|V
OUT
–|
For a given VOUT–, the maximum duty cycle occurs at
minimum VIN.
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =|VOUT–| V
IN + |VOUT–|
( )
V
IN2IOUT(MAX)
( )
2(1+δ)
•RDS(ON) +V
IN+|VOUT–|
( )
3
V
IN
IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟(RDR )(CMILLER )
•1
VDRVCC −VTHMIN
+1
VTHMIN
⎡
⎣
⎢⎤
⎦
⎥(f)
P
SYNC =V
IN+|VOUT–|
V
IN
IOUT(MAX)
( )
2(1+δ)RDS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input to output differential
voltages. For (VIN + |VOUT–|) < 20V the high current
efficiency generally improves with larger MOSFETs, while
for (VIN + |VOUT–|) > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
CIN and COUT Selection
The input and output capacitance, CIN /COUT, are required to
filter the square wave current through the top and bottom
MOSFETs respectively. Use a low ESR capacitor sized to
handle the maximum RMS current.
ICIN(RMS) =ICOUT(RMS) =IOUT •|VOUT–|
V
IN
The formula shows that the RMS current is greater than
the maximum IOUT when |VOUT–| is greater than VIN.
Choose capacitors with higher RMS rating with sufficient
margin. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life,
which makes it advisable to derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The ∆VOUT is approximately bounded by:
ΔVOUT–≤IL(PEAK) •ESR+
I
OUT
f•COUT
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where IL(PEAK) is the peak inductor current and it’s given as:
IL(PEAK) =
I
OUT
(V
IN+
|V
OUT
–|)
V
IN
+V
IN •|VOUT–|
2•L•f•(V
IN
+|V
OUT
–|)
Since IL(PEAK) reach its maximum values at minimum
VIN, the output voltage ripple is highest at minimum VIN
and maximum IOUT. Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering and
has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing
from inrush currents and switching does not pose an
overvoltage hazard to the power switch and controller.
To dampen input voltage transients, add a small 5μF to
40μF aluminum electrolytic capacitor with an ESR in the
range of 0.5Ω to 2Ω. High performance through-hole
capacitors may also be used, but an additional ceramic
capacitor in parallel is recommended to reduce the effect
of lead inductance.
During shutdown and startup conditions, the output
capacitor can experience a small reverse voltage (a positive
voltage on VOUT– with respect to GND) as the result of IC
quiescent current and/or capacitor charging current flowing
into the VOUT– node while VOUT– is not being actively driven
negative by the converter. This reverse voltage, which is
typically clamped to a diode drop above ground by the
reverse diode of the external bottom MOSFET, should be
carefully considered when choosing the output capacitor.
Certain polarized capacitors can be permanently damaged
given enough reverse voltage. If considering a polarized
capacitor at the output, always consult the manufacturer
if there is any question regarding reverse voltage on the
capacitor. Alternatively, an all ceramic capacitor solution
at the output would make the reverse voltage a non-issue
Setting Output Voltage
The LTC3896 output voltage is set by an external feedback
resistor divider carefully placed across the output, as shown
in Figure 5. The regulated output voltage is determined by:
VOUT–=–0.8V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
To improve the frequency response, a feedforward
capacitor, CFF, may be used. Great care should be taken
to route the VFB line away from noise sources, such as
the inductor or the SW line.
The LTC3896 also has the option to be programmed to a
fixed –5V or –3.3V output through control of the VPRG
pin. Figure 6 shows how the VFB pin is used to sense
ground in fixed output mode. Tying VPRG to INTVCC or
VOUT– programs VOUT– to –5V or –3.3V, respectively.
Floating VPRG sets VOUT– to adjustable output mode using
external resistors.
LTC3896
VFB
VOUT–
RBCFF
RA
3896 F05
LTC3896
VFB
VPRG
VOUT–
–5V/–3.3V
INTVCC/ VOUT–
COUT
3896 F06
Figure 5. Setting Adjustable Output Voltage
Figure 6. Setting Output to Fixed –5V/–3.3V Voltage
LTC3896
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RUN Pin
The LTC3896 is enabled using the RUN pin. It has a
rising threshold of 1.2V with respect to GND with 80mV
of hysteresis. The RUN pin is referenced to the GND pin,
allowing the LTC3896 to be used with a true ground-
referenced external signal or logic with no level shifters
needed. Pulling the RUN pin below 1.12V shuts down
the main control loop. Pulling it below 0.7V disables the
controller and most internal circuits, including the DRVCC
and INTVCC LDOs. In this state the LTC3896 draws only
10μA of quiescent current.
The RUN pin is high impedance below 3V and must be
externally pulled up/down or driven directly by logic. The
RUN pin can tolerate up to 150V (absolute maximum), so
it can be conveniently tied to VIN in always-on applications
where the controller is enabled continuously and never
shut down. Above 3V, the RUN pin has approximately a
15MΩ impedance to an internal 3V clamp.
The RUN pin can be configured as an undervoltage (UVLO)
lockout on the VIN supply with a resistor divider from VIN
to GND, as shown in Figure 7.
to VOUT– (Figure 8), the OVLO pin serves as a precise
voltage monitor. Switching is disabled when the OVLO
pin rises above 1.2V with respect to VOUT–, which can be
configured to limit switching to a specific range of total
voltage applied to the external switching MOSFETs.
Figure 7. Using the RUN Pin as a UVLO
Figure 8. Programming the OVLO Pin
Figure 9. Using the SS Pin to Program Soft-Start
LTC3896
RUN
VIN
RB
RA
3891 F07
LTC3896
OVLO
VIN
RB
RA
3896 F08
VOUT–
LTC3896
VOUT–
VOUT–
CSS
SS
3896 F09
The rising and falling UVLO thresholds, referenced to
ground, are calculated using the RUN pin thresholds:
VUVLO(RISING) =1.2V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
VUVLO(FALLING) =1.12V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
Overvoltage Lockout Pin (OVLO)
The LTC3896 implements a protection feature that inhibits
switching when the total voltage between input and output
(VIN + |VOUT–|) rises above a programmable operating
range. By using a resistor divider from the input supply
The rising and falling OVLO thresholds are calculated using
the OVLO pin thresholds:
VOVLO(RISING) =1.2V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
VOVLO(FALLING) =1.1V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
where VOVLO is the total voltage between VIN and VOUT–.
Soft-Start (SS) Pin
The start-up of VOUT– is controlled by the voltage on the
SS pin. When the voltage on the SS pin is less than the
internal 0.8V reference (with respect to VOUT–), the LTC3896
regulates the VFB pin voltage to the voltage on the SS pin
instead of the internal reference. The SS pin can be used
to program an external soft-start function.
Soft-start is enabled by simply connecting a capacitor from
the SS pin to VOUT–, as shown in Figure 9. An internal 10μA
current source charges the capacitor, providing a linear
ramping voltage at the SS pin with respect to VOUT–. The
LTC3896 will regulate its feedback voltage (and hence
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VOUT–) according to the voltage on the SS pin, allowing
VOUT– to fall smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
tSS =CSS •
0.8V
10µA
The SS pin also controls the timing of the regulator
shutdown (REGSD) feature (as discussed in Regulator
Shutdown of the Operation section). If the application does
not require the use of the EXTVCC LDO (the EXTVCC pin is
tied to VOUT–), the REGSD feature must be defeated with
a pull-up resistor between SS and INTVCC, as shown in
Figure 10. Any resistor 330kΩ or smaller between SS and
INTVCC defeats the 5μA pull-down current on SS that turns
on once SS reaches 2.2V with respect to VOUT– (with the
EXTVCC LDO not enabled), preventing SS from discharging
to 2.0V and shutting down the regulator. Note the current
through this pull-up resistor adds to the internal 10μA
SS pull-up current at start-up, causing the total soft-start
time to be shorter than what it is calculated without the
pull-up resistor. The total soft-start time with the pull-up
resistor is approximately:
tSS ≈CSS •
0.8V
10µA +4.6V
RSS
⎛
⎝
⎜⎞
⎠
⎟
where RSS is the value of the resistor between the SS and
INTVCC pins.
DRVCC Regulators (OPTI-DRIVE)
The LTC3896 features three separate low dropout linear
regulators (LDO) that can supply power at the DRVCC pin.
The internal VIN LDO uses an internal P-channel pass device
between the VIN and DRVCC pins. The internal EXTVCC LDO
uses an internal P-channel pass device between the EXTVCC
and DRVCC pins. The NDRV LDO utilizes the NDRV pin to
drive the gate of an external N-channel MOSFET acting
as a linear regulator with its drain connected to VIN. Note
the return path for the DRVCC regulators is the VOUT– pin.
The NDRV LDO provides an alternative method to supply
power to DRVCC from the input supply without dissipating
the power inside the LTC3896 IC. It includes an internal
charge pump that allows NDRV to be driven above the
VIN supply, allowing for low dropout performance. The
VIN LDO has a slightly lower regulation point than the
NDRV LDO, such that all DRVCC current flows through the
external N-channel MOSFET (and not through the internal
P-channel pass device) once DRVCC reaches regulation.
When laying out the PC board, care should be taken to
route NDRV away from any switching nodes, especially
SW, TG, and BOOST. Coupling to the NDRV node could
cause its voltage to collapse and the NDRV LDO to lose
regulation. If this occurs, the internal VIN LDO would
take over and maintain DRVCC voltage at a slightly lower
regulation point. However, internal heating of the IC would
become a concern.
High frequency noise on the drain of the external NFET
could also couple into the NDRV node (through the gate-
to-drain capacitance of the NDRV NFET) and adversely
affect NDRV regulation. The following are methods that
could mitigate this potential issue (refer to Figure 11a).
1. Add local decoupling capacitors to VOUT– right next to
the drain of the external NDRV NFET in the PCB layout.
2. Insert a resistor (~100Ω) in series with the gate of the
NDRV NFET.
3. Insert a small capacitor (~1nF) between the gate and
source of the NDRV NFET.
Figure 10. Using the SS Pin to Program Soft-Start
with EXTVCC Unused/Tied to VOUT–
LTC3896
VOUT–EXTVCC
VOUT–
CSS
RSS
SS
INTVCC
3896 F10
LTC3896
24
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When testing the application circuit, be sure the NDRV
voltage does not collapse over the entire input voltage
and output current operating range of the buck regulator.
If the NDRV LDO is not being used, connect the NDRV pin
to DRVCC (Figure 11b).
The DRVCC supply is regulated between 5V to 10V with
respect to VOUT–, depending on how the DRVSET pin is
set. The internal VIN and EXTVCC LDOs can supply a peak
current of at least 50mA. The DRVCC pin must be bypassed
to VOUT– with a minimum of 4.7μF ceramic capacitor. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers.
The DRVSET pin programs the DRVCC supply voltage
and the DRVUV pin selects different DRVCC UVLO and
EXTVCC switchover threshold voltages. Table 1 summarizes
the different DRVSET pin configurations along with the
voltage settings that go with each configuration. Table 2
summarizes the different DRVUV pin settings. Tying the
DRVSET pin to INTVCC programs DRVCC to 10V. Tying the
DRVSET pin to VOUT– programs DRVCC to 6V. Placing a
50kΩ to 100kΩ resistor between DRVSET and VOUT– the
programs DRVCC between 5V to 10V, as shown in Figure 12.
Table 1
DRVSET PIN DRVCC VOLTAGE
VOUT–6V
INTVCC 10V
Resistor to VOUT– 50k to 100k 5V to 10V
Table 2
DRVUV PIN
DRVCC UVLO RISING/
FALLING THRESHOLDS
EXTVCC SWITCHOVER
RISING/FALLING
THRESHOLD
VOUT–4.0V/3.8V 4.7V/4.45V
INTVCC 7.5V/6.7V 7.7V/7.45V
All voltages with respect to VOUT–
Large VIN + |VOUT–| applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3896
to be exceeded. The DRVCC current, which is dominated
by the gate charge current, may be supplied by the VIN
LDO, NDRV LDO or the EXTVCC LDO. When the voltage
on the EXTVCC pin is less than its switchover threshold
(4.7V or 7.7V with respect to VOUT–, as determined by the
DRVUV pin described above), the VIN and NDRV LDOs are
enabled. Power dissipation in this case is highest and is
equal to (VIN + |VOUT–|) • IDRVCC. If the NDRV LDO is not
being used, this power is dissipated inside the IC. The
gate charge current is dependent on operating frequency
Figure 12. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
NDRV LDO
or EXTV
CC
LDO
Internal V
IN
LDO
DRVSET PIN RESISTOR (kΩ)
50
55
60
65
70
75
80
85
90
95
100
105
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
DRV
CC
VOLTAGE (V)
3896 F12
Figure 11.
R1*
C1*
C2*
LTC3896
V
IN
NDRV
DRV
CC
V
OUT
–
V
IN
*R1, C1, AND C2 ARE OPTIONAL
V
OUT
–
3896 F11a
LTC3896
V
IN
NDRV
DRV
CC
V
OUT
–
V
IN
V
OUT
–
3896 F11b
Figure 11a. Configuring the NDRV LDO
Figure 11b. Disabling the NDRV LDO
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as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
For example, if DRVCC is set to 6V, the DRVCC current is
limited to less than 49mA if VIN + |VOUT–| is 40V when
not using the EXTVCC or NDRV LDOs at a 70°C ambient
temperature:
TJ = 70°C + (49mA)(40V)(28°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the VIN supply current must be checked while
operating in forced continuous mode (MODE = INTVCC)
at maximum VIN + |VOUT–|.
When the voltage applied to EXTVCC rises above its
switchover threshold (with respect to VOUT–), the VIN and
NDRV LDOs are turned off and the EXTVCC LDO is enabled.
The EXTVCC LDO remains on as long as the voltage applied
to EXTVCC remains above the switchover threshold minus
the comparator hysteresis. The EXTVCC LDO attempts to
regulate the DRVCC voltage to the voltage as programmed
by the DRVSET pin, so while EXTVCC is less than this
voltage, the LDO is in dropout and the DRVCC voltage is
approximately equal to EXTVCC. When EXTVCC
with respect
to VOUT– is greater than the programmed DRVCC voltage,
up to an absolute maximum of 14V, DRVCC is regulated
to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the output (4.7V/7.7V ≤
|VOUT–| ≤ 14V) during normal operation and from the VIN
or NDRV LDO when the output is out of regulation (e.g.,
start-up, short-circuit). If more current is required through
the EXTVCC LDO than is specified, an external Schottky
diode can be added between the EXTVCC and DRVCC pins.
In this case, do not apply more than 10V between the
EXTVCC and VOUT– pins and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the output using the EXTVCC
LDO, since the VIN current resulting from the driver and
control currents will be scaled by a factor of (Duty Cycle)/
(Switcher Efficiency).
For –5V to –14V regulator outputs, this means connecting
the EXTVCC pin directly to ground. Tying the EXTVCC pin to
ground with an –8.5V output supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (49mA)(8.5V)(28°C/W) = 82°C
However, for –3.3V and other low voltage outputs, additional
circuitry is required to derive DRVCC power from the output.
The following list summarizes the four possible connections
for EXTVCC:
1. EXTVCC tied to VOUT–. This will cause DRVCC to be
powered from the internal VIN or NDRV LDO resulting in
an efficiency penalty of up to 10% at high input voltages.
If EXTVCC is tied to VOUT–, the REGSD feature must
be defeated with a pull-up resistor 330kΩ or smaller
between SS and INTVCC.
2. EXTVCC connected directly to ground. This is the normal
connection for a –5V to –14V regulator and provides
the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the range 5V to 14V above VOUT–, it
may be used to power EXTVCC providing it is compatible
with the MOSFET gate drive requirements. Ensure that
EXTVCC ≤ VIN.
4. EXTVCC connected to ground through an external Zener
diode. If the output voltage is more negative than –14V,
a Zener diode can be used to drop the necessary voltage
between ground and EXTVCC such that EXTVCC with
respect to VOUT– remains below 14V (Figure 13). In
this configuration, a bypass capacitor from EXTVCC to
VOUT– of at least 0.1μF is recommended. An optional
resistor between EXTVCC and VOUT– can be inserted to
ensure adequate bias current through the Zener diode.
3896 F13
LTC3896
VOUT–
EXTVCC
|VOUT–| > 14V
0.1µF
EXTVCC – VOUT– < 14V
Figure 13. Using a Zener Diode Between EXTVCC and Ground
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INTVCC Regulator
An additional P-channel LDO supplies power at the INTVCC
pin from the DRVCC pin. Whereas DRVCC powers the gate
drivers, INTVCC powers much of the LTC3896’s internal
circuitry. The INTVCC supply must be bypassed with a
0.1μF ceramic capacitor to VOUT–. INTVCC is also used as a
pull-up to bias other pins, such as MODE, ILIM, VPRG, etc.
Topside MOSFET Driver Supply (CB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
The LTC3896 features an internal 11Ω switch between
DRVCC and the BOOST pin. This internal switch eliminates
the need for an external bootstrap diode between DRVCC
and BOOST. Capacitor CB in the Functional Diagram is
charged through this internal switch from DRVCC when the
SW pin is low. When the topside MOSFET is to be turned
on, the driver places the CB voltage across the gate-source
of the MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET on,
the BOOST voltage is above the input supply: VBOOST =
VIN + VDRVCC. The value of the boost capacitor, CB, needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s).
Burst Clamp Programming
Burst Mode operation is enabled if the voltage on the
MODE pin is 0V (with respect to VOUT–) or in the range
between 0.5V to 1V. The burst clamp, which sets the
minimum peak inductor current, can be programmed by
the MODE pin voltage. If the MODE pin is grounded, the
burst clamp is set to 25% of the maximum sense voltage
(VSENSE(MAX)). A MODE pin voltage between 0.5V and 1V
varies the burst clamp linearly between 10% and 60% of
VSENSE(MAX) through the following equation:
Burst Clamp =
V
MODE −
0.4V
1V
•100
where VMODE is the voltage on the MODE pin (with respect
to VOUT–) and burst clamp is the percentage of VSENSE(MAX).
The burst clamp level is determined by the desired amount
of output voltage ripple at low output loads. As the burst
clamp increases, the sleep time between pulses and the
output voltage ripple increase.
The MODE pin is high impedance and VMODE can be
set by a resistor divider from the INTVCC pin to VOUT–
(Figure 14a). Alternatively, the MODE pin can be tied directly
to the VFB pin to set the burst clamp to 40% (VMODE =
0.8V), or through an additional divider resistor (R3). As
shown in Figure 14b, this resistor can be placed below
VFB to program the burst clamp between 10% and 40%
(VMODE= 0.5V to 0.8V) or above VFB to program the burst
clamp between 40% and 60% (VMODE = 0.8V to 1.0V).
Figure 14. Programming the Burst Clamp
3896 F14
LTC3896
BURST CLAMP = 10% to 60% BURST CLAMP = 10% to 40% BURST CLAMP = 40% to 60%
(14a) (14b) (14c)
USING INTVCC TO PROGRAM THE BURST CLAMP USING VFB TO PROGRAM THE BURST CLAMP
R2
VMODE = 0.5V TO 1.0V
R1
VOUT–
MODE
INTVCC
VOUT–
LTC3896 R3
R1
VOUT–
MODE
VFB
VOUT–
R2
LTC3896 R3
R1
VOUT–
VFB
MODE
VOUT–
R2
VMODE = 0.8V TO 1.0V
VMODE = 0.5V TO 0.8V
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Fault Conditions: Current Limit and Current Foldback
The LTC3896 includes current foldback to help limit load
current when the output is overloaded or shorted to ground.
If the output voltage (|VOUT–|) falls below 70% of its nominal
level, then the maximum sense voltage is progressively
lowered from 100% to 45% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC3896 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3896 (≈80ns), the input voltage and inductor value:
ΔIL(SC) =tON(MIN)
V
IN
L
⎛
⎝
⎜⎞
⎠
⎟
The resulting average short-circuit current is:
ISC =45% •ILIM(MAX) −
1
2
ΔIL(SC)
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip,
the overtemperature shutdown circuitry will shut down
the LTC3896. When the junction temperature exceeds
approximately 175°C, the overtemperature circuitry
disables the DRVCC LDO, causing the DRVCC supply to
collapse and effectively shutting down the entire LTC3896
chip. Once the junction temperature drops back to the
approximately 155°C, the DRVCC LDO turns back on. Long
term overstress (TJ > 125°C) should be avoided as it can
degrade the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3896 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows
the turn-on of the top MOSFET to be locked to the rising
edge of an external clock signal applied to the PLLIN pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3896 can only be synchronized to an
external clock whose frequency is within range of the
LTC3896’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
The LTC3896 is guaranteed to synchronize to an external
clock that swings up to at least 2.8V and down to 0.5V or
less with respect to GND.
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3896 F15
400
200
500
700
900
300
100
065 75 85 95 105 115 125
Figure 15. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
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Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 3 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC3896 operates in forced continuous mode at light
loads if the MODE pin is set to Burst Mode operation or
forced continuous operation. If the MODE pin is set to
pulse-skipping operation, the LTC3896 maintains pulse-
skipping operation when synchronized.
Table 3
FREQ PIN PLLIN PIN FREQUENCY
VOUT–DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor to VOUT–DC Voltage 50kHz to 900kHz
Any of the Above External Clock
75kHz to 850kHz
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3896 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
|V
OUT
–|
V
IN +|VOUT –|
•
1
f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3896 is approximately
80ns. However, the peak sense voltage decreases the
minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3896 circuits: 1) IC VIN current, 2) DRVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2. DRVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from DRVCC to VOUT–. The resulting dQ/dt is a current
out of DRVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
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Supplying DRVCC from the output through EXTVCC will
scale the VIN current required for the driver and control
circuits by a factor of (Duty Cycle)/(Efficiency). For
example, in a 15V to –5V application, 10mA of DRVCC
current results in approximately 2.5mA of VIN current.
This reduces the midcurrent loss from 10% or more
(if the driver was powered directly from VIN) to only a
few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor
and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS, then the resistance of one
MOSFET can simply be summed with the resistances of
L, RSENSE and ESR to obtain I2R losses. For example, if
each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and
RESR = 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ.
4. Transition losses apply only to the top MOSFET(s) and
become significant only when operating at high VIN +
|VOUT–| voltages (typically 20V or greater). Transition
losses can be estimated from:
Transition Loss =(1.7) •(V
IN +|VOUT
–
|)
3
V
IN
•IO(MAX) •CRSS •f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum of
20μF to 40μF of capacitance having a maximum of 20mΩ to
50mΩ of ESR. Other losses including Schottky conduction
losses during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT– shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT– to its steady-state value. During this recovery
time VOUT– can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 16 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
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bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing
RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT–. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume VIN = 7V to 22V, VOUT– =
–5V, IOUT(MAX) = 5A, VSENSE(MAX) = 75mV and f = 350kHz.
Tie the FREQ pin to VOUT– to program 350kHz operation.
Float the ILIM pin to program a maximum current sense
threshold of 75mV.
For an inverting buck-boost converter in continuous
conduction mode, the average inductor current and the
inductor ripple current can be determined by the following
equations:
IL(AVG) =IOUT
V
IN +|VOUT
–
|
V
IN
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
ΔIL=1
(f)(L) V
IN
|VOUT–|
V
IN +|VOUT–|
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
From these two equations and taking a starting point of
30% ripple current at maximum inductor ripple current
(at maximum VIN), the following equation can be used to
calculate the inductor value:
L=1
(f)(0.3)(IOUT(MAX))
•(V
IN(MAX))2(|VOUT
–
|)
(V
IN(MAX)+|VOUT–|)2
=1
(350kHz)(0.3)(5A)
•(22V)2(5V)
(22V +5V)2
≈6.32µH
Select a standard value of 6.2µH inductor.
The resulting ripple current at minimum VIN is:
ΔIL=
1
(350kHz)(6.2µH)
•
(7V)(5V)
(7V +5V) ≈1.34A
The peak inductor current will be the maximum average
inductor current plus one half of the ripple current. This
occurs at minimum VIN and full load:
IL(PEAK _ MAX) =(5A)
(7V
+
5V)
7V
+
1.34A
2
≈9.24A
The minimum on-time occurs at maximum VIN:
tON(MIN) =
|V
OUT
–|
V
IN(MAX)
+|V
OUT
–|
•
1
f=529ns
LTC3896
31
3896f
For more information www.linear.com/LTC3896
applicaTions inForMaTion
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (66mV):
RSENSE ≤
66mV
9.24A
≈0.007Ω
Choosing 1% resistors with VPRG floating: RA = 68.1kΩ
and RB = 357kΩ yields an output voltage of –4.99V.
Alternatively, VPRG can be connected to INTVCC and VFB
tied to GND to program the –5V fixed output.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
P
MAIN =
(5V)(27V)
(22V)2(5A)21+(0.005)(50°C−25°C)
[ ]
(0.035Ω)+(27V)3
22V
5A
2(2.5Ω)(215pF) •
1
6V −2.3V +1
2.3V
⎡
⎣
⎢⎤
⎦
⎥(350kHz) =571mW
A short-circuit to ground will result in a folded back
current of:
ISC =34mV
0.007Ω−1
2
80ns(22V)
6.2µH
⎛
⎝
⎜⎞
⎠
⎟=4.72A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (4.72A)2 (1.125)(0.022Ω) = 551mW
which is less than under full-load conditions. CIN is chosen
for an RMS current rating of at least 4.3A at temperature.
COUT is chosen based on the ESR that is required to satisfy
the output voltage ripple requirement. The selected COUT
must support the maximum RMS operating current of
4.3A at minimum VIN.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CDRVCC must return to the combined COUT (–) terminals.
The path formed by the top N-channel MOSFET, bottom
N-channel MOSFET and the CIN and COUT capacitors
should have short leads and PC trace lengths.
2. Does the LTC3896 VFB pin’s resistive divider connect to
the (-) terminal of COUT? The resistive divider must be
connected between the (–) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current feeds from the input or output
capacitors.
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
4. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the VOUT– pin? This
capacitor carries the MOSFET drivers’ current peaks.
5. Keep the SW, TG, and BOOST nodes away from sensitive
small-signal nodes. All of these nodes have very large
and fast moving signals and therefore should be kept on
the output side of the LTC3896 and occupy minimum
PC trace area.
6. Use a modified star virtual ground technique for VOUT–:
a low impedance, large copper area central grounding
point on the same side of the PC board as the input
and output capacitors with tie-ins for the bottom of the
DRVCC decoupling capacitor, the bottom of the voltage
feedback resistive divider and the VOUT– pin of the IC.
LTC3896
32
3896f
For more information www.linear.com/LTC3896
applicaTions inForMaTion
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance
over the operating voltage and current range expected
in the application. The frequency of operation should be
maintained over the input voltage range down to dropout
and until the output load drops below the low current
operation threshold—typically 25% of the maximum
designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest
noise pickup at the current or voltage sensing inputs or
inadequate loop compensation. Overcompensation of the
loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, the top MOSFET and
the bottom MOSFET to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3896
33
3896f
For more information www.linear.com/LTC3896
Typical applicaTions
Figure 16. High Efficiency 35V – 72V to –48V/2A Inverting Regulator
COUT
4.7µF
100V
2220
×8
R
SENSE
10mΩ
MBOT
MTOP
×2
C
B
0.1µF
L1
47µH
C
SNS
1nF
C
ITHA
15nF
C
ITHB
100pF
R
A
10k
C
SS
0.1µF
C
INTV
CC
0.1µF
RPGOOD
100k
C
DRV
CC
4.7µF
47µF
C
INA
0.1µF
×3
C
INC
R
B
590k
R
ITH
4.99k
MNDRV
R
SS
301k
C
INB
2.2µF
×2
V
IN
INTV
CC
DRVSET
DRVUV
ITH
FREQ
LTC3896
TG
SW
BG
SENSE+
SENSE–
EXTV
CC
BOOST
NDRV
V
IN
36V to 72V
V
OUT
–
–48V
2A
PHASMD
PLLIN
PGOOD
VPRG
CLKOUT
RUN
SS
MTOP: BSC520N15NS3G
MBOT: BSC019N15NS3G
MNDRV: IPD320N20N3G
L1: WURTH 7443634700
C
INA
: SUNCON 100CE47LX
COUT: TDK C5750X7R2A475M230KA
MODE
PINS NOT USED IN THIS CIRCUIT
DRV
CC
ILIM
OVLO
0V
0V
VOUT–
VOUT–
VOUT–
VOUT–
5V
GND
V
FB
3896 F16
LTC3896
34
3896f
For more information www.linear.com/LTC3896
Typical applicaTions
Figure 17. High Efficiency 2-Phase 36V–72V to –24V/10A Inverting Regulator
COUT1
6.8µF
50V
1812
×4
COUT2
6.8µF
50V
1812
×4
R
SENSE1
7mΩ
MBOT2
MTOP1
×2
C
B1
0.1µF
L1
22µH
C
SNS1
1nF
C
ITHA1
220nF
C
ITHB1
100pF
R
A
10.7k
C
SS
0.1µF
C
INT1
0.1µF
C
DRV1
4.7µF
47µF
C
INA1
2.2µF
C
INC1
R
B
309k
R
ITH1
2k
MNDRV1
R
SS
100k
C
INB1
2.2µF
×2
DEXT
12V
1W
CEXT
0.1µF
R
FREQ1
36.5k
R
SENSE2
7mΩ
MBOT2
MTOP2
×2
C
B2
0.1µF
L2
22µH
C
SNS2
1nF
C
ITHB2
100pF
C
INT2
0.1µF
C
DRV2
4.7µF
2.2µF
C
INC2
MNDRV2
C
INB2
2.2µF
×2
R
FREQ2
36.5k
V
IN
INTV
CC
DRVSET
DRVUV
ITH
FREQ
LTC3896
TG
SW
BG
SENSE+
SENSE–
BOOST
NDRV
V
IN
36V to 72V
V
OUT
–
–24V
10A
PHASMD
PLLIN
VPRG
RUN
SS
MTOP1, MTOP2: BSC440N10NS3G
MBOT1, MBOT2: BSC079N10NSG
MNDRV1, MNDRV2: BSC440N10NS3G
L1, L2: WURTH 7443642200
CINA: SUNCON 100CE47LX
COUT1, COUT2: TDK C4532X7R1H685M250kB
MODE
DRV
CC
ILIM
OVLO
0V
GND
V
FB
CLKOUT
EXTV
CC
V
IN
INTV
CC
DRVSET
DRVUV
ITH
FREQ
LTC3896
TG
SW
BG
SENSE+
SENSE–
BOOST
NDRV
PHASMD
PLLIN
VPRG
RUN
SS
MODE
DRV
CC
ILIM
OVLO
GND
V
FB
CLKOUT
EXTV
CC
PGOOD
PGOOD
MASTER
SLAVE
INTV
CC
_M
INTV
CC
_M
CLKOUT_M
CLKOUT_M
V
OUT
–
ITH
VOUT–
VOUT–
VOUT–
VOUT–
V
FB
EXTV
CC
EXTV
CC
SS
SS
ITH
V
FB
V
OUT
–
V
OUT
–
3896 F17
VOUT–
VOUT–
VOUT–
VOUT–
LTC3896
35
3896f
For more information www.linear.com/LTC3896
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
Please refer to http://www.linear.com/product/LTC3896#packaging for the most recent package drawings.
4.75
(.187) REF
FE38 (AB) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1865 Rev B)
Exposed Pad Variation AB
LTC3896
36
3896f
For more information www.linear.com/LTC3896
LINEAR TECHNOLOGY CORPORATION 2016
LT 0416 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3896
relaTeD parTs
Typical applicaTion
High Efficiency 7V–72V to –12V/5A Inverting Regulator
PART NUMBER DESCRIPTION COMMENTS
LTC3863 60V Low IQ, Inverting DC/DC Controller Fixed Frequency 50kHz to 850kHz, 3.5V ≤ VIN ≤ 60V, Negative VOUT from
–0.4V to Beyond –150V , IQ = 70μA, MSOP-12E, 3mm × 4mm DFN-12
LTC7149 60V, 4A Synchronous Step-Down Regulator PLL Fixed Frequency 300kHz to 3MHz, 3.4V ≤ VIN ≤ 60V, for Inverting Outputs
0V ≤ VOUT ≤ –28V, 28-Lead (4mm × 5mm) QFN and TSSOP Packages
LT8710 80V Synchronous SEPIC/ Inverting/Boost Controller Fixed Frequency Up to 750kHz, 4.5V ≤ VIN ≤ 80V, with Output Current Control
TSSOP-20 Package
LTC3704 Wide Input Range, No RSENSE Positive-to-Negative
DC/DC Controller
PLL Fixed Frequency 50kHz to 1MHz, 2.5V ≤ VIN ≤ 36V, MSOP-10
LTC3895 150V Low IQ, Synchronous Step-Down DC/DC
Controller
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ 60V,
IQ = 40μA
LTC3892/
LTC3892-1
60V Low IQ, Dual, 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN,
Adjustable 5V to 10V Gate Drive, IQ = 29μA
LTC3639 High Efficiency, 150V 100mA Synchronous Step-
Down Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 150V, 0.8V ≤ VOUT ≤ VIN, IQ = 12μA,
MSOP-16(12)
LTC7138 High Efficiency, 140V 400mA Step-Down Regulator Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN, IQ = 12μA,
MSOP-16(12)
LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC
Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50μA
LTC3810 100V Synchronous Step-Down DC/DC Controller Constant On-time Valley Current Mode 4V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 0.93VIN,
SSOP-28
LTC3638 High Efficiency, 140V 250mA Step-Down Regulator Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN, IQ = 12μA,
MSOP-16(12)
LTC7812 38V Synchronous Boost+Buck Controller Low EMI
and Low Input/Output Ripple
4.5V (Down to 2.5V After Start-up) ≤ VIN ≤ 38V, Boost VOUT Up to 60V,
0.8V ≤ Buck VOUT ≤ 24V, IQ = 33μA, 5mm × 5mm QFN-32
LT8631 100V, 1A Synchronous Micropower Step-Down
Regulator
PLL Fixed Frequency 100kHz to 1MHz, 3V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 60V,
TSSOP-20 Package with High Voltage Spacing
C
OUTB
R
SENSE
3mΩ
MBOT
MTOP
C
B
0.1µF
L1
10µH
C
SNS
1nF
C
ITHA
4.7nF
C
ITHB
47pF
R
A
10k
C
SS
0.1µF
C
INTV
CC
0.1µF
R
PGOOD
100k
C
DRV
CC
4.7µF
100µF
C
INA
2.2µF
C
INC
RB
140k
R
ITH
5.11k
MNDRV
C
INB
2.2µF
R
NDRV
100
R
FREQ
47.5k
C
OUTA
V
IN
INTV
CC
DRVSET
DRVUV
ITH
FREQ
LTC3896
TG
SW
BG
SENSE+
SENSE–
BOOST
NDRV
V
IN
7V to 72V
V
OUT
–
–12V
5A
PHASMD
PGOOD
VPRG
CLKOUT
RUN
SS
MTOP: BSC070N10NS5
MBOT: BSC040N10NS5
MNDRV: IRFR120NTRPBF
L1: WURTH 7443631000
C
INA
: UNITED CHEMI-CON EMVY101ARA101MKE0S
C
OUTA
: TDK C4532X7R1E226M250KC
C
OUTB
: AVX 1210YD106KAT2A
×2
MODE
10µF
16V
1210
×2
PINS NOT USED IN THIS CIRCUIT:
DRV
CC
ILIM
OVLO
V
OUT
-
5V
V
OUT
-
V
OUT
-
V
OUT
-
×3
GND
V
FB
EXTV
CC
PLLIN
22µF
25V
1812
×8
3896 TA02
