CS4272-DZZR - Cirrus Logic

Cirrus Logic, Inc.

www.cirrus.com

CS4272

24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

!High Performance

– 114 dB Dynamic Range

– -100 dB THD+N

!Up to 192 kHz Sampling Rates

!Differential Analog Architecture

!Volume Control with Soft Ramp

– 1 dB Step Size

– Zero Crossing Click-free Transitions

!Selectable Digital Filters

– Fast and Slow Roll Off

!ATAPI Mixing Functions

!Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

2S up to 24-bit

– Right Justified 16-, 18-, 20-, and 24-Bit

!Control Output for External Muting

!Selectable 50/15 µs De-emphasis

A/D Features

!High Performance

– 114 dB Dynamic Range

– -100 dB THD+N

!Up to 192 kHz Sampling Rates

!Differential Analog Architecture

!Multi-bit Delta Sigma Conversion

!High-pass Filter or DC Offset Calibration

!Low-Latency Digital Anti-alias Filtering

!Automatic Dithering of 16-bit Data

!Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

2S up to 24-bit

System Features

!Direct Interface with 5V to 2.5V Logic Levels

!Internal Digital Loopback

!On-chip Oscillator

!Stand-Alone or Control Port Functionality

2.5 V to 5 V

Left and

Right Mute

Controls

∆Σ Modulator

Low-Latency

Anti-Alias Filter

External

Mute Control

Configuration

Internal Voltage

Reference Internal

Oscillator

Volume

Control

Mixer

Selectable

Interpolation

Filter

Selectable

Interpolation

Filter

Reset Left

Differential

Output

Right

Differential

Output

Switched Capacitor

DAC and Filter

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

Low-Latency

Anti-Alias Filter

High Pass Filter &

DC Offset Calibration

High Pass Filter &

DC Offset Calibration

PCM Serial Interface / Loopback

Left

Differential

Input

Right

Differential

Input

Volume

Control

Level TranslatorLeve l Translator

Serial

Audio

Input

Serial

Audio

Output

3.3 V to 5 V 5 V

Hardware or

I2C/SPI

Control D ata

Switched Capacitor

DAC and Filter

AUGUST '05

DS593F1

CS4272

2DS593F1

Stand-Alone Mode Feature Set

!System Features

– Serial Audio Port Master or Slave Operation

– Internal Oscillator for Master Clock

!D/A Features

– Auto-mute on Static Samples

– 44.1 kHz 50/15 µs De-emphasis Available

– Selectable Serial Audio In terface Formats

"Left Justified up to 24-bit

"I2S up to 24-bit

!A/D Features

– Automatic Dithering for 16-bit Data

– High-pass Filter

– Selectable Serial Audio In terface Formats

"Left Justified up to 24-bit

"I2S up to 24-bit

Software Mode Feature Set

!System Features

– Serial Audio Port Master or Slave Operation

– Internal Oscillator for Master Clock

– Internal Digital Loopback Available

!D/A Features

– Selectable Auto-mute

– Selectable Interpolation Filters

– Selectable 32-, 44.1-, and 48-kHz De-emphasis

Filters

– Configurable ATAPI Mixing Functions

– Configurable Volume and Muting Controls

– Selectable Serial Audio In terface Formats

"Left Justified up to 24-bit

"I2S up to 24-bit

"Right Justified 16, 18, 20, and 24-bit

!A/D Features

– Selectable Dithering for 16-bit Da ta

– Selectable High-pass Filter or DC Offset Calibration

– Selectable Serial Audio In terface Formats

"Left Justified up to 24-bit

"I2S up to 24-bit

General Description

The CS4272 is a high-performance, integrated audio

CODEC. The CS4272 perfor ms stereo an alog-to-dig ital

(A/D) and digital-to-analog (D/A) conversion of up to

24-bit serial values at sample rates up to 192 kHz.

The D/A offers a volume control that operates with a

1 dB step size. It incorporates selectable soft ramp and

zero crossing transition functions to eliminate clicks and

pops.

The D/A’s integrated digital mixin g functions allow a va-

riety of output configurations ranging from a channel

swap to a stereo-to-mono do wnmix.

Standard 50/15 µs de-emphasis is available for sam-

pling rates of 32, 44.1, and 48 kHz for compatibility with

digital audio programs mastered using the 50/15 µs pre-

emphasis technique.

Integrated level translators allow easy interfacing be-

tween the CS4272 and other devices operating over a

wide range of logic levels.

An on-chip oscillator eliminates the need for an external

crystal oscillator circuit. This can reduce overall design

cost and conserve circuit board sp ace. The CS4272 au-

tomatically uses the on-chip oscillator in the absence of

an applied master clock, making this feature easy to

use.

Independently addressable high-pass filters are avail-

able for the right and left channel of the A/D. This allows

the A/D to be used in a wide variety of applications

where one audio channel and one DC measurement

channel is desired.

The CS4272’s wide dynamic range, negligible distor-

tion, and low noise make it ideal for applications such as

A/V receivers, DVD-R, CD-R, digital mixing consoles,

effects processors, set-top box systems, and automo-

tive audio systems.

Ordering Information

Product Description Package Pb-Free Grade Temp Range Container Order #

CS4272 24-Bit, 192 kHz

Stereo Audio CODEC 28-pin

TSSOP YES Commercial -10° to +70° C Tube CS4272-CZZ

Tape & Reel CS4272-CZZR

Automotive -40° to +85° C Tube CS4272-DZZ

Tape & Reel CS4272-DZZR

CDB4272 CS4272 Evaluation Board No - - - CDB4272

CS4272
DS593F1 3
TABLE OF CONTENTS
 PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 5
 PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 7
 CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 9
SPECIFIED OPERATING CONDITIONS................................................................................. 9
ABSOLUTE MAXIMUM RATINGS........................................................................................... 9
DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE............................................ 10
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ............................................ 11
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 12
ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE............................................ 14
ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ............................................ 15
ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 16
DC ELECTRICAL CHARA CTERISTIC S ...... .... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ......... 17
DIGITAL CHARACTERISTICS............................................................................................... 17
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 18
SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT....................................... 21
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................. 22
 TYPICAL CONNECTION DIAGRAM  ..................................................................................... 23
 APPLICATIONS  ..................................................................................................................... 24
1 Stand-Alone Mode .... ................. ... ... ... ................ .... ... ................ ... ... .... ................ ... ... ......24
1.1 Recommended Power-Up Sequence  ................................................................. 24
1.2 Master/Slave Mode ....................... ... ................................................................... 24
1.3 System Clock ing .... ... ................ .... ... ................ ... ................ .... ... ................ ... ...... 24
1.3.1 Crystal Applications (XTI/XTO) ........................................................... 24
1.3.2 Clock Ratio Selection .......................................................................... 25
1.4 16-Bit Auto-Dither  ............................................................................................... 26
1.5 Auto-Mute  ..................... ... ... ................ ... .... ................ ... ................ ... .... ............... 26
1.6 High Pass Filter ................................................................................................... 26
1.7  Interpolation Filter .............................................................................................. 26
1.8 Mode Selection & De-Emphasis ............ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ... 26
1.9 Serial Audio Interface Format Selection  ............................................................. 26
2 Control Port Mode  ........... ... ... .... ... ... ... ... .... ... ................ ... .... ... ... ................ ... .... ... ... ......... 27
2.1 Recommended Power-Up Sequence - Access to Control Port Mode  ................ 27
2.2 Master / Slave Mode Selection ........ ... ... .... ... ................ ... ... .... ... ... ... ................ ... 27
2.3 System Clock ing .... ... ................ .... ... ................ ... ................ .... ... ................ ... ...... 27
2.3.1 Crystal Applications (XTI/XTO) ........................................................... 27
2.3.2 Clock Ratio Selection .......................................................................... 28
2.4 Internal Digital Loopback   .... ... ... .... ... ... ... ................. ... ... ... ... ................. ... ... ... ... ... 30
2.5 Dither for 16-Bit Data .......................................................................................... 30
2.6 Auto-Mute  ..................... ... ... ................ ... .... ................ ... ................ ... .... ............... 30
2.7 High Pass Filter and DC Offset Calibration ......................................................... 30
2.8  Interpolation Filter .............................................................................................. 31
2.9 De-Emphasis  ...... ... ... .... ... ... ... ... .... ................ ... ... .... ................ ... ... ................ ... ... 31
2.10 Oversampling Modes ........................................................................................ 31
3 De-Emphasis Filter .......................................................................................................... 31
4 Analog Connections  ........ ... ... .... ... ... ... ... .... ................ ... ... .... ... ................ ... ... .... ... ............ 32
4.1 Input Connections ............... ... ... ................. ... ... ... ................ .... ... ................ ... ... ... 32
4.2 Output Connections ............ ... ... .... ... ................ ... .... ... ... ................ ... .... ... ... ......... 33
5 Mute Control .... ... ................ ... .... ... ................ ... ... ................. ... ... ... ................ .... ... ... ......... 34
6 Synchronization of Multiple Devices ................................................................................ 34
7 Grounding and Power Supply Decoupling ....................................................................... 34
 CONTROL PORT INTERFACE .............................................................................................. 35

CS4272
4DS593F1
1 SPI Mode .................. .... ... ................ ... ... .... ................ ... ... ................ .... ... ... ......................35
2 I²C Mode ................... ................. ... ... ................ ... .... ... ................ ... ... .... ................ ... .........36
 REGISTER QUICK REFERENCE  ..........................................................................................37
 REGISTER DESCRIPTION  ....................................................................................................38
1 Mode Control 1 - Address 01h ... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ................ ... ...38
1.1 Functional Mode (Bits 7:6) ..................................................................................38
1.2 Ratio Select (Bits 5:4)  ............... .... ... ... ................ .... ... ... ................ ... .... ...............38
1.3 Master / Slave Mode (Bit 3)  .............. ... ... .... ... ................ ... ... .... ... ... ................ ... ...38
1.4 DAC Digital Interface Format (Bits 2:0) ...............................................................38
2 DAC Control - Address 02h  ................... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ... ...39
2.1 Auto-Mute (Bit 7) ........... ... ... ... ... .... ................ ... ... .... ... ................ ... ... .... ...............39
2.2 Interpolation Filter Select (Bit 6) ..........................................................................39
2.3 De-Emphasis Control (Bits 5:4) ........ ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ...39
2.4 Soft Volume Ramp-Up After Error (Bit 3) ............................................................40
2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2) ..........................................40
2.6 Invert Signal Polarity (Bits 1:0) ................................ ... ... ... ... .... ... ................ ... ... ...40
3 DAC Volume & Mixing Control - Address 03h  ..................... ... ... ... ... .... ... ... ... .... ... ... ... ... ...40
3.1 Channel B Volume = Channel A Volume (Bit 6)  ........... ... ... .... ... ... ... .... ... ... .........40
3.2 Soft Ramp or Zero Cross Enable (Bits 5:4) .........................................................40
3.3 ATAPI Channel Mixing and Muting (Bits 3:0) ......................................................41
4 DAC Channel A Volume Control - Address 04h  ..............................................................42
5 DAC Channel B Volume Control - Address 05h  ..............................................................42
5.1 Mute (Bit 7) ..........................................................................................................42
5.2 Volume Control (Bits 6:0) .......... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ...............42
6 ADC Control - Address 06h  ................... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ... ...43
6.1 Dither for 16-Bit Data (Bit 5) ................................................................................43
6.2 ADC Digital Interface Format (Bit 4) ....................................................................43
6.3 ADC Channel A & B Mute (Bits 3:2) .... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... ...43
6.4 Channel A & B High Pass Filter Disable (Bits 1:0) ..... ... ... ... .... ... ... ... .... ... ............43
7 Mode Control 2 - Address 07h ... ... ... ... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ...43
7.1 Digital Loopback (Bit 4) ....... ... ... ................. ... ... ... .... ................ ... ... ... .... ...............43
7.2 AMUTEC = BMUTEC (Bit 3) ............................................................................... 43
7.3 Freeze (Bit 2)  ... ... ... ... .... ... ... ................ ... .... ... ................ ... ... ................. ... ... .........44
7.4 Control Port Enable (Bit 1) ..... ... .... ......................................................................44
7.5 Power Down (Bit 0)  .............................................................................................44
8 Chip ID - Register 08h  .....................................................................................................44
8.1 Chip ID (Bits 7:4) .................................................................................................44
8.2 Chip Revision (Bits 3:0) .......................................................................................44
 PARAMETER DEFINITIONS ..................................................................................................45
 PACKAGE DIMENSIONS .....................................................................................................46
 APPENDIX ............ ... ... ... .... ................ ... ... ... ................. ... ... ................ ... .... ... ......................... 47

CS4272

DS593F1 5

1. PIN DESCRIPTIONS - SOFTWARE MODE

XTO BMUTEC

XTI AOUTB-

MCLK AOUTB+

LRCK AOUTA+

SCLK AOUTA-

SDOUT AMUTEC

SDIN FILT+

DGND AGND

VD VA

VL AINB-

SCL/CCLK AINB+

SDA/CDIN AINA+

AD0/CS AINA-

RST VCOM

821

12 17

14 15

28-Pin TSSOP

CS4272

6DS593F1

Pin Name #Pin Description

XTO

XTI 1,2 Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate

MCLK. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27.

MCLK 3Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications

(XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27.

LRCK 4Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audi o da ta line.

SCLK 5Serial Clock (Input/Output) - Serial clock for the serial audio interface.

SDOUT 6Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

SDIN 7Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

DGND 8Digital Ground (Input) - Ground reference for the internal digital section.

VD 9Digital Power (Input) - Positive power for the internal digital section.

VL 10 Logic Power (Input) - Positive power for the digital input/output interface.

SCL/CCLK 11 Serial Control Port Clock (Input) - Serial clock for the serial control port.

SDA/CDIN 12 Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDIN is the input data line for the

control port interface in SPI mode.

AD0/CS 13 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS

is the chip select signal for SPI format.

RST 14 Reset (Input) - The device enters a low power mode when this pin is driven low.

VCOM 15 Common Mode Voltage (Output) - Filter connection for internal common mode voltage.

AINA-

AINA+

AINB+

AINB-

16,

17,

18,

Differential Analog Inpu t (Input) - The full scale differenti al input signals are presented to the delta-

sigma modulators. The full scale level is specified in the ADC Analog Characteristics specification table.

VA 20 Analog Power (Input) - Positive power for the internal analog section.

AGND 21 Analog Ground (Input) - Ground reference for the internal analog section.

FILT+ 22 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circ ui ts.

AMUTEC 23 Channel A Mut e Contr ol (Output) - This pin is active during power-up initialization, reset, muting, when

master clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA-

AOUTA+

AOUTB+

AOUTB-

24,

25,

26,

Differential Analog Audio Output (Output) - The full scale differential ou tput level is specified in the

DAC Analog Characteristics specification table.

BMUTEC 28 Channel B Mut e Contr ol (Output) - This pin is active during power-up initialization, reset, muting, when

master clock to left/right clock frequency ratio is incorrect, or power-down.

CS4272

DS593F1 7

2. PIN DESCRIPTIONS - STAND-ALONE MODE

XTO BMUTEC

XTI AOUTB-

MCLK AOUTB+

LRCK AOUTA+

SCLK AOUTA-

SDOUT (M/S)AMUTEC

SDIN FILT+

DGND AGND

VD VA

VL AINB-

M0 AINB+

M1 AINA+

I2S/LJ AINA-

RST VCOM

821

12 17

14 15

28-Pin TSSOP

CS4272

8DS593F1

Pin Name #Pin Description

XTO

XTI 1,2 Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate the

master clock. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on

page 27.

MCLK 3Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications

(XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27.

LRCK 4Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audi o da ta line.

SCLK 5Serial Clock (Input/Output) - Serial clock for the serial audio interface.

SDOUT

(M/S)6Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be

pulled-up or pulled-down to select Master or Slave Mode. See “Master/Slave Mode” on page 24.

SDIN 7Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

DGND 8Digital Ground (Input) - Ground reference for the internal digital section.

VD 9Digital Power (Input) - Positive power for the internal digital section.

VL 10 Logic Power (Input) - Positive power for the digital input/output interface.

M0 11 Mode Select 0 (Input) - In conjunction with M1, selects operating mode. Functionality is described in the

Hardware Mode Speed Configuration table.

M1 12 Mode Select 1 (Input) - In conjunction with M0, selects operating mode. Functionality is described in the

Hardware Mode Speed Configuration table.

I2S/LJ 13 Serial Audio Interface Select (Input) - Selects either the left-justified or I2S format for the Serial Audio

Interface.

RST 14 Reset (Input) - The device enters a low power mode when this pin is driven low.

VCOM 15 Common Mode Voltage (Output) - Filter connection for internal common mode voltage.

AINA-

AINA+

AINB+

AINB-

16,

17,

18,

Differential Analog Inpu t (Input) - The full scale differenti al input signals are presented to the delta-

sigma modulators. The full scale level is specified in the ADC Analog Characteristics specification table.

VA 20 Analog Power (Input) - Positive power for the internal analog section.

AGND 21 Analog Ground (Input) - Ground reference for the internal analog section.

FILT+ 22 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circ ui ts.

AMUTEC 23 Channel A Mut e Contr ol (Output) - This pin is active during power-up initialization, reset, muting, when

master clock to left/right clock frequency ratio is incorrect, or power-down.

AOUTA-

AOUTA+

AOUTB+

AOUTB-

24,

25,

26,

Differential Analog Audio Output (Output) - The full scale differential ou tput level is specified in the

Analog Characteristics specification table.

BMUTEC 28 Channel B Mut e Contr ol (Output) - This pin is active during power-up initialization, reset, muting, when

master clock to left/right clock frequency ratio is incorrect, or power-down.

CS4272

DS593F1 9

3. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measu rements taken at nominal supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device .

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

Parameters Symbol Min Nom Max Units

DC Power Supplies: Positive Analog

Positive Digital

Positive Logic

4.75

3.1

2.37

5.0

3.3

5.25

Ambient Operating Temperature (Power Applied)

Commercial Grad e

Automotive Grade TA-10

-40 -

-+70

+85 °C

°C

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Logic

Digital

-0.3

+6.0

Input Current (Note 2) Iin --±10 mA

Analog Input Voltage VIN GND-0.3 - VA+0.3 V

Digital Input Voltage VIND -0.3 - VL+0.3 V

Ambient Operating Temperature (Power Applied) TA-50 - +95 °C

Storage Temperature Tstg -65 - +150 °C

CS4272

10 DS593F1

DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Notes 3 to 7)

Notes: 3. One-half LSB of Triangular PDF dither is added to data.

4. Performance me asurements ta ken with a full-scale 997 Hz sine wave under Te st load RL = 3 kΩ, CL =

10 pF

5. Measurement bandwidth is 10 Hz to 20 kHz.

6. Logic “0” = GND = 0V; Logic “1” = VL; VL = VA unless otherwise noted.

7. VFS is tested under load RL but does not include attenuation due to Z OUT

Parameter Symbol Min Typ Max Unit

Dynamic Performance

Dynamic Range 24-Bits A-Weighted

unweighted

16-Bits unweighted

108

105

114

111

Total Harmonic Distortion + Noise 0 dB

-20 dB

-60 dB

THD+N -

-100

-91

-51

-94

-45

Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch ICGM - 0.1 - dB

Gain Drift - 100 - ppm/°C

Analog Output Characteristics and Specifications

Full Scale Differential Output Voltage VFS 0.91xVA 0.96xVA 1.01xVA Vpp

Output Resistance (note 7) Zout - 100 - Ω

Minimum AC-Load Resistance RL-3-kΩ

Maximum Load Capacitance CL- 100 - pF

CS4272

DS593F1 11

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (Notes 3 to 7)

Parameter Symbol Min Typ Max Unit

Dynamic Performance

Dynamic Range 24-Bits A-Weighted

unweighted

16-Bits unweighted

106

103

114

111

Total Harmonic Distortion + Noise 0 dB

-20 dB

-60 dB

THD+N -

-100

-91

-51

-92

-43

Idle Channel Noise / Signal-to-Noise Ratio - 114 - dB

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch ICGM - 0.1 - dB

Gain Drift - 100 - ppm/°C

Analog Output Characteristics and Specifications

Full Scale Differential Output Voltage VFS 0.91xVA 0.96xVA 1.01xVA Vpp

Output Resistance (note 7) Zout - 100 - Ω

Minimum AC-Load Resistance RL-3-kΩ

Maximum Load Capacitance CL- 100 - pF

CS4272

12 DS593F1

DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(Note 12)

Parameter Fast Roll-Off UnitMin Typ Max

Single Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.454

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

StopBand .547 - - Fs

StopBand Attenuation (Note 10) 90 - - dB

Group Delay - 12/Fs - s

De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1kHz) Fs = 44.1 kHz

Fs = 48 kHz

±0.23

±0.14

±0.09

Double Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.430

.499 Fs

Frequency Resp onse 10 Hz to 20 kHz -0.01 - 0.01 dB

StopBand .583 - - Fs

StopBand Attenuation (Note 10) 80 - - dB

Group Delay - 4.6/Fs - s

Quad Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.105

.490 Fs

Frequency Resp onse 10 Hz to 20 kHz -0.01 - 0.01 dB

StopBand .635 - - Fs

StopBand Attenuation (Note 10) 90 - - dB

Group Delay - 4.7/Fs - s

CS4272
DS593F1 13
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(cont) (N ot e 12 )
Notes: 8. Slow Roll-Off interpolation filter is only available in control port mode.
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 21 to 44) have 
been normalized to Fs and can be de-no rmalized  by multiplying the X-axis scale by Fs.
10. Single and Double Speed Mode Measuremen t Bandwidth is from stopband to 3 Fs. 
Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-
Alone Mode.
12. Plots of this data are contained in the “Appendix” on pag e 47. See Figure 21 through Figure 44.
Parameter Slow Roll-Off (Note 8) UnitMin Typ Max
Single Speed Mode - 48 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-0.417
0.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 64 - - dB
Group Delay  - 6.5/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.23
±0.14
±0.09
dB
dB
dB
Double Speed Mode - 96 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-.296
.499 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .792 - - Fs
StopBand Attenuation (Note 10) 70 - - dB
Group Delay - 3.9/Fs - s
Quad Speed Mode - 192 kHz 
Passband (Note 9)  to -0.01 dB corner
to -3 dB corner 0
0-
-.104
.481 Fs
Fs
Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB
StopBand .868 - - Fs
StopBand Attenuation (Note 10) 75 - - dB
Group Delay - 4.2/Fs - s

CS4272

14 DS593F1

ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.

Notes: 13. Referred to the typical full-scale input voltage.

Notes: 14. Measured between AIN+ and AIN-

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 108

105 114

111 -

-dB

Total Harm onic Distortion + Noise (Note 13)

-1 dB

-20 dB

-60 dB

THD+N -

-100

-91

-51

-94

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harm onic Distortion + Noise (Note 13)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-94

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harm onic Distortion + Noise (Note 13)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-94

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -±5%

Gain Drift - ±100 - ppm/°C

Offset Error HPF enabled

HPF disabl ed -

-0

100 -

-LSB

LSB

Analog Input Characteristics

Full-scale Input Voltage 1.07xVA 1.13xVA 1.19xVA Vpp

Input Impedance (Dif ferential) (Note 14) 37 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS4272

DS593F1 15

ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE

Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.)

Notes: 15. Referred to the typical full-scale input voltage.

Notes: 16. Measured between AIN+ and AIN-

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 106

103 114

111 -

-dB

Total Harm onic Distortion + Noise (Note 15)

-1 dB

-20 dB

-60 dB

THD+N -

-100

-91

-51

-92

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

Total Harm onic Distortion + Noise (Note 15)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-92

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

Total Harm onic Distortion + Noise (Note 15)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-92

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -±5%

Gain Drift - ±100 - ppm/°C

Offset Error HPF enabled

HPF disabl ed -

-0

100 -

-LSB

LSB

Analog Input Characteristics

Full-scale Input Voltage 1.07xVA 1.13xVA 1.19xVA Vpp

Input Impedance (Dif ferential) (Note 16) 37 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS4272
16 DS593F1
ADC DIGITAL FILTER CHARACTERISTICS          (Note 19)
Notes: 17. The filter frequency response scales precisely with Fs.
18. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
19. Plots of this data are contained in the “Appendix” on page 47. See Figure 45 through Figure 56.
Parameter Symbol Min Typ Max Unit
Single Speed Mode
Passband (-0.1 dB).  (Note 17) 0 - 0.47 Fs
Passband Ripple.  - - ±0.035 dB
Stopband. (Note 17) 0.58 - - Fs
Stopband Attenuation.  -95 - - dB
Group Delay.  tgd -12/Fs- s
Double Speed Mode
Passband (-0.1 dB).  (Note 17) 0 - 0.45 Fs
Passband Ripple.  - - ±0.035 dB
Stopband. (Note 17) 0.68 - - Fs
Stopband Attenuation.  -92 - - dB
Group Delay.  tgd -9/Fs- s
Quad Speed Mode
Passband (-0.1 dB).  (Note 17) 0 - 0.24 Fs
Passband Ripple.  - - ±0.035 dB
Stopband. (Note 17) 0.78 - - Fs
Stopband Attenuation.  -97 - - dB
Group Delay.  tgd -5/Fs- s
High Pass Filter Characteristics
Frequency Response -3.0 dB. 
-0.13 dB.  (Note 18) -1
20 -
-Hz
Hz
Phase Deviation @ 20 Hz.  (Note 18) - 10 - Deg
Passband Ripple.  - - 0 dB
Filter Settling Time.  105/Fs s

CS4272

DS593F1 17

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode)

Notes: 20. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

21. Valid with the recommended capacitor values on FILT+ and VCOM as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Power Supply

Power Supply Current VA

(Normal Operation) VL,VD = 5 V

VL,VD = 3.3 V

41.5

Power Supply Current VA

(Power-Down Mode)(Note 20) VL,VD=5 V IA

-0.025

1.76 -

-mA

Power Consumption VL, VD=5 V

(Normal Operation) VL, VD = 3.3 V

(Power-Down Mode)

433

305

510

358

Power Supply Rejection Ratio (1 kHz) (Note 21) PSRR - 60 - dB

Common Mode

Nominal Common Mode Voltage VCOM - 0.48xVA - VDC

Maximum DC Current Source/Sink from VCOM - 1 - µA

VCOM Output Impedance - 25 - kΩ

FILT+

FILT+ Nominal Voltage FILT+ - VA - VDC

MUTEC

MUTEC Low-Level Output Voltage - 0 - V

MUTEC High-Level Output Voltage - VA - V

Maximum MUTEC Drive Current - 3 - mA

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VL) VIH 70% - - V

Low-Level Input Voltage (% of VL) VIL --30%V

High-Level Output Voltage at Io = 2 mA VOH VL - 1.0 - - V

Low-Level Output Voltage at Io = 2 mA VOL --0.4V

Input Leakage Current Iin --±10 µA

CS4272

18 DS593F1

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;

Logic "1" = VL, CL = 20 pF)

Notes: 22. In Control Port Mode, the Ratio[1:0] bits must be configured according to tables 8 and 9 on

pages 28 and 29.

Parameter Symbol Min Typ Max Unit

Sample Rate Single Speed Mode

Double Speed Mode

Quad Speed Mode

100

200

kHz

MCLK Specifications

MCLK Frequency Stand-Alone Mode

(note 22) Control Port Mode fmclk

fmclk 1.024

1.024 -

-25.600

51.200 MHz

MHz

MCLK Input Pulse Width High/Low Stand-Alone Mode

(note 22) Control Port Mode tclkhl

tclkhl 16

-ns

MCLK Output Duty Cycle 45 50 55 %

Master Mode

LRCK Duty Cycle - 50 - %

SCLK Duty Cycle - 50 - %

SCLK falling to LRCK edge tslr -10 - 10 ns

SCLK falling to SDOUT valid tsdo 0 - 32 ns

SDIN valid to SCLK rising setup time tsdis 16 - - ns

SCLK rising to SDIN hold time tsdih 20 - - ns

Slave Mode

LRCK Duty Cycle 40 50 60 %

SCLK Period

(note 22) Single Speed Mode

Double Speed Mode

Quad Speed Mode

tsclkw

SCLK Pulse Width High tsclkh 30 - - ns

SCLK Pulse Width Low tsclkl 48 - - ns

SCLK falling to LRCK edge tslr -10 - 10 ns

SCLK falling to SDOUT valid tsdo 0 - 32 ns

SDIN valid to SCLK rising setup time tsdis 16 - - ns

SCLK rising to SDIN hold time tsdih 20 - - ns

Crystal Oscillator Specifications (XTI/XTO)

Crystal Frequency Range fosc 16.384 - 25.600 MHz

128()Fs

---------------------

128()Fs

---------------------

64()Fs

------------------

CS4272

DS593F1 19

sdis

slr

SDOUT

SCLK

Output

LRCK

Output

SDIN

sdo

sdih

sdis

slr

SDOUT

SCLK

Input

LRCK

Input

SDIN

sdo

sdih

sclkh

tsclkl

sclkw

Figure 1. Master Mode Serial Audio Port Timing

Figure 2. Slave Mode Serial Audio Port Timing

CS4272

20 DS593F1

Figure 3. Format 0, Left Justified up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5 +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

Figure 4. Format 1, I²S up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5 +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

LRCK

SCLK

Left Channel

SDATA +5 +4 +3 +2 +1 LSB

MSB-1-2-3-4-5

32 clocks

Right Channel

LSB +5 +4 +3 +2 +1 LSB

MSB - 1 - 2 - 3 - 4 -5

-6 +6

-6

Figure 5. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only)

Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only)

Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)

Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)

CS4272

DS593F1 21

SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT

(Inputs: logic 0 = AGND, logic 1 = VL)

Notes: 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Parameter Symbol Min Max Unit

I²C Mode

SCL Clock Frequency. fscl -100KHz

RST Rising Edge to Start. tirs 500 - ns

Bus Free Time Between Transmissions. tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse). thdst 4.0 - µs

Clock Low time. tlow 4.7 - µs

Clock High Time. thigh 4.0 - µs

Setup Time for Repeated S tart Condition. tsust 4.7 - µs

SDA Hold Time from SCL Falling. (Note 23) thdd 0-µs

SDA Setup time to SCL Rising. tsud 250 - ns

Rise Time of Both SDA and SCL Lines. tr-1µs

Fall Time of Both SDA and SCL Lines. tf-300ns

Setup Time for Stop Condition. tsusp 4.7 - µs

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 6. I²C Mode Control Port Timing

CS4272

22 DS593F1

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(Inputs: logic 0 = AGND, logic 1 = VL)

Notes: 24. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

25. Data must be held for sufficient time t o br idg e the tra n sitio n tim e of CCLK.

26. For FSCK < 1 MHz

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency. fsclk -6MHz

RST Rising Edge to CS Falling. tsrs 500 - ns

CCLK Edge to CS Falling. (Note 24) tspi 500 - ns

CS High Time Between Transmissions. tcsh 1.0 - µs

CS Falling to CCLK Edge. tcss 20 - ns

CCLK Low Time. tscl 82 - ns

CCLK High Time. tsch 82 - ns

CDIN to CCLK Rising Setup Time. tdsu 40 - ns

CCLK Rising to DATA Hold Time. (Note 25) tdh 15 - ns

Rise Time of CCLK and CDIN. (Note 26) tr2 -100ns

Fall Time of CCLK and CDIN. (Note 26) tf2 -100ns

tr2 tf2

dsu

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 7. SPI Control Port Timing

CS4272

DS593F1 23

4. TYPICAL CONNECTION DIAGRAM

)LJ(I2S/ CS / AD0

SDA / CDIN (M1)

SCL / CC LK (M 0)

AINA+

AINA-

AINB+

AINB-

RST

Power Down

and Mode

Settings

(Control Port)

XTI

XTO

AOUTA-

AOUTA+

AMUTEC

AOUTB-

AOUTB+

BMUTEC

Analog Conditioning

Mute

LRCK

SCLK

MCLK Timing Logic

Clock

SDIN)S(M/ SDOUT Audio Data

Processor

DGND

FILT+

AGND

VCOM

VDVA

+5 V

+5 V to 3.3 V

CS4272

40 pF

¤ See "Master/Slave Mode Se lection".

+5 V to 2 .5 V

47 kΩ

5.1 Ω

** Optional. See "Crystal

Applications (XTI/XTO)".

Analog Input

Buffer

47 µF 0.1 µF

1 µF 0.1 µF

1 µF0.1 µF

* Only one must be used. See

"Grounding and Pow er Supply

De c o u p lin g ."

∗ Not to exceed 1 µF.

∗

Figure 8. CS4272 Typi ca l Conn e ction Diagram

CS4272

24 DS593F1

5. APPLICATIONS

5.1 Stand-Alone Mode

5.1.1 Recommended Power-Up Sequence

1) When using the CS4272 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are

stable. When using the CS4272 with inte rnally generated MCLK, ho ld RST low until the power supply is stable.

2) Bring RST high. If the internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from

the release of RST.

5.1.2 Master/Slave Mode

The CS4272 supports operation in either Master Mode or Slave Mode.

In Master Mode , LR CK and SCLK are o utputs a nd ar e sync hronously generated on-chip. LRCK is equal to Fs and

SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-

mended that SCLK be 64x Fs to maximize system performance.

In Stand-Alone Mode, the CS4272 will default to Slave Mode. Master Mode may be accessed by placing a 47 kΩ

pull-up to VL on the SDOUT (M/S) pin.

Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4.

5.1.3 System Clocking

The CS4272 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed

modes as shown in Table 1 below.

5.1.3.1 Crystal Applications (XTI/XTO)

An external crystal may be used in conjunction with the CS427 2 to generate the master clock signa l. To accomplish

this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as

shown in the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 2.

In this configuration, MCLK is a buffered output and, as shown in the Typical Connection Diagram, nothing other

than the crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the

MCLK pin prior to 1 ms from the release of RST.

To operate the CS4272 with an externally generated MCLK signal, no crystal should be used, XTI should be con-

nected to ground and XTO should be left unconnected. In this configuration, MCL K is an input an d must be dr iven

externally with an appropriate speed clock.

Table 1. Speed Modes

Mode Sampling Frequency

Single Speed 4-50 kHz

Double Speed 50-100 kHz

Quad Speed 100-200 kHz

Table 2. Crystal Frequencies

Mode Crystal Frequency

Single Speed 512 x Fs

Double Speed 25 6 x Fs

Quad Speed 128 x Fs

CS4272

DS593F1 25

5.1.3.2 Clock Ratio Selection

Depending on the use of an external crystal, or whether the CS4272 is in Master or Slave Mode, different

MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Tables 3 and 4 below.

Table 3. Clock Ratio s - Stand Alone Mode With External Crystal

External Crystal Used, MCLK=Output

Master Mode

MCLK/LRCK SCLK/LRCK LRCK

Single Speed 256 64 Fs

Double Speed 128 64 Fs

Quad Speed 128 64 Fs

Slave Mode

MCLK/LRCK SCLK/LRCK LRCK

Single Speed 256 32, 64, 128 Fs

Double Speed 128 32, 64 Fs

Quad Speed 128 32, 64 Fs

Table 4. Clock Ratios - Stand Alone Mode Without External Crystal

External Crystal Not Used , MCLK=Input

Master Mode

MCLK/LRCK SCLK/LRCK LRCK

Single Speed 256 64 Fs

Double Speed 128 64 Fs

Quad Speed 64 32 Fs

Slave Mode

MCLK/LRCK SCLK/LRCK LRCK

Single Speed 256 32, 64, 128 Fs

384 32, 48, 64, 96, 128 Fs

512 32, 64, 128 Fs

Double Speed 128 32, 64 Fs

192 32, 48, 64 Fs

256 32, 64 Fs

Quad Speed 64 32 Fs

96 48 Fs

128 32, 64 Fs

CS4272

26 DS593F1

5.1.4 16-Bit Auto-Dither

The CS4272 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK

to LRCK ratio is used. In this configura tion, one half of a bit of dith er is added to the LSB of the 16 -bit word. This

applies only to the serial audio output of the ADC and will not affect DAC performance. See Figure 9.

5.1.5 Auto-Mute

The DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sam-

ple of non-static data will release the mute. Detection and muting are done independently for each channel. The

common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute

period.

5.1.6 High Pass Filter

The operational amplifiers in the input circuitry driving the CS4272 may generate a small DC offset into the ADC.

The CS4272 includes a high pass filter after the decimator to remove any DC offset which could result in recording

a DC level, possibly yielding "clicks" when switching between devices in a multichannel system.

In Stand-Alone Mode, the high pass filter continuously subtracts a measure of the DC offset from the output of the

decimation filter. This function cannot be disabled in Stand-Alone Mode.

5.1.7 Interpolation Filter

In Stand-Alone Mode, the fast roll-off interpolation filter is used.

Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47.

5.1.8 Mode Selection & De-Emphasis

The sample rate, Fs, ca n be adju sted fro m 4 kHz to 200 kHz. In Stand-Alone Mo de, the CS42 72 must be set to th e

proper mode via the mode pins, M1 and M0. De-emphasis, optimized for a 44.1 kHz sampling frequency, is avail-

able.

5.1.9 Serial Audio Interface Format Selection

Either I2S or left justified serial audio data format may be selected in Stand-Alone Mode. The selection will affect

both the input and output format. Placing a 10 kΩ pull-up to VL on the I2S/LJ pin will select the I2S format, while

placing a 10 kΩ pull-down to DGND on the I2S/LJ pin will select the left justified format.

Table 5. CS4272 Stand-Alone Mode Control

Mode 1 Mode 0 Mode Sample Rate (Fs) De-Emphasis

0 0 Single Speed Mode 4 kHz - 50 kHz 44.1 kHz

0 1 Single Speed Mode 4 kHz - 50 kHz Off

1 0 Double Speed Mode 50 kHz - 100 kHz Off

1 1 Quad Speed Mode 100 kHz - 200 kHz Off

1 6-B it Wo rd

1514131211109876543210

½ B it Dith e r

Figure 9. ADC 16-Bit Auto-Dither

CS4272

DS593F1 27

5.2 Control Port Mode

5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode

1) When using the CS4272 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are

stable. When using the CS4272 with inte rnally generated MCLK, ho ld RST low until the power supply is stable.

In this state, the Control Port is reset to its default settings.

2) Bring RST high. The device will remain in a low power state and the control port will be accessible. If internally

generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from the release of RST.

3) Write 03h to register 07h within 10 ms following the release of RST. This sets the Control Port Enable (CPEN)

and Power Down (PDN) bits, activating the Control Port and placing the part in power-down. When using the

CS4272 with internally generated MCLK, it is necessary to wait 1 m s following the release of RST before initi-

ating this Control Port write.

4) The desired register settings can be loaded while keeping the PDN bit set.

5) Clear the PDN bit to initiate the power-up sequence. This power-up sequence requires approximately 85 µS.

5.2.2 Master / Slave Mode Selection

The CS4272 supports operation in either Master Mod e or Slave Mode.

In Master Mode , LR CK and SCLK are o utputs a nd ar e sync hronously generated on-chip. LRCK is equal to Fs and

SCLK is equal to 64x Fs.

In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-

mended that SCLK be 64x Fs to maximize system performance.

Configuration of clock ratios in each of these modes will be outlined in the Tables 8 and 9.

In Control Port Mode the CS4272 will default to Slave Mode. The user may change this default setting by changing

the status of the M/S bit in the Mode Control 1 register (01h).

5.2.3 System Clocking

The CS4272 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed

modes as shown in Table 6 below.

5.2.3.1 Crystal Applications (XTI/XTO)

An external crystal may be used in conjunction with the CS4272 to generate the MCLK signal. To accomplish this,

a 20 pF fundamental mode parallel resonant crystal must be conn ected between the XTI an d XTO pins as shown in

the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 7 . In this

configuratio n, MCL K is a bu ff er ed ou tp ut an d, as sh own in the Typical Connection Diagram, nothing other than the

crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the MCLK pin

prior to 1 ms from the release of RST.

Table 6. Speed Modes

Mode Sampling Frequency

Single Speed 4-50 kHz

Double Speed 50-100 kHz

Quad Speed 100-200 kHz

CS4272
28 DS593F1
To operate the CS4272 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCL K is an  input an d must  be dr iven
externally with an appropriate speed clock.
5.2.3.2 Clock Ratio Selection
Depending on the use of an external crystal, or whether the CS4272 is in Master or Slave Mode, different
MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Register Bits that must
be set in order to obtain them are shown in Tables 8 and 9 below.   
   
Notes: 27. For the Ratio1 and Ratio0 bits listed above, “d” indicates that any value may written.
Table 7. Crystal Frequencies
Mode Crystal Frequency
Single Speed 512 x Fs
Double Speed 25 6 x Fs
Quad Speed 128 x Fs
Table 8. Clock Ratios - Control Port Mode With External Crystal
External Crystal Used, MCLK=Output
Master Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed 256 64 Fs 0 d27
512 64 Fs 1 d27
Double Speed 128 64 Fs 0 d27
256 64 Fs 1 d27
Quad Speed 128 64 Fs d27 d27
Slave Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed 256 32, 64, 128 Fs 0 d27
512 32, 64, 128 Fs 1 d27
Double Speed 128 32, 64 Fs 0 d27
256 32, 64 Fs 1 d27
Quad Speed 128 32, 64 Fs d27 d27

CS4272
DS593F1 29
Notes: 28. For the Ratio0 bit listed above, “d” indicates that any value may written.
Table 9. Clock Ratios - Control Port Mode Without External Crystal
External Crystal Not Used , MCLK=Input
Master Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed
256 64 Fs 0 0
384 64 Fs 0 1
512 64 Fs 1 0
768 64 Fs 1 1
Double Speed
128 64 Fs 0 0
192 64 Fs 0 1
256 64 Fs 1 0
384 64 Fs 1 1
Quad Speed
64 32 Fs 0 0
96 32 Fs 0 1
128 64 Fs 1 0
192 64 Fs 1 1
Slave Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed
256 32, 64, 128 Fs 0 d28
384 32,  48, 64 , 96 , 12 8 Fs 0 d28
512 32, 64, 128 Fs 0 d28
768 32,  48, 64 , 96 , 12 8 Fs 1 d28
1024 32, 64, 12 8 Fs 1 d28
Double Speed
128 32, 64 Fs 0 d28
192 32, 48, 64 Fs 0 d28
256 32, 64 Fs 0 d28
384 32, 48, 64 Fs 1 d28
512 32, 64 Fs 1 d28
Quad Speed
64 32 Fs 0 d28
96 48 Fs 0 d28
128 32, 64 Fs 0 d28
192 48 Fs 1 d28
256 32, 64 Fs 1 d28

CS4272

30 DS593F1

5.2.4 Internal Digital Loopback

In Control Port Mo de, the CS4272 supports an inte rnal digital loopback mode in which th e output of the ADC is rout-

ed to the input of the DAC. This mode may be activated by se tting the LOOP bit in the Mode Contro l 2 register (07h).

When this bit is set, the status of the DAC_DIF(2:0) bits in register 01h will be disregarded by the CS4272. Any

changes made to the DAC_DIF(2:0) bits while the LOOP bit is set will have no impact on operation until the LOOP

bit is released, at which time the Digital Interface Format of the DAC will operate according to the format selected in

the DAC_DIF(2:0) bits. While the LOOP bit is set, data will be present on the SDOUT pin in the format selected in

the ADC_DIF bit in register 06h.

5.2.5 Dither for 16-Bit Data

The CS4272 may be configured to properly dither for 16-bit data. To do this, the Dither16 bit in the ADC Control

Register (06h) must be set. When set, a half bit of dither is added to the least significant bit of the 16 most significant

bits of the data word. The remaining bits should be disregarded. See Figure 10. This function is useful when 16-bit

devices are downstream of the ADC. This bit should not be set when using word lengths greater than 16 bits.

It should be noted that this function is supported for all serial audio output formats, and may be activated in either

Master or Slave Mo d e.

5.2.6 Auto-Mute

The Auto-Mute fu nction is controlled by the sta tus of the AMUTE bit in the DAC Control re gister. When set, the DAC

output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-

static data will release the mute. Detection and muting are done independently for each channel. Auto-Mute detec-

tion and muting can become dependent on either channel if the MUTECA=B function is enabled. The common mode

on the output will be retained and the Mute Control pin for that channel will become active during the mute period.

The muting function is effected, similar to volume control changes, by the Soft and ZeroCross bits in the DAC Vol-

ume and Mixing Control register. The AMUTE bit is set by default.

5.2.7 High Pass Filter and DC Offset Calibration

The operational amplifie rs in the input circuitry driving the CS4272 may generate a small DC offset into the A/D con-

verter. The CS4272 includes a high pass filter after the decimator to remove any DC offset which could result in

recording a DC level, possibly yielding "clicks" when switching betw een de vices in a multichann e l syste m .

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The

high pass filter can be independe ntly enabled an d disabled for ch annels A and B. If th e HPFDisableA or HPF Dis-

ableB bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen

and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform

a system DC offset calibration by:

1) Running the CS4272 with the high pass filter enable d until the filter settles. See the Dig ital Filter Characteristics

for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

16-Bit Word

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Disregard Contents

½ Bit Dithe r

Figure 10. Example of Dither for 16-Bit Data with 24-Bit Left Justified Format

CS4272

DS593F1 31

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration

point and the CS4272.

5.2.8 Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS4272 incorporates select-

able interpolation filters for each mode of operation. Fast and slow roll-off filte rs are available in each of Single, Dou-

ble, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and

styles. The FILT_SEL bit in the DAC Control register (02h) is used to select which filter is used. By default, the fast

roll-off filter is selected.

Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47.

5.2.9 De-Emphasis

Three de-emphasis modes are available via the Control Port. The available filters are optimized for 32 kHz,

44.1 kHz, and 48 kHz sampling rates. See Table 13 for de-emphasis selection in Control Port Mode.

5.2.10 Oversampling Modes

The CS4272 operates in one of three oversampling modes based on the input sample rate. Mode selection is de-

termined by the M1 and M0 bits in the Mode Co ntrol 1 re gister. Single-Speed mode supports input sample rates up

to 50 kHz and uses a 128x oversampling ra tio. Double-Speed mode supports input sample rates up to 1 00 kHz and

uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an over-

sampling ratio of 32x. See Table 11 for Control Port Mode settings.

5.3 De-Emphasis Filter

The CS4272 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz.

The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please

see section 5.1.8 for the desired de-emphasis control for Stand-Alone mod e and section 5.2.9 for control port mode.

The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µS pre-emphasis equal-

ization as a means of noise reduction.

De-emphasis is only available in Single Speed Mode.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10. 61 k Hz

Figure 11. De-Emphasis Curve

CS4272

32 DS593F1

5.4 Analog Connections

5.4.1 Input Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals with-

in the stopband of the filter. However, there is no rejection for input signals which are (n ×6. 144 MHz) the digit al

passband frequency, where n=0,1,2,... Refer to Figure 12 for a recommended analog input buffer that will attenuate

any noise energy at 6.144 MHz, in addition to providing the optimum so urce impedance for the modulato rs. The use

of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since

these can degrade signal linearity. Figure 13 shows the full-scale analog input levels.

AIN+

AIN-

VCOM

470 pF

C0G

470 pF

C0G

CS4272

634 Ω

91 Ω

634 Ω

91 Ω

2700 pF

C0G

10 µF

10 kΩ

10 kΩ0. 01 µF

1 µF0.1 µF

Figure 12. CS4272 Recommended Analog Input Buffer

AIN+

AIN-

CS4272

AIN+

AIN-

Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp

3.9 V

2.5 V

1.1 V

3.9 V

2.5 V

1.1 V

Figure 13. Full-Scale Analog Input

CS4272

DS593F1 33

5.4.2 Output Connections

The recommended output filter configuration is shown in Figure 14. This filter configuration accounts for the normally

differing AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration

which minimizes the number of requir ed AC coupling capacitors.

The CS4272 does not include phase or amplitude compensation for an external filter, and therefore the DAC system

phase and amplitude response will be dependent on the external analog circuitry. Figure 15 shows the full-scale an-

alog output levels.

AOUT+

AOUT- -

470 pF

C0G

CS4272

560 Ω

22 µF

4.99 kΩ

2200 pF

C0G

715 Ω

2.32 kΩ

4.42 kΩ

1.33 kΩ

1.50 kΩ22 µF

1.5 nF

C0G

6.8 nF

C0G

47 kΩ

Analog

Out

Figure 14. CS4272 Recommended Analog Output Filter

CS4272

AOUT+

AOUT-

Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp

3.75 V

2.5 V

1.25 V

3.75 V

2.5 V

1.25 V

Figure 15. Full-Scale Analog Output

CS4272

34 DS593F1

5.5 Mute Control

The Mute Control pins become active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is in-

correct, and during power-down. The Auto-Mute function causes the MUTEC pin corresponding to an individual

channel to activate following the reception of 8192 consecutive audio samples of static 0 or -1 on the respective

channel. A single sample of non-zero data on this channel will cause the MUTEC pin to deactivate. In Control Port

Mode, however, auto -mute dete ction and muting can beco me depende nt on either channel if the MuteB=A fun ction

is enabled. The MUTEC pins are intended to be used as control for an external mute circuit in order to add off-chi p

mute capability.

Use of the Mute Control function is not mandatory but re commended for d esigns requir ing the absolute minimu m in

extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle

channel noise/signal-to -noise ratios which are only limited by the external mute circuit. The MUTEC pins are active-

low. See Figure 16 below for a suggested active-low mute circuit.

5.6 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure

synchronous sampling, the MCLK and LRCK must be the same for all of the CS4272’s in the system. If onl y one

MCLK source is needed, one solution is to place one CS4272 in Master Mode, and slave all of the other CS4272’s

to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the

same external source and time the CS4272 reset with the inactive edge of MCLK. This will ensure that all converters

begin sampling on the same clock edge.

5.7 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4272 requires careful attention to power supply and grounding arrange-

ments if its potential per formance is to be realized. Figure 8 shows the recommended power arrangements, with VA

and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply

(VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be

powered from VD. Power supply decoupling capacitors should be as near to the CS4272 as possible, with the low

value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away fr om the VREF and

VCOM pins in order to avoi d un wanted co up ling into t he mod ulator s. T he VREF a nd VCOM de co uplin g capacitors,

particularly the 0.1 µF, must be positioned to minimize the electrical path from VREF and AGND. The CDB4272

evaluation board demonstrates the optimum layout and power supply arrangements. To mi nimize digital noise, con-

nect the CS4272 digital outputs only to CMOS inputs.

LPF

+VEE

-VEE

560 ΩAudio

Out

2 kΩ

10 kΩ

-VEE

+VA

MMUN2111LT1

AOUT

MUTEC

CS4272

Couple

47 kΩ

Figure 16. Suggested Active-Low Mute Circuit

CS4272

DS593F1 35

6. CONTROL PORT INTERFACE

The Control Port is used to load all the internal settings of the CS4272. The operation of the Control Port may be

completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control

Port pins should remain static if no operation is required.

The Control Port has 2 modes: SPI and I²C, with the CS4272 operating as a slave to control messages in both

modes. If I²C operation is desired, AD0/CS should be tied to VA or AGND. If the CS4272 ever dete cts a high to low

transition on AD0/CS after power-up, SPI mode will be selected. The Control Port registers are write-only in SPI

mode.

Upon release of the RST pin, the CS4272 will wait approximately 10 ms before it begins its start-up sequence. The

part default s to Sta nd-Alon e Mo de, in wh ich all op erat ional modes are controlled as described under “Stand-Alone

Mode” on page 24. The Control Port is active at all times, and if bit 1 of register 07h (CPEN) is set, the part enters

Control-Port Mode and all operational modes are controlled by the Control Port registers. This bit can be set at any

time, but to avoid unpre dictable output noi ses, bit 1 (CPEN) and bit 0 (PDN) of register 07h should be set by writing

03h before the end of the 10 ms start-up wait period. All registers can then be set as desired before releasing the

PDN bit to begin the start-up sequence. If system requirements do not allow writing to the control port immediately

following the release of RST, the SDIN line should be held at logic “0” until the proper serial mode can be selected.

6.1 SPI Mode

In SPI mode, CS is the CS4272 chip select signa l, CCLK is the control port bit clock, CDIN is the input data line from

the microcontroller an d the chip address is 0010000. All control signals are inputs and data is clocked in on the rising

edge of CCLK.

Figure 17 shows the operation of the Control Port in SPI mode. To write to a register, bring CS low. The first 7 bits

on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be

low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that

is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See

Table 10 on page 36.

The CS4272 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP

will stay constant for succ essive writes. If INCR is set, then MAP will auto incr ement after each byte is written, al-

lowing block writes to successive registers.

MAP

MSB

LSB

DATA

byte 1 byte n

R/W

MAP = M emor y Addr ess Point er

ADDRESS

CHIP

CDIN

CCLK

0010000

Figure 17. Control Port Timing, SPI mode

CS4272

36 DS593F1

6.2 I²C Mode

I²C

mode, SDA is a bi-dire ctional data line. Data is c locked in to and out o f the part by the clock, SC L, with the clock

to data relatio ns hip as shown i n F i gu re 1 8. Th ere is no CS pin. Pin AD0 forms the partial chip address and should be

tied to VA or AGND as requ ire d. The up per 6 bits of the 7- b it addres s field mus t be 0 01000 . To c ommunic ate with the

CS4272

the LSB of the chip address field, which is the first byte sent to the CS4272, should match the setting of the

AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write,

the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then

followed by the data to be written. If the op eration is a read, then the contents of the regi ster pointed to by the MAP will

be output after the chip addre ss.

The CS4272 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP

will stay constant for succ essive writes. If INCR is set, then MAP will auto incr ement after each byte is written, al-

lowing block reads or writes of successive registers.

Table 10. Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

INCR - Auto MAP Increment Enable

Default = ‘0’.

0 - Disabled

1 - Enabled

MAP(3:0) - Memory Address Pointer

Default = ‘0000’.

SDA

SCL

001000

ADDR

AD0 R/W

Start

ACK DATA

1-8 ACK

DATA

1-8

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 18. Control Port Timing, I²C Mode

CS4272

DS593F1 37

7. REGISTER QUICK REFERENCE

This table shows the register names and thei r associated default values.

Addr Function 7 6 5 4 3 2 1 0

01h Mode Control 1 M1 M0 Ratio1 Ratio0 M/S DAC_DIF2 DAC_DIF1 DAC_DIF0

000 0 0 0 0 0

02h DAC Control AMUTE FILT_SEL DEM1 DEM0 RMP_UP RMP_DN INV_B INV_A

100 0 0 0 0 0

03h DAC Volume &

Mixing Control Reserved B=A Soft ZeroCross ATAPI3 ATAPI2 ATAPI1 ATAPI0

001 0 1 0 0 1

04h DAC Ch A Vol-

ume Control MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

000 0 0 0 0 0

05h DAC Ch B Vol-

ume Control MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

000 0 0 0 0 0

06h ADC Control Reserved Reserved Dither16 ADC_DIF0 MUTEA MUTEB HPFDisableA HPFDisableB

000 0 0 0 0 0

07h Mode Control 2 Reserved Reserved Reserved LOOP MUTECA=B F REEZE CPEN PDN

000 0 0 0 0 0

08h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

000 0 0 0 0 0

CS4272
38 DS593F1
8. REGISTER DESCRIPTION
** All registers are read /write in I²C mode and write only in SPI mode, unless otherwise noted**
8.1 Mode Control 1 - Address 01h
8.1.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample  rates.
8.1.2 Ratio Select (Bits 5:4)
Function:
These bits are used to  select the clocking ratios in Control Port M ode. Please refer to  Table 8, “Clock 
Ratios - Control Port Mode With External Crystal,” on page 28 or Table 9, “Clock Ratios - Control Port 
Mode Without  External Crystal,” on page 29 for information on which of these bits to set to obtain spe-
cific clock ratios.
8.1.3 Master / Slave Mode (Bit 3)
Function:
This bit selects either master or slave operation. Setting this bit will select master mode, while clearing 
this bit will select slave mode.
8.1.4 DAC Digital Interface Format (Bits 2:0)
Function:
The required relationship be tween LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital 
Interface Format and the options are detailed in Table 12 and Figures 3-5.
76543210
M1 M0 Ratio1 Ratio0 M/S DAC_DIF2 DAC_DIF1 DAC_DIF0
Table 11.  Functional Mode Selection
M1 M0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates (default)
0 1 Single-Speed Mode: 4 to 50 kHz sample rates
1 0 Double-Speed Mode: 50 to 100 kHz sample rates
1 1 Quad-Speed Mode: 100 to 200 kHz sample rates
Table 12. DAC Digital Interface Formats
DAC_DIF2 DAC_DIF1 DAC_DIF0 Description Format Figure
0 0 0 Left Justified, up to 24-bit data (default) 0 3
001 I2S, up to 24-bit data 14
0 1 0 Right Justified, 16-bit Data 2 5
0 1 1 Right Justified, 24-bit Data 3 5
1 0 0 Right Justified, 20-bit Data 4 5
1 0 1 Right Justified, 18-bit Data 5 5
110 Reserved
111 Reserved

CS4272

DS593F1 39

8.2 DAC Control - Address 02h

8.2.1 Auto-Mute (Bit 7)

Function:

When set, enables the Auto-Mute function. See “Auto-Mute” on page 30.

8.2.2 Interpolation Filter Select (Bit 6)

Function:

This Function allows the user to select whether the Interpolation Filter has a fast or slow roll off. When

set, this bit selects the slow roll off filter, when cleared it selects the fast roll off filter. The - 3 dB corner

is approximately the same for both filters, but the slope of the roll off is greater for th e fast roll off filter.

8.2.3 De-Emphasis Control (Bits 5:4)

Function:

Implementation of the standard 50/15 µs digital de-emphasis filter response, Figure 19, requires re -

configuration of the digital filter to mainta in the proper filter response for 32, 44.1 or 48 kHz sample

rates. NOTE: De-emphasis is available only in Single-Speed Mode. See Table 13 below.

76543210

AMUTE FILT_SEL DEM1 DEM0 RMP_UP RMP_DN INV_A INV_B

Table 13. De-Emphasi s Mo d e Sel ec ti on

DEM1 DEM0 Description

0 0 Disabled (default)

0 1 44.1 kHz de-emphasis

1 0 48 kHz de-emphasis

1 1 32 kHz de-emphasis

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 19. De-Emphasis Curve

CS4272

40 DS593F1

8.2.4 Soft Volume Ramp-Up After Error (Bit 3)

Function:

An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change

or error, and after changing the Functional Mode. When this bit is set, this un-mute is effected, similar

to attenuation changes, by the Soft and ZeroCro ss bits in the DAC Volume & Mixing Control register.

When cleared, an immediate un-mute is performed in these instances.

Note: For best results, it is recommended that this feature be used with the RMP_DN bit.

8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2)

Function:

A mute will be performed prior to executing a filter mode change. When this bit is set, this mute is

effected, similar to attenuation changes, by the Soft and ZeroCross bi ts in the DAC Volume & Mixing

Control register. When clear ed, an immediate mute is performed prior to executing a filter mode

change.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP

bit.

8.2.6 Invert Signal Polarity (Bits 1:0)

Function:

When set, this bit activates an inversion of the si gnal polarity for the appropria te channel. This is use-

ful if a board layout error has occurred, or other situations where a 180 degree phase shift is desirable.

8.3 DAC Volume & Mixing Control - Address 03h

8.3.1 Channel B Volume = Channel A Volume (Bit 6)

Function:

The AOUTA and AOUTB volume levels are independ ently controlled by the A an d the B Channel Vol-

ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de-

termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function

is enabled. Volume and mu ting functions are effected by the Soft Ram p and ZeroCross functions be-

low.

8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally

ramping, in 1/8 dB steps, from the current level to the ne w level at a rate of 1 dB per 8 left/right clock

periods. See Table 14 on page 41.

Zero Cross Enable

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will

occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur

after a time-out p eriod between 512 and 1024 sample pe riods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal doe s no t en coun te r a zero cro s sin g. The zero cross functi on is indep endently mon-

76543210

Reserved B=A Soft ZeroCross ATAPI3 ATAPI2 ATAPI1 ATAPI0

CS4272

DS593F1 41

itored and implemented for each channel. See Table 14 on page 41.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal level ch anges, either by attenuation changes or

muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level

change will occur a fter a time-out period between 512 and 1024 sa mple periods (10.7 ms to 21.3 ms

at 48 kHz sample rate) if the signal does not encounter a zer o crossing. The zero cross function is

independently monitored and implemented for each chann el. See Table 14 on page 41.

8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0)

Function:

The CS4272 implements the channel mixing functions of the ATAPI CD-ROM specification. See

Table 15 on page 42

Table 14. Soft Cross or Zero Cross Mode Selection

Soft ZeroCross Mode

0 0 Changes to affect immediately

0 1 Zero Cross enabled

1 0 Soft Ramp enabled (defau lt)

1 1 Soft Ramp and Zero Cross enabled

A Channel

Volume

Control

Left Channel

Audio Data

Right Channel

Audio Data

B Channel

Volume

Control

AoutA

AoutB

Figure 20. ATAPI Block Diagram

CS4272

42 DS593F1

8.4 DAC Channel A Volume Control - Address 04h

See 8.5 DAC Channel B Volum e Control - Address 05h

8.5 DAC Channel B Volume Control - Address 05h

8.5.1 Mute (Bit 7)

Function:

The DAC output will mute when this bit is set. Though this bit is active high, it should be noted that

the MUTEC pins are active low. The common mode voltage on the output will be retained when this

bit is set. The muting function is effected, similar to attenuation changes, by the Soft and ZeroCross

bits in the Volume and Mixing Control register. The MUTEC pin for the respective channel will become

active during the mute period if the MUTE bit is set. Both the AMUTEC and BMUTEC will become

active if either MUTE register is enabled and the MUTECB=A bit (register 7) is enabled.

8.5.2 Volume Control (Bits 6:0)

Function:

The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB.

Volume settings are decoded as shown in Table 16. The volume changes are implemented as dicta t-

ed by the Soft and ZeroCross bits in the DAC Volume & Mixing Control register (see section 8.3.2).

Table 15. ATAPI Decode

ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA AOUTB

0000 MUTE MUTE

0001 MUTE bR

0010 MUTE bL

0 0 1 1 MUTE b[(L+R)/2]

0100 aR MUTE

0101 aR bR

0110 aR bL

0 1 1 1 aR b[(L+R)/2]

1000 aL MUTE

1001 aL bR

1010 aL bL

1 0 1 1 aL b[(L+R)/2]

1100 a[(L+R)/2] MUTE

1101 a[(L+R)/2] bR

1110 a[(L+R)/2] bL

1 1 1 1 a[(L+R)/2] b[(L+R)/2]

76543210

MUTE VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

Table 16. Digital Volume Control Example Settings

Binary Code Decimal Value Volume Setting

0000000 0 0 dB

0010100 20 -20 dB

0101000 40 -40 dB

0111100 60 -60 dB

1011010 90 -90 dB

CS4272
DS593F1 43
8.6 ADC Control - Address 06h
8.6.1 Dither for 16-Bit Data (Bit 5)
Function:
When set, this bit activates the Dither for 16-Bit Da ta  featur e as describ ed in “Dith er for 16 -Bit Data” 
on page 30.
8.6.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationsh ip between LRCK, SCLK and SDOUT  for the ADC is defined by the ADC Dig-
ital Interface Format. The options are detailed in Table 17 and may be seen in Figure  3 and 4.
8.6.3 ADC Channel A & B Mute (Bits 3:2)
Function:
When this bit is set, the output of the ADC for the selected channel will be muted.
8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0)
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current 
DC offset value will be frozen and continue to be subtracted from the conversion result. See “High 
Pass Filter and DC Offset Calibration” on page 30.
8.7 Mode Control 2 - Address 07h
8.7.1 Digital Loopback (Bit 4)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer 
to “Internal Digital Loopback” on page 30.
8.7.2 AMUTEC = BMUTEC (Bit 3)
Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through an AND g ate prior to the output pins. Therefore, the external AMUTEC and BMUTEC 
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid. 
76543210
Reserved Reserved Dither16 ADC_DIF MUTEA MUTEB HPFDisableA HPFDisableB
Table 17. ADC Digital Interface Formats
ADC_DIF Description Format Figure
0 Left Justified, up to 24-bit data (default) 0 3
1I2S, up to 24-bit data 14
76543210
Reserved Reserved Reserved LOOP MUTECA=B FREEZE CPEN PDN

CS4272

44 DS593F1

8.7.3 Freeze (Bit 2)

Function:

This function allows modifications to the control po rt re gisters withou t th e chan ges taking effect u ntil

FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneous-

ly, set the FREEZE bit, make all register changes, then clear the FREEZE bit.

8.7.4 Control Port Enable (Bit 1)

Function:

This bit is cleared by default, allowing the device to power-up in Sta nd-Alone Mode. Control Port

Mode can be accessed by setting this bit. This will allow the operation of the device to be controlled

by the registers and the pin definitions will conform to Control Port Mode. See “Recommended Power-

Up Sequence - Access to Control Port Mode” on page 27.

8.7.5 Power Down (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The power-down bit is set by default

and must be cleared before normal operation in Control Port Mode can occur. The contents of the

control registers are retained when the device is in power-down.

8.8 Chip ID - Register 08h

This is a Read-Only register.

8.8.1 Chip ID (Bits 7:4)

Function:

Chip ID code for the CS4272. Permanently set to 0000b (0h).

8.8.2 Chip Revision (Bits 3:0)

Function:

Chip Revision code for the CS4272.

Revision A is coded as 0000b (0h).

Revision B is coded as 0000b (0h).

B7 B6 B5 B4 B3 B2 B1 B0

PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0

CS4272

DS593F1 45

9. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measur ement to full- scale.

This technique ensures that th e distortion components are below the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society,

AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response

at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-sca le digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.

CS4272

46 DS593F1

10.PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting li ne, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowabl e dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

THERMAL CHARACTERISTICS AND SPECIFICATIONS

Notes: 4. θJA is specified according to JEDEC specifications for multi-layer PCBs.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.47----1.20

A1 0.002 0.004 0.006 0.05 0.10 0.15

A2 0.03150 0.035 0.04 0.80 0.90 1.00

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.378 BSC 0.382 BSC 0.386 BSC 9.60 BSC 9.70 BSC 9.80 BSC 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.029 0.50 0.60 0.75

∝0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Parameters Symbol Min Typ Max Units

Package Thermal Resistance (Note 4) 28-TSSOP θJA

θJC

-37

13 -

-°C/Watt

°C/Watt

Allowable Junction Temperature - - 135 °C

28L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

CS4272

DS593F1 47

11.APPENDIX

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 21. DAC Single Speed (fast) Stopband Rejection Figure 22. DAC Single Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 23. DAC Single Speed (fast) Transition Band (detail) Figure 24. DAC Single Speed (fast) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 25. DAC Single Speed (slow) Stopband Rejection Figure 26. DAC Single Speed (slow) Transition Band

CS4272

48 DS593F1

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

Figure 27. DAC Single Speed (slow) Transition Band (detail) Figure 28. DAC Single Speed (slow) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 29. DAC Double Speed (fast) Stopband Rejection Figure 30. DAC Double Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 31. DAC Double Speed (fast) Transition Band (detail) Figure 32. DAC Double Speed (fast) Passband Ripple

CS4272

DS593F1 49

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 33. DAC Double Speed (slow) Stopband Rejection Figure 34. DAC Double Speed (slow) Tr ansition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.3

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 35. DAC Double Speed (slow) Transition Band (detail) Figure 36. DAC Do uble Speed (slow) Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 37. DAC Quad Speed (fast) Stopband Rejection Figure 38. DAC Quad Speed (fast) Transition Band

CS4272

50 DS593F1

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.2

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 39. DAC Quad Speed (fast) Transition Band (detail) Figure 40. DAC Quad Speed (fast) Passband Ripple

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 41. DAC Quad Speed (slow) Stopband Rejection Figure 42. DAC Quad Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.02 0.04 0.06 0.08 0.1 0.1

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 43. DAC Quad Speed (slow) Transition Band (detail) Figure 44. DAC Quad Speed (slow) Passband Ripple

CS4272

DS593F1 51

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 45. ADC Single Speed Mode Stopband Rejection Figure 46. ADC Single Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (n or m alized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 47. ADC Single Speed Mode Transition Band (Detail) Figure 48. ADC Single Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

Figure 49. ADC Double Speed Mode Stopband Rejection Figure 50. ADC Double Speed Mode Transition Band

CS4272

52 DS593F1

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 51. ADC Double Speed Mode Transition Band (Detail) Figure 52. ADC Double Speed Mode Passband Ripple

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Frequency (normaliz ed to Fs)

Amplitude (dB)

Figure 53. ADC Quad Speed Mode Stopband Rejection Figure 54. ADC Quad Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25

Frequency (normalized to Fs)

Amplitude (dB)

Figure 55. ADC Quad Speed Mode Transition Band (Detail) Figure 56. ADC Quad Speed Mode Passband Ripple

CS4272
DS593F1 53
Table 18. Revision History 
Release Date Changes
A1 January 2003 Advance Release
PP1 March 2003 Preliminary Release
PP2 October 2003 - Updated Figure 8 on page 23.
- Updated Table 9 on page 2 9.
- Updated the DC Elec tric al Cha racteristics table on page 17 .
- Updated the DAC Analo g Filt er  Respon se  tables on pages 10 a nd 11.
- Updated the ADC Digital Filter Characteristics table on page 16.
- Updated the DAC Full Scale Differential Output Voltage specifica tio n on  
pages 10 and 11.
PP3 September 2004 Add lead-free device ordering info.
F1 August 2005 Final Release
- Updated Orde r ing  Info rm a tio n on  page 2.
- Updated Specified Operating Conditions t a ble on  page 9 to reflect ordering-
suffix independent temperature grade information.
- Updated DAC Analo g Ch ar ac ter istics tables on pages 1 0 and 11 to reflect 
ordering-suffix independent temperature grade information.
- Updated ADC Analo g Ch ar ac ter istics tables on pages 1 4 and 15 to refle ct 
ordering-suffix independent temperature grade information.
- Updated the DC Elec tric al Cha racteristics table on page 17 .
- Corrected error in the SCLK Period units shown in the Switching Characte r-
istics - Serial Audio Port table on page 18.
- Corrected error in the Memory Address Pointer table on page 36.
- Updated Chip ID register description on page 44.
Contacting Cirrus Logic Support
For all product questions and inq uiries contact a Cirrus Logic Sales Representative. 
To find one nearest you go to www.cirrus.com
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