HCPL-2400, HCPL-2430 20 MBd High CMR Logic Gate Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-2400 and HCPL-2430 high speed opto-couplers combine an 820 nm AlGaAs light emitting diode with a high speed photodetector. This combina-tion results in very high data rate capability and low input current. The totem pole output (HCPL-2430) or three state output (HCPL-2400) eliminates the need for a pull up resistor and allows for direct drive of data buses. * High speed: 40 MBd typical data rate The detector has optical receiver input stage with builtin Schmitt trigger to provide logic compatible waveforms, eliminating the need for additional waveshaping. The hysteresis provides differential mode noise immunity and minimizes the potential for output signal chatter. The electrical and switching characteristics of the HCPL2400 and HCPL-2430 are guaranteed over the temperature range of 0C to70C. Functional Diagram ANODE 1 1 8 VCC 2 7 CATHODE 1 2 7 VO1 3 6 CATHODE 2 3 6 5 ANODE 2 4 4 NC GND * High speed AlGaAs emitter * Compatible with TTL, STTL, LSTTL, and HCMOS logic families * Totem pole and tri state output (no pull up resistor required) * Safety approval - UL recognized - 3750 V rms for 1 minute per UL1577 - IEC/EN/DIN EN 60747-5-2 approved with VIORM= 630 V peak (Option 060) for HCPL-2400 * High power supply noise immunity HCPL-2430 8 1 NC * AC performance guaranteed over temperature - CSA approved HCPL-2400/11 VCC * High common mode rejection: HCPL-2400: 10 kV/s at VCM = 300 V (typical) VO2 5 GND * MIL-PRF-38534 hermetic version available (HCPL-5400/1 and HCPL-5430/1) Applications * Isolation of high speed logic systems * Computer-peripheral interfaces * Switching power supplies TRUTH TABLE (POSITIVE LOGIC) LED ENABLE OUTPUT ON OFF ON OFF L L H H L H Z Z TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H A 0.1 F bypass capacitor must be connected between pins 5 and 8. * Isolated bus driver (networking applications) * Ground loop elimination * High speed disk drive I/O * Digital isolation for A/D, D/A conversion * Pulse transformer replacement HCPL-2400 Functional Diagram CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. These optocouplers are compatible with TTL, STTL, LSTTL, and HCMOS logic families. When Schottky type TTL devices (STTL) are used, a data rate performance of 20 MBd over temperature is guaranteed when using the application circuit of Figure 13. Typical data rates are 40MBd. Selection Guide 8-Pin DIP (300 Mil) Minimum CMR Single Dual Channel Channel dV/dt VCM Package Package (V/s) (V) HCPL-2400 1000 300 HCPL-2430 1000 50 500 50 500 50 500 50 Minimum Input On Current (mA) 4 4 6 6 6 Maximum Propagation Delay (ns) 60 60 60 60 60 Hermetic Package HCPL-540X* HCPL-543X* HCPL-643X* *Technical data for the Hermetic HCPL-5400/01, HCPL-5430/31, and HCPL-6430/31 are on separate Avago publications. Ordering Information HCPL-2400 and HCPL-2430 are UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number HCPL-2400 HCPL-2430 RoHS Compliant Non RoHS Compliant -000E No option -300E #300 -500E #500 -060E #060 -360E -360 -000E No option -300E #300 -500E #500 -020E - -060E - Package Surface Mount Gull Wing Tape & Reel UL 5000 Vrms/1 IEC/EN/DIN EN Minute rating 60747-5-2 Quantity 50 per tube 300mil DIP-8 X X X X X 50 per tube X 1000 per reel X X 50 per tube X 50 per reel 50 per tube 300mil DIP-8 X X X X 50 per tube X 1000 per reel X 50 per tube X 50 per tube To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-2430-500E to order product of Gull Wing Surface Mount package in Tape in RoHS compliant. Example 2: HCPl-2400 to order product of 8-Pin DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE`. Schematic ICC 8 ANODE 2 IF + ICC 8 IE 7 IO 6 VF CATHODE VCC 7 VO1 VE VO - 5 3 GND LED ON OFF ON OFF ENABLE L L H H IO 3 - VF2 + 4 IF2 TRUTH TABLE (POSITIVE LOGIC) 6 5 SHIELD OUTPUT L H Z Z TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H HCPL-2400 Schematic IO 1 IF1 + VF1 - 2 VCC VO2 GND Package Outline Drawings 8-Pin DIP Package (HCPL-2400, HCPL-2430) 7.62 0.25 (0.300 0.010) 9.65 0.25 (0.380 0.010) 8 TYPE NUMBER 7 6 5 6.35 0.25 (0.250 0.010) OPTION CODE* DATE CODE A XXXXZ YYWW RU 1 2 3 4 UL RECOGNITION 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 0.320 (0.043 0.013) 0.65 (0.025) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 2.54 0.25 (0.100 0.010) 8-Pin DIP Package with Gull Wing Surface Mount Option 300 (HCPL-2400, HCPL-2430) LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 8 7 6 1.016 (0.040) 5 6.350 0.25 (0.250 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 0.635 0.25 (0.025 0.010) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 2.0 (0.080) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12 NOM. Solder Reflow Thermal Profile 300 TEMPERATURE (C) PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. 200 PEAK TEMP. 245C PEAK TEMP. 240C 2.5C 0.5C/SEC. SOLDERING TIME 200C 30 SEC. 160C 150C 140C PEAK TEMP. 230C 30 SEC. 3C + 1C/-0.5C 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 260 +0/-5 C TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C Note: Non-halide flux should be used. Regulatory Information The HCPL-24XX has been approved by the following organizations: VDE Approved according to VDE 0884/06.92 (Option 060 only). UL Recognized under UL 1577, Component Recognition Program, File E55361. IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. (Option 060 only) Insulation and Safety Related Specifications Parameter Symbol Value Units Minimum External L(101) 7.1 mm Air Gap (External Clearance) Minimum External L(102) 7.4 mm Tracking (External Creepage) Minimum Internal 0.08 mm Plastic Gap (Internal Clearance) Tracking Resistance CTI 200 Volts (Comparative Tracking Index) Isolation Group IIIa Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802. IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (HCPL-2400 Option 060 ONLY) Description Symbol Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage VIORM Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, VPR tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) VIOTM Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 12, Thermal Derating curve.) Case Temperature TS Input Current IS,INPUT Output Power PS,OUTPUT Insulation Resistance at TS, VIO = 500 V R S Characteristic Units I-IV I-III 55/85/21 2 630 V peak 1181 V peak 945 V peak 6000 V peak 175 230 600 109 C mA mW *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2 for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits in application. Absolute Maximum Ratings (No derating required up to 70C) Parameter Symbol Minimum Maximum Units Storage Temperature TS -55 125 C Operating Temperature TA -40 85 C IF(AVG) 10 mA Peak Forward Input Current IFPK 20 mA Reverse Input Voltage VR 2 V Three State Enable Voltage (HCPL-2400 Only) VE -0.5 10 V Supply Voltage VCC 0 7 V Average Output Collector Current I O -25 25 mA Output Collector Voltage VO -0.5 10 V Output Voltage VO -0.5 18 V Output Collector Power Dissipation (Each Channel) PO 40 mW Total Package Power Dissipation (Each Channel) PT 350 mW Average Forward Input Current Note 12 Lead Solder Temperature 260C for 10 sec., 1.6 mm below seating plane (for Through Hole Devices) Reflow Temperature Profile (Option #300) See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Minimum Maximum Units Power Supply Voltage VCC 4.75 5.25 V Forward Input Current (ON) IF(ON) 4 8 mA Forward Input Voltage (OFF) VF(OFF) 0.8 V Fan Out N 5 TTL Loads Enable Voltage (Low) HCPL-2400 Only) VEL 0 0.8 V Enable Voltage (High) HCPL-2400 Only) VEH 2 VCC V Operating Temperature TA 0 70 C Electrical Specifications 0C TA 70C, 4.75 V VCC 5.25 V, 4 mA IF(ON) 8 mA, 0 V VF(OFF) 0.8 V. All typicals at TA=25C, VCC = 5 V, IF(ON) = 6.0 mA, VF(OFF) = 0 V, except where noted. See Note 11. Parameter Symbol Logic Low Output Voltage VOL Device HCPL- Min. Typ.* Logic High Output VOH Voltage Max. 0.5 Units Test Conditions V 2.4 V 2.7 Output Leakage Current IOHH Logic High Enable Current VEH 2400 Logic Low Enable Voltage VEL 2400 0.8 V Logic High Enable IEH 2400 20 A 100 2.0 A IOL = 8.0 mA (5 TTL Loads) 1 IOH = -4.0 mA IOH = -0.4 mA 2 V VE = 2.4 V 100 VE = 5.25 V Logic Low Enable Current -0.4 VE = 0.4 V 2400 -0.28 mA Logic Low Supply Current ICCL 2400 19 26 mA VCC = 5.25 V, VE = 0 V, IO = Open VCC = 5.25 V, IO = Open 2430 34 46 Logic High Supply ICCH 2400 17 26 mA Current VCC = 5.25 V, VE = 0 V, IO = Open 2430 32 42 VCC = 5.25 V, IO = Open High Impedance State Supply Current ICCZ 2400 22 28 VCC = 5.25 V, VE = 5.25 V IOZL mA High Impedance State Output Current 2400 20 A VO = 0.4 V IOZH 20 A VO = 2.4 V IOZH 100 A VO = 5.25 V VE = 2 V Logic Low Short Circuit IOSL 52 mA Output Current VO = VCC = 5.25 V, IF = 8 mA Logic High Short Circuit IOSH -45 mA Output Current VCC = 5.25 V, IF = 0 mA, VO = GND Input Current Hysteresis IHYS 0.25 VCC = 5 V Input Forward Voltage VF 1.1 1.3 1.0 Input Reverse Breakdown BVR 3.0 Voltage 2.0 Temperature Coefficient of Forward Voltage Input Capacitance VF TA = 25C V TA = 25C 20 mV/C IF = 6 mA pF 3 4 IR = 10 A TA CIN 2 IF = 8 mA 1.55 -1.44 *All typical values at TA = 25C and VCC = 5 V, unless otherwise noted. mA 1.5 5.0 Note VO = 5.25 V, VF = 0.8 V Current IEL Fig. f = 1 MHz, VF = 0 V 4 2 Switching Specifications 0C TA 70C, 4.75 V VCC 5.25 V, 4 mA IF(ON) 8 mA, 0 V VF(OFF) 0.8 V. All typicals at TA = 25C, VCC = 5 V, IF(ON) = 6.0 mA, VF(OFF) = 0 V, except where noted. See Note 11. Parameter Symbol Device HCPL- Min. Figure Note 55 ns IF(ON) = 7 mA 5, 6, 7 Propagation Delay tPHL Time to Logic Low Output Level 15 33 60 1, 4, 5, 6 Propagation Delay tPLH 55 ns IF(ON) = 7 mA 5, 6, 7 Time to Logic High Output Level 15 30 60 1, 4, 5, 6 Pulse Width |tPHL-tPLH| Distortion Propagation Delay Skew Typ.* Max. 2 15 5 25 tPSK 35 Units Test Conditions ns IF(ON) = 7 mA 5, 8 6 ns Per Notes & Text 15, 16 7 Output Rise Time tr 20 ns 5 Output Fall Time tf 10 ns 5 Output Enable Time to Logic High tPZH 2400 15 ns 9, 10 Output Enable Time to Logic Low tPZL 2400 30 ns 9, 10 Output Disable Time from Logic High tPHZ 2400 20 ns 9, 10 Output Disable Time from Logic Low tPLZ 2400 15 ns 9, 10 Logic High Common |CMH| 1000 10,000 V/s Mode Transient Immunity VCM = 300 V, TA = 25C, IF = 0 mA 11 9 Logic Low Common |CML| 1000 10,000 V/s Mode Transient Immunity VCM = 300 V, TA = 25C, IF = 4 mA 11 9 Power Supply Noise PSNI 0.5 Vp-p Immunity VCC = 5.0 V, 48 Hz = FAC 50 MHz *All typical values at TA = 25C and VCC = 5 V, unless otherwise noted. 10 Package Characteristics ParameterSym. Device Min. Typ.* Max. Units Test Conditions Fig. Input-Output VISO 3750 V rms RH 50%, Momentary t = 1 min., Withstand Voltage** TA = 25C Input-Output RI-O 1012 VI-O = 500 Vdc Resistance Input-Output CI-O 0.6 pF f = 1 MHz Capacitance VI-O = 0 Vdc Input-Input II-I 2430 0.005 A RH 45% Insulation Leakage t = 5 s, Current VI-I = 500 Vdc Resistance RI-I 2430 1011 VI-I = 500 Vdc (Input-Input) Capacitance CI-I 2430 0.25 pF f = 1 MHz (Input-Input) Note 3, 13 3 8 8 8 *All typical values are at TA = 25C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publication number 5963-2203E. Notes: 1. Each channel. 2. Duration of output short circuit time not to exceed 10 ms. 3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 4. tPHL propagation delay is measured from the 50% level on the rising edge of the input current pulse to the 1.5 V level on the falling edge of the output pulse. The tPLH propagation delay is measured from the 50% level on the falling edge of the input current pulse to the 1.5 V level on the rising edge of the output pulse. 5. The typical data shown is indicative of what can be expected using the application circuit in Figure 13. 6. This specification simulates the worst case operating conditions of the HCPL-2400 over the recommended operating temperature and VCC range with the suggested application circuit of Figure 13. 7. Propagation delay skew is discussed later in this data sheet. 8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. 9. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 10. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and still remain in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V. 11. Use of a 0.1 F bypass capacitor connected between pins 8 and 5 adjacent to the device is required. 12. Peak Forward Input Current pulse width < 50 s at 1 KHz maximum repetition rate. 13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500Vrms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table, if applicable. 10 Figure 1. Typical logic low output voltage vs. logic low output current. Figure 2. Typical logic high output voltage vs. logic high output current. Figure 4. Typical diode input forward current characteristic. Figure 5. Test circuit for tPLH, tPHL, tr, and tf. Figure 6. Typical propagation delay vs. ambient temperature. Figure 7. Typical propagation delay vs. input forward current. 11 Figure 3. Typical output voltage vs. input forward current. Figure 8. Typical pulse width distortion vs. ambient temperature. Figure 9. Test circuit for tPHZ, tPZH, tPLZ and tPZL. Figure 10. Typical enable propagation delay vs. ambient temperature. VCC HCPL-2400/11 + VFF - 1 NC B A 8 0.1 F * 2 7 3 6 4 NC GND 5 OUTPUT VO MONITORING NODE CL = 15 pF VCM + - PULSE GENERATOR HCPL-2400 fig 11a OUTPUT POWER - PS, INPUT CURRENT - IS IF VCC 800 PS (mW) 700 IS (mA) 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - C Figure 11. Test diagram for common mode transient immunity and typical waveforms. 12 Figure 12. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-2. HCPL-2400 fig 12 Applications Figure 13. Recommended 20 MBd HCPL-2400/30 interface circuit. Figure 14. Alternative HCPL-2400/30 interface circuit. DATA IF INPUTS 50% CLOCK 1.5 V VO IF DATA 50% OUTPUTS VO 1.5 V t PSK CLOCK t PSK Figure 15. Illustration of propagation delay skew - tPSK. t PSK Figure 16. Parallel data transmission example. HCPL-2400 fig 15 HCPL-2400 fig 16 Figure 17. Modulation code selections. 13 Figure 18. Typical HCPL-2400/30 output schematic. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 5). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest pro-pagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 16 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signals are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPHZ. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-2400/30 optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges. Application Circuit A recommended LED drive circuit is shown in Figure 13. This circuit utilizes several techniques to minimize the total pulse-width distortion at the output of the optocoupler. By using two inverting TTL gates connected in series, the inherent pulse-width distortion of each gate cancels the distortion of the other gate. For best results, the two series-connected gates should be from the same package. The circuit in Figure 13 also uses techniques known as prebias and peaking to enhance the performance of the optocoupler LED. Prebias is a small forward voltage applied to the LED when the LED is off. This small prebias voltage partially charges the junction capacitance of the LED, allowing the LED to turn on more quickly. The speed of the LED is further increased by applying momentary current peaks to the LED during the turn-on and turn-off transitions of the drive current. These peak currents help to charge and discharge the capacitances of the LED more quickly, shortening the time required for the LED to turn on and off. Switching performance of the HCPL-2400/30 optocouplers is not sensitive to the TTL logic family used in the recommended drive circuit. The typical and worst-case switching parameters given in the data sheet can be met using common 74LS TTL inverting gates or buffers. Use of faster TTL families will slightly reduce the overall propagation delays from the input of the drive circuit to For product information and a complete list of distributors, please go to our website: the output of the optocoupler, but will not necessarily result in lower pulse-width distortion or propagation delay skew. This reduction in overall propagation delay is due to shorter delays in the drive circuit, not to changes in the propagation delays of the optocoupler; optocoupler propagation delays are not affected by the speed of the logic used in the drive circuit. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0563EN AV02-0962EN - January 4, 2008