March 2001
®
AS7C1025
AS7C31025
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Copyright © Alliance Semiconductor. All rights reserved.
3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9
Features
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• Low power consumption: STANDBY
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C1025
AS7C31025
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A9
A8
A4
A5
A6
A7
A12
A11
A10
32-pin TSOP II
AS7C1025
AS7C31025
Selection guide
Shaded areas contain advance information.
AS7C1025-12
AS7C31025-12
AS7C1025-15
AS7C31025-15
AS7C1025-20
AS7C31025-20 Unit
Maximum address access time 12 15 20 ns
Maximum output enable access time 3 4 5 ns
Maximum operating current AS7C1025 130 85 80 mA
AS7C31025 100 85 80 mA
Maximum CMOS standby current AS7C1025 5 5 5 mA
AS7C31025 5 5 5 mA
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank
memory systems.
When
CE
is high the devices enter standby mode. The standard AS7C1025 is guaranteed not to exceed 27.5 mW power
consumption in standby mode, and typically requires only 5 mW. Both devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0-I/O7 is
written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025) or 3.3V supply
(AS7C31025). The AS7C1025 and AS7C31025 are packaged in common industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = Low, H = High
Parameter Device Symbol Min Max Unit
Vo ltag e o n V CC relative to GND AS7C1025 Vt1 –0.50 +7.0 V
AS7C31025 Vt1 –0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 oC
Ambient temperature with VCC applied Tbias –55 +125 oC
DC current into outputs (low) IOUT –20mA
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9
Recommended operating conditions
†VIL min = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
Shaded areas contain advance information.
Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)2
Parameter Device Symbol Min Nominal Max Unit
Supply voltage AS7C1025 VCC 4.5 5.0 5.5 V
AS7C31025 VCC 3.0 3.3 3.6 V
Input voltage
AS7C1025 VIH 2.2 – VCC + 0.5 V
AS7C31025 VIH 2.0 – VCC + 0.5 V
VIL†–0.5 – 0.8 V
Ambient operating temperature commercial TA0–70
oC
industrial TA–40 – 85 oC
Parameter Sym Test conditions Device
-12 -15 -20
UnitMin Max Min Max Min Max
Input leakage
current | ILI | VCC = Max, VIN = GND to VCC –1–1–1µA
Output
leakage
current
| ILO | VCC = Max, CE = VIH, Vout =
GND to VCC
–1–1–1µA
Operating
power supply
current
ICC CE = VIL, f = fMax, IOUT = 0 mA
AS7C1025 – 130 – 120 – 110
mA
AS7C31025 – 100 – 85 – 80
Standby
power supply
current1
ISB CE = VIH, f = fMax, fOUT = 0 AS7C1025 – 50 – 40 – 40 mA
AS7C31025 – 50 – 40 – 40
ISB1
CE ≥ VCC–0.2V, VIN ≤ 0.2V or
VIN ≥ VCC –0.2V, f = 0, fOUT = 0
AS7C1025 – 5 – 5 – 5 mA
AS7C31025 – 5 – 5 – 5
Output
voltage
VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4–2.4–2.4– V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 4 of 9
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE and OE controlled)3,6,8,9
Parameter Symbol
-12 -15 -20
Unit NotesMin Max Min Max Min Max
Read cycle time tRC 12 – 15 – 20 – ns
Address access time tAA –12–15–20 ns 3
Chip enable (
CE
) access time tACE –12–15–20 ns 3
Output enable (
OE
) access time tOE –6–7–8 ns
Output hold from address change tOH 3–3–3– ns 5
CE
Lo w to output in low Z tCLZ 0–0–0– ns 4, 5
CE
Low to output in high Z tCHZ –3–4–5 ns 4, 5
OE
Low to output in low Z tOLZ 0–0–0– ns 4, 5
OE
High to output in high Z tOHZ –3–4–5 ns 4, 5
Power up time tPU 0–0–0– ns 4, 5
Power down time tPD –12–15–20 ns 4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 5 of 9
Write cycle (over the operating range)11
Shaded areas contain advance information.
Write waveform 1 ( WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Parameter Symbol
-12 -15 -20
Unit NotesMin Max Min Max Min Max
Write cycle time tWC 12 – 15 – 20 – ns
Chip enable (
CE
) to write end tCW 8–12–12– ns
Address setup to write end tAW 8–12–12– ns
Address setup time tAS 0–0–0– ns
Write pulse width tWP 8–9–12– ns
Address hold from end of write tAH 0–0–0– ns
Data valid to write end tDW 6–8–12– ns
Data hold time tDH 0 – 0 – 0 – ns 4, 5
Write enable to output in high Z tWZ – 5 – 5 – 5 ns 4, 5
Output active from write end tOW 3 – 3 – 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data validD
IN
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9
Data retention characteristics (over the operating range)13
Data retention waveform
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is High for read cycle.
7CE
and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, where C=5pF.
Parameter Symbol Test conditions Min Max Unit
VCC for data retention VDR VCC = 2.0V
CE
≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
2.0 – V
Data retention current ICCDR –500µA
Chip enable to data retention time tCDR 0–ns
Operation recovery time tRtRC –ns
Input leakage current | ILI | –1µA
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C(14)
320W
D
OUT
GND
+3.3V
168W
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 7 of 9
Typical DC and AC characteristics
Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
Ambient temperature (°C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
vs. ambient temperature T
a
vs. supply voltage V
CC
I
CC
I
SB
I
CC
I
SB
Ambient temperature (°C)
-55 80 125
35-10
0.2
1
0.04
5
25
625
Normalized I
SB1
(log scale)
Normalized supply current I
SB1
vs. ambient temperature T
a
V
CC
= V
CC
(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Ambient temperature (°C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
Normalized supply current I
CC
vs. ambient temperature T
a
vs. cycle frequency 1/t
RC
, 1/t
WC
vs. supply voltage V
CC
V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
Output voltage (V)
VCC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current IOH
Output voltage (V)
VCC
Output sink current (mA)
Output sink current IOL
vs. output voltage VOL
vs. output voltage VOH
0
20
60
80
40
100
120
140
Capacitance (pF)
0750 1000
500250
0
5
15
20
10
25
30
35
Change in tAA (ns)
Typical access time change ∆tAA
vs. output capacitive loading
00
V
CC
= V
CC
(NOMINAL)V
CC
= V
CC
(NOMINAL)V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
T
a
= 25
°
C
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9
Package dimensions
32-pin TSOP II
eD
E1
Pin 1
b
B
A1
A2
c
E
Seating
Plane
E2 A
NN/2+1
1N/2
D
E1 E
32-pin SOJ
300 mil/400 mil
L
α
c
ZD
cbA1
A
Seating plane
Symbol
32-pin TSOP II (mil)
Min Max
A–1.2
A1 0.05 0.15
b0.30.52
C 0.12 0.21
D 20.82 21.08
E1 10.03 10.29
E 11.56 11.96
e 1.27 BSC
L 0.40 0.60
ZD 0.95 REF.
α0° 5°
Symbol
32-pin SOJ
300 mil
32-pin SOJ
400 mil
Min Max Min Max
A - 0.145 - 0.145
A1 0.025 - 0.025 -
A2 0.086 0.105 0.086 0.115
B 0.026 0.032 0.026 0.032
b 0.014 0.020 0.015 0.020
c 0.006 0.013 0.007 0.013
D 0.820 0.830 0.820 0.830
E 0.250 0.275 0.360 0.380
E1 0.292 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
®
AS7C1025
AS7C31025
3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
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appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
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claims arising from such use
Ordering codes
Part numbering system
Package \ Access time Vol t ag e Te m p e r a tu r e 12 ns 15 ns 20 ns
sTSOP II
5V Commercial AS7C1025-12TC AS7C1025-15TC AS7C1025-20TC
Industrial AS7C1025-12TI AS7C1025-15TI AS7C1025-20TI
3.3V Commercial AS7C31025-12TC AS7C31025-15TC AS7C31025-20TC
Industrial AS7C31025-12TI AS7C31025-15TI AS7C31025-20TI
300-mil SOJ
5V Commercial AS7C1025-12TJC AS7C1025-15TJC AS7C1025-20TJC
Industrial AS7C1025-12TJI AS7C1025-15TJI AS7C1025-20TJI
3.3V Commercial AS7C31025-12TJC AS7C31025-15TJC AS7C31025-20TJC
Industrial AS7C31025-12TJI AS7C31025-15TJI AS7C31025-20TJI
400-mil SOJ
5V Commercial AS7C1025-12JC AS7C1025-15JC AS7C1025-20JC
Industrial AS7C1025-12JI AS7C1025-15JI AS7C1025-20JI
3.3V Commercial AS7C31025-12JC AS7C31025-15JC AS7C31025-20JC
Industrial AS7C31025-12JI AS7C31025-15JI AS7C31025-20JI
AS7C X 1025 –XX X X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
Access
time
Package:
T = TSOP II
J = SOJ
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
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