8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
GND
FB_IN
VDDO
QA1
QA0
GND
CLK1
VDD
VDDA
CLK_SEL
VDDO
QB2
QB3
GND
GND
nc
PLL_SEL
VDD
ICS8752
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
÷2
÷4
÷6
÷8
÷12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
CLK0
CLK1
CLK_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
11
0
00
01
10
11
00
01
10
11
VCO
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew
LVCMOS clock generator and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752 is targeted
for high performance clock applications. Along with a fully in-
tegrated PLL, the ICS8752 contains frequency configurable
outputs and an external feedback input for regenerating clocks
with “zero delay”.
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which reference
clock is used. The output divider values of Bank A and B are
controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively .
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
•Fully integrated PLL
•8 L VCMOS outputs, 7Ω typical output impedance
•Selectable L VCMOS CLK0 or CLK1 inputs for
redundant clock applications
•Input/Output frequency range: 18.33MHz to 240MHz
at VCC = 3.3V ± 5%
•VCO range: 220MHz to 480MHz
•External feedback for “zero delay” clock regeneration
•Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
•Output skew: 100ps (maximum)
•Bank skew: 55ps (maximum)
•3.3V or 2.5V supply voltage
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request
•Functionally compatible with MPC952 in some applications
HiPerClockS™
,&6
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
C
DP
ecnaticapaCnoitapissiDrewoP )tuptuorep( V
ADD
V,
DD
V,
ODD
V564.3=32Fp
R
TUO
ecnadepmItuptuO 7 Ω
rebmuNemaNepyTnoitpircseD
2,1 ,0BLES_VID 1BLES_VID tupnInwodlluP .3elbaTnidebircsedsaBknaBrofseulavredividtuptuosenimreteD .slevelecafretniLTTVL/SOMCVL
4,3 ,0ALES_VID 1ALES_VID tupnInwodlluP .3elbaTnidebircsedsaAknaBrofseulavredividtuptuosenimreteD .slevelecafretniLTTVL/SOMCVL
5EOn/RMtupnInwodlluP eht,WOLcigolnehW.elbanetuptuodnateseRretsaMWOLevitcA .delbasidsiteseRretsaMeht,HGIHnehW.tesererasredividlanretni .slevelecafretniLTTVL/SOMCVL
60KLCtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolC
,71,31,7 92,82,42 DNGrewoP.dnuorgylppusrewoP
8NI_BFtupnInwodlluP ."yaledorez"htiwskcolcgnitarenegrofrotcetedesahpottupnikcabdeeF .slevelecafretniLTTVL/SOMCVL
9LES_KLCtupnInwodlluP rotcetedesahpsa1KLCro0KLCneewtebstceleS.tupnitceleskcolC .1KLCstceles,HGIHnehW.0KLCstceles,WOLnehW.ecnerefer .slevelecafretniLTTVL/SOMCVL
01V
ADD
rewoP.nipylppusgolanA
23,11V
DD
rewoP.snipylppusevitisoP
211KLCtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolC
,51,41 91,81 ,1AQ,0AQ 3AQ,2AQ tuptuO 7.stuptuokcolcAknaB Ω.ecnadepmituptuolacipyt .slevelecafretniLTTVL/SOMCVL
,02,61 52,12 V
ODD
rewoP.snipylppustuptuO
,32,22 72,62 ,1BQ,0BQ 3BQ,2BQ tuptuO 7.stuptuokcolcBknaB Ω.ecnadepmituptuolacipyt .slevelecafretniLTTVL/SOMCVL
03cndesunU.tcennocoN
13LES_LLPtupnIpulluP .sredividehtottupniehtsa1KLCro0KLCdnaLLPehtneewtebstceleS .1KLCro0KLCstcelesWOLnehW.LLPstcelesHGIHnehW .slevelecafretniLTTVL/SOMCVL
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 3. CONTROL INPUT FUNCTION TABLE
TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB
stupnIstuptuO
NI_BF _VID 1BLES _VID 0BLES
tuptuOBQ edoMrediviD )2ETON(
)zHM(1KLC,0KLC )1ETON( _VID 1ALES _VID 0ALES tuptuOAQ edoMrediviD reilpitluMAQ )2ETON(
muminiMmumixaM
BQ00 ÷455021
00 ÷22
01 ÷41
10 ÷6766.0
11 ÷85.0
BQ01 ÷666.6308
00 ÷23
01 ÷45.1
10 ÷61
11 ÷857.0
BQ10 ÷85.7206
00 ÷24
01 ÷42
10 ÷633.1
11 ÷81
BQ11 ÷21 33.8104
01 ÷26
01 ÷43
10 ÷62
11 ÷85.1
.zHM084otzHM022siegnarycneuqerfOCV:1ETON ;reilpitlumehtsemitycneuqerfxKLCotlauqeycneuqerftuptuoAQ:2ETON .xKLCotlauqeycneuqerftuptuoBQ
stupnIstuptuO
EOn/RMLES_LLPLES_KLC _VID 1ALES _VID 0ALES _VID 1BLES _VID 0BLES xAQxBQ
1X X X X X X Z-iHZ-iH
01X 0 0 0 0 2/OCVf4/OCVf
01X 0 1 0 1 4/OCVf6/OCVf
01X 1 0 1 0 6/OCVf8/OCVf
01X 1 1 1 1 8/OCVf21/OCVf
00 0 0 0 0 0 2/0KLCf4/0KLCf
00 0 0 1 0 1 4/0KLCf6/0KLCf
00 0 1 0 1 0 6/0KLCf8/0KLCf
00 0 1 1 1 1 8/0KLCf21/0KLCf
00 1 0 0 0 0 2/1KLCf4/1KLCf
00 1 0 1 0 1 4/1KLCf6/1KLCf
00 1 1 0 1 0 6/1KLCf8/1KLCf
00 1 1 1 1 1 8/1KLCf21/1KLCf
.delbasiderastupuolla,HGIHsiEOn/RMnehW.WOLsiEOn/RM,noitarepolamronroF:ETON
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA
stupnIstuptuO
NI_BF _VID 1ALES _VID 0ALES
AQtuptuO edoMrediviD )2ETON(
)zHM(1KLC,0KLC )1ETON( _VID 1BLES _VID 0BLES tuptuOBQ edoMrediviD reilpitluMBQ )2ETON(
muminiMmumixaM
AQ00 ÷2011042 )3ETON(
00 ÷45.0
01 ÷6333.0
10 ÷852.0
11 ÷21 761.0
AQ01 ÷455021
00 ÷41
01 ÷6766.0
10 ÷85.0
11 ÷21 333.0
AQ10 ÷666.6308
00 ÷45.1
01 ÷61
10 ÷857.0
11 ÷21 5.0
AQ11 ÷85.7206
01 ÷42
01 ÷6333.1
10 ÷81
11 ÷21 766.0
.zHM084otzHM022siegnarycneuqerfOCV:1ETON ;reilpitlumehtsemitycneuqerfxKLCotlauqeycneuqerftuptuoBQ:2ETON .xKLCotlauqeycneuqerftuptuoAQ VrofdilavzHM042foycneuqerfmumixaM:3ETON
CC
.ylno%5±V3.3=
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VDDx 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only . Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ADD
egatloVylppuSgolanA 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSevitisoP 501Am
I
ADD
tnerruCylppuSgolanA 51Am
I
ODD
tnerruCylppuStuptuO 02Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI
,1KLC,0KLC ,LES_KLC,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V
DD
V=
NI
V564.3=051Aµ
LES_LLPV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI
,1KLC,0KLC ,LES_KLC,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V
DD
=V564.3,
V
NI
V0= 5-Aµ
LES_LLP V
DD
=V564.3,
V
NI
V0= 051-Aµ
V
HO
1ETON;egatloVhgiHtuptuO 4.2V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
."tiucriCtseTdaoLtuptuOV3.3"
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
FER
ycneuqerFecnerefeRtupnI ybdetimilsiycneuqerfecnerefertupnI:ETON .egnarkcolOCVehtdnanoitcelesredivideht 02042zHM
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
)edoMLLP(ycneuqerFtuptuO
÷2011042zHM
÷455021zHM
÷676.6308zHM
÷85.7206zHM
1÷ 233.8104zHM
f
OCV
egnaRkcoLOCVLLP 022084zHM
)Ø(t1ETON;tesffOesahPcitatS ,zHM004=OCVf 8÷kcabdeeF 03-07071sp
t
)b(ks4,2ETON;wekSknaB egdegnisirnoderusaeM Vta
ODD
2/ 55sp
t
)o(ks4,3ETON;wekStuptuO egdegnisirnoderusaeM Vta
ODD
2/ 001sp
t
)cc(tij elcyC-ot-elcyC 4ETON;rettiJ
seicneuqerFtnereffiD sknaBtnereffiDno 004sp
tastuptuOllA ycneuqerFemaS 57sp
t
L
emiTkcoLLLP 1Sm
t
R
emiTesiRtuptuO%08ot%02004059sp
t
F
emiTllaFtuptuO%08ot%02004059sp
cdoelcyCytuDtuptuO 740535%
ftaderusaemsretemarapllA
XAM
.esiwrehtodetonsselnu ,langistupnikcabdeefegarevaehtdnakcolctupniehtneewtebecnereffidemitehtsadenifeD:1ETON .elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON VtaderusaeM
ODD
.2/ .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 5D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 573.25.2526.2V
V
ADD
egatloVylppuSgolanA 573.25.2526.2V
V
ODD
egatloVylppuStuptuO 573.25.2526.2V
I
DD
tnerruCylppuSevitisoP 001Am
I
ADD
tnerruCylppuSgolanA 51Am
I
ODD
tnerruCylppuStuptuO 02Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI
,1KLC,0KLC ,LES_KLC,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V
DD
V=
NI
V526.2=051Aµ
LES_LLPV
DD
V=
NI
V526.2=5Aµ
I
LI
tnerruCwoLtupnI
,1KLC,0KLC ,LES_KLC,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V
DD
,V526.2=
V
NI
V0= 5-Aµ
LES_LLP V
DD
,V526.2=
V
NI
V0= 051-Aµ
V
HO
1ETON;egatloVhgiHtuptuO 8.1V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
."tiucriCtseTdaoLtuptuO5.2"
TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
FER
ycneuqerFecnerefeRtupnI ybdetimilsiycneuqerfecnerefertupnI:ETON .egnarkcolOCVehtdnanoitcelesredivideht 02021zHM
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
)edoMLLP(ycneuqerFtuptuO
÷2011042zHM
÷455021zHM
÷676.6308zHM
÷85.7206zHM
1÷ 233.8104zHM
f
OCV
egnaRkcoLOCVLLP 022084zHM
)Ø(t1ETON;tesffOesahPcitatS zHM004=OCVf 8÷kcabdeeF 09-05091sp
t
)b(ks4,2ETON;wekSknaB egdegnisirnoderusaeM Vta
ODD
2/ 55sp
t
)o(ks4,3ETON;wekStuptuO egdegnisirnoderusaeM Vta
ODD
2/ 09sp
t
)cc(tij elcyC-ot-elcyC 4ETON;rettiJ
seicneuqerFtnereffiD sknaBtnereffiDno 004sp
tastuptuOllA ycneuqerFemaS 57sp
t
L
emiTkcoLLLP 1Sm
t
R
emiTesiRtuptuO%08ot%02004059sp
t
F
emiTllaFtuptuO%08ot%02004059sp
cdoelcyCytuDtuptuO 540555%
ftaderusaemsretemarapllA
XAM
.esiwrehtodetonsselnu ,langistupnikcabdeefegarevaehtdnakcolctupniehtneewtebecnereffidemitehtsadenifeD:1ETON .elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON VtaderusaeM
ODD
.2/ .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
LVCMOS
VDD,
VDDA,
VDDO
2.5V OUTPUT LOAD TEST CIRCUIT
GND
1.25V±5%
-1.25V±5%
SCOPE
Qx
LVCMOS
3.3V OUTPUT LOAD TEST CIRCUIT
-1.65V±5%
GND
VDD,
VDDA,
VDDO
1.65V±5%
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
OUTPUT SKEW
Qx
Qy
tsk(o)
VDDO
2
VDDO
2
Cycle-to-Cycle Jitter
t
cycle n
t
cycle n+1
QAx, QBx
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
➤
➤
➤
➤
VDDO
2
VDDO
2
VDDO
2
STATIC PHASE OFFSET
➤
➤
t(Ø)
V
DD
/2
V
DD
/2
FB_IN
CLK0, CLK1
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
OUTPUT RISE AND FALL TIME
Clock Outputs 20%
80% 80%
20%
tRtF
odc & tPERIOD
QAx, QBx
Pulse Width
t
PERIOD
V
DDO
2
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8752 is: 1546
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by V elocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA
LOBMYS ABB
MUMINIMLANIMONMUMIXAM
N23
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b03.073.054.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR06.5
ECISAB00.9
1E CISAB00.7
2E .feR06.5
eCISAB08.0
L54.006.057.0
q0
°
-- 7
°
ccc ----01.0
PACKAGE OUTLINE - Y SUFFIX
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
14
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
YC2578SCIYC2578SCIPFQLdaeL23yartrep052C°07otC°0
TYC2578SCIYC2578SCIleeRdnaepaTnoPFQLdaeL230001C°07otC°0
8752CY www.icst.com/products/hiperclocks.html REV. A AUGUST 19, 2002
15
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TEEHSYROTSIHNOISIVER
veRelbaTegaPegnahCfonoitpircseDetaD
A1T2 .noitpircsedEOn/RMdesiveR.elbaTsnoitpircseDniP 20/91/8
