64K x 16 Static RAM
CY62126DV30 MoBL®
ADVANCE
INFORMATION
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05230 Rev. ** Revised August 19, 2002
26DV30
Features
•High speed: 55 ns
•Wide voltage range: 2.2V–3.6V
•Pin Compatible with CY62126BV
•Ultra-low active power
—Typical active current: 0.5 mA @ f = 1MHz
—Typical active current: 5 mA @ f = fmax
•Low st andby power
•Easy memory expansion with CE and OE featur es
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Available in 44-lead TSOP Type II and 48-ball FBGA
packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces pow er co ns ump tio n by 90 % wh en addres s es are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are plac ed in a hi gh-imp edanc e st ate when : des electe d
(CE HIGH), outputs are disabled (OE HIG H), bo th By te Hi gh
Enable and By te Low Enab le are disable d (BHE, BL E HIGH),
or during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then dat a fr om memory will a ppear on I/O8 to I/O15. See
the T ruth Table near the b ack of this dat a sheet fo r a comp lete
description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array I/O0 – I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
2048 x 512
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8 – I/O15
CE
WE
BLE
BHE
A0
A1
A9
A10
Note:
1. For best prac tice rec omm en da ti ons , ple ase ref er to the Cypress applica ti on note ‘System Design Guidelines’ on http://www .cypress.com