26DV30 ADVANCE INFORMATION CY62126DV30 MoBL(R) 64K x 16 Static RAM Features * * * * * * * * * reduces power consumption by 90% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). High speed: 55 ns Wide voltage range: 2.2V-3.6V Pin Compatible with CY62126BV Ultra-low active power -- Typical active current: 0.5 mA @ f = 1MHz -- Typical active current: 5 mA @ f = fmax Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Available in 44-lead TSOP Type II and 48-ball FBGA packages Functional Description[1] The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table near the back of this data sheet for a complete description of read and write modes. Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 2048 x 512 I/O0 - I/O7 I/O8 - I/O15 BHE WE CE OE BLE A14 A15 A12 A13 A11 COLUMN DECODER Note: 1. For best practice recommendations, please refer to the Cypress application note `System Design Guidelines' on http://www.cypress.com Cypress Semiconductor Corporation Document #: 38-05230 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised August 19, 2002 CY62126DV30 MoBL(R) ADVANCE INFORMATION Pin Configurations[2, 3] FBGA (Top View) 4 3 5 TSOP II (Forward) Top View 1 2 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D I/O4 VSS E VCC I/O12 DNU NC 6 I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ...-0.3V to Vccmax + 0.3V 1 44 2 3 4 43 42 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC DC Voltage Applied to Outputs in High Z State[5] .................................... -0.3V to VCC + 0.3V DC Input Voltage[5] ................................ -0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Ambient Temperature (TA) VCC[4] Industrial -40C to +85C 2.2V to 3.6V Product Portfolio Power Dissipation VCC Range (V) Product CY62126DV30L Speed (ns) Min. Typ.[6] Max. 2.2 3.0 3.6 55 Operating, ICC (mA) f = 1 MHz f = fmax Standby, ISB2 (A) Typ.[6] Max. Typ.[6] Max. Typ.[6] 0.5 1 5 10 1.5 CY62126DV30LL Max. 4 3 Notes: 2. NC pins are not connected to the die. 3. E3 (DNU) can be left as NC or VSS to ensure proper application. 4. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) > 500s. 5. VIL(min.) = -2.0V for pulse durations less than 20 ns. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. Document #: 38-05230 Rev. ** Page 2 of 12 CY62126DV30 MoBL(R) ADVANCE INFORMATION Electrical Characteristics Over the Operating Range CY62126DV30-55 Parameter VOH Description Test Conditions Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Min. 2.2 < VCC < 2.7 IOH= -0.1 mA 2 2.7 < VCC < 3.6 IOH= -1.0 mA 2.4 2.2 < VCC < 2.7 IOL= 0.1 mA 2.7 < VCC < 3.6 IOL= 2.1 mA Typ.[6] Max. Unit V 0.4 V 0.4 2.2 < VCC < 2.7 1.8 2.7 < VCC < 3.6 2.2 2.2 < VCC < 2.7 -0.3 VCC + 0.3V V 0.6 V VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC -1 +1 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled -1 +1 A ICC VCC Operating Supply Current f = fMAX = 1/tRC 5 10 mA 0.5 1 Automatic CE Power-Down Current-- CMOS Inputs CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only),f=0 (OE,WE,BHE and BLE) 1.5 4 Automatic CE Power-Down Current-- CMOS Inputs CE > VCC - 0.2V L VIN > VCC - 0.2V or VIN < 0.2V, LL f = 0, Vcc=3.6V 2.7 < VCC < 3.6 ISB1 ISB2 f = 1 MHz 0.8 VCC = 3.6V Iout = 0mA CMOS level L LL A 3 1.5 A 4 3 Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit TA = 25C, f = 1 MHz, VCC = VCC(typ) 6 pF 8 pF Thermal Resistance Description Thermal Resistance (Junction to Ambient)[7] Test Conditions Symbol BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board JA 55 C/W JC 16 C/W Thermal Resistance (Junction to Case)[7] Note: 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05230 Rev. ** Page 3 of 12 CY62126DV30 MoBL(R) ADVANCE INFORMATION AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT 10% GND Rise TIme: 1 V/ns R2 50 pF 90% 10% 90% Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5V 3.0V Unit R1 16600 1216 Ohms R2 15400 1374 Ohms RTH 8000 645 Ohms VTH 1.2 1.75 Volts Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current Min. Typ.[6] Max. 1.5 tCDR[7] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time VCC= 1.5V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Unit V L 1.2 LL 0.8 A 0 ns 100 s Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5 V tCDR VCC(min) tR CE Note: 8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100s. Document #: 38-05230 Rev. ** Page 4 of 12 CY62126DV30 MoBL(R) ADVANCE INFORMATION Switching Characteristics Over the Operating Range[9] 55 ns Parameter Description Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[10] tHZOE 55 OE HIGH to High Z tLZCE CE LOW to Low Z 10 55 ns 25 ns ns 20 10 [10, 11] ns ns 5 [10, 11] [10] ns 55 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 55 ns tDBE BHE/BLE LOW to Data Valid 25 ns tLZBE BHE/BLE LOW to Low Z tHZBE BHE/BLE HIGH to High Z Write Cycle 20 0 ns ns 5 ns 20 ns [12] tWC Write Cycle Time 55 ns tSCE CE LOW to Write End 45 ns tAW Address Set-Up to Write End 45 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 45 ns tBW BHE/BLE Pulse Width 50 ns tSD Data Set-Up to Write End 25 ns tHD Data Hold from Write End 0 ns Z[10, 11] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[10] 20 5 ns ns Notes: 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05230 Rev. ** Page 5 of 12 ADVANCE INFORMATION CY62126DV30 MoBL(R) Switching Waveforms [13, 14] Read Cycle No. 1 (Address Transition Controlled) tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) DATA VALID [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE BHE/BLE ttLZOE LZOE tHZOE tDOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05230 Rev. ** Page 6 of 12 ADVANCE INFORMATION CY62126DV30 MoBL(R) Switching Waveforms (continued) [12, 16, 17] Write Cycle No. 1 (WE Controlled) tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 18 tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05230 Rev. ** Page 7 of 12 ADVANCE INFORMATION CY62126DV30 MoBL(R) Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 18 tHD DATAIN VALID tLZWE tHZWE [17] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 18 Document #: 38-05230 Rev. ** tHD DATAIN VALID Page 8 of 12 CY62126DV30 MoBL(R) ADVANCE INFORMATION Truth Table CE WE OE BHE BLE H X X X X High Z Inputs/Outputs Deselect/Power-Down Mode Standby (ISB) Power L X X H H High Z Output Disabled Active (ICC) L H L L L Data Out (I/OO-I/O15) Read Active (ICC) L H L H L Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8-I/O15); I/O0-I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO-I/O15) Write Active (ICC) L L X H L Data In (I/OO-I/O7); I/O8-I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8-I/O15); I/O0-I/O7 in High Z Write Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62126DV30L-55ZI Package Name Z44 Package Type 44-Lead TSOP II Operating Range Industrial CY62126DV30LL-55ZI CY62126DV30L-55BAI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62126DV30LL-55BAI Document #: 38-05230 Rev. ** Page 9 of 12 ADVANCE INFORMATION CY62126DV30 MoBL(R) Package Diagrams 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-** Document #: 38-05230 Rev. ** Page 10 of 12 ADVANCE INFORMATION CY62126DV30 MoBL(R) Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05230 Rev. ** Page 11 of 12 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ADVANCE INFORMATION CY62126DV30 MoBL(R) Document Title: CY62126DV30 MoBL(R) 64K x 16 Static RAM Document Number:38-05230 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117689 08/27/02 JUI New Data Sheet Document #: 38-05230 Rev. ** Page 12 of 12