64K x 16 Static RAM
CY62126DV30 MoBL®
ADVANCE
INFORMATION
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05230 Rev. ** Revised August 19, 2002
26DV30
Features
•High speed: 55 ns
•Wide voltage range: 2.2V–3.6V
•Pin Compatible with CY62126BV
•Ultra-low active power
—Typical active current: 0.5 mA @ f = 1MHz
—Typical active current: 5 mA @ f = fmax
•Low st andby power
•Easy memory expansion with CE and OE featur es
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Available in 44-lead TSOP Type II and 48-ball FBGA
packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces pow er co ns ump tio n by 90 % wh en addres s es are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are plac ed in a hi gh-imp edanc e st ate when : des electe d
(CE HIGH), outputs are disabled (OE HIG H), bo th By te Hi gh
Enable and By te Low Enab le are disable d (BHE, BL E HIGH),
or during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then dat a fr om memory will a ppear on I/O8 to I/O15. See
the T ruth Table near the b ack of this dat a sheet fo r a comp lete
description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array I/O0 – I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
2048 x 512
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8 – I/O15
CE
WE
BLE
BHE
A0
A1
A9
A10
Note:
1. For best prac tice rec omm en da ti ons , ple ase ref er to the Cypress applica ti on note ‘System Design Guidelines’ on http://www .cypress.com
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 2 of 12
Pin Configurations[2, 3]
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...–0.3V to Vccmax + 0.3V
DC Voltage Applied to Outputs
in High Z State[5]....................................–0.3V to VCC + 0.3V
DC Input Voltage[5] ................................–0.3V to VCC + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper application.
4. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) > 500µs.
5. VIL(min.) = –2.0V for pulse durations less than 20 ns.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
265
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC DNU
VCC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top Vi ew
TSOP II (Fo r wa rd)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
Operating Range
Range Ambient Temper ature (TA) VCC[4]
Industrial –40°C to +85°C 2.2V to 3.6V
Product Portfol io
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (µA)
f = 1 MHz f = fmax
Min. Typ.[6] Max. Typ.[6] Max. Typ.[6] Max. Typ.[6] Max.
CY62126DV30L 2.2 3.0 3.6 55 0.5 1 5 10 1.5 4
CY62126DV30LL 3
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 3 of 12
Electrical Characteristics Over the Operating Range
Test Conditions
CY62126DV30-55
Parameter Description Min. Typ.[6] Max. Unit
VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH= –0.1 mA 2 V
2.7 < VCC < 3.6 IOH= –1.0 mA 2.4
VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL= 0.1 mA 0.4 V
2.7 < VCC < 3.6 IOL= 2.1 mA 0.4
VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3V V
2.7 < VCC < 3.6 2.2
VIL Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 V
2.7 < VCC < 3.6 0.8
IIX Input Leakage
Current GND < VI < VCC -1 +1 µA
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled -1 +1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 3.6V
Iout = 0mA
CMOS level
510 mA
f = 1 MHz 0.5 1
ISB1 Automati c CE
Power-Down
Current— CMOS
Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V ,
f = fmax (Address and Data
Only),f=0 (OE,WE,BHE and
BLE)
L1.5 4µA
LL 3
ISB2 Automati c CE
Power-Down
Current— CMOS
Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V ,
f = 0, Vcc=3.6V
L1.5 4µA
LL 3
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ) 6pF
COUT Output Capacitance 8pF
Thermal Resistance
Description Test Conditions Symbol BGA Unit
Thermal Resistance
(Juncti on to Ambi ent )[7] Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board ΘJA 55 °C/W
Thermal Resistance
(Juncti on to Ca se)[7] ΘJC 16 °C/W
Note:
7. Tested initially and after any design or process changes that may affect these parameters.
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 4 of 12
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT VTH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise TIme: 1 V/ns Fall Time: 1 V/ns
Parameters 2.5V 3.0V Unit
R1 16600 1216 Ohms
R2 15400 1374 Ohms
RTH 8000 645 Ohms
VTH 1.2 1.75 Volts
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[6] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC= 1.5V
CE > VCC – 0. 2V,
VIN > VCC – 0.2V or VIN < 0.2V
L1.2 µA
LL 0.8
tCDR[7] Chip Deselect to Data
Retenti on Time 0ns
tR[8] Operation Recovery Time 100 µs
Data Retention W aveform
Note:
8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100µs.
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
CE
VCC
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 5 of 12
Switching Characteristics Over the Operating Range[9]
Parameter Description
55 ns
Min Max Unit
Read Cycle
tRC Read Cycle Time 55 ns
tAA Address to Data Valid 55 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 55 ns
tDOE OE LOW to Data Valid 25 ns
tLZOE OE LOW to Low Z[10] 5ns
tHZOE OE HIGH to High Z[10, 11] 20 ns
tLZCE CE LOW to Low Z[10] 10 ns
tHZCE CE HIGH to High Z[10, 11] 20 ns
tPU CE LOW to Power-Up 0ns
tPD CE HIGH to Power-Down 55 ns
tDBE BHE/BLE LOW to Data Valid 25 ns
tLZBE BHE/BLE LOW to Low Z 5ns
tHZBE BHE/BLE HIGH to High Z 20 ns
Write Cycle[12]
tWC Wri te Cy c le Time 55 ns
tSCE CE LOW to Write End 45 ns
tAW Address Set-Up to Write End 45 ns
tHA Address Hold from Write End 0ns
tSA Address Set-Up to Write Start 0ns
tPWE WE Pulse Width 45 ns
tBW BHE/BLE Pulse Width 50 ns
tSD Data Set-Up to Write End 25 ns
tHD Data Hold from Write End 0ns
tHZWE WE LOW to High Z[10, 11] 20 ns
tLZWE WE HIGH to Low Z[10] 5ns
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output load i ng of
the specified IOL/IOH and 30 pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 6 of 12
Switching Waveforms
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
14. WE is HIGH for read cycle.
15. Addr ess valid prior to or coi ncident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
Read Cycle No. 2 (OE Controlled)[14, 15]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DOE
t
LZOE
tDBE
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 7 of 12
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE goes HIG H simulta neously with WE HIGH, the output remai ns in a high- impedan ce st ate.
18. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN VALID
NOTE
Write Cycle No. 1 (WE Controlled) [12 , 16, 17]
18
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
Write Cycle No. 2 (CE Controlled)
BHE/BLE tBW
[12, 16, 17]
tSA
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 8 of 12
Switching Waveforms (continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 18
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
[17]
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
VALID
Write Cycle No. 4 (BHE/BLE Cont rolled, OE LOW)[17]
NOTE 18
t
BW
BHE/BLE
tSCE
t
PWE
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 9 of 12
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Stand by (ISB)
L X X H H High Z Output Disabled Active (ICC)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L Hi gh Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62126DV30L-55ZI Z44 44-Lead TSOP II Industrial
CY62126DV30LL-55ZI
CY62126DV30L-55BAI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30LL-55BAI
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 10 of 12
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV 48A
51-85150-**
CY62126DV30 MoBL®
ADVANC E INFORMATION
Document #: 38-05230 Rev. ** Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
CY62126DV30 MoBL®
ADVANCE INFORMATION
Document #: 38-05230 Rev. ** Page 12 of 12
Document Title: CY62126DV30 MoBL® 64K x 16 Static RAM
Document Numbe r:38-05230
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 117689 08/27/02 JUI New Dat a Sheet
