Z86E33/733/E34 Z86E43/743/E44 CMOS Z8(R) OTP Microcontrollers Product Specification PS022901-0508 Copyright (c)2008 by Zilog(R), Inc. All rights reserved. www.zilog.com Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer (c)2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS022901-0508 CMOS Z8(R) OTP Microcontrollers Product Specification iii Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. PS022901-0508 Date Revision Level Description Page No May 2008 01 All Original issue. Revision History CMOS Z8(R) OTP Microcontrollers Product Specification iv Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 22 34 37 37 38 38 46 77 79 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PS022901-0508 Table of Contents CMOS Z8(R) OTP Microcontrollers Product Specification 1 Architectural Overview Zilog's Z86E33/733/E34, E43/743/E44 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip Z8(R) MCU family featuring enhanced wake-up circuitry, programmable Watchdog Timers, Low Noise EMI options, and easy hardware/ software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has access to three additional control registers that allow easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E33/733/E34 have 24 pins, and the Z86E43/743/E44 have 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel I/O with or without handshake, and address/ data bus for interfacing external memory. Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Power connections follow these conventional descriptions: Connection Circuit Device Power VCC VDD Ground GND VSS Features Table 1 lists the features of Z86E33/733/E34, E43/743/E44. Table 1. Z86E33/733/E34, E43/743/E44 Features Device ROM (KB) RAM1 (Bytes) I/O Lines Speed (MHz) Z86E33 4 237 24 12 Z86733 8 237 24 12 Z86E34 16 237 24 12 Z86E43 4 236 32 12 Z86743 8 236 32 12 PS022901-0508 Architectural Overview CMOS Z8(R) OTP Microcontrollers Product Specification 2 Table 1. Z86E33/733/E34, E43/743/E44 Features (Continued) Device ROM (KB) RAM1 (Bytes) I/O Lines Speed (MHz) Z86E44 16 236 32 12 1 General-Purpose PS022901-0508 * * * Standard Temperature (VCC = 3.5 V to 5.5 V) * * * * * * Software Enabled Watchdog Timer (WDT) * * * * * * * * Low-Power Consumption: 60 mW Extended Temperature (VCC = 3.5 V to 5.5 V) Available Packages: - 28-Pin DIP/SOIC/PLCC OTP (E33/733/E34) - 40-Pin DIP OTP (E43/743/E44) - 44-Pin PLCC/LQFP OTP (E43/743/E44) Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 24/32 Input/Output Lines Clock-Free WDT Reset Auto Power-On Reset (POR) Programmable OTP Options: - RC Oscillator - EPROM Protect - Auto Latch Disable - Permanently Enabled WDT - Crystal Oscillator Feedback Resistor Disable - RAM Protect Fast Instruction Pointer: 0.75 s Two Standby Modes: STOP and HALT Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Two Comparators Architectural Overview CMOS Z8(R) OTP Microcontrollers Product Specification 3 * On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive Functional Block Diagram Figure 1 displays the functional block diagram. (E43/743/E44 Only) Output Input VCC GND Machine Timing & Inst. Control Port 3 Counter/ TimerS (2) Interrupt Control Two Analog Comparators XTAL AS DS R/W RESET RESET WDT, POR ALU OTP FLAGS Register Pointer Program Counter Register File Port 2 Port 0 4 I/O (Bit Programmable) 4 Address or I/O (Nibble Programmable) Port 1 8 Address/Data or I/O (Byte Programmable) ((E43/743/E44 Only) Figure 1. Functional Block Diagram PS022901-0508 Architectural Overview CMOS Z8(R) OTP Microcontrollers Product Specification 4 D7-0 AD 11-0 Z8 MCU AD 11-0 Address MUX D7-0 AD 13-0 Address Counter EPROM Data MUX TEST ROM D7-0 Z8 Port 2 OTP Options PGM + Test Mode Logic VPP P33 CLR CLK (P00) (P01) PGM P02 EPM P32 OE P31 CE XT1 Figure 2. EPROM Programming Block Diagram PS022901-0508 Architectural Overview CMOS Z8(R) OTP Microcontrollers Product Specification 5 Pin Description R/W 40 1 DS P25 P24 P26 P23 P27 P22 P04 P21 P05 P20 P06 P03 P14 P13 P15 P12 DIP 40-Pin P07 VCC GND P02 P16 P11 P17 P10 XTAL2 P01 XTAL1 P00 P31 P30 P32 P36 P33 P37 P34 AS P35 20 21 RESET Figure 3. 40-Pin DIP Pin Configuration Standard Mode Table 2. 40-Pin DIP Pin Identification Standard Mode PS022901-0508 Pin No Symbol Function Direction 1 R/W Read/Write Output 2-4 P25-P27 Port 2, Pins 5,6,7 Input/Output 5-7 P04-P06 Port 0, Pins 4,5,6 Input/Output 8-9 P14-P15 Port 1, Pins 4,5 Input/Output 10 P07 Port 0, Pin 7 Input/Output 11 VCC Power Supply 12-13 P16-P17 Port 1, Pins 6,7 Input/Output 14 XTAL2 Crystal Oscillator Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 6 Table 2. 40-Pin DIP Pin Identification Standard Mode (Continued) PS022901-0508 Pin No Symbol Function Direction 15 XTAL1 Crystal Oscillator Input 16-18 P31-P33 Port 3, Pins 1,2,3 Input 19 P34 Port 3, Pin 4 Output 20 AS Address Strobe Output 21 RESET Reset Input 22 P35 Port 3, Pin 5 Output 23 P37 Port 3, Pin 7 Output 24 P36 Port 3, Pin 6 Output 25 P30 Port 3, Pin 0 Input 26-27 P00-P01 Port 0, Pins 0,1 Input/Output 28-29 P10-P11 Port 1, Pins 0,1 Input/Output 30 P02 Port 0, Pin 2 Input/Output 31 GND Ground 32-33 P12-P13 Port 1, Pins 2,3 Input/Output 34 P03 Port 0, Pin 3 Input/Output 35-39 P20-P24 Port 2, Pins 0, 1,2,3,4 Input/Output 40 DS Data Strobe Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification P00 P01 P10 P11 P02 GND GND P13 P12 P03 P20 7 1 6 40 39 7 P21 P30 P22 P36 P23 P37 P24 P35 DS NC RESET 44-Pin PLCC R/RL R/W AS P25 P34 P26 P33 P27 P32 XTAL2 P17 P16 VCC P07 VCC P15 P14 18 P31 XTAL1 29 28 P06 17 P05 P04 Figure 4. 44-Pin PLCC Pin Configuration Standard Mode Table 3. 44-Pin PLCC Pin Identification PS022901-0508 Pin No Symbol Function Direction 1-2 GND Ground 3-4 P12-P13 Port 1, Pins 2,3 Input/Output 5 P03 Port 0, Pin 3 Input/Output 6-10 P20-P24 Port 2, Pins 0,1,2,3,4 Input/Output 11 DS Data Strobe Output 12 NC No Connection 13 R/W Read/Write Output 14-16 P25-P27 Port 2, Pins 5,6,7 Input/Output 17-19 P04-P06 Port 0, Pins 4,5,6 Input/Output 20-21 P14-P15 Port 1, Pins 4,5 Input/Output 22 P07 Port 0, Pin 7 Input/Output 23-24 VCC Power Supply 25-26 P16-P17 Port 1, Pins 6,7 Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 8 Table 3. 44-Pin PLCC Pin Identification (Continued) PS022901-0508 Pin No Symbol Function Direction 27 XTAL2 Crystal Oscillator Output 28 XTAL1 Crystal Oscillator Input 29-31 P31-P33 Port 3, Pins 1,2,3 Input 32 P34 Port 3, Pin 4 Output 33 AS Address Strobe Output 34 R//RL ROM/ROMless select Input 35 RESET Reset Input 36 P35 Port 3, Pin 5 Output 37 P37 Port 3, Pin 7 Output 38 P36 Port 3, Pin 6 Output 39 P30 Port 3, Pin 0 Input 40-41 P00-P01 Port 0, Pins 0,1 Input/Output 42-43 P10-P11 Port 1, Pins 0,1 Input/Output 44 P02 Port 0, Pin 2 Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 33 P21 P00 P01 P10 P11 P02 GND GND P12 P13 P03 P20 9 23 34 22 P22 P30 P36 P23 P37 P24 P35 DS RESET NC 44-Pin LQFP R/RL R/W AS P25 P34 P26 P33 P27 P32 P04 44 6 P06 P14 P15 P07 VCC 7 8 9 10 11 XTAL1 5 XTAL2 4 P17 3 P16 2 VCC 1 P05 12 P31 Figure 5. 44-Pin LQFP Pin Configuration Standard Mode Table 4. 44-Pin LQFP Pin Identification PS022901-0508 Pin No Symbol Function Direction 1-2 P05-P06 Port 0, Pins 5,6 Input/Output 3-4 P14-P15 Port 1, Pins 4,5 Input/Output 5 P07 Port 0, Pin 7 Input/Output 6-7 VCC Power Supply 8-9 P16-P17 Port 1, Pins 6,7 Input/Output 10 XTAL2 Crystal Oscillator Output 11 XTAL1 Crystal Oscillator Input 12-14 P31-P33 Port 3, Pins 1,2,3 Input 15 P34 Port 3, Pin 4 Output 16 AS Address Strobe Output 17 R//RL ROM/ROMless select Input Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 10 Table 4. 44-Pin LQFP Pin Identification (Continued) PS022901-0508 Pin No Symbol Function Direction 18 RESET Reset Input 19 P35 Port 3, Pin 5 Output 20 P37 Port 3, Pin 7 Output 21 P36 Port 3, Pin 6 Output 22 P30 Port 3, Pin 0 Input 23-24 P00-P01 Port 0, Pin 0,1 Input/Output 25-26 P10-P11 Port 1, Pins 0,1 Input/Output 27 P02 Port 0, Pin 2 Input/Output 28-29 GND Ground 30-31 P12-P13 Port 1, Pins 2,3 Input/Output 32 P03 Port 0, Pin 3 Input/Output 33-37 P20-24 Port 2, Pins 0,1,2,3,4 Input/Output 38 DS Data Strobe Output 39 NC No Connection 40 R/W Read/Write Output 41-43 P25-P27 Port 2, Pins 5,6,7 Input/Output 44 P04 Port 0, Pin 4 Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 11 NC 40 1 NC D5 D4 D6 D3 D7 D2 NC D1 NC D0 NC NC NC NC NC NC DIP 40-Pin NC VCC GND PGM NC NC NC NC NC CLK CE CLR OE NC EPM NC VPP NC NC NC NC 20 21 NC Figure 6. 40-Pin DIP Pin Configuration EPROM Mode Table 5. 40-Pin DIP Package Pin Identification EPROM Mode PS022901-0508 Pin No Symbol Function Direction 1 NC No Connection 2-4 D5-D7 Data 5,6,7 5-10 NC No Connection 11 VCC Power Supply 12-14 NC No Connection 15 CE Chip Select Input 16 OE Output Enable Input 17 EPM EPROM Prog. Mode Input 18 VPP Prog. Voltage Input 19-25 NC No Connection 26 CLR Clear Input 27 CLK Clock Input 28-29 NC No Connection Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 12 Table 5. 40-Pin DIP Package Pin Identification EPROM Mode (Continued) PS022901-0508 Pin No Symbol Function Direction 30 /PGM Prog. Mode Input 31 GND Ground 32-34 NC No Connection 35-39 D0-D4 Data 0,1,2,3,4 40 NC No Connection Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification CLR CLK NC NC PGM GND 1 6 D1 GND NC NC NC D0 13 40 39 7 NC D2 NC D3 NC D4 NC NC NC NC 44-Pin PLCC NC NC NC D5 NC D6 VPP D7 EPM NC NC NC VCC NC VCC NC NC 18 OE OE 29 28 NC 17 NC NC Figure 7. 44-Pin PLCC Pin Configuration EPROM Programming Mode Table 6. 44-Pin PLCC Pin Configuration EPROM Programming Mode PS022901-0508 Pin No Symbol Function Direction 1-2 GND Ground 3-5 NC No Connection 6-10 D0-D4 Data 0,1,2,3,4 11-13 NC No Connection 14-16 D5-D7 Data 5,6,7 17-22 NC No Connection 23-24 VCC Power Supply 25-27 NC No Connection 28 CE Chip Select Input 29 OE Output Enable Input 30 EPM EPROM Prog. Mode Input 31 VPP Prog. Voltage Input Input/Output Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 14 Table 6. 44-Pin PLCC Pin Configuration EPROM Programming Mode (Continued) PS022901-0508 Pin No Symbol Function Direction 32-39 NC No Connection 40 CLR Clear Input 41 CLK Clock Input 42-43 NC No Connection 44 /PGM Prog. Mode Input Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 33 34 D1 CLR CLK NC NC PGM GND GND NC NC NC D0 15 40 22 NC D2 NC D3 NC D4 NC NC NC NC 44-Pin LQFP NC NC NC D5 NC D6 VPP D7 EPM NC NC NC VCC NC VCC NC NC 1 OE OE 12 11 NC 44 NC NC Figure 8. 44-Pin LQFP Pin Configuration EPROM Programming Mode Table 7. 44-Pin LQFP Pin Identification EPROM Programming Mode PS022901-0508 Pin No Symbol Function Direction 1-5 NC No Connection 6-7 VCC Power Supply 8-10 NC No Connection 11 CE Chip Select Input 12 OE Output Enable Input 13 EPM EPROM Prog. Mode Input 14 VPP Prog. Voltage Input 15-22 NC No Connection 23 CLR Clear Input 24 CLK Clock Input 25-26 NC No Connection 27 /PGM Prog. Mode 28-29 GND Ground 30-32 NC No Connection Input Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 16 Table 7. 44-Pin LQFP Pin Identification EPROM Programming Mode (Continued) PS022901-0508 Pin No Symbol Function Direction 33-37 D0-D4 Data 0,1,2,3,4 Input/Output 38-40 NC No Connection 41-43 D5-D7 Data 5,6,7 44 NC No Connection Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 17 P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin DIP/SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration Table 8. 28-Pin DIP/SOIC/PLCC Pin Identification Standard Mode PS022901-0508 Pin No Symbol Function Direction 1-3 P25-P27 Port 2, Pins 5,6, Input/Output 4-7 P04-P07 Port 0, Pins 4,5,6,7 In/Output 8 VCC Power Supply 9 XTAL2 Crystal Oscillator Output 10 XTAL1 Crystal Oscillator Input 11-13 P31-P33 Port 3, Pins 1,2,3 Input 14-15 P34-P35 Port 3, Pins 4,5 Output 16 P37 Port 3, Pin 7 Output 17 P36 Port 3, Pin 6 Output 18 P30 Port 3, Pin 0 Input 19-21 P00-P02 Port 0, Pins 0,1,2 Input/Output 22 VSS Ground 23 P03 Port 0, Pin 3 Input/Output 24-28 P20-P24 Port 2, Pins 0,1,2,3,4 Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 4 P05 P23 1 P22 P24 P25 P26 P27 P04 18 26 25 5 P21 P06 P20 P07 P03 VDD VSS XTAL2 P02 XTAL1 P01 P36 P37 P35 P34 P00 P30 19 18 12 P33 11 P32 P31 Figure 10. Standard Mode 28-Pin PLCC Pin Configuration D5 D6 D7 NC NC NC NC VCC NC CE OE EPM VPP NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin DIP/SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D4 D3 D2 D1 D0 NC VSS PGM CLK CLR NC NC NC NC Figure 11. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration PS022901-0508 Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 4 NC 1 D2 D3 D4 D5 D6 D7 NC 19 26 25 5 D1 D0 NC NC NC VCC VSS NC PGM CE CLK 19 18 NC NC NC NC EPM 12 CLR NC 11 VPP OE Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration Table 9. 28-Pin EPROM Pin Identification EPROM Mode PS022901-0508 Pin # Symbol Function Direction 1-3 D5-D7 Data 5,6,7 Input/Output 4-7 NC No Connection 8 VCC Power Supply 9 NC No connection 10 CE Chip Select Input 11 OE Output Enable Input 12 EPM EPROM Prog. Mode Input 13 VPP Prog. Voltage Input 14-18 NC No Connection 19 CLR Clear 20 CLK Clock 21 /PGM Prog. Mode 22 VSS Ground 23 NC No Connection 24-28 D0-D4 Data 0,1,2,3,4 Input Input/Output Pin Description CMOS Z8(R) OTP Microcontrollers Product Specification 20 Electrical Characteristics Absolute Maximum Ratings Table 10. Absolute Maximum Ratings Parameter Min Max Units Ambient Temperature under Bias -40 +105 C Storage Temperature -65 +150 C Voltage on any Pin with Respect to VSS -0.6 +7 V Voltage on VDD Pin with Respect to VSS -0.3 +7 V Voltage on XTAL1, P32, P33 and RESET Pins with Respect to VSS -0.6 VDD+1 V Total Power Dissipation 1.21 W Maximum Allowable Current out of VSS 220 mA Maximum Allowable Current into VDD 180 mA Notes 1 2 Maximum Allowable Current into an Input Pin -600 +600 A 3 Maximum Allowable Current into an Open-Drain Pin -600 +600 A 4 Maximum Allowable Output Current Sunk by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Maximum Allowable Output Current Sunk by RESET Pin 3 mA Notes 1. This applies to all pins except XTAL pins and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 21 Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [IDD - (sum of IOH), + sum of [(VDD - VOH) x IOH] + sum of (VOL x IOL) Standard Test Conditions The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load). From Output Under Test 150 pF Figure 13. Test Load Diagram Capacitance TA = 25 C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND. PS022901-0508 Parameter Min Max Input capacitance 0 12 pF Output capacitance 0 12 pF I/O capacitance 0 12 pF Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 22 DC Electrical Characteristics Table 11. DC Electrical Characteristics TA = 0 C to +70 C Typical @ 25C Units Conditions Symbol Parameter VCC1 Min Max VCH Clock Input High Voltage 3.5V 0.7 VCC VCC +0.3 1.8 V 5.5V 0.7 VCC VCC +0.3 2.5 V Clock Input Low Voltage 3.5V 5.5V GND -0.3 0.2 VCC GND -0.3 0.2 VCC Input High Voltage 3.5V VCL VIH VIL VOH VOH1 VOL VOL1 VOL2 VRH VRL VOLR Driven by External Clock Generator 0.9 V 1.5 V 0.7 VCC VCC +0.3 2.5 V 5.5V 0.7 VCC VCC +0.3 2.5 V Input Low Voltage 3.5V 1.5 V 5.5V GND -0.3 0.2 VCC GND -0.3 0.2 VCC 1.5 V Output High Voltage Low EMI Mode 3.5V VCC -0.4 3.3 5.5V VCC -0.4 4.8 3.5V VCC -0.4 3.3 V IOH = -2.0 mA 5.5V VCC -0.4 4.8 V IOH = -2.0 mA Output High Voltage Notes Driven by External Clock Generator IOH = -0.5 mA Output Low Voltage Low EMI Mode 3.5V 0.4 0.2 V IOL = 1.0 mA 5.5V 0.4 0.2 V IOL = 1.0 mA Output Low Voltage 3.5V 0.4 0.1 V IOL = +4.0 mA 2 5.5V 0.4 0.1 V IOL = +4.0 mA 2 Output Low Voltage 3.5V 1.2 0.5 V IOL = +10 mA 2 5.5V 1.2 0.5 V IOL = +10 mA 2 Reset Input High Voltage 3.5V .8 VCC VCC 1.7 V 3 5.5V .8 VCC VCC 2.1 V 3 Reset Input Low Voltage 3.5V GND -0.3 0.2 VCC GND -0.3 0.2 VCC 1.3 V 3 1.7 V 3 0.6 0.3 V IOL = 1.0 mA 3 0.6 0.2 V IOL = 1.0 mA 3 5.5V Reset Output Low 3.5V Voltage 5.5V PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 23 Table 11. DC Electrical Characteristics TA = 0 C to +70 C (Continued) Max Typical @ 25C Units Conditions 3.5V 25 10 mV 5.5V 25 10 mV Symbol Parameter VCC1 VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range 3.5V 0 VCC -1.0V V 4 5.5V 0 VCC -1.0V V 4 Input Leakage 3.5V -1 2 0.032 A VIN = 0V, VCC 5.5V -1 2 0.032 A VIN = 0V, VCC Output Leakage 3.5V -1 2 0.032 A VIN = 0V, VCC 5.5V -1 2 0.032 A VIN = 0V, VCC Reset Input Current 3.5V -20 -130 -65 A 5.5V -20 -180 -112 A Supply Current 3.5V 15 5 mA @ 12 MHz 5,6 5.5V 20 15 mA @ 12 MHz 5,6 Standby Current HALT Mode 3.5V 4 2 mA 5,6 5.5V 6 4 mA VIN = 0V, VCC @ 12 MHz 3.5V 3 1.5 mA 5.5V 5 3 mA Clock Divide by 5,6 16 @ 12 MHz 5,6 3.5V 10 2 A VIN = 0V, VCC 7,8,9 5.5V 10 3 A VIN = 0V, VCC 7,8,9 3.5V 15 7 A VIN = 0V, VCC 7,8 5.5V 30 10 A VIN = 0V, VCC 7,8 IIL IOL IIR ICC ICC1 ICC2 IALL IALH Standby Current STOP Mode Min Notes 5,6 Auto Latch Low Current 3.0V 0.7 8 2.4 A 0V < VIN < VCC 10 5.5V 1.4 15 4.7 A 0V < VIN < VCC 10 Auto Latch High Current 3.5V -0.6 -5 -1.8 A 0V < VIN < VCC 10 5.5V -1 -8 -3.8 A 0V < VIN < VCC 10 PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 24 Table 11. DC Electrical Characteristics TA = 0 C to +70 C (Continued) Symbol Parameter VCC1 Min Max Typical @ 25C Units Conditions TPOR 3.5V 2.0 ms 24 7 ms 5.5V 1.0 ms 13 4 ms 2.3 3.0 2.8 V VLV Power-On Reset Auto Reset Voltage Notes 11,12 Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V 2. STD Mode (not Low EMI Mode) 3. Z86E43/743/E44 only. 4. For analog comparator inputs when analog comparators are enabled 5. All outputs unloaded, I/O pins floating, inputs at rail. 6. CL1=CL2=22 pF. 7. Same as note 5 except inputs at VCC 8. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 9. WDT running 10. Auto Latch (mask option) selected. 11. Device does function down to the Auto Reset voltage 12. Max. temperature is 70 C Table 12. DC Electrical Characteristics TA= -40 C to +105 C Typical @ 25C Units Conditions Symbo l Parameter VCC1 Min Max VCH Clock Input High Voltage 4.5V 0.7 VCC VCC +0.3 2.5 V 5.5V 0.7 VCC VCC +0.3 2.5 V Clock Input Low Voltage 4.5V 5.5V GND -0.3 0.2 VCC GND -0.3 0.2 VCC Input High Voltage 4.5V VCL VIH VIL VOH Notes Driven by External Clock Generator 1.5 V 1.5 V 0.7 VCC VCC +0.3 2.5 V 5.5V 0.7 VCC VCC +0.3 2.5 V Input Low Voltage 4.5V 1.5 V 5.5V GND -0.3 0.2 VCC GND -0.3 0.2 VCC 1.5 V Output High Voltage Low EMI Mode 4.5V VCC -0.4 4.8 IOH = -0.5 mA 2 5.5V VCC -0.4 4.8 IOH = -0.5 mA 2 PS022901-0508 Driven by External Clock Generator Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 25 Table 12. DC Electrical Characteristics TA= -40 C to +105 C (Continued) Symbo l Parameter VCC1 Min VOH1 Output High Voltage 4.5V 5.5V Output Low Voltage Low EMI Mode 4.5V VOL VOL1 VOL2 VRH VOLR Typical @ 25C Units Conditions Notes VCC -0.4 4.8 V IOH = -2.0 mA 2 VCC -0.4 4.8 V IOH = -2.0 mA 2 0.4 0.2 V IOL = 1.0 mA 5.5V 0.4 0.2 V IOL = 1.0 mA Output Low Voltage 4.5V 0.4 0.1 V IOL = +4.0 mA 2 5.5V 0.4 0.1 V IOL = +4.0 mA 2 Output Low Voltage 4.5V 1.2 0.5 V IOL = +12 mA 2 5.5V 1.2 0.5 V IOL = +12 mA 2 Reset Input High Voltage 4.5V .8 VCC VCC 1.7 V 3 5.5V .8 VCC VCC 2.1 V 3 0.6 0.3 V IOL = 1.0 mA 3 0.6 0.2 V IOL = 1.0 mA 3 Reset Output Low 4.5V Voltage 5.5V Max VOFFSET Comparator Input Offset Voltage 4.5V 25 10 mV 5.5V 25 10 mV VICR Input Common Mode Voltage Range 4.5V 0 VCC -1.5V V 4 5.5V 0 VCC -1.5V V 4 Input Leakage 4.5V -1 2 <1 A VIN = 0V, VCC 5.5V -1 2 <1 A VIN = 0V, VCC Output Leakage 4.5V -1 2 <1 A VIN = 0V, VCC 5.5V -1 2 <1 A VIN = 0V, VCC Reset Input Current 4.5V -18 -180 -112 A 3 5.5V -18 -180 -112 A 3 Supply Current 4.5V 20 15 mA @ 12 MHz 5,6 5.5V 20 15 mA @ 12 MHz 5,6 Standby Current HALT Mode 4.5V 6 2 mA VIN = 0V, VCC @ 12 MHz 5,6 5.5V 6 4 mA VIN = 0V, VCC @ 12 MHz 5,6 IIL IOL IIR ICC ICC1 PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 26 Table 12. DC Electrical Characteristics TA= -40 C to +105 C (Continued) Symbo l Parameter VCC1 ICC2 IALL IALH TPOR VLV Standby Current STOP Mode Auto Latch Low Current Auto Latch High Current Power-On Reset Auto Reset Voltage Max Typical @ 25C Units Conditions Notes 4.5V 10 2 A VIN = 0V, VCC 7,8,9 5.5V 10 3 A VIN = 0V, VCC 7,8,9 4.5V 40 10 A VIN = 0V, VCC 7,8 5.5V 40 10 A VIN = 0V, VCC 7,8 Min 4.5V 1.4 20 4.7 A 0V < VIN < VCC 10 5.5V 1.4 20 4.7 A 0V < VIN < VCC 10 4.5V -1.0 -10 -3.8 A 0V < VIN < VCC 10 5.5V -1.0 -10 -3.8 A 0V < VIN < VCC 10 4.5V 1.0 14 4 ms 5.5V 1.0 14 4 ms 2.0 3.3 2.8 V 11 Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. STD Mode (not Low EMI Mode). 3. Z86E43/743/E44 only. 4. For analog comparator inputs when analog comparators are enabled. 5. All outputs unloaded, I/O pins floating, inputs at rail. 6. CL1=CL2=22 pF. 7. Same as note 5 except inputs at VCC. 8. Clock must be forced Low, when XTAL1 is clock driven and XTAL2. 9. WDT is not running. 10. Auto Latch (mask option) selected. 11. Device does function down to the Auto Reset voltage. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 27 R/W 13 12 19 Port0, DM 16 20 18 3 Port1 A7-A0 D7-D0 IN 22 1 9 AS 8 4 11 6 5 DS (Read) 17 10 Port1 A7-A0 D7-D0 OUT 14 15 7 DS (Write) Figure 14. External I/O or Memory Read/Write Timing (Z86E43/743/E44 Only) Table 13. DC Electrical Characteristics TA = 0 C to +70 C, 12 MHz No. Symbol Parameter VCC1 Min 1 TdA(AS) Address Valid to AS Rise Delay 3.5V 35 ns 2 5.5V 35 ns 2 3.5V 45 ns 2 5.5V 45 ns 2 2 3 TdAS(A) TdAS(DR) PS022901-0508 AS Rise to Address Float Delay Max Units Notes AS Rise to Read Data Req'd Valid 3.5V 250 ns 2,3 5.5V 250 ns 2,3 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 28 Table 13. DC Electrical Characteristics TA = 0 C to +70 C, 12 MHz (Continued) No. Symbol Parameter VCC1 Min 4 TwAS AS Low Width 3.5V 55 ns 2 5.5V 55 ns 2 3.5V 0 ns 5.5V 0 ns 3.5V 200 ns 2,3 5.5V 200 ns 2,3 3.5V 110 ns 2,3 5.5V 110 ns 2,3 5 6 7 8 9 10 11 12 13 14 15 16 17 TdAS(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) PS022901-0508 Address Float to DS Fall DS (Read) Low Width DS (Write) Low Width Max Units Notes DS Fail to Read Data Req'd Valid 3.5V 150 ns 2,3 5.5V 150 ns 2,3 Read Data to DS Rise Hold Time 3.5V 0 ns 2 5.5V 0 ns 2 DS Rise to Address Active Delay 3.5V 45 ns 2 5.5V 55 ns 2 DS Rise to AS Fall Delay 3.5V 30 ns 2 5.5V 45 ns 2 3.5V 45 ns 2 5.5V 45 ns 2 3.5V 45 ns 2 5.5V 45 ns 2 Write Data Valid to DS Fall (Write) 3.5V Delay 5.5V 55 ns 2 55 ns 2 DS Rise to Write Data Not Valid Delay 3.5V 45 ns 2 5.5V 55 ns 2 310 ns 2,3 310 ns 2,3 R/W Valid to AS Rise Delay DS Rise to R/W Not Valid Address Valid to Read Data Req'd 3.5V Valid 5.5V AS Rise to DS Fall Delay 3.5V 65 ns 2 5.5V 65 ns 2 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 29 Table 13. DC Electrical Characteristics TA = 0 C to +70 C, 12 MHz (Continued) No. Symbol Parameter VCC1 Min 18 TdDM(AS) DM Valid to AS Rise Delay 3.5V 35 ns 2 5.5V 35 ns 2 DS Valid to Address Valid Hold Time 3.5V 35 ns 2 5.5V 35 ns 2 19 ThDS(AS) Max Units Notes Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing numbers given are for minimum TpC. 3. When using extended memory timing, add 2 TpC Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0. Table 14. DC Electrical Characteristics TA = -40 C to +105 C, 12 MHz No. Symbol Parameter VCC1 Min 1 TdA(AS) Address Valid to AS Rise Delay 4.5V 35 ns 2 5.5V 35 ns 2 4.5V 45 ns 2 5.5V 45 ns 2 2 3 4 5 6 7 8 9 TdAS(A) TdAS(DR) TwAS TdAS(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) PS022901-0508 AS Rise to Address Float Delay Max Units Notes AS Rise to Read Data Req'd Valid 4.5V 250 ns 2,3 5.5V 250 ns 2,3 AS Low Width Address Float to DS Fall DS (Read) Low Width DS (Write) Low Width 4.5V 55 ns 2 5.5V 55 ns 2 4.5V 0 ns 5.5V 0 ns 4.5V 200 ns 2,3 5.5V 200 ns 2,3 4.5V 110 ns 2,3 5.5V 110 ns 2,3 DS Fail to Read Data Req'd Valid 4.5V 150 ns 2,3 5.5V 150 ns 2,3 Read Data to DS Rise Hold Time 4.5V 0 ns 2 5.5V 0 ns 2 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 30 Table 14. DC Electrical Characteristics TA = -40 C to +105 C, 12 MHz (Continued) No. Symbol Parameter VCC1 Min 10 TdDS(A) DS Rise to Address Active Delay 4.5V 45 ns 2 5.5V 55 ns 2 DS Rise to AS Fall Delay 4.5V 45 ns 2 5.5V 45 ns 2 4.5V 45 ns 2 5.5V 45 ns 2 4.5V 45 ns 2 5.5V 45 ns 2 Write Data Valid to DS Fall (Write) 4.5V Delay 5.5V 55 ns 2 55 ns 2 DS Rise to Write Data Not Valid Delay 4.5V 55 ns 2 5.5V 55 ns 2 310 ns 2,3 310 ns 2,3 11 12 13 14 15 16 17 18 19 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) ThDS(AS) R/W Valid to AS Rise Delay DS Rise to R/W Not Valid Address Valid to Read Data Req'd 4.5V Valid 5.5V AS Rise to DS Fall Delay Max Units Notes 4.5V 65 ns 2 5.5V 65 ns 2 4.5V 35 ns 2 5.5V 35 ns 2 DS Valid to Address Valid Hold Time 4.5V 35 ns 2 5.5V 35 ns 2 DM Valid to AS Rise Delay Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing numbers given are for minimum TpC. 3. When using extended memory timing, add 2 TpC. Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 31 3 1 Clock 2 3 2 7 2 TIN 5 4 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Figure 15. Additional Timing Diagram Table 15. Additional Timing Table (Divide-By-One Mode) TA = 0 C to +70 C No Symbol Parameter VCC1 Min Max Min Max Units Notes 1 TpC 3.5V 250 DC 166 DC ns 2,3,4 5.5V 250 DC 166 DC ns 2,3,4 2 3 4 TrC,TfC TwC TwTinL PS022901-0508 Input Clock Period Clock Input Rise & Fall Times 3.5V 25 25 ns 2,3,4 5.5V 25 25 ns 2,3,4 Input Clock Width 3.5V 100 100 ns 2,3,4 5.5V 100 100 ns 2,3,4 3.5V 100 100 ns 2,3,4 5.5V 70 70 ns 2,3,4 Timer Input Low Width Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 32 Table 15. Additional Timing Table (Divide-By-One Mode) TA = 0 C to +70 C (Continued) No Symbol Parameter VCC1 Min 5 TwTinH 3.5V 5TpC 5TpC 2,3,4 5.5V 5TpC 5TpC 2,3,4 3.5V 8TpC 8TpC 2,3,4 5.5V 8TpC 8TpC 2,3,4 6 7 8A 8B 9 10 11 TpTin Timer Input High Width Timer Input Period Max Min Max Units Notes TrTin, TfTin Timer Input Rise & Fall Timer 3.5V 100 100 ns 2,3,4 5.5V 100 100 ns 2,3,4 TwIL Int. Request Low Time 3.5V 100 100 ns 2,3,4,5 5.5V 70 70 ns 2,3,4,5 3.5V 5TpC 5TpC 2,3,4,6 5.5V 5TpC 5TpC 2,3,4,6 Int. Request Input High Time 3.5V 5TpC 5TpC 2,3,4,5 5.5V 5TpC 5TpC 2,3,4,5 Stop Mode Recovery Width Spec 3.5V 12 12 ns 4,7 5.5V 12 12 ns 4,7 Oscillator Startup Time 3.5V 5TpC 5TpC 4,7,8 5.5V 5TpC 5TpC 4,7,8 TwIL TwIH Twsm Tost Int. Request Low Time Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC; for a logic 0. 3. SMR D1 = 0. 4. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7 = 0. 5. Interrupt request via Port 3 (P31-P33). 6. Interrupt request via Port 3 (P30). 7. SMR-D5 = 1, POR STOP Mode Delay is on. 8. For RC and LC oscillator, and for oscillator driven by clock driver. Table 16. Additional Timing Table (Divide-By-One Mode) TA = -40 C to +105 C No Symbol Parameter VCC1 Min Max Min Max Units Notes 1 TpC 4.5V 250 DC 166 DC ns 2,3,4 5.5V 250 DC 166 DC ns 2,3,4 PS022901-0508 Input Clock Period Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 33 Table 16. Additional Timing Table (Divide-By-One Mode) TA = -40 C to +105 C (Continued) No Symbol Parameter VCC1 2 TrC,TfC Clock Input Rise & Fall Times 4.5V 5.5V Input Clock Width 4.5V 100 5.5V 3 4 5 6 7 8A 8B 9 10 11 TwC TwTinL TwTinH TpTin Timer Input Low Width Timer Input High Width Timer Input Period Min Max Min Max Units Notes 25 25 ns 2,3,4 25 25 ns 2,3,4 100 ns 2,3,4 100 100 ns 2,3,4 4.5V 100 100 ns 2,3,4 5.5V 70 70 ns 2,3,4 4.5V 5TpC 5TpC 2,3,4 5.5V 5TpC 5TpC 2,3,4 4.5V 8TpC 8TpC 2,3,4 5.5V 8TpC 8TpC 2,3,4 TrTin, TfTin Timer Input Rise & Fall Timer 4.5V 100 100 ns 2,3,4 5.5V 100 100 ns 2,3,4 TwIL Int. Request Low Time 4.5V 100 100 ns 2,3,4,5 5.5V 70 70 ns 2,3,4,5 4.5V 5TpC 5TpC 2,3,4,6 5.5V 5TpC 5TpC 2,3,4,6 Int. Request Input High Time 4.5V 5TpC 5TpC 2,3,4,5 5.5V 5TpC 5TpC 2,3,4,5 Stop Mode Recovery Width Spec 4.5V 12 12 ns 4,7 5.5V 12 12 ns 4,7 Oscillator Startup Time 4.5V 5TpC 5TpC 4,7,8 5.5V 5TpC 5TpC 4,7,8 TwIL TwIH Twsm Tost Int. Request Low Time Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC; for a logic 0. 3. SMR D1 = 0. 4. Maximum frequency for internal system clock is 4 MHz when using Low EMI OSC PCON Bit D7=0. 5. Interrupt request via Port 3 (P31-P33). 6. Interrupt request via Port 3 (P30). 7. SMR-D5 = 1, POR STOP Mode Delay is on. 8. For RC and LC oscillator, and for oscillator driven by clock driver. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 34 Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 Delayed DAV DAV (Input) 4 6 5 RDY (Output) Delayed RDY Figure 16. Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 Delayed DAV DAV (Output) 11 9 8 10 RDY (Input) Delayed RDY Figure 17. Output Handshake Timing Table 17. Additional Timing Table (Divide by Two Mode) TA = 0 C to +70 C No Symbol Parameter 1 2 3 TpC TrC,TfC TwC PS022901-0508 VCC1 Min Max Min Max Units Conditions Notes Input Clock Period 3.5V 62.5 DC 250 DC ns 2,6,4 5.5V 62.5 DC 250 DC ns 2,6,4 15 25 ns 2,6,4 15 25 ns 2,6,4 Clock Input Rise & 3.5V Fall Times 5.5V Input Clock Width 3.5V 31 31 ns 2,6,4 5.5V 31 31 ns 2,6,4 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 35 Table 17. Additional Timing Table (Divide by Two Mode) TA = 0 C to +70 C (Continued) No Symbol Parameter VCC1 Min 4 TwTinL Timer Input Low Width 3.5V 70 5.5V 5 TwTinH Timer Input High Width 3.5V Units Conditions Notes 70 ns 2,6,4 70 70 ns 5TpC 5TpC 2,6,4 5.5V 5TpC 5TpC 2,6,4 8TpC 2,6,4 6 TpTin Timer Input Period 3.5V 8TpC 5.5V 8TpC 7 TrTin, TfTin Timer Input Rise & 3.5V Fall Timer 5.5V Max Min Max 2,6,4 8TpC 2,6,4 100 100 ns 2,6,4 100 100 ns 2,6,4 70 ns 2,6,4,5 ns 8A TwIL Int. Request Low Time 3.5V 70 5.5V 70 70 8B TwIL Int. Request Low Time 3.5V 5TpC 5TpC 2,6,4,5 5.5V 5TpC 5TpC 2,6,4,5 5TpC 5TpC 2,6,4,5 2,6,4,5 9 TwIH Int. Request Input 3.5V High Time 5.5V 5TpC 5TpC 10 Twsm Stop Mode Recovery Width Spec 3.5V 12 12 ns 6,7 5.5V 12 12 ns 6,7 Oscillator Startup Time 3.5V 5TpC 5TpC 6,7 5.5V 5TpC 5TpC 6,7 11 12 Tost Twdt 3.5V Watchdog Timer Delay Time Before 5.5V Timeout 3.5V 2,6,4,5 7 10 ms D0 =0 8,9 3.5 5 ms D1 = 0 5,11 14 20 ms D0 =1 5,11 5.5V 7 10 ms D1 = 0 5,11 3.5V 28 40 ms D1 = 0 5,11 5.5V 14 20 ms D1 = 1 5,11 3.5V 112 160 ms D0 = 1 5,11 5.5V 56 80 ms D1 = 1 5,11 Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing Reference uses 0.7 VC0 for a logic 1 and 0.2 VGC for a logic 0. 3. SMR D1 = 0. 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Interrupt request via Port 3 (P31-P33) 6. Interrupt request via Port 3 (P30). 7. Maximum frequency for internal system clock is 2 MHz when using Low EMI OSC PCON Bit D7 = 0 8. Reg. WDTMR. 9. Using internal RC. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 36 Table 18. Additional Timing Table (Divide by Two Mode) TA = -40 C to +105 C No Symbol Parameter 1 TpC VCC1 Min Max Min Max Units Conditions Notes Input Clock Period 3.5V 62.5 DC 250 DC ns 2,6,4 5.5V 62.5 DC 250 DC ns 2,6,4 25 ns 2,6,4 2 TrC,TfC Clock Input Rise & 3.5V Fall Times 5.5V 3 TwC Input Clock Width 15 ns 2,6,4 3.5V 31 15 31 25 ns 2,6,4 5.5V 31 31 ns 2,6,4 70 ns 2,6,4 ns 4 TwTinL Timer Input Low Width 3.5V 70 5.5V 70 70 5 TwTinH Timer Input High Width 3.5V 5TpC 5TpC 2,6,4 5.5V 5TpC 5TpC 2,6,4 8TpC 2,6,4 6 TpTin Timer Input Period 3.5V 8TpC 5.5V 8TpC 7 TrTin, TfTin Timer Input Rise & 3.5V Fall Timer 5.5V 8TpC 2,6,4 2,6,4 100 100 ns 2,6,4 100 100 ns 2,6,4 70 ns 2,6,4,5 ns 8A TwIL Int. Request Low Time 3.5V 70 5.5V 70 70 8B TwIL Int. Request Low Time 3.5V 5TpC 5TpC 2,6,4,5 5.5V 5TpC 5TpC 2,6,4,5 2,6,4,5 2,6,4,5 9 TwIH Int. Request Input 3.5V High Time 5.5V 5TpC 5TpC 5TpC 5TpC 10 Twsm Stop Mode Recovery Width Spec 3.5V 12 12 ns 6,7 5.5V 12 12 ns 6,7 Oscillator Startup Time 3.5V 5TpC 5TpC 6,7 5.5V 5TpC 5TpC 6,7 11 Tost PS022901-0508 2,6,4,5 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 37 Table 18. Additional Timing Table (Divide by Two Mode) TA = -40 C to +105 C (Continued) No Symbol Parameter 12 Twdt VCC1 Min Watchdog Timer 3.5V Delay Time Before 5.5V Timeout 3.5V Max Min Max Units Conditions Notes ms D0 =0 8,9 7 10 3.5 5 ms D1 = 0 5,11 14 20 ms D0 =1 5,11 5.5V 7 10 ms D1 = 0 5,11 3.5V 28 40 ms D1 = 0 5,11 5.5V 14 20 ms D1 = 1 5,11 3.5V 112 160 ms D0 = 1 5,11 5.5V 56 80 ms D1 = 1 5,11 Notes 1. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V and the VCC voltage specification of 3.5 V guarantees only 3.5 V. 2. Timing Reference uses 0.7 VC0 for a logic 1 and 0.2 VGC for a logic 0. 3. SMR D1 = 0. 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Interrupt request via Port 3 (P31-P33) 6. Interrupt request via Port 3 (P30). 7. Maximum frequency for internal system clock is 2 MHz when using Low EMI OSC PCON Bit D7 = 0 8. Reg. WDTMR. 9. Using internal RC. Pin Functions EPROM Programming Mode D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. VCC Power Supply. This pin must supply 5 V during the EPROM read mode and 6 V during other modes. CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. OE Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 38 CLR Clear (active High). This pin resets the internal address counter at the High Level. CLK Address Clock. This pin is a clock input. The internal address counter increases by one for each clock cycle. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on pins P31 and RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP, EPM, OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following: * * * Using a clamping diode to VCC Adding a capacitor to the affected pin Enable EPROM/Test Mode Disable OTP option bit. Standard Mode XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output. R/W Read/Write (output, write Low). The R/W signal is Low when the CCP is writing to the external program or data memory (Z86E43/743/E44 only). RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished either through Power-On, Watchdog Timer reset, Stop Mode Recovery, or external reset. During Power-On Reset and Watchdog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. After the POR time, RESET is a Schmitt-triggered input. (RESET is available on Z86E43/743/E44 only.) To avoid asynchronous and noisy reset problems, the Z86E43/743/E44 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, DS is held active Low while AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 510 TpC cycles after RESET is released. For Power-On Reset, the reset output time is 5 ms. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 39 The Z86E43/743/E44 does not reset WDTMR, SMR, P2M, and P3M registers on a StopMode Recovery operation. ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to VCC, the device functions nor Note: When using in ROM Mode in High EMI (noisy) environment, the ROMless pins should be connected directly to VCC. DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of DS. For WRITE operations, the falling edge of DS indicates that output data is valid. AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle for external memory transfer. Address output is from Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of AS. Under program control, AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS-compatible I/0 port. These eight I/O lines can be configured under software control as a nibble I/0 port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Either nibble output that can be globally programmed as push-pull or opendrain. Low EMI output buffers can be globally programmed by the software. Port 0 can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to Port 0's upper nibble. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or Al 5-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless mode, after a hardware reset, Port 0 is configured as address lines Al 5-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include re-configuration to eliminate this extended timing mode. In ROM mode, Port 0 is defined as input after reset. Port 0 can be set in the High-Impedance Mode if selected as an address output state, along with Port 1 and the control signals AS, DS, and R/W (Figure 18). PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 40 4 MCU Port 0 (I/O) 4 Handshake Controls DAV0 and RDY0 (P32 and P35) Open-Drain OEN PAD Out 1.5 2.3 Hysteresis VCC @ VCC = 5.0V In Auto Latch R~ ~ 500 K Figure 18. Port 0 Configuration Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-compatible port with multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be programmed as inputs or outputs or can be configured under software control as an Address/ Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 1 can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and DAV1 (Ready and Data Available). To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines (see Figure 19). PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 41 Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86E43/743/E44 to share common resources in multiprocessor and DMA applications. In ROM mode, Port 1 is defined as input after reset. Port 2 (I/O) MCU Handshake Controls DAV1 and RDY1 (P33 and P34) Open Drain Open PAD Out 1.5 2.3 Hysteresis In Auto Latch R ~~ 500 k Figure 19. Port 1 Configuration (Z86E43/743/E44 Only) Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. These eight I/O lines can be configured under software control as an input or output, independently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. When used as an I/O port, Port 2 can be placed under handshake control. After reset, Port 2 is defined as an input. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 42 In Handshake Mode, Port 3 lines P31 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (see Figure 20). Port 2 (I/O) MCU Handshake Controls DAV2 and RDY2 (P31 and P36) Open Drain Open PAD Out 1.5 2.3 Hysteresis In Auto Latch R ~~ 500 k Figure 20. Port 2 Configuration Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33P30) and four fixed outputs (P37-P34). These eight lines can be configured by software for interrupt and handshake control functions. Port 3, Pin 0 is Schmitt- triggered. P31, P32, and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36, and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 43 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D0 to 1 state. For the interrupt function, P30 and P33 are falling edge triggered interrupt inputs. P31 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (see Figure 21). Access to Counter/Timer 1 is made through P31 (TIN) and P36 (TOUT). Handshake tines for Port 0, Port 1, and Port 2 are also available on Port 3 (see Table 19). Note: When enabling or disabling analog mode, the following is recommended: 1. Allow two NOP decays before reading this comparator output. 2. Disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. IRQ register bits 3 to 0 must be cleared after enabling analog mode. Note: P33-P30 differs from the Z86C33/C43/233/243 in that there is no clamping diode to VCC due to the EPROM high-voltage circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 44 MCU Port 3 (I/O or Control) Auto Latch R ~~ 500 k P30 R247 = P3M D1 P30 Data Latch IRQ3 0 = Digital 1 = Analog DIG. P31 (AN1) + - IRQ2, TIN, P31 Data Latch ANL. P32 (AN2) P33 (REF) IRQ0, P32 Data Latch + - IRQ1, P33 Data Latch From Stop-Mode Recovery Source Figure 21. Port 3 Configuration PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 45 Table 19. Port 3 Pin Assignments Pin I/O P30 IN P31 IN P32 CTC1 Analog Interrupt P0 HS P1 HS P2 HS Ext IRQ3 TIN AN1 IRQ2 IN AN2 IRQ0 P33 IN REF IRQ1 P34 OUT AN1-Out P35 OUT P36 OUT P37 OUT D/R D/R D/R R/D DM R/D TOUT R/D An2-Out Comparator Inputs. Port 3, P31, and P32, each have a comparator front end. The comparator reference voltage P33 is common to both comparators. In analog mode, P31 and P32 are the positive input of the comparators and P33 is the reference voltage of the comparators. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33P31) that are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Auto Latches are available on Port 0, Port 1, Port 2, and P30. There are no Auto Latches on P31, P32, and P33. Low EMI Emission. The Z86E43/743/E44 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently. Use of this feature results in: * * * * The pre-drivers slew rate reduced to 10 ns typical. Low EMI output drivers have resistance of 200 Ohms (typical). Low EMI Oscillator. Internal SCLK/TCLK= XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time, when Low EMI Oscillator is selected. Note: For emulation only: Do not set the emulator to emulate Port 1 in low EMI mode. Port 1 must always be configured in Standard Mode. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 46 Functional Description The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watchdog Timer 3. Stop Mode Recovery Source Note: Having the Auto Power-On Reset circuitry built-in, the MCU does not need to be connected to an external power-on reset circuit. The reset time is TPOR. The MCU does not re-initialize WDTMR, SMR, P2M, and P3M registers to their reset values on a Stop Mode Recovery operation. Note: The device VCC must rise up to the operating VCC specification before the TPOR expires. Program Memory. The MCU can address up to 4/8/16 KB of Internal Program Memory (see Figure 22). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 12 (000Ch) to address 4095 (0FFFh)/8191 (1FFFh)/ 16384 (3FFFh), consists of programmable EPROM. After reset, the program counter points at the address 000Ch, which is the starting address of the user program. In ROMless mode, the Z86E43/743/E44 can address up to 64 KB of External Program Memory. The ROM/ROMless option is only available on the 44-pin devices. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 47 ROM Module 65535 External ROM and RAM 4096/8192/16384 4095/8191/16383 Location of First Byte of Instruction Executed After RESET 12 ROMLess Module On-Chip EPROM External ROM and RAM 11 IRQ5 IRQ5 10 IRQ5 IRQ5 9 IRQ4 IRQ4 8 IRQ4 IRQ4 Interrupt 7 Vector (Lower Byte) 6 IRQ3 IRQ3 IRQ3 IRQ3 5 IRQ2 IRQ2 4 Interrupt Vector 3 (Upper Byte) 2 IRQ2 IRQ2 IRQ1 IRQ1 IRQ1 IRQ1 1 IRQ0 IRQ0 0 IRQ0 IRQ0 (Z86E43/743/E44 Only) Figure 22. Program Memory Map EPROM Protect. When in ROM Protect Mode, and executing out of External Program Memory, instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in EPROM Protect Mode and executing out of Internal Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. Data Memory (DM). In ROM Mode, the Z86E43/743/E44 can address up to 60156/48 KB of external data memory beginning at location 4096/8192/16384. In ROMless mode, the Z86E43/743/E44 can address up to 64 KB of data memory. External data memory may be included with, or separated from, the external program memory space. DM, an optional I/0 function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 23). The state of the DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (DM inactive) memory, and an LDE instruction references data (DM active Low) memory. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 48 EPROM ROMless Mode External Data Memory External Data Memory 65535 4096/8192/16384 4095/8191/16383 Not Addressable 0 (Z86E43/743/E44 Only) Figure 23. Data Memory Map Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration registers in the expanded register group. The instructions can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (see Figure 24). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Group E0-EF can only be accessed through working register and indirect addressing modes. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 49 R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Group Working Register Group Default after RESET = 00h Figure 24. Register Pointer Register Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space RO through R15 is implemented as 16 groups of 16 registers per group (see Figure 26). These register banks are known as the Expanded Register File (ERF). The low nibble (D3-D0) of the Register Pointer (RP) select the active ERF Bank, and the high nibble (D7-D4) of register RP select the working register group. Three system configuration registers reside in the Expanded Register File at bank FH: PCON, SMR, and WDTMR. The rest of the Expanded Register is not physically implemented and is reserved for future expansion. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 50 r7 r6 r5 r4 r3 r2 r1 r0 R232 (Register Pointer) This upper nibble of the register file addresses provided by the register pointer specifies the active working-register group. FF F0 EF 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F 10 0F 00 Specified Working Register Group The lower nibble of the register file addresses provided by the instruction points to the specified register. Register Group 1 R15 to R0 Register Group 0 R15 to R4 I/O Ports R3 to R0 * Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP). Figure 25. Register Pointer PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 51 RESET CONDITION D7 D6 D5 D4 D3 D2 D1 D0 REGISTER % FF SPL 0 0 0 0 0 0 0 0 % FE SPH 0 0 0 0 0 0 0 0 % FD RP 0 0 0 0 0 0 0 0 % FC FLAGS U U U U U U U U % FB IMR 0 U U U U U U U % FA IRQ 0 0 0 0 0 % F9 IPR U U U U U U U U % F8 P01M 0 1 0 0 1 1 0 0 * % F7 P3M 0 0 0 0 0 0 0 0 * % F6 P2M 1 1 1 1 1 1 1 1 % F5 PRE0 U U U U U U U U % F4 T0 U U U U U U U U % F3 PRE1 U U U U U U U U % F2 T1 U U U U U U U U % F1 TMR 0 0 0 0 0 % F0 Reserved REGISTER POINTER 7 6 5 4 3 2 1 0 Expanded Register Group Pointer Working Register Group Pointer Z8 Reg. File %FF %F0 EXPANDED REG. GROUP (F) REGISTER * * %7F ** Reserved %0F %00 Notes: U = Unknown For ROMless condition: "10110110" * Will not be reset with a STOP-Mode Recovery. ** Will not be reset with a STOP-Mode Recovery, except bit D0. % (F) 0F WDTMR % (F) 0E Reserved % (F) 0D SMR2 % (F) 0C Reserved % (F) 0B SMR % (F) 0A Reserved % (F) 09 Reserved % (F) 08 Reserved % (F) 07 Reserved % (F) 06 Reserved % (F) 05 Reserved % (F) 04 Reserved % (F) 03 Reserved % (F) 02 Reserved % (F) 01 Reserved % (F) 00 PCON 0 0 0 0 0 0 RESET CONDITION U U U 0 1 1 0 1 U U U U U U 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 EXPANDED REG. GROUP (0) RESET CONDITION REGISTER * % (0) 03 P3 1 1 1 1 U U U U * % (0) 02 P2 U U U U U U U U % (0) 01 P1 U U U U U U U U % (0) 00 P0 U U U U U U U U Figure 26. Expanded Register File Architecture General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. The register R254 is general-purpose on Z86E33/733/E34. R254 and R255 are set to 00h after any reset or Stop Mode Recovery. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 52 RAM Protect. The upper portion of the RAM's address spaces 80h to EFh (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R251) is used to turn off/on the RAM protect by loading a 0 or 1, respectively. A "1" in D6 indicates RAM Protect enabled. Stack. The Z86E43/743/E44 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254-R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096/8192/ 16384 to 65535 in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z8 that resides within the 236 general-purpose registers (R4-R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to 00H after any reset or Stop Mode Recovery. Counter/Timers. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The Ti prescaler is driven by internal or external clock sources; however, the TO prescaler is driven by the internal clock only (see Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256), that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching one (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 serves as a timer output (TOUT) through which T0, T1, or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 53 OSC Internal Data Bus Read Write Write /2 PRE0 Initial Value Register T0 Initial Value Register /16 6-Bit Down Counter 8-Bit Down Counter /4 Internal Clock IRQ4 /2 External Clock Clock Logic /4 Internal Clock Gated Clock Triggered Clock TIN P31 T0 Current Value Register Write 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register Write TOUT P36 IRQ5 T1 Current Value Register Read Internal Data Bus Figure 27. Counter/Timer Block Diagram Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30) and two in counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 20). PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 54 IRQ0 IRQ2 IRQ1, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7) IRQ IMR 6 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 28. Interrupt Block Diagram Table 20. Interrupt Types, Sources, and Vectors Name Source Vector Location Comments IRQ0 DAV0, IRQ0 0,1 External (P32), Rising/Falling Edge Triggered IRQ1 IRQ1 2,3 External (P33), Falling Edge Triggered IRQ2 DAV2, IRQ2, TIN 4,5 External (P31), Rising/Falling Edge Triggered IRQ3 IRQ3 6,7 External (P30), Falling Edge Triggered 1RQ4 T0 8,9 Internal IRQ5 T1 10,11 Internal PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 55 When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in bits D7 and D6 of the IRQ Register (R250). The configuration is shown in Table 21. Table 21. IRQ Register Configuration IRO Interrupt Edge D7 D6 P31 P32 0 0 F F 0 1 F R 1 0 R F 1 1 R/F R/F Notes 1. F = Falling Edge 2. R = Rising Edge Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, RC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 10 kHz to 16 MHz max, with a series resistance (RS) less than or equal to 100 . The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to device pin Ground. The RC oscillator option can be selected in the programming mode. The RC oscillator configuration must be an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to Ground (Table 29). PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 56 XTAL1 XTAL1 XTAL1 C1 C1 C1 XTAL1 R L XTAL2 XTAL2 XTAL2 C2 XTAL2 C2 VSS** Ceramic Resonator or Crystal C1, C2 = 33 pF TYP * LC RC C1, C2 = 22 pF @ 5V VCC (TYP) L = 130 H * f = 3 MHz f = 8 MHz * Typical value including pin parasitics External Clock C1 = 100 pF * R = 2K * f = 6 MHz * Figure 29. Oscillator Configuration Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR timer allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status 2. Stop Mode Recovery (if D5 of SMR=0) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is by-passed after Stop Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, you must execute a NOP (Opcode = FFh) immediately before the appropriate sleep instruction, that is: PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 57 FF NOP ; clear the pipeline 6F STOP ; enter STOP mode FF NOP ; clear the pipeline 7F HALT ; enter HALT mode or STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. STOP Mode is terminated by one of the following resets: either by WDT time-out, POR, a Stop Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address 000Ch. Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00 (Figure 30). PCON (FH) 00h D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output* 0 Port 1 Open-Drain 1 Port 1 Push-pull Active* 0 Port 0 Open-Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* * Default Setting After Reset 0 Port 3 Low EMI 1 Port 3 Standard* Low EMI Character 0 Low EMI 1 Standard Figure 30. Port Configuration Register (PCON) (Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 58 Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A "1" in this location brings the comparator outputs to P34 and P37, and a "0" releases the Port to its standard I/O configuration. The default value is 0. Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit (D1=0) or configured as push-pull active by setting this bit (D1=1). The default value is 1. Port 0 Open-Drain (D2). Port 0 can be configured as an open-drain by resetting this bit (D2=0) or configured as push-pull active by setting this bit (D2=1). The default value is 1. Low EMI Port 0 (D3). Port 0 can be configured as a Low EMI Port by resetting this bit (D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1. Low EMI Port 1 (D4). Port 1 can be configured as a Low EMI Port by resetting this bit (D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1. Note: The emulator does not support Port 1 low EMI mode and must be set D4 = 1. Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1. Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1. Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscillator. A "1" in this location configures the oscillator with standard drive. While a "0" configures the oscillator with low noise drive, however, it does not affect the relationship of SCLK and XTAL. The low EMI mode will reduce the drive of the oscillator (OSC). The default value is 1. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop Mode Recovery (Figure 31). All bits are Write Only except bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4 of the SMR register specify the Stop Mode Recovery Source. The SMR is located in Bank F of the Expanded Register File at address 0BH. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 59 SMR (Fh) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF** 1 ON External Clock Divide-by-2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL STOP-Mode Recovery Source 000 POR Only and/or External Reset* 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON Stop Recovery Level 0 Low* 1 High Stop Flag (Read only) 0 POR* 1 Stop Recovery * Default setting after RESET ** Default setting after RESET and STOP-Mode Recovery Figure 31. Stop Mode Recovery Register (Write-Only Except Bit D7, Which Is Read-Only) SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. Stop Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake up source of the Stop Mode Recovery (Figure 32). Table 22 shows the SMR source selected with the setting of D2 to D4. P33-P31 cannot be used to wake up PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 60 from STOP mode when programmed as analog inputs. When the Stop Mode Recovery sources are selected in this register then SMR2 register bits D0, D1 must be set to zero. Note: If the Port 2 pin is configured as an output, this output level will be read by the SMR circuitry. SMR D1 D0 0 0 VDD SMR D4 D3 D2 0 0 0 VDD P30 P31 P32 SMR D4 0 0 0 D3 0 1 1 SMR2 D1 D0 0 1 P20 P20 P23 P23 D2 SMR D4 D3 D2 SMR D4 D3 D2 1 1 0 0 1 0 1 0 P20 1 P33 SMR D4 D3 D2 1 1 0 SMR2 D1 D0 1 0 SMR D4 D3 D2 1 1 1 P20 P27 P23 P27 To POR RESET STOP-Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 MUX P33 from Pads Digital/Analog Mode Select (P3M) Figure 32. Stop Mode Recovery Source PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 61 Table 22. Stop Mode Recovery Source D4 D3 D2 SMR Source selection 0 0 0 POR recovery only 0 0 1 P30 transition 0 1 0 P31 transition (Not in analog mode) 0 1 1 P32 transition (Not in analog mode) 1 0 0 P33 transition (Not in analog mode) 1 0 1 P27 transition 1 1 0 Logical NOR of Port 2 bits 0-3 1 1 1 Logical NOR of Port 2 bits 0-7 Stop Mode Recovery Delay Select (D5). The 5 ms RESET delay after Stop Mode Recovery is disabled by programming this bit to a zero. A "1" in this bit will cause a 5 ms RESET delay after Stop Mode Recovery. The default condition of this bit is 1. If the fast wake up mode is selected, the Stop Mode Recovery source needs to be kept active for at least 5TpC. Stop Mode Recovery Level Select (D6). A "1" in this bit defines that a high level on any one of the recovery sources wakes the MCU from STOP Mode. A 0 defines low level recovery. The default value is 0. Cold or Warm Start (D7). This bit is set by the device upon entering STOP Mode. A "0" in this bit indicates that the device has been reset by POR (cold). A "1" in this bit indicates the device was awakened by a SMR source (warm). Stop Mode Recovery Register 2 (SMR2). This register contains additional Stop Mode Recovery sources. When the Stop Mode Recovery sources are selected in this register then SMR Register Bits D2, D3, and D4 must be 0. SMR:10 Operation D1 DO 0 0 POR and/or external reset recovery 0 1 Logical AND of P20 through P23 1 0 Logical AND of P20 through P27 Description of Action Watchdog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 62 Reset and initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT is driven either by an on-board RC oscillator or an external oscillator from XTAL1 pin. The POR clock source is selected with bit 4 of the WDT register. Note: Execution of the WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. WDT Time-Out Period (D0 and D1). Bits 0 and 1 control a tap circuit that determines the time-out periods that can be obtained (Table 23). The default value of DO and Dl are 1 and 0, respectively. Table 23. Time-out Period of WDT D1 DO Time-out of the Internal RC Time-out of the OSC System Clock 0 0 5 ms ms1 128 SCLK 256 SCLK1 0 1 10 1 0 20 ms 512 SCLK 1 1 80 ms 2048 SCLK Note: The default setting is 10 ms. WDT During HALT Mode (D2). This bit determines whether or not the WDT is active during HALT Mode. A "1" indicates that the WDT is active during HALT. A "0" disables the WDT in HALT Mode. The default value is "1 ". WDT During STOP Mode (D3). This bit determines whether or not the WDT is active during STOP mode. A "1" indicates active during STOP. A "0" disables the WDT during STOP Mode. This is applicable only when the WDT clock source is the internal RC oscillator. Clock Source For WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1, and the WDT is stopped in STOP Mode. The default configuration of this bit is 0, which selects the RC oscillator. Permanent WDT. When this feature is enabled, the WDT is enabled after reset and will operate in Run and HALT Mode. The control bits in the WDTMR do not affect the WDT operation. If the clock source of the WDT is the internal RC oscillator, then the WDT will run in STOP mode. If the clock source of the WDT is the XTAL1 pin, then the WDT will not run in STOP mode. PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 63 Note: WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but will activate the TPOR delay. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system clock cycles from the execution of the first instruction after Power-On Reset, Watchdog reset or a Stop Mode Recovery (Figure 33 and Figure 34). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register File at address location 0Fh. Clock Free WDT Reset. The WDT will enable the Z8 to reset the I/0 pins whenever the WDT times out, even without a clock source running on the XTAL1 and XTAL2 pins. WDTMR Bit D4 must be 0 for the clock Free WDT to work. The I/O pins will default to their default settings. WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC External Clock 128 TpC 5 ms 00 256 TpC 10 ms 01* 512 TpC 25 ms 10 2048 TpC 80 ms 11 WDT During HALT 0 OFF 1 ON* WDT During STOP 0 OFF 1 ON* XTAL1/INT RC Select for WDT 0 On-Board RC* 1 XTAL Reserved (Must be 0) * Default setting after RESET Figure 33. Watchdog Timer Mode Register Write Only PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 64 RESET 4 Clock Filter Clear CLK 18 Clock RESET RESET Generator Internal RESET WDT Select (WDTMR) WDT TAP SELECT CLK Source Select (WDTMR) XTAL Internal RC OSC VDD VLV + M U X 5ms POR CLK CLR 5ms15ms25ms100ms WDT/POR Counter Chain 2V Operating Voltage Det. - WDT From STOP Mode Recovery Source STOP Delay Select (SMR) Figure 34. Resets and WDT Auto Reset Voltage. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC is below VLV (Figure 35). PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 65 VCC 3.7 (Volts) 3.5 3.3 3.1 2.8 2.7 2.5 2.3 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Figure 35. Typical VLV Voltage vs. Temperature PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 66 Z8 Control Register Diagrams Ordering Information PCON (FH) 00h D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output* 0 Port 1 Open-Drain 1 Port 1 Push-pull Active* 0 Port 0 Open-Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* * Default Setting After Reset Must be set to "1" for Z86E33/733/E34 0 Port 3 Low EMI 1 Port 3 Standard* Low EMI Character 0 Low EMI 1 Standard Figure 36. Port Configuration Register (PCON) (Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 67 SMR (Fh) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF** 1 ON External Clock Divide-by-2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL STOP-Mode Recovery Source 000 POR Only and/or External Reset* 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON Stop Recovery Level 0 Low* 1 High Stop Flag (Read only) 0 POR* 1 Stop Recovery Note: Note used in conjunction with SMR2 Source * Default setting after RESET ** Default setting after RESET and STOP-Mode Recovery Figure 37. Stop Mode Recovery Register (Write Only Except Bit D7, Which is Read Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 68 WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC External Clock 128 TpC 5 ms 00 256 TpC 10 ms 01* 512 TpC 20 ms 10 2048 TpC 80 ms 11 WDT During HALT 0 OFF 1 ON* WDT During STOP 0 OFF 1 ON* XTAL1/INT RC Select for WDT 0 On-Board RC* 1 XTAL Reserved (Must be 0) * Default setting after RESET Figure 38. Watchdog Timer Mode Register (Write Only) SMR (0F) Dh D7 D6 D5 D4 D3 D2 D1 D0 STOP-Mode Recovery Source 2 00 POR only* 01 AND P20, P21, P22, P23 10 AND P20, P21, P22, P23, P24, P25, P26, P27 Reserved (Must be 0) Note: Not used in conjunction with SMR Source Figure 39. Stop Mode Recovery Register2 (Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 69 R240 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Figure 40. Reserved R241 Timer D7 D6 D5 D4 D3 D2 D1 D0 0 No Function 1 Load T0 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T1 0 Disable T1 Count 1 Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out Default After Reset = 00h Figure 41. Timer Mode Register (F1h: Read/Write) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 70 R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 T1 Invalid Value (When Written) (Range 1-258 Decimal 01-00 HEX) T1 Current Value (When READ) Figure 42. Counter/Timer 1 Register (F2h: Read/Write) R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 = T1 Single Pass 1 = T1 Modulo N Clock Source 1 = T1 Internal 0 = T1 External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) *Default After Reset Figure 43. Prescaler 1 Register (F3h: Write Only) R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) Figure 44. Counter/Timer 0 Register (F4h: Read/Write) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 71 R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 = T1 Single Pass 1 = T1 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 45. Prescaler 0 Register (F5h: Write Only) R246 P2M D7 D6 D5 D4 D3 D2 D1 * Default after Reset D0 P20 - P27 I/O Definition 0 Defines Bit as output 1 Defines Bit as input Figure 46. Port 2 Mode Register (F6h: Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 72 R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Pull-Ups Open Drain 1 Port 2 Push-Pull Active 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode 0 P32 = Input P35 = Output 1 P32 = DAV0/RDY0 P35 = DAV0/RDY0 0 P33 = Input P34 = Output 01 P33 = Input 10 P34 = DM 11 P33 = DAV1/RDY1 P34 = RDY0/DAV0 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = DAV2/RDY2 P36 = RDY2/DAV2 0 P30 = Input P37 = Output Reserved (Must be 0) Default After Reset = 00h Z86E33/733/E34 Must be 00 Figure 47. Port 3 Mode Register (F7h: Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 73 R248 P01M D7 D6 D5 D4 D3 D2 D1 D0 P00 - P03 Mode 00 Output 01 Input 1X A11-A8 Stack Selection 0 External 1 Internal* P10-P17 Mode 00 Byte Output 01 Byte Input* 10 AD7-AD0 11 High-Impedance AD7-AD0, AS, DS, R/W, A11-A8, A15-A12, If Selected External Memory Timing 0 Normal 1 Extended P04-P07 Mode 00 Output 01 Input* 1X A15-A12 Reset Condition = 0100 1101B For ROMless Condition = 1011 0110B Z86E33/733/E34 Must be 00 * Default after Reset Figure 48. Port 0 and 1 Mode Register (F8h: Write Only) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 74 R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 49. Interrupt Priority Register (F9h: Write Only) R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Default After Reset = 00h = = = = = = P32 P33 P31 P30 T0 T1 Input Input Input Input Inter Edge P31 P32 P31 P32 P31 P32 P31 P32 = 00 = 01 = 10 = 11 Figure 50. Interrupt Request Register (FAh: Read/Write) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 75 R251 IMR D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5 -IRQ0 (D0 = IRQ0) 1 Enables RAM Protect* 1 Enables Interrupts * This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently Figure 51. Interrupt Mask Register (FBh: Read/Write) R252 Flags D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Halt Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 52. Flag Register (FCh: Read/Write) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 76 R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register File Working Register Pointer Default After Reset = 00h Figure 53. Register Pointer (FDh: Read/Write) R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 (Z86E33/733/E34 ) 0 = 0 State 1 = 1 State (Z86E43/743/E44 ) Stack Pointer Upper Byte (SP8-SP15) Default After Reset = 00h Figure 54. Stack Pointer High (FEh: Read/Write) R254 SPL D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Lower Byte (SP0-SP7) Default After Reset = 00h Figure 55. Stack Pointer Low (FFh: Read/Write) PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 77 Package Information Figure 56. 40-PIN DIP Package Diagram Figure 57. 44-PIN LQFP Package Diagram PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 78 Figure 58. 28-Pin DIP Package Diagram Figure 59. 28-Pin SOIC Package Diagram PS022901-0508 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 79 Ordering Information Table 24.Ordering Information Product PS022901-0508 Speed (MHz) Package Type Pin Count Z86E3312PSC 12 PDIP 28 Z86E3312SCC 12 SOIC 28 Z86E3312PSC 12 PLCC 28 Z86E3412PEC 12 PDIP 28 Z86E3412PSC 12 PDIP 28 Z86E3412SSC 12 SOIC 28 Z86E3412VSC 12 PLCC 28 Z86E4312FSC 12 LQFP 44 Z86E4312PSC 12 PDIP 40 Z86E4312VSC 12 PLCC 44 Z86E4412FSC 12 LQFP 44 Z86E4412PEC 12 PDIP 40 Z86E4412PSC 12 PDIP 40 Z86E4412VSC 12 PLCC 44 Z8673312PSC 12 PDIP 28 Z8673312SSC 12 SOIC 28 Z8673312VSC 12 PLCC 28 Z8674312FSC 12 LQFP 44 Z8674312PSC 12 PDIP 40 Z8674312VSC 12 PLCC 44 Electrical Characteristics CMOS Z8(R) OTP Microcontrollers Product Specification 80 Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog's offerings, please visit Zilog's Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog's Technical Support at http://support.zilog.com. PS022901-0508 Customer Support