Preliminary Data Sheet October 2001 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Features Basic forward/reverse battery SLIC functionality at a low cost Pin compatible with Agere Systems Inc. L9218/L9219 SLIC Low active power (typical 154 mW during on-hook transmission) Low-power scan mode for low-power on-hook power dissipation (57 mW typical) Distortion-free on-hook transmission Convenient operating states: -- Forward powerup -- Reverse powerup -- Low-power scan -- Disconnect (high impedance) -- PPM operational states Minimal external components required Two gain options to optimize codec interface Adjustable supervision functions: -- Off-hook detector with hysteresis -- Ring trip detector Adjustable loop current limit Adjustable overhead voltage Ramped rate of battery reversal Periodic pulse metering (PPM) compatible Thermal protection with thermal shutdown indication Description This general-purpose electronic subscriber loop interface circuit (SLIC) is optimized for low cost, while still providing a satisfactory set of features. This part is a pin-for-pin replacement for the Agere L9218/L9219 SLIC. The L9217 requires a +5 V power supply and single battery to operate. This device offers forward and reverse battery operation. The rate of battery reversal may be ramped to meet international requirements. Additionally, a low-power scan mode, wherein all circuitry except the off-hook supervision is shut down to conserve power, is available. The dc current limit may be programmed via a single external resistor. Both the loop supervision and ring trip supervision functions are offered with user-controlled thresholds via external resistors. Overhead is adequate for 3.14 dBm into 900 of on-hook transmission. The device is periodic pulse metering (PPM) compatible, offering a convenient point for meter pulse injection and filter point for rejection of the meter pulse signal. In the PPM active modes, overhead voltage is automatically increased to accommodate on-hook transmission of meter pulse signals. The level that the overhead is increased to is set by a single external resistor. In this way, the L9217 can accomodate high-voltage meter pulse signals. The L9217 is offered with a receive gain that is optimized to interface to a first-generation type codec (L9217A). It is also offered with a gain option that is optimized to interface to a third- or fourth-generation type codec (L9217G); in both cases, minimizing external components is required at this interface. Data control is via a parallel data control scheme. The device is available in a 28-pin PLCC package. It is built by using a 90 V complementary bipolar (CBIC) process. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Table of Contents Contents Page Features ......................................................................1 Description...................................................................1 Pin Information ............................................................4 Functional Description .................................................6 Absolute Maximum Ratings ........................................7 Recommended Operating Conditions .........................7 Electrical Characteristics .............................................8 Ring Trip Requirements .........................................12 Test Configurations ...................................................13 Applications ...............................................................15 dc Applications .......................................................20 Battery Feed.........................................................20 Overhead Voltage.................................................20 Rate of Battery Reversal ......................................21 Loop Range..........................................................21 Off-Hook Detection...............................................21 Ring Trip Detection...............................................22 Longitudinal Balance ..............................................23 Periodic Pulse Metering (PPM)...............................23 ac Design ...............................................................24 Codec Types ........................................................24 ac Interface Network ............................................24 Receive Interface .................................................24 Example 1: Real Termination (First-Generation Codec) ...................................25 Example 2: Complex Termination (First-Generation Codec) ...................................27 Power Derating .......................................................29 Pin-for-Pin Compatibility with L9218/L9219 ............29 PCB Layout Information ............................................29 Outline Diagram.........................................................30 28-Pin PLCC ..........................................................30 Ordering Information..................................................31 2 Figures Page Figure 1. Functional Diagram ..................................... 3 Figure 2. 28-Pin PLCC ............................................... 4 Figure 3. Ring Trip Circuits ....................................... 12 Figure 4. L9217 Basic Test Circuit ........................... 13 Figure 5. Metallic PSRR ........................................... 13 Figure 6. Longitudinal PSRR .................................... 13 Figure 7. Longitudinal Balance ................................. 14 Figure 8. RFI Rejection............................................. 14 Figure 9. Longitudinal Impedance ............................ 14 Figure 10. ac Gains .................................................. 14 Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec ....................... 15 Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec ...................... 18 Figure 13. Loop Current vs. Loop Voltage................ 20 Figure 14. Off-Hook Detection Circuit....................... 21 Figure 15. Ring Trip Equivalent Circuit and Equivalent Application............................. 22 Figure 16. ac Equivalent Circuit ............................... 25 Figure 17. Interface Circuit Using First-Generation Codec (5 V Codec)................................ 28 Figure 18. Interface Circuit Using First-Generation Codec (+5 V Only Codec) ....................... 28 Tables Page Table 1. Pin Descriptions ........................................... 4 Table 2. Input State Coding ....................................... 6 Table 3. Supervision Coding ..................................... 6 Table 4. Power Supply .............................................. 8 Table 5. 2-Wire Port .................................................. 9 Table 6. Analog Pin Characteristics ........................ 10 Table 7. PPM............................................................ 10 Table 8. ac Feed Characteristics ............................. 11 Table 9. Logic Inputs and Outputs ........................... 12 Table 10. Parts List for Loop Start Application Circuit Using T7504-Type Codec......................... 16 Table 11. 900 Termination, 850 + 50 nF Hybrid First-Generation Codec Design Parameters .............................................. 17 Table 12. Parts List for Loop Start Application Circuit Using T8536-Type Codec ............. 19 Table 13. FB1/FB2 Values vs.Typical Ramp Time .......................................................... 21 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 OVH FB2 FB1 CF2 CF1 AGND VCC BGND IPROG Description (continued) POWER CONDITIONING AND REFERENCE FORWARD AND REVERSE BATTERY RECTIFIER DCOUT 3 + AX - VTX = 41 V/A TG TXI AAC VITR = 9.66 PPMOUT - A=1 PT =5 + A = -1 - PR PPMIN PPM + TIP/RING CURRENT SENSE - RCVN + RCVP A VERSION GAIN = 3.93 G VERSION GAIN = 1 B0 BATTERY FEED STATE CONTROL B1 B2 LCTH LOOP CLOSURE DETECTOR + - + RTSP RTSN RING TRIP DETECTOR NSTAT - 12-3557GM(F) Figure 1. Functional Diagram Agere Systems Inc. 3 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 VCC FB1 FB2 IPROG PPMOUT OVH TG Pin Information 4 3 2 1 28 27 26 RCVP 5 25 VTX RCVN 6 24 TXI LCTH 7 23 VITR DCOUT 8 22 NSTAT VBAT 9 21 PPMIN PR 10 20 RTSP CF2 11 19 RTSN 12 13 14 15 16 17 18 CF1 B2 B1 B0 AGND BGND PT 28-PIN PLCC 12-3558C(F) Figure 2. 28-Pin PLCC Table 1. Pin Descriptions PLCC Symbol Type Description 1 IPROG I Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of the device. 2 FB2 -- Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of battery reversal. 3 FB1 -- Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of battery reversal. 4 VCC -- 5 V Power Supply. 5 RCVP I Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. 6 RCVN I Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. 4 Agere Systems Inc. Preliminary Data Sheet October 2001 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Pin Information (continued) Table 1. Pin Descriptions (continued) PLCC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol LCTH Type Description I Loop Closure Threshold Input. Connect a resistor to DCOUT to set off-hook threshold. DCOUT O dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. VBAT -- Battery Supply. Negative high-voltage power supply. PR I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing circuitry. Connect to the loop through overvoltage protection. CF2 -- Filter Capacitor 2. Connect a 0.1 F capacitor from this pin to AGND. CF1 -- Filter Capacitor 1. Connect a 0.47 F capacitor from this pin to pin CF2. B2 I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B2 has internal pull-down. B1 I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B1 has internal pull-down. B0 I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B0 has internal pull-down. AGND -- Analog Signal Ground. BGND -- Battery Ground. Ground return for the battery supply. PT I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing circuitry. Connect to loop through overvoltage protection. RTSN I Ring Trip Sense Negative. Connect this pin to the ringing generator signal through a high-value resistor. RTSP I Ring Trip Sense Positive. Connect this pin to the ring relay and the ringer series resistor through a high-value resistor. PPMIN I Receive PPM Signal Input. This high-impedance input controls the PPM differential voltage on tip and ring. The PPM signal may be present at this pin at all times: however, PPM will only be transmitted to tip and ring if the appropriate PPM state is chosen. ac couple the PPM signal to this node. NSTAT O Ring Trip Detector Output/Loop Detector Output. When low, this logic output indicates that ringing is tripped or that an off-hook condition exists. VITR O ac Output Voltage. The voltage at this point is directly proportional to the differential tip/ring current. TXI I ac/dc Separation. Connect a 0.1 F capacitor from this point to VTX. VTX O ac Output Voltage. This output is a voltage that is directly proportional to the differential tip/ring current. TG -- Transmit Gain. Connect a 8.06 k from TG to VTX to set the transmit gain of the SLIC. OVH I PPM Overhead. Connect a resistor from this node to ground to set the overhead voltage during PPM high overhead modes. PPMOUT O PPM Signal Output. Connect a resistor from this node to TG for hybrid cancellation of the periodic pulse metering (PPM) signal. Agere Systems Inc. 5 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Functional Description Table 2. Input State Coding B0 1 B1 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 B2 State/Definition 1 Powerup, Forward Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is unaffected by resistor OVH and is adequate for 3.14 dBm overload into 900 . 1 Powerup, Reverse Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is negative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is unaffected by resistor OVH and is adequate for 3.14 dBm overload into 900 . 0 Powerup, Forward Battery, High Overhead. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is increased via ressitor OVH 0 Powerup, Reverse Battery, High Overhead. Normal talk and battery feed state. Pin PT is negative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is increased via resistor OVH. 1 Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin PT is positive with respect to pin PR. On-hook transmission is disabled. 1 Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance state (>100 k). Supervision outputs read on hook. Device will power up in this state. 0 Powerup, Reverse Battery, High Overhead with PPM. Normal talk and battery feed state. Pin PT is negative with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is increased via resistor OVH. 0 Powerup, Forward Battery, High Overhead with PPM. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is increased via resistor OVH. Table 3. Supervision Coding NSTAT 0 = off-hook or ring trip. 1 = on-hook and no ring trip. 6 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Absolute Maximum Ratings (at TA = 25 C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter 5 V Power Supply Battery (Talking) Supply Logic Input Voltage Analog Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) PT or PR Fault Voltage (dc) PT or PR Fault Voltage (10 x 1000 s) Current into Ring Trip Inputs Symbol VCC VBAT -- -- TJ Tstg RH -- VPT, VPR VPT, VPR IRTSP, IRTSN Min -- -- -0.5 -7.0 150 -40 5 -- VBAT - 5 VBAT - 15 -- Typ -- -- -- -- -- -- -- 3 -- -- 240 Max 7.0 -75 7.0 7.0 -- 125 95 -- 3 15 -- Unit V V V V C C % V V V A Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following: 1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters. 2. Inductance in the V BAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage. Recommended Operating Conditions Parameter Ambient Temperature VCC Supply Voltage VBAT Supply Voltage Agere Systems Inc. Min -40 4.75 -24 Typ -- 5.0 -48 Max 85 5.25 -70 Unit C V V 7 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Electrical Characteristics Minimum and maximum values are testing requirements in the temperature range of 25 C to 85 C and battery range of -24 V to -70 V. These minimum and maximum values are guaranteed to -40 C based on component simulations and design verification of samples, but devices are not tested to -40 C in production. The test circuit shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device. Typical values are characteristics of the device design at 25 C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are V CC = 5.0 V, VBAT = -48 V, unless otherwise noted. Table 4. Power Supply Parameter Power Supply--Powerup, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply--Scan, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply--Disconnect, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply Rejection 500 Hz to 3 kHz (See Figures 5, 6, 16, and 17.)1: VCC VBAT Min Typ Max Unit -- -- -- 5.2 -2.66 154 6.5 -2.95 175 mA mA mW -- -- -- 3.4 -0.9 57 4.3 -1 70 mA mA mW -- -- -- 1.9 -0.1 14 -- -- -- mA mA mW 30 36 -- -- -- -- dB dB Thermal Protection Shutdown (Tjc)1 150 165 -- C -- -- -- -- 30 43 27 36 -- -- -- -- C/W C/W C/W C/W Thermal Resistance Still Air, Junction to Ambient (JA)1, 2: Natural Convection 2S2P Board Natural Convection 2S0P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board 1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. Airflow, PCB board layers, and other factors can greatly affect this parameter. 8 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Electrical Characteristics (continued) Table 5. 2-Wire Port Parameter Min Typ Max Unit Tip or Ring Drive Current = dc + Longitudinal + Signal Currents 80 -- -- mA Signal Current 15 -- -- mArms 8.5 15 -- mArms 15 -- -- 5 45 -- mA % Powerup Open Loop Voltage Levels (PPMOFF): Common-mode Voltage Differential Voltage V BAT = -48 V4 (Gain = 2) Differential Voltage V BAT = -48 V4 (Gain = 7.86) -- |VBAT + 7.5| |VBAT + 8.0| VBAT/2 |VBAT + 6.5| |VBAT + 6.5| -- |VBAT + 5.9| |VBAT + 5.9| V V V Powerup Open Loop Voltage Levels (PPMON) Minimum Programmed Overhead: Differential Voltage V BAT = -48 V (Gain = 7.86) -- -- |VBAT + 18.67| V Disconnect State: Leakage -- 10 150 A -- 72 100 Loop Resistance Range (-3.17 dBm overload into 900 ; not including protection): ILOOP = 20 mA at VBAT = -48 V 1800 -- -- Longitudinal to Metallic Balance--IEEE 5 Std. 455 (See Figure 7.)6: 200 Hz to 3400 Hz 58 61 -- dB Metallic to Longitudinal Balance (open loop): 200 Hz to 4 kHz 46 -- -- dB RFI Rejection (See Figure 8.)3, 0.5 Vrms, 50 Source, 30% AM Mod 1 kHz: 500 kHz to 100 MHz -- -- -- -55 -- -45 -- dBV Longitudinal Current Capability per Wire 1 dc Loop Current Limit2: Allowed Range Including Tolerance3 Accuracy (RLOOP = 100 , VBAT = -48 V) dc Feed Resistance (for ILOOP below regulation level) (does not include protection resistor) 1. The longitudinal current is independent of dc loop current. 2. Current-limit ILIM is programmed by a resistor, RPROG, from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting begins (see Figure 13). 3. This parameter is not tested in production. It is guaranteed by design and device characterization. 4. Specification is reduced to |VBAT1 + 10.5 V| minimum when V BAT1 = -70 V at 85 C. 5. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. 6. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in the Applications section of this document. Agere Systems Inc. 9 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Electrical Characteristics (continued) Table 6. Analog Pin Characteristics Parameter Min Typ Max Unit 121 -200 125 -- 129 200 V/A mV 8.8 6.0 -- -- 13.6 10.2 mA mA -- -8.7 IN - 0.5 10 -8.2 IN -- -7.7 IN + 0.5 mV V A -- -- -0.2 1 -1 -- A M Differential PT/PR Current Sense (DCOUT): Gain (PT/PR to DCOUT) Offset Voltage at ILOOP = 0 Loop Closure Detector Threshold (RLCTH = 22.1 k)1: On- to Off-hook Threshold (scan mode) Off- to On-hook Threshold (active mode) Ring Trip Comparator: Input Offset Voltage2 Internal Voltage Source Current at Input RTSP3 RCVN, RCVP: Input Bias Current Input Resistance 1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. The programming equation or relationship between off-hook threshold and resistor value is different for active mode versus scan mode (see Applications section for more details). 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 A to 30 A. Table 7. PPM Parameter PPM Source*: Frequency (f1) Frequency (f2) Input Signal Signal Gain (from PPMIN to amplifier outputs) Harmonic Distortion Isolation Min Typ Max Unit 11.88 15.80 0 9 -- 50 12 16 -- 10 5 -- 12.12 16.20 0.525 11 -- -- kHz kHz Vrms -- % dB * PPM signal should be ac-coupled into PPMIN. 10 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Electrical Characteristics (continued) Table 8. ac Feed Characteristics Parameter Min Typ Max Unit 150 -- 1300 Longitudinal Impedance at PT/PR 2 -- 0 -- Total Harmonic Distortion--200 Hz to 4 kHz2: Off-hook On-hook -- -- -- -- 0.3 1.0 % % -391 -403 -415 V/A 7.62 -7.62 7.86 -7.86 8.09 -8.09 -- -- 1.94 -1.94 2.00 -2.00 2.06 -2.06 -- -- Gain vs. Frequency (transmit and receive) (600 termination; reference 1 kHz2): 200 Hz to 300 Hz 300 Hz to 3.4 kHz 3.4 kHz to 16 kHz 16 kHz to 266 kHz -1.00 -0.3 -3.0 -- 0.0 0.0 -0.1 -- 0.05 0.05 0.3 2.5 dB dB dB dB Gain vs. Level (transmit and receive)(reference 0 dBV 2): -55 dB to +3 dB -0.05 0 0.05 dB 2-Wire Idle-channel Noise (600 termination): Psophometric2 C-message 3 kHz Flat2 -- -- -- -87 2 10 -77 12 20 dBmp dBrnC dBrn Transmit Idle-channel Noise: Psophometric2 C-message 3 kHz Flat2 -- -- -- -82 7 15 -77 12 20 dBmp dBrnC dBrn ac Termination Impedance1 Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit) L9217A, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)3 Receive - Gain, f = 1 kHz (RCVN to PT/PR)3 L9217G, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)4 Receive - Gain, f = 1 kHz (RCVN to PT/PR)4 1. With a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 and 1300 can be synthesized. With a third-generation codec, this parameter is set by codec or by a combination of codec and external network. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Use this gain option with an Agere first-generation or third-generation codec. 4. Use this gain option with an Agere third-generation codec. Agere Systems Inc. 11 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Electrical Characteristics (continued) Table 9. Logic Inputs and Outputs All outputs are open collectors with internal, 30 k pull-up resistor. Input pins have internal pull-down or some method to power up in the disconnect state. Parameter Symbol Min Typ Max Unit Input Voltages: Low Level (permissible range) High Level (permissible range) VIL VIH -0.5 2.0 0.4 2.4 0.7 VCC V V Input Currents: Low Level (VCC = 5.25 V, VI = 0.4 V) High Level (VCC = 5.25 V, VI = 2.4 V) IIL IIH -50 -35 -115 -60 -200 -100 A A VOL VOH 0 2.4 0.2 -- 0.4 VCC V V Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 4.75 V, IOL = 360 A) High Level (VCC = 4.75 V, IOH = -20 A) Ring Trip Requirements 8 F TIP RING Ringing signal: -- Voltage, minimum 35 Vrms, maximum 100 Vrms -- Frequency, 17 Hz to 33 Hz -- Crest factor, 1.2 to 1.6 Ring trip: -- 100 ms (typical) 10 k 2 F 100 TIP RING Pretrip: -- The circuits in Figure 3 will not cause ring trip. 12-2572f(F) Figure 3. Ring Trip Circuits 12 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Test Configurations VBAT VCC 0.1 F VBAT 0.1 F BGND VCC AGND 50 TIP VITR XMT 75 k RLOOP 100 /600 L9217 SLIC 50 RING RCVN 46 k RCVP RCV 19.4 k PPMOUT 6.19 k DCOUT TG 43.2 k IPROG 8.06 k VTX 0.1 F TXI 22.1 k LCTH B0 B1 2 M RTSP 402 VBAT B2 NSTAT PPMIN 274 k RTSN CF1 2 M 41.7 k CF2 OVH V 0.47 F 0.1 F 12-3559Em (F) Figure 4. L9217 Basic Test Circuit VBAT OR VCC 100 VBAT OR VCC DISCONNECT BYPASS CAPACITOR 4.7 F 100 4.7 F VS VS VBAT OR VCC VBAT OR VCC 67.5 TIP + 900 - TIP 10 F BASIC TEST CIRCUIT VT/R + VM - RING PSRR = 20log DISCONNECT BYPASS CAPACITOR VS VT/R BASIC TEST CIRCUIT 67.5 56.3 RING 10 F PSRR = 20log VS VM 12-2582.b (F) Figure 5. Metallic PSRR Agere Systems Inc. 12-2583.b (F) Figure 6. Longitudinal PSRR 13 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Test Configurations (continued) ILONG 100 F TIP + VPT - TIP VS 368 + BASIC TEST CIRCUIT VM 368 - ILONG RING 100 F BASIC TEST CIRCUIT - VPR + RING LONGITUDINAL BALANCE = 20 log VS VM ZLONG = VPT VPR OR ILONG ILONG 12-2585.a (F) 12-2584.c (F) Figure 9. Longitudinal Impedance Figure 7. Longitudinal Balance 0.01 F 82.5 TIP 600 50 VS 1 6, 7 0.01 F L7591 4 2.15 F 2 VBAT XMT TIP BASIC TEST CIRCUIT + 600 RING VT/R - 82.5 BASIC TEST CIRCUIT RCV RING HP * 4935A TIMS VS VS = 0.5 Vrms 30% AM 1 kHz MODULATION, f = 500 kHz--1 MHz DEVICE IN POWERUP MODE, 600 TERMINATION GXMT = VXMT VT/R GRCV = VT/R VRCV 5-6756.bm (F) * HP is a registered trademark of Hewlett-Packard Company. Figure 8. RFI Rejection 12-2587.e (F) Figure 10. ac Gains 14 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications A basic loop start reference circuit, using bused ringing with the L9217 SLIC and T7504 first-generation codec, is shown in Figure 11. This circuit is designed for a 900 termination impedance and an 850 + 50 nF transhybrid. Transmit gain is set at 0 dBm and receive gain is set at -7 dBm. VCC CCC 0.1 F RPROG 35.7 k RLCTH 7 1 4 IPROG VCC LCTH VBAT CBAT 0.1 F CHY 4.7 nF PPMIN CPPM 0.01 F OPEN 21 28 RFLT* 9 VBAT PPMIN PPMOUT TG 22.1 k VTX 8 ROVH 27 DCOUT TXI OVH (for 2.5 Vrms PPM) VITR 49.9 k RPT TIP 18 50 EMR LCAS L9217 SLIC 10 50 RTSP 2.94 M RTS1 402 20 RCVP 25 RGP1 8.06 k 24 CB 0.1 F PR GSX CB1 0.47 F - 23 RT2 45.3 k RHB1 97.6 k RHB 86.6 k + DX +2.4 V PCM HIGHWAY CHB 0.47 nF RRCV 63.4 k 5 DR RGP 14.7 k RTSP NSTAT RTSN 3.32 M 22 B2 13 B1 14 B0 15 CF2 11 RGN 9.76 k RCVN 6 CRTS1 0.015 F VBAT RX 86.6 k CB2 0.47 F 19 RTSN VRING 26 RT1 33.2 k PT L7591 RPR RING RPPM 6.19 k CF1 12 SUPERVISION OUTPUT VFRO FSX FSR MCLK CONTROL AND CLOCK 1/4 T7504 CODEC CONTROL INPUTS AGND BGND 17 16 CF1 0.47 F CF2 0.1 F * Placeholder for potential resistor to form filter against PPM generator noise if necessary. Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec Agere Systems Inc. 15 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) Table 10. Parts List for Loop Start Application Circuit Using T7504-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Characteristics RPROG ac Characteristics CB1 CB2 CB RT1 RRCV RGP RT2 RX RHB1 CHB RHB RGP1 RGN Meter Pulse CHY CPPM RPPM ROVH Supervision RLCTH RTS1 CRTS1 RTSN RTSP 16 Value Function L9217 Agere L7591 Agere L7581/2/3 or EMR T7504 Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. First-generation codec. 50 , Fusible 50 , Fusible Protection resistor. Protection resistor. 0.1 F, 20%, 100 V 0.1 F, 20%, 10 V 0.47 F, 20%, 100 V 0.1 F, 20%, 100 V VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. 35.7 k, 1%, 1/16 W Set low current limit. 0.47 F, 20%, 10 V 0.47 F, 20%, 10 V 0.1 F, 20%, 10 V 33.2 k, 1%, 1/16 W 63.4 k, 1%, 1/16 W 14.7 k, 1%, 1/16 W 45.3 k, 1%, 1/16 W 86.6 k, 1%, 1/16 W 97.6 k, 1%, 1/16W 0.47 nF, 10%, 10 V 86.6 k, 1%, 1/16 W 8.06 k, 1%, 1/16 W 9.76 k, 1%, 1/16 W ac/dc separation capacitor. ac/dc separation capacitor. dc blocking capacitor. With RGP and RRCV, sets ac termination impedance. With RGP and RT1, sets receive gain. With RT1 and RRCV, sets ac termination impedance and receive gain. With RX, sets transmit gain in codec. With RT2, sets transmit gain in codec. Sets hybrid balance. With RGS provides gain shaping for hybrid. With CGS provides gain shaping for hybrid. Sets dc transmit gain of SLIC. dc offset. 4.7 nF, 20%, 10 V 0.01 F, 20%, 10 V 6.19 k, 1%, 1/16 W 49.9 k, 1%, 1/16 W Meter pulse rejection. Meter pulse injection. Meter pulse rejection. Increases PPM overhead mode. 22.1 k, 1%, 1/16 W 402 , 5%, 2 W 0.015 F, 20%, 10 V 3.32 M, 1%, 1/16 W 2.94 M, 1%, 1/16 W Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN, RTSP, forms filter pole. With RTSP, sets threshold. With CRTS1, RTSN, sets threshold. Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) Table 11 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted to program these values are also shown. Table 11. 900 Termination, 850 + 50 nF Hybrid First-Generation Codec Design Parameters Design Parameter Loop Closure Threshold dc Loop Current Limit ac Termination Impedance Hybrid Balance Line Impedance Transmit Gain Receive Gain Agere Systems Inc. Parameter Value 10 mA 20 mA 900 850 + 50 nF 0 dBm -7 dBm Components Adjusted RLCTH RPROG R T1, RGP, RRCV, RGP1 CHB, RHB, RHB1 RT2, R X, RN1, RN2, CN RRCV, RGP, RT1 17 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) A basic loop start reference circuit, using bused ringing with the L9217 SLIC and T8536 third-generation codec, is shown in Figure 12. VBAT CBAT 0.1 F VCC CCC 0.1 F 1 RLCTH 7 22.1 k 8 ROVH 27 4 9 IPROG VCC PPMIN CPPM 0.01 F OPEN 21 28 RFLT* RPROG 35.7 k VBAT PPMIN RPT TG VTX DCOUT OVH (for 3.5 Vrms PPM) TXI 18 50 RPR RING VITR L9217 SLIC 10 50 RTSP 2.94 M RTS1 510 PT L7591 EMR LCAS CRTS1 0.015 F RTSN 3.4 M RPPM 6.19 k PPMOUT LCTH 61.9 k TIP CHY 4.7 nF RCVP RCVN NSTAT PR B0 20 B1 RTSP B2 19 26 25 24 RGP1 8.06 k CB 0.1 F 23 5 CB1 0.1 F 6 22 15 14 13 DX1 RCIN 20 M VFXI 1/4 T8536 CODEC DX2 DR1 VFROP PCM HIGHWAY DR2 VFRON FS BCLK SLIC0a CONTROL AND CLOCK VDD SLIC3a CVDD 0.1 F SLIC2a DGND SLIC4a RTSN CF2 11 CF1 12 AGND BGND 17 16 CF1 0.47 F VRING VBAT CF2 0.1 F * Placeholder for potential resistor to form filter against PPM generator noise if necessary. Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec 18 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) Table 12. Parts List for Loop Start Application Circuit Using T8536-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Characteristics RPROG ac Characteristics CB1 CB RGP1 RCIN Supervision RLCTH RTS1 CRTS1 RTSN RTSP Meter Pulse CHY CPPM RPPM ROVH Agere Systems Inc. Value Function L9217 Agere L7591 Agere L7581/2/3 or EMR T8536 Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. Third-generation codec. 50 , Fusible 50 , Fusible Protection resistor. Protection resistor. 0.1 F, 20%, 100 V 0.1 F, 20%, 10 V 0.47 F, 20%, 100 V 0.1 F, 20%, 100 V VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. 35.7 k, 1%, 1/16 W Set low current limit. 0.1 F, 20%, 10 V 0.1 F, 20%, 10 V 8.06 k, 1%, 1/16 W 20 M, 5%, 1/16 W ac/dc separation capacitor. dc blocking capacitor. Sets dc transmit gain of SLIC. dc bias. 22.1 k, 1%, 1/16 W 510 , 5%, 2 W 0.015 F, 20%, 10 V 3.4 M, 1%, 1/16 W 2.94 M, 1%, 1/16 W Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN and RTSP, forms second 2 Hz filter pole. With RTSP, sets threshold. With RTSN, sets threshold. 4.7 nF, 20%, 10 V 0.01 F, 20%, 10 V 6.19 k, 1%, 1/16 W 61.9 k, 1%, 1/16 W Meter pulse rejection. Meter pulse injection. Meter pulse rejection. Increases PPM overhead mode. 19 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) Starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: dc Applications Region 1: On-hook and low-loop currents. The slope corresponds to the dc resistance of the SLIC, Rdc1 (default is 72 typical). The open circuit voltage is the battery voltage less the overhead voltage of the device, VOH (default is 6.5 V typical). These values are suitable for most applications, but can be adjusted if needed. Battery Feed The dc feed characteristic can be described by: V T/R = IL = ( V BA T - V O H ) x R L --------------------------------------------R L + 2R P + R dc V BA T - V O H --------------------------------R L + 2R P + R dc where: IL = dc loop current. VT/R = dc loop voltage. |VBAT| = battery voltage magnitude. VOH = overhead voltage. This is the difference between the battery voltage and the open loop tip/ring voltage. RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. 0.637 RPROG (k) + 2 mA = ILIM x (mA) Overhead Voltage In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the battery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage. This is expressed as an equation: VOH = |VBAT| - (VPT - VPR) 50 LOOP CURRENT (mA) Region 2: Current limit. The dc current is limited to a starting value determined by external resistor R PROG, an internal current source, and the gain from tip/ring to pin VITR. Current limit with a 100 load is set by the equation: Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. In modes without PPM, the L9217 is set to allow undistorted on-hook transmission of a 3.17 dBm signal into a 900 loop impedance. 40 ILIM TESTED 1 12.5 k 30 ILIM ONSET In high overhead and PPM modes, overhead is automatically increased to accommodate on-hook transmission of meter pulse signals. The increase in overhead is set by a resistor from pin OVH to ground. This is expressed as an equation: 20 -1 R dc1 10 0 0 10 30 20 LOOP VOLTAGE (V) 40 50 VOVH (V) = 6.37 + 0.09535 x ROVH (k) Note: VBAT = -48 V; ILIM = 22 mA; Rdc1 = 115 . 12-3050.i (F) Figure 13. Loop Current vs. Loop Voltage 20 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) Off-Hook Detection dc Applications (continued) The loop closure detection threshold is set by resistor RLCTH. The supervision output bit NSTAT is high in an on-hook condition. The off-hook comparator goes low during an off-hook conditon: Rate of Battery Reversal The rate of battery reversal is controlled or ramped by capacitors FB1 and FB2. A chart showing FB1/FB2 values versus typical ramp rate is given below. Leave FB1/FB2 open if it is not desired to ramp the rate of battery reversal. ITR (mA) = 0.4167 RLTCH (k) -1.9 mA ACTIVE off-hook to on-hook ITR (mA) = 0.4167 RLTCH (k) + 2.7 mA SCAN on-hook to off-hook Table 13. FB1/FB2 Values vs. Typical Ramp Time RP CFB1/CFB2 Transition Time 0.01 F 0.1 F 0.22 F 0.47 F 1.0 F 1.22 F 1.3 F 1.4 F 1.6 F 20 ms 220 ms 440 ms 900 ms 1.8 s 2.25 s 2.5 s 2.7 s 3.2 s TIP ITR + RL 0.125 V/mA DCOUT - RLCTH RING LCTH RP 0.05 mA + - NSTAT 12-2553fm (F) Figure 14. Off-Hook Detection Circuit Loop Range The equation below can be rearranged to provide the loop range for a required loop current: RL = V B AT - V OH --------------------------- - 2R P - R D C Agere Systems Inc. IL 21 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) dc Applications (continued) Ring Trip Detection The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing. PHONE HOOK SWITCH RLOOP RC PHONE V BAT VRING RTSP RTSP + 2.94 M RS 402 /510 C RTS1 0.015 F RTSN 3.32 M/3.40 M NSTAT IP = IN IN + - 8.4 V - R TSN 15 k Figure 15. Ring Trip Equivalent Circuit and Equivalent Application Ring trip detection threshold is given by the following equation: [ RTSN ( M ) + 0.015 - RTSP ( M ) ] x [ V BAT - 8.4 ] x 1000 ITH (mA) = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------[ RTSN ( M ) + 0.015 ] x R S 22 Agere Systems Inc. Preliminary Data Sheet October 2001 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Applications (continued) even during non-PPM active times. To apply PPM to tip/ring, from a normal overhead state first switch to a high overhead state without PPM; the overhead voltage at tip/ring will increase to 7 V to 13 V. The ramp up time of the overhead increase is on the order of hundreds of milliseconds. Thus, wait 1 s before applying the PPM signal by going to a PPM active high overhead state. Once in a high overhead, there is no timing requirement in switching in and out of a PPM active mode. Without the inital 1 s delay, AT/AR will get into saturation and PPM signal at T/R will get distorted, producing crosstalk in the handset. Longitudinal Balance The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure 5 and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This can be illustrated by the equation: ( 368 + RP ) x ( 368 + ZT - RP ) LB = 20 x log ------------------------------------------------------------------------------------------368 x ( 2 x [ ZT - 2 x RP ] x + ) where: LB: longitudinal balance. RP: protection resistor value in . ZT: magnitude of the termination impedance in . : protection resistor mismatch in . : SLIC internal tip/ring sensing mismatch. The can be calculated using the above equation with these exceptions: = 0, ZT = 600 , RP = 100 , and the longitudinal balance specification on a specific code. Now with available, the equation will predict the actual longitudinal balance for RP, ZT, and . Be aware that ZT may vary with frequency for complex impedance applications. Periodic Pulse Metering (PPM) PPM input signals may be a maximum 0.525 Vrms at PPMIN. The gain from PPMIN tip/ring is 10. Thus, for 2.5 Vrms at tip and ring, apply a 0.375 Vrms signal at PPMIN. The PPM signal should be ac coupled to PPMIN through a 0.01 F capacitor. When applied to tip and ring, the PPM signal will also be returned through the SLIC and will appear at the SLIC VITR output. The concern is that this high-voltage signal can overload the codec input and cause distortion of the (desired) ac signal. Therefore, some sort of PPM rejection scheme must be employed, see Figure 1, Functional Diagram. The L9217 outputs on the PPMOUT pin, which is the output of the PPM input amplifier. Connecting a resistor, RPPM, from PPMOUT to node TG will provide a path for a hybrid reject of the returned meter pulse signal. The return path from tip and ring to VITR for the PPM signal is through the internal AX amplifier. TG is the input to this amplifier. Through RPPM, by applying a PPM signal equal in magnitude, but 180 degrees out of phase to the returned PPM signal at TG, the PPM signal is cancelled, preventing overload at the codec input. Even if the cancellation is not perfect, the idea is to reduce the PPM signal so as not to overload the codec. Codecs typically have a low-pass filter at their input to reject any residual meter pulse signal. Periodic pulse metering (PPM), also referred to as TTX, is input to the PPMIN input of the L9217. Upon application of appropriate logic control, this signal is presented to the tip/ring subscriber loop. The state of the L9217 may be changed while applying PPM signals. The L9217 assumes that a shaped PPM signal is applied to the PPMIN input. RPPM = [{(VPPMIN x 10)/(RPPMLOAD + RDC + 2RP)}/201.2]-1 Sufficient drive current is available in the tip and ring drive amplifiers to support 3.5 Vrms PPM signals into a 200 load with a 45 mA dc current limit. For undistorted transmission of meter pulse signals, increase the overhead as described in the Overhead Voltage section of this data sheet. The value of RPPM is selected by: PPM signals are input to a separate PPMIN input. This input is controlled via the logic table. PPMIN is off during all states except the forward/reverse PPM active state. Thus, PPM signals may be present at all times, Agere Systems Inc. 23 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) ac Interface Network ac Design The ac interface network between the L9217 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9217 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9217 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal-to-noise ratio (S/N) in the receive direction. Codec Types At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. Below is a brief codec feature summary. First-Generation Codecs. These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, 5 V only or 5 V operation, and -law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Further, ac parameters are fixed by the external R/C network, so software control of ac parameters is difficult. Third-Generation Codecs. This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, TTX generation, test algorithms, and echo cancellation. Again, this type of codec may be 5 V only or 5 V operation, single quad or 16-channel, and -law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and the T8531/36 (5 V only 16-channel with self-test). 24 Receive Interface Because the design requirements are very different with a first- or third-generation codec, the L9217 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9217 and codec. With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9217 provides a transconductance from T/R to VITR in the transmit direction and a single ended to differential gain in the receive direction from either RCVN or RCVP to T/R. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voiceband as low as 300 up to over 1000 . Thus, if the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Furthermore, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason a high-gain SLIC is required with a first-generation codec. Agere Systems Inc. Preliminary Data Sheet October 2001 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Applications (continued) SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operating near maximum signal levels, thus compromising the S/N. ac Design (continued) Receive Interface (continued) It appears the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and transmission level points (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voiceband frequency, must ensure that the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency to meet the return loss requirements. Further stability issues may add external components or excessive ground plane requirements to the design. To meet the unique requirements of both types of codecs, the L9217 offers two receive gain choices. These receive gains are mask programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9217A is offered with a receive gain of 7.86. For interface with a third-generation codec, the L9217G is offered with a receive gain of 2. In either case, the transconductance in the transmit direction, or the transmit gain is 403 . In the receive direction, the issue is to optimize S/N. Again, the designer must consider all the considered TLPs. The idea is, for all desired TLPs, to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember noise floor is constant, so the hotter the signal from the codec, the better the S/N. The problem is, if the codec is feeding a high-gain Example 1: Real Termination (First-Generation Codec) ac equivalent circuits for real termination using a T7504 codec is shown in Figure 15. RX VGSX -0.403 V/mA RT2 VFXIN - VITR VFXIP ZT/R VS ZT - AV = 1 + RP TIP IT/R + VT/R - RP RING - AV = 3.93 + CURRENT SENSE RT1 RCVN R HB1 RRCV RCVP + 2.4 V VFR RG + AV = -1 - L9217 SLIC 1/4 T7504 CODEC 12-3581Cm (F) Figure 16. ac Equivalent Circuit Agere Systems Inc. 25 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) ac Design (continued) Example 1: Real Termination (First-Generation Codec) (continued) The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination impedance. Termination Impedance: VT R ZT = --------------IT R 3168 Z T = 2R P + ----------------------------------RT3 RT3 1 + --------- + -----------RGP RRCV Receive Gain: VT R grcv = -------------V fr 7.86 grcv = ------------------------------------------------------------------------------------ZT RC V RCV R 1 + --------------- + R --------------- 1 + ------------- R T3 R GP Z T/R Transmit Gain: V GSX gtx = --------------VT R RX 403 gtx = ---------- x ----------ZT R T6 Hybrid Balance: V GSX hbal = 20log --------------VT R To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The following expressions assume the test network is the same as the termination impedance. RX RHB = ------------------------g tx x g rcv RX hbal = 20log ------------ - g tx x g rcv RHB 26 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) Below are design equations for complex termination (see Figure 17 and Figure 18). RT1 7.86 = 2R P + -----------201.2 1 1 * ----------------------------------- - ------------------ RT3 R T3 RN1 1 + --------- + ------------ 1 + -------- RGP RT2 = RRCV 7.86 R T GP R T G S 1 ----------- + ----------------------------------- + ----------------- 201.2 RT3 RT3 RN1 1 + --------- + ------------ 1 + -------- R GP RRCV RTGP || RTGS RN2 RTGP || RTGS RN2 2 7.86 1 RN2 1 R TGP 1 1 = ---------------- ----------- ------------------------------------2- R TGP || R TGS + ----------- * ------------------------------------- * ---------------------------------------------- - --------------------- C N1 C TG CT R T3- --------------R N1 201.2 R TGP + R TGS R T3 ( R N1 + R N2 ) 1 + ----------+ 1 + ----------- R GP R RCV R N2 1 ------- RX 1 Z TG gtx = ---------- ---------------- ----------R T6 201.2 Z T 7.86 1 grcv = ------------------------------------------------ x -----------------------R ZT RC V R RCV 1 + --------------- + --------------- 1 + ------------R T3 R GP ZT R RX hbal = 20log ------------ - g tx x g rcv RHB where: ZT/R = R1 + R2 || C ZTG = RTGP || (RTGS + C G) RTGP = 8.06 k R1 RTGS = ------- RTGP R2 R22 CG = ------------------------------------------ x C R TGP ( R 1 + R 2 ) and 2R P CNRN2 = ------------- CG RTGP 3167 3167 R TGS RN1 = RN2 ------------- -------------- - 1 2R P R TGP The equations above do not include the blocking capacitors. Agere Systems Inc. 27 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) (continued) RTGS CGS RX -IT/R 201.2 RTGP = 8.06 k CB1 RT6 AX - + CODEC OP AMP CN RT3 RN1 RCVN RCVN RCVP RCVP CODEC OUTPUT DRIVE AMP RRCV RGP RN2 5-6401L(F) Figure 17. Interface Circuit Using First-Generation Codec (5 V Codec) RTGS CG Rx -IT/R 201.2 RTGP = 8.06 k RT6 AX CB1 CN RN1 CODEC OP AMP -2.4 V RT3 RCVN RRCV RCVP CB2 RGP RN2 - + CODEC OUTPUT DRIVE AMP 5-6400o(F) Figure 18. Interface Circuit Using First-Generation Codec (+5 V Only Codec) 28 Agere Systems Inc. Preliminary Data Sheet October 2001 Applications (continued) Loop power = 0.219 W SLIC power = 1.579 W - 0.219 W = 1.36 Power Derating SLIC power = 1.36 W < 1.51 W Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and protection resistor values will influence the overall thermal performance. This section shows the relevant design equations and considerations in evaluating the SLIC thermal performance. Consider the L9217 SLIC in a 28-pin PLCC package. The thermal resistance on a 2-layer board with natural convection is 43 C/W. The SLIC will enter the thermal shutdown state at a minimum of 150 C. The thermal shutdown design should ensure that the SLIC temperature does not reach 150 C under normal operating conditions. Assume a maximum ambient operating temperature of 85 C, a design current limit of 25 mA, and a maximum battery of -52 V. Further, assume a (worst-case) minimum dc loop of 200 , and that 50 protection resistors are used at both tip and ring. 1. TTSD - TAMBIENT(max) = allowed thermal rise. 150 C - 85 C = 65 C 2. Allowed thermal rise = package thermal impedance * SLIC power dissipation. 65 C = 43 C/W * SLIC power dissipation SLIC power dissipation (P DISS) = 1.51 W Thus, if the total power dissipated in the SLIC is less than 1.51 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total PDISS = Maximum battery * maximum current limit (including effects of accuracy) + SLIC quiescent power For the L9217, SLIC quiescent power (PQ) is maximum at 0.175 W. Thus, Total PDISS = (-52 V L9217A/G Low-Cost Line Interface with Reverse Battery and PPM * [25 mA * 1.08]) + 0.175 W Total PDISS = 1.404 W + 0.175 W Total PDISS = 1.579 W Thus, in this example, the thermal design ensures that the SLIC will not enter the thermal shutdown state. Pin-for-Pin Compatibility with L9218/L9219 The L9217 can be a pin-for-pin replacement for the L9218/L9219. The exceptions are as follows: L9217 has 3 logic control inputs: B0, B1, and B2. The L9218 has only 2 logic control inputs: B0 and B1. Pin 13 in L9218 is NC, so a connection between the controller and pin 13 will not affect L9218 operation. In L9217, pin 28 is PPMOUT, pin 21 is PPMIN, and pin 27 is OVH. In L9218/9, pin 28 is NC, pin 21 is NC, and pin 27 is TSD PCB Layout Information Make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PCB copper in the area of--and specifically on--the leads connected to this device for the lowest operating temperature. When powering the device, ensure that no external potential creates a voltage on any pin of the device that exceeds the device ratings. In this application, some of the conditions that cause such potentials during powerup are the following: 1. An inductor connected to PT and PR (this can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters). 2. Inductance in the VBAT lead (this could resonate with the VBAT filter capacitor to cause a destructive overvoltage). This device is normally used on a circuit card that is subjected to hot plug-in, meaning the card is plugged into a biased backplane connector. In order to prevent damage to the IC, all ground connections must be applied before, and removed after, all other connections. The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC PDISS = Total power - loop power Loop power = (ILIM)2 * (RdcLOOP min + 2RP) Loop power = (25 mA (200 + 100 ) Agere Systems Inc. * 1.08)2 * 29 L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Outline Diagram 28-Pin PLCC Dimensions are in millimeters. 12.446 0.127 11.506 0.076 PIN #1 IDENTIFIER ZONE 4 1 26 25 5 11.506 0.076 12.446 0.127 11 19 12 18 4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.10 0.330/0.533 5-2506r.8(F) 30 Agere Systems Inc. L9217A/G Low-Cost Line Interface with Reverse Battery and PPM Preliminary Data Sheet October 2001 Ordering Information Device LUCL9217AAR-DT LUCL9217AAR-D LUCL9217GAR-DT LUCL9217GAR-D Agere Systems Inc. Package Comcode 28-Pin PLCC (Tape & Reel, Dry-bagged) Gain of 8 108760737 28-Pin PLCC (Dry-bagged) Gain of 8 108760729 28-Pin PLCC (Tape & Reel, Dry-bagged) Gain of 2 108760760 28-Pin PLCC (Dry-bagged) Gain of 2 108760752 31 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. October 2001 DS02-002ALC (Replaces DS01-253ALC)