Pre liminar y D ata She et
October 2001
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Features
■Basic f orward/reverse battery SLIC functionality at
a low cost
■Pin comp atible with Agere Systems Inc.
L9218/ L9219 S LIC
■Low active power (typical 154 mW during on-hook
transmission)
■Low-power scan mode for low-power on-hook
power dissipation (57 mW typical)
■Distortion-free on- hook transmission
■Conveni ent operating s t ates:
— Forward powerup
— Reverse powerup
— Low-power scan
— Disconnect (high impedance)
— PPM operational states
■Mini mal external com ponents required
■Two gain options to optimize codec interface
■Adju stable supervision functions :
— Off-hook detector with hysteresis
— Ring trip detector
■Adjustable loop current limit
■Adju stable overhead voltage
■Ramped rate of battery reversal
■Periodic pulse metering (PPM) compatible
■Therm al protection with thermal shutdown indica-
tion
Description
This general-purpose elect ronic subs criber loop
interface circuit (SLIC) is optimized fo r low cost,
while still pro v iding a sat is fa ct or y set of fe a tu re s.
This part is a pin-for-pin replacement for the Agere
L9218/L9 219 SL IC.
The L9217 requires a +5 V power supply and single
battery to operate. This dev ice offers forward and
reverse bat tery operation. The rate of batt ery rever-
sal may be ramped to meet internationa l require-
ments. Additionally, a low-power scan mode, wherein
all circuitry except the off-hook supervision is shut
down to conserve power, is available.
The dc current limit may be programmed via a singl e
external resistor. Both the loop supervision and ring
trip supervision functions are off ered with user-con -
trolled thresholds via external resistors. Overhead is
adequate for 3.14 dBm into 900 Ω of on-hook trans-
mission.
The device is periodic pulse metering (PPM) comp at-
ible, offering a convenient point for meter pulse inj ec-
tion and filter poin t for rejection of the meter pulse
signal. In the PPM active modes, overhead voltage i s
automatically increased to accommodate on-hook
transmission of meter pulse signals. The l evel that
the overhead is increased to is set by a single ext er-
nal resistor. In this way, the L9217 can ac como date
high-voltage meter pulse signals.
The L9217 is offered wi th a receive gain that i s opti-
mized t o interface to a first-generation type codec
(L9217A). It is also offered with a gain option that is
optimized to interface to a third- or fourth-generation
type codec (L9217G ); in both cases, minimizing
external components is required at this interface.
Data control i s via a parallel data control scheme.
The device is available in a 28-pin PLCC package. It
is built b y using a 90 V complementary bipolar
(CBIC) process.
2Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Table of Contents
Contents Page
Features ......................................................................1
Description...................................................................1
Pin Information ............................................................4
Fu nc tional Descri pt ion......... ....... ....... ....... .............. .....6
Absolute Ma xi mu m Ratings ......... ....... ........ ....... .........7
Recommen ded Operat ing Conditions .........................7
Ele ctrical Char acteristics.......... ....... ....... ....... .............. 8
Ring Trip Requirements .........................................12
Te st Configura tio n s . ....... ....... ....... ....... ..... ....... ....... ...1 3
Applications...............................................................15
dc App li c a tions .......... ....... ....... ..... ....... ....... ............20
Bat te r y Fee d..... ....... ....... ....... ....... ..... ....... ....... .....20
Overhead Voltage.................................................20
Rat e of Ba tte r y Rever sa l....... ....... ..... ....... ....... .....21
Loop Range..........................................................21
Off-Hook Detection...............................................21
Ring Trip Detection...............................................22
Longitudinal Balance ..............................................23
Periodic Pulse Metering (PPM )...............................23
ac Des ign ............... ........ ....... ....... .............. ....... .....24
Codec Types........................................................24
ac Interface Network .... ....... ....... .............. ....... .....24
Receive Interface .................................................24
Example 1: Real Termination
(First-Generation Codec)...................................25
Example 2: Complex Termination
(First-Generation Codec)...................................27
Power Der at ing.......... ....... ..... ....... ....... .............. .....29
Pin-fo r-Pin Compatibility with L9218/L9219............29
PCB Layout Information ............................................29
Outline Diag r a m..... .... ........ ....... .............. ....... ....... .....30
28-Pin PLCC ..........................................................30
Ord e r i ng In fo r mati o n..... ....... ....... ..... ....... ....... ..... ....... 3 1
Figures Page
Figure 1. Functional Diagram ..................................... 3
Figure 2. 28 -Pin PLCC ............................................... 4
Figure 3. Ri ng Trip Circuits....................................... 12
Figure 4. L9217 Basic Test Circuit ........... ................ 13
Figure 5. M etallic PSRR........................................... 13
Figure 6. Lo ngitudinal PSRR.................................... 13
Figure 7. Lo ngitudinal Balance................................. 14
Figure 8. RF I Rejection ............................................. 14
Figure 9. Longitudinal Impedance ............................ 14
Figure 10. ac Gains.................................................. 14
Figure 11. Basic Loop Start Application Circuit
Using T7504-Type Codec................. ...... 15
Figure 12. Basic Loop Start Application Circuit
Using T8536-Type Codec ................ ...... 18
Figure 13. Loop Current vs. Loop Voltage................ 20
Figure 14. O ff-Hook Detection Circuit ....................... 21
Figure 15. Ring Trip Equivalent Circuit and
Equivalen t Ap p li ca tio n.. ....... ....... ..... ....... . 22
Figure 16. ac Equivalent Circuit ............................... 25
Figure 17. I nterface Circuit Using First-Generation
Codec (±5 V Codec)................................ 28
Figure 18. I nterface Circuit Using First-Generation
Codec (+5 V Only Codec)................. ...... 28
Tables Page
Table 1. Pin Descriptions ........................................... 4
Table 2. Input State Coding ....................................... 6
Table 3. Supervision Coding ..................................... 6
Table 4. Power Supply .. ................... ......................... 8
Table 5. 2-Wire Port .................................................. 9
Table 6. Analog Pi n Characteristics ........................ 10
Table 7. PPM............................................................ 10
Table 8. ac Feed Characteristics ............................. 11
Table 9. Logic Inputs and Outputs ........................... 12
Table 10. Parts List for Loop Start App lication Circuit
Using T7504-Type Codec..... .. ............ ..... . 16
Table 11. 900 Ω Termination, 850 Ω + 50 nF
Hybrid First-Generat ion Codec Design
Parameters .............................................. 17
Table 12. Parts List for Loop Start App lication
Circuit Using T8536-Ty pe Codec . ............ 19
Table 13. F B 1/FB 2 Values vs.Typical Ramp
Time.......................................................... 21
Agere Systems In c. 3
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Description (continued)
12-3557GM(F)
Fi gure 1. Functional Diagram
–
+
–
+
+
–
A = 1
A = –1
POWER CONDITIONING AND REFE RENCE
BGND
AGND
IPROG
VCC
CF2
PT
PR
RTSN
RTSP
LCTH
RING TRIP DETECTOR
LOOP CLOSURE DETECTOR
BATTERY FEED
STAT E CONT R OL
B0
RCVP
RCVN
B1
NSTAT
FB2
+
+
–
–
TIP/RING
CURRENT
SENSE
B2
A VERSION GAIN = 3.93
G VERSION GAIN = 1
FORWARD AND REVERSE BATTERY
DCOUT
VTX
TG
TXI
VITR
–
+AX
RECTIFIER 3
AAC
β = 9.66
β = 41 V/A
CF1
FB1
PPMOUT
PPMIN
OVH
β = 5
PPM
4Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Pin Information
12-3558C(F)
Fi gure 2. 28 -P i n PL CC
Tab le 1. Pin Descriptions
PLCC Symbol Type Description
1 IPROG ICurrent- Li m it Program Input . A resistor to DCOUT sets the dc current limi t of the
device.
2FB2 —Po larity Reversa l Slowdo wn. Connect a capacitor to gr ound to control the rate of bat-
tery reversal.
3FB1 —Po larity Reversa l Slowdo wn. Connect a capacitor to gr ound to control the rate of bat-
tery reversal.
4 VCC —5 V Po wer Supply.
5RCVP IReceive ac Signal I nput (Noninvertin g). This high-impedance inp ut controls the ac
differential voltage on tip and ring.
6RCVN IReceive ac Signal Input (Inverting). Th is high-impedance inp ut contro ls the ac differ-
ential voltage on ti p and ri ng.
VTX
TXI
VITR
NSTAT
PPMIN
RTSP
RCVN
DCOUT
VBAT
PR
5
6
7
8
9
10
11
42128273
12 14 15 16 17 1813
25
24
23
22
21
20
19
I
PROG
B0
CF1
PT
BGND
B1
B2
AGND
28-PIN PLCC
LCTH
RCVP
CF2 RTSN
OVH
PPMOUT
FB2
FB1
V
CC
26
TG
28-PIN PLCC
Agere Systems In c. 5
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Pin Information (continued)
Tab le 1. Pin Descriptions (continued)
PLCC Symbol Type Description
7LCTH ILoop Closure Threshold Input. Connect a resistor to DCOUT to set off-hook
threshold.
8DCOUT Odc Output Voltag e. Thi s output is a voltage th at is directly proportional to th e abso-
lute val ue of the different ial tip/ring current.
9 VBAT —Batter y Supp ly. Negative hig h-voltage power supply.
10 PR I/O Prote cted Ring. The out put of the ring driver amp lifier and input to loop sensing cir-
cuitry. Connect to the loop through overvol t age protection.
11 CF2 —F ilter Capacitor 2. Connec t a 0.1 µF capacitor from this pin to AG ND.
12 CF1 —F ilter Capacitor 1. Connec t a 0.47 µF capacitor from this pi n to pin CF2.
13 B2 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B2 has internal pull-down.
14 B1 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B1 has internal pull-down.
15 B0 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B0 has internal pull-down.
16 AGND —Analog Signal Ground.
17 BGND —Battery Ground. Ground return for the battery supply.
18 PT I/O Prote cted Tip. The output of t he tip driver amplifier and input to loop sensing cir-
cuitry. Connect to loop through overvoltage protecti on.
19 RTSN IRing Trip Sense Negative. Connect this pin to the ringing generator signal through a
high-value resistor.
20 RTSP IRin g Tri p Sense Positive. Connect this pi n to the ring relay and the ringer s eries
resistor through a high-value resistor.
21 PPMIN IR e c eive PPM Sign a l Input. This high-impedance input controls the PPM differential
voltage on tip and ring. The P PM signal m ay be present at this pin a t all time s: how-
ever, PPM will only be transm itted to t ip and ring if the appropriate P PM state i s cho-
sen. ac couple the PPM signal to this node.
22 NSTAT ORing Trip D etect or Output / Loop De tector Output . When l ow, this logic output indi-
cates that ringing is tripped or that an off -hook condit ion exists.
23 VITR Oac Output Voltage. The vo ltage at this point is directly proportional to the differenti al
tip/ring current.
24 TXI Iac/dc Separation. Connect a 0.1 µF capacitor from this point to V TX.
25 VTX Oac Output Voltage. This out put is a vol tage that is direc tly proportional to the differ-
ential tip/ri ng current.
26 TG —Transmit Gain. Conn ect a 8.06 kΩ f rom TG to VTX to set the trans m it gain of the
SLIC.
27 OVH IPPM Overhead. Connect a resistor from this node to ground to set the overhead volt-
age during PPM high overhead modes.
28 PPMOUT OPPM Signal Output. Connect a re sistor from this node to TG for hybrid cancellation
of the periodic pul se metering (PPM) signal.
6Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Functional Description
Tab le 2. Input State Coding
Table 3. Supervi sion Coding
B0 B1 B2 State/Definition
1 1 1 Powerup, Forward Battery, Normal Overh ead . Norm al talk and battery fe ed state. Pin PT is
positive with respect to P R. On-hook trans mission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
1 0 1 Powerup, Reverse Battery, Normal Overh ead. Norma l talk and battery fee d state. Pin PT is
negative wit h respec t to PR. On- hook t ransmission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
1 1 0 Powerup, Forwa rd Ba tt ery, High Overhead. Normal talk and battery feed state. Pin PT is po si-
tive with respect to PR. On-hook transm ission is enabl ed. PPM is not active. Overhea d is in-
creased via ressitor OVH
1 0 0 Powerup, Reverse Battery, High Overh ead . Normal talk and battery feed state . Pin PT is neg-
ative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is in-
creased via resistor OVH.
0 1 1 L ow-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin
PT is positive with respect to pin PR. On-hook transmission is disabled.
0 0 1 Disconnect. The tip and ring amplifiers are turned off, and the SLI C goes to a high-imped anc e
state (>100 kΩ). Supervision outputs read on hook. Device will power up in this state.
0 0 0 Powerup, Reverse Battery, High Overh ead with PPM. Nor mal talk and battery feed state. Pin
PT is negative wit h respect t o PR. On-hook transmission is enabled. PPM is active. Overhead i s
increased via resistor OVH.
0 1 0 Powerup, Forwa rd Ba tt ery, High Overhead with P PM . Normal talk and battery feed state. Pin
PT is positive with respect to PR. On-hook transmission is enable d. PPM is active. Overhead is
increased via resistor OVH.
NSTAT
0 = off-hook or ring trip.
1 = on-hook and no ring trip.
Agere Systems In c. 7
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Absolute Maximum Ratings (at TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. T hese are abso-
lute stress ratings only. Func tional operation of the devi ce is not implied at these or any other conditi ons in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximu m ratings for extended
periods can adversely aff ect device rel iability.
Note: The I C can be damaged unless all grou nd connections a re ap plied before, and removed af ter, all other connecti ons. Fu rthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings . Some of the kn own examples of condit ions th at cause such potenti als dur ing powerup are the following :
1. An inductor connected to tip and ring can force an overvoltage on VBAT through th e protection de vices if the VBAT connec tion chatters.
2. Inductance in the VBAT lead could reson ate with the VBAT filter capacitor to cause a destructive overvoltage.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
5 V P ower Supply VCC — — 7.0 V
Battery (Talking) Supply VBAT — — –75 V
Logic Input Voltage —–0.5 —7.0 V
Analog Input Voltage —–7.0 —7.0 V
Maximum Junction Temperature TJ150 — — °C
Storage Temperature Rang e Tstg –40 —125 °C
Relative Humidity Range RH5 — 95 %
Ground Potential Difference (BGND to AGND) — — ±3 — V
PT or PR F ault Vo ltage (dc) VPT, VPR VBAT – 5 — 3 V
PT or PR Fault V oltage (10 x 1000 µs) VPT, VPR VBAT – 15 —15 V
Current into Ring Trip Inputs IRTSP, IRTSN —±240 —µA
Parameter Min Typ Max Unit
Ambient Temperature –40 —85 °C
VCC Supply Voltage 4.75 5.0 5. 25 V
VBAT Supply Voltag e –24 –48 –70 V
8Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics
Minimum and maximum values are test i ng requirements in the temperature range of 25 °C to 85 °C and battery
range of –24 V to –70 V. Thes e minimum and ma ximu m values are guarant eed to –40 °C based on compone nt
simulations and des ign verification of samples, but devices are not tested to –40 °C in production. The test circuit
shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device.
Typical v alues are c haracteristics of the device design at 25 °C based on engineering evaluati ons and are not part
of the test requ irem ents. Supply values used for typical characterization are V CC = 5. 0 V, VBAT = –48 V, unless ot h-
erwise noted.
Tab le 4. Po wer Sup pl y
1. This par ameter is not t ested i n production. It is guaranteed by des ign and device characterizati on.
2. Air flow, PCB board laye rs, and other factors can greatly affect this p ara meter.
Parameter Min Typ Max Unit
Power Supply—Powerup, No Loop Current:
ICC
IBAT (VBAT = –48 V )
Power Dissipation (VBAT = –48 V)
—
—
—
5.2
–2.66
154
6.5
–2.95
175
mA
mA
mW
Powe r Supply—S can, No Loop Current:
ICC
IBAT (VBAT = –48 V )
Power Dissipation (VBAT = –48 V)
—
—
—
3.4
–0.9
57
4.3
–1
70
mA
mA
mW
Powe r Supply—Disconnect, No Loop Current:
ICC
IBAT (VBAT = –48 V )
Power Dissipation (VBAT = –48 V)
—
—
—
1.9
–0.1
14
—
—
—
mA
mA
mW
Powe r Supply Rejection 500 Hz to 3 kH z
(See Figures 5, 6, 16, and 17.)1:
VCC
VBAT
30
36 —
——
—dB
dB
Therm al Protection Shutd own (Tjc)1150 165 —°C
Th er mal Res is tance St ill A ir , Ju nc t io n to A mbient (θJA)1, 2:
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minut e (LFPM) 2S2P B oard
Wind Tunnel 100 Linear Feet per Minut e (LFPM) 2S0P B oard
—
—
—
—
30
43
27
36
—
—
—
—
°C/W
°C/W
°C/W
°C/W
Agere Systems In c. 9
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Tab le 5. 2-Wire Port
1. The longitu dinal curr ent is independen t of dc loop current.
2. Current-limit ILIM is programmed by a resistor, RPROG, fr om pin I PROG to DCOUT. ILIM is specified at the loop resistanc e where current limiting
begins (see Figure 13).
3. This p arameter is not tested in product ion. It is guaran teed by design and de vice characterization.
4. Spec ifica tion is re duced to |VBAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C.
5.
IEEE
is a registered trademark of The Institute of Electrical an d Ele c tronics Engine ers, Inc.
6. Longitudin al balance of circuit card wil l depend o n loop se ries prote c tion resistor matching and magnitude. M ore information is av aila bl e in
the Applications section of this document.
Parameter Min Typ Max Unit
Tip or Ring Drive Current = dc + Longitudinal + Signal
Currents 80 — — mA
Signal Current 15 — — mArms
Longitudi nal Cur rent Capa bilit y per W ire18.5 15 —mArms
dc Loop Current Limit2:
Allowed Range Including To lerance3
Accuracy (RLOOP = 100 Ω, V BAT = –48 V) 15
——
±545
—mA
%
Powerup Open Loop Volt age Levels (PPM OF F):
Common-mode Voltage
Differential Voltage VBAT = –48 V4 (Gain = 2)
Differential Voltage VBAT = –48 V4 (Gain = 7.86)
—
|VBAT + 7.5|
|VBAT + 8.0|
VBAT/2
|VBAT + 6.5|
|VBAT + 6.5|
—
|VBAT + 5.9|
|VBAT + 5.9|
V
V
V
Powerup Open Loop Volt age Levels (PPM ON)
Minimum Prog ramm ed Overhead:
Differential Voltage VBAT = –48 V (Gain = 7.86) — — |VBAT + 18.67| V
Disconn ect State:
Leakage —10 150 µA
dc Feed Resistance (for ILOOP below regulation level)
(does not include protection resi st or) —72 100 Ω
Loop Resist ance Range (–3.17 dBm overload into
900 Ω; not including protection ):
ILOOP = 20 mA at VBAT = –48 V 1800 — — Ω
Longitudi nal to Meta llic Ba lanc e—
IEEE
5 Std. 455
(See Fi gure 7.)6:
200 Hz to 3400 Hz 58 61 —dB
Metallic to Longitudinal Balance (open loop):
200 Hz to 4 kHz 46 — — dB
RFI Rejection (See Figure 8.)3, 0.5 Vrm s, 50 Ω Source,
30% AM Mod 1 kHz:
500 kHz to 100 MHz —
——
–55 —
–45 —
dBV
10 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Tab le 6. Analog Pin Characte ristics
1. Loop closure threshold is programmed by resistor RLCTH from pi n LCTH to pin DCOUT. The p rogramming equation or re latio nship betw een
off-hook threshold and resistor val ue is dif ferent for active mode versus s c an mode (see Applicatio ns section fo r more deta ils).
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. IN is the sourcing current at RT SN. Guaranteed if I N is within 5 µA to 30 µA.
Tabl e 7. PPM
* PPM signal should be ac-coupled into PPMIN.
Parameter Min Typ Max Unit
Differential PT/PR Current Se nse (DCOUT):
Gain (PT/PR to DCO UT)
Offset Voltage at ILOOP = 0 121
–200 125
—129
200 V/A
mV
Loop Closure Dete ctor Threshold (RLCTH = 22.1 kΩ)1:
On- to Off-hoo k Threshold (scan mode)
Off- to On-hoo k Threshold (active m ode) 8.8
6.0 —
—13.6
10.2 mA
mA
Ring Trip Comparator:
Input Of fset Voltage2
Internal Voltage So urce
Current at Input RTSP3
—
–8.7
IN – 0.5
±10
–8.2
IN
—
–7.7
IN + 0 .5
mV
V
µA
RCVN, RCVP:
Input Bias Current
Input Resistan ce —
—–0.2
1–1
—µA
MΩ
Parameter Min Typ Max Unit
PPM Sour ce *:
Frequency (f1)
Frequency (f2)
Input Signal
11.88
15.80
0
12
16
—
12.12
16.20
0.525
kHz
kHz
Vrms
Signal Gai n (from PPMIN to amplifier outputs) 9 10 11 —
Harmonic Di stortion — 5 — %
Isolation 50 — — dB
Agere Systems In c. 11
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Tabl e 8. ac Feed Characteristics
1. With a first-generation c odec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 Ω and
1300 Ω can be synthesized. With a third-generation codec, this parameter is set by codec or by a combination of codec and external net-
work.
2. This p arameter is not tested in product ion. It is guaran teed by design and de vice characterization.
3. Use this gain optio n with an Agere first-generation or third-generation codec.
4. Use this gain optio n with an Agere third-generation codec.
Parameter Min Typ Max Unit
ac Termination Impedance1150 —1300 Ω
Longitudinal Impeda nc e at PT/PR2 — 0 — Ω
Total Harmonic Distortion—200 Hz to 4 kHz2:
Off-hook
On-hook —
——
—0.3
1.0 %
%
Tra n smi t Gai n , f = 1 kHz (PT/PR to VITR) ( cu rr e n t l im it) –391 –403 –415 V/A
L9217A, Open Loop:
Re ceiv e + G a in, f = 1 kH z ( RCVP to PT / PR) 3
Receive – Gain, f = 1 kHz (RCVN to PT/PR)3
L9217G, Op en Loop:
Re ceiv e + G a in, f = 1 kH z ( RCVP to PT / PR) 4
Receive – Gain, f = 1 kHz (RCVN to PT/PR)4
7.62
–7.62
1.94
–1.94
7.86
–7.86
2.00
–2.00
8.09
–8.09
2.06
–2.06
—
—
—
—
Gain vs. Frequency (transmit and receive)
(600 Ω termination; reference 1 kHz2):
200 Hz to 300 Hz
300 Hz to 3.4 kHz
3.4 kHz to 16 kH z
16 kHz to 266 kHz
–1.00
–0.3
–3.0
—
0.0
0.0
–0.1
—
0.05
0.05
0.3
2.5
dB
dB
dB
dB
Gain vs. Level (tra nsmi t and receive)(reference 0 dBV2):
–55 dB to +3 dB –0.05 00.05 dB
2-Wire Idle-channel Noise (600 Ω termination) :
Psophometric2
C-message
3 kHz Flat2
—
—
—
–87
2
10
–77
12
20
dBmp
dBrnC
dBrn
Transmit Idle-channel Noise:
Psophometric2
C-message
3 kHz Flat2
—
—
—
–82
7
15
–77
12
20
dBmp
dBrnC
dBrn
12 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Tabl e 9. Logic Inputs and Outputs
All outputs are open collectors with in ternal, 30 kΩ pul l-up resistor. Input pins have internal pull-down or some
method to power up in the disconnect state.
Parameter Symbol Min Typ Max Unit
Input Voltag es:
Low Level (permissible range)
High Level (permissible range) VIL
VIH –0.5
2.0 0.4
2.4 0.7
VCC V
V
Input Currents:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V) IIL
IIH –50
–35 –115
–60 –200
–100 µA
µA
Outp ut Voltages (open collector with internal pull-up re sistor):
Low Level (VCC = 4.75 V, IOL = 360 µA)
High Level (VCC = 4.75 V, IOH = –20 µA) VOL
VOH 0
2.4 0.2
—0.4
VCC V
V
Ring Trip Requirements
■Ringing signal:
— Voltage, minimum 35 Vrms, maximum 100 Vrms
— Frequency, 17 Hz t o 33 Hz
— Cre st factor, 1.2 to 1.6
■ Ring trip:
— ≤100 ms (typical)
■Pretrip:
— The c ir c uits in Fig ur e 3 w ill no t ca u se ring tr ip. 12-2572f(F)
Fi gure 3. R i ng T rip Circui ts
RING
RING
100 Ω
10 kΩ
TIP
TIP 2 µF
8 µF
Preliminary Data Sheet
October 2001
Agere Systems In c. 13
with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Test Configurations
12-3559Em (F)
Figure 4. L9217 Basic Test Circuit
VBAT VCC
0.1 µF0.1 µF
0.47 µF
0.1 µF
RLOOP
43.2 kΩ
22.1 kΩ
B1
NSTAT
VBAT BGND VCC AGND
IPROG
LCTH
RTSP
RTSN
VITR
RCVP
B0
CF1
CF2
L9217
SLIC
TG 8.06 kΩ
100 Ω/600 Ω
2 M Ω
274 k Ω
2 MΩ
402 Ω
VBAT
50 Ω
50 Ω
RING
TIP XMT
75 kΩ
RCV
RCVN 46 k Ω
19. 4 k Ω
DCOUT
B2
VTX
TXI 0.1 µF
PPMIN
OVH
41.7 kΩ
V
PPMOUT 6.19 kΩ
12-2582.b (F)
Figu re 5. Metalli c PSR R
12-2583.b (F)
Fi gure 6. Longit udina l PSRR
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
VT/R
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
+
–
PSRR = 20log VS
VT/R
900 Ω
BYPASS CAPACITOR
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
BYPASS CAPACITOR
56.3 Ω
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
PSRR = 20log VS
VM
67.5 Ω
10 µF
10 µF
67.5 Ω
VM
+
–
14 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Test Configurations (continued)
12-2584.c (F)
Figu re 7. Lo ngitudi na l Ba lan c e
VS = 0.5 Vrms 30% A M 1 kHz M O DULATION ,
f = 500 kHz —1 MHz
DEVICE IN POWERUP MODE, 600 Ω TERMINATION
5-6756.bm (F)
*
HP
is a registered trademark of Hewl ett-Packard C ompan y.
Figure 8. RFI Rejection
12-2585.a (F)
Fi gure 9. Lo ngi t ud in a l Impedance
12-2587.e (F)
Figure 10. ac Gains
TIP
RING
BASIC
TEST CIRCUIT
LONGITUDINAL BALANCE = 20 log VS
VM
368 Ω
100 µF
100 µF
368 Ω
VM
+
–
VS
BASIC TEST
CIRCUIT
TIP
RING
VBAT
0.01 µF
0.01 µF
600 Ω
2.15 µF
82.5 Ω
82.5 Ω
HP
* 4935A
TIMS
50 Ω12
4
6, 7 L7591
VS
TIP
RING
BASIC
TEST CIRCUIT
+
–
+
–
ILONG
ILONG
VPT
VPR
ZLONG = OR
∆ VPT
∆ ILONG ∆ VPR
∆ILONG
TIP
RING
BASIC
TEST CIRCUIT
600 ΩVT/R
+
–
GXMT =VXMT
VT/R
GRCV =VT/R
VRCV
XMT
RCV
VS
Agere Systems In c. 15
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications
A basic loop start reference circuit, using bused ringing with the L9217 S LIC and T7504 first-generation codec, is
shown in Figure 11. This circui t is desi gned for a 90 0 Ω termination impedan ce and an 850 Ω + 50 nF transhybrid.
T ransmit gain is set at 0 dBm and receiv e gain is set at –7 dBm.
* Placeholder for potential resistor to form filter against PPM generator noise if necessary.
Figure 11.
Basic Loop Sta rt Application Circ uit Using T7504-Type Codec
RPROG
35.7 kΩ
RLCTH
22.1 kΩ
RPT
50 Ω
L7591
RPR
PT
18
1
7LCTH
8DCOUT
50 ΩPR
10
RTSP
20
RTS1
402 Ω
RTSN
19
RTSN
3.32 MΩ
VRING
VBAT CF2
11 CF1
12
CF1
0.47 µF
AGND
16 BGND
17
IPROG VBAT
9
CBAT
0.1 µF
RCVP
RCVN
5
6
RGP
RT1
33.2 kΩ
RT2
45.3 kΩ
RRCV
63.4 kΩ
RHB1
97.6 kΩ
RX
86.6 kΩGSX
VFRO
DX
DR
FSX
FSR
MCLK
1/4 T7504
CODEC
PCM
HIGHWAY
CONTRO
L
AND
CLOCK
–
+
L9217
SLIC
CRTS1
0.015 µF
RTSP
2.94 MΩ
CF2
0.1 µF
VBAT
+2.4 V
CB2
0.47 µF
22 SUPERVISION
B1
B0 14
15
CONTROL
INPUTS
NSTAT
B2 13
VITR 23
TXI 24
VTX 25
TG 26
CB
0.1 µF
RGP1
8.06 kΩ
TIP
RING
EMR
CB1
0.47 µF
RHB
86.6 kΩCHB
0.47 nF
14.7 kΩ
CPPM
0.01 µF
PPMIN
RPPM
6.19 kΩ
RGN
9.76 kΩ
PPMIN PPMOUT
2821
OUTPUT
VCC
4
CCC
0.1 µF
VCC
ROVH
49.9 kΩ
27 OVH (for 2.5 Vrms PPM)
LCAS
CHY
4.7 nF
OPEN
RFLT*
16 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Tab le 10. Parts List for Loop Start App lication Circuit Using T75 04-Type Codec
Name Value Function
Integrated Circuit s
SLIC L9217 Subscriber loop interface circuit (SLIC).
Protect or Agere L7591 Secondary protection.
Ringing Relay Agere L7581/2/3 or EMR Switches ringi ng signals.
Codec T7504 First-generation codec .
Overvo l tag e Protecti on
RPT 50 Ω, Fusible Protec ti on resisto r.
RPR 50 Ω, Fusible Protec ti on resisto r.
Power Supply
CBAT1 0.1 µF, 20%, 100 V VBAT filter capacitor.
CCC 0.1 µF, 20%, 10 V VCC filter cap a citor.
CF1 0.47 µF, 20%, 100 V With CF2, improv es idle-chan nel noise.
CF2 0.1 µF, 20%, 100 V Wi th CF1, improv es idle-chan nel noise.
dc Chara cteri stics
RPROG 35.7 kΩ, 1%, 1/16 W Set low current limit.
ac Characteristics
CB1 0.47 µF, 20%, 10 V ac/dc separation capacitor.
CB2 0.47 µF, 20%, 10 V ac/dc separation capacitor.
CB0.1 µF, 20%, 10 V dc blocking capacitor.
RT1 33. 2 kΩ, 1%, 1/16 W With RGP and RRCV, sets ac termination impeda nce.
RRCV 63.4 kΩ, 1%, 1/16 W With RGP and RT1, sets receive gain.
RGP 14.7 kΩ, 1%, 1/16 W With RT1 and RRCV, sets ac te rmin ation impedanc e
and receive gain.
RT2 45. 3 kΩ, 1%, 1/16 W With RX, sets transmit gain in codec.
RX86.6 kΩ, 1%, 1/16 W With RT2, sets tra nsmi t gain in codec.
RHB1 97.6 kΩ, 1%, 1/16W Sets hybrid balance.
CHB 0.47 nF, 10%, 10 V With RGS provides gain shaping for hybrid.
RHB 86.6 kΩ, 1%, 1/16 W With CGS provides gain shaping for hybrid.
RGP1 8.06 kΩ, 1%, 1/16 W Sets dc transmit gain of SLIC.
RGN 9.76 kΩ, 1%, 1/16 W dc offset.
Meter Pulse
CHY 4.7 nF, 20%, 10 V M et er pulse rejection.
CPPM 0.01 µF, 20%, 10 V Meter pulse injection.
RPPM 6.19 kΩ, 1%, 1/16 W Meter pulse rejection.
ROVH 49.9 kΩ, 1%, 1/16 W Increas es PPM overhead mode.
Supervision
RLCTH 22.1 kΩ, 1%, 1/16 W Sets loop closure (off -hook) threshol d.
RTS1 402 Ω, 5%, 2 W Ringing source series resistor.
CRTS1 0.015 µF, 20% , 10 V With RTSN, RTSP, forms filter pole.
RTSN 3.32 MΩ, 1%, 1/16 W Wi th RTSP, sets threshold.
RTSP 2.94 MΩ, 1%, 1/16 W Wi th CRTS1, RTSN, sets threshold.
Agere Systems In c. 17
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Table 1 1 shows the design parameters of the appli cat ion circuit shown in Figure 11. Components that are adjust ed
to program these v alues are also shown.
Tab le 11. 900 Ω Terminati on , 850 Ω + 50 nF Hybrid Fi rs t-Generation Co dec De sign Parame ters
Design Parameter Param eter Va lue Components Adjusted
Loop Closure Threshold 10 m A RLCTH
dc Loop Current Limit 20 m A RPROG
ac Termination Impedance 900 ΩRT1, RGP, R RCV, RGP1
Hybrid Bal ance Line Impedance 850 Ω + 50 nF CHB, RHB, RHB1
Trans mi t Gain 0 dBm RT2, RX, RN1, RN2, CN
Receive Gai n –7 dBm RRCV, RGP, RT1
18 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
A basic loop start reference circuit, using bused ringing with the L9217 SLIC and T85 36 third-generation codec , is
shown in Figure 12.
* Placeholder for potential resistor to form filter against PPM generator noise if necessary.
Fi gure 12.
Basic Loop Star t Application Circu it Using T8536-Type Codec
RPROG
35.7 kΩ
RLCTH
22.1 kΩ
RPT
50 Ω
L7591
RPR
PT
18
1
7LCTH
8DCOUT
50 ΩPR
10
RTSP
20
RTS1
510 ΩRTSN
19
RTSN
3.4 MΩ
VRING
VBAT
CF2
11 CF1
12
CF1
0.47 µF
AGND
16 BGND
17
L9217
SLIC
CRTS1
0.015 µF
RTSP
2.94 MΩ
CF2
0.1 µF
RCVN
NSTAT
6DR2
FS
BCLK
1/4 T8536 PCM
HIGHWAY
CONTROL
AND
CLOCK
B0
B1
15
14
RCVP 5
VFRON
VFXI
VFROP
SLIC0a
SLIC3a
SLIC2a
DGND
DX1
DX2
DR1
CVDD
0.1 µF
VDD
CODEC
B2 13 SLIC4a
22
VITR 23
TIP
RING
EMR
TXI 24
VTX 25
TG 26
CB
0.1 µF
RGP1
8.06 kΩ
CB1 0.1 µF
TXI
IPROG
RPPM
6.19 kΩ
CPPM
0.01 µF
PPMIN
PPMIN PPMOUT
2821
VBAT
9
CBAT
0.1 µF
VBAT
VCC
4
CCC
0.1 µF
VCC
ROVH
61.9 kΩ
27 OVH (for 3.5 Vrms PPM)
RCIN
20 MΩ
LCAS
CHY
4.7 nF
OPEN
RFLT*
Agere Systems In c. 19
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Tab le 12. Parts L ist for Loop Start Application Circuit Using T8536-Type Codec
Name Value Function
Integrated Circuits
SLIC L9217 Subscriber loop interface ci rcuit (SLIC).
Protector Agere L7591 Secondar y protect i on.
Ringing Rel ay Agere L7581/2/3 or EMR Swi tches ringing signals.
Codec T8536 Third-generation codec.
Overvoltage Protection
RPT 50 Ω, Fu si b le Protect ion resistor.
RPR 50 Ω, Fu si b le Protect ion resistor.
Power Supply
CBAT1 0.1 µF, 20%, 100 V VBAT filter capacitor.
CCC 0.1 µF, 20%, 10 V VCC fil t e r c a pacitor.
CF1 0.47 µF, 20% , 100 V W ith CF2, i mproves idle -channel noise.
CF2 0.1 µF, 20%, 100 V W ith CF1, improves idle -cha nnel noise.
dc Characteristics
RPROG 35.7 kΩ, 1%, 1/16 W Set low current l i mit.
ac Characteristics
CB1 0.1 µF, 20%, 10 V ac/dc separation capacitor.
CB0.1 µF, 20%, 10 V dc blocking capacitor.
RGP1 8. 06 kΩ, 1%, 1/16 W Sets dc transmi t gain of SLIC.
RCIN 20 MΩ, 5%, 1/16 W dc bias.
Supervision
RLCTH 22.1 kΩ, 1%, 1/16 W Sets loop closure (off-hook) threshold.
RTS1 510 Ω, 5%, 2 W Ringing source se ries resistor.
CRTS1 0.015 µF, 20%, 10 V With RTSN and RTSP, forms second 2 Hz filter pole.
RTSN 3.4 MΩ, 1%, 1/16 W W ith RTSP, sets threshold.
RTSP 2.94 MΩ, 1%, 1/16 W With RTSN, sets threshold.
Meter Pulse
CHY 4.7 nF, 20%, 10 V M eter pulse rejection.
CPPM 0.01 µF, 20%, 10 V Meter pulse injecti on.
RPPM 6.19 kΩ, 1%, 1/16 W Meter pulse rejection.
ROVH 61.9 kΩ, 1%, 1/16 W Increases PPM overhead mode.
2020 Ag e re Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applications
Battery Feed
The dc feed characteristic can be described by:
where:
IL = dc loop current.
VT/R = dc loop volt age.
|VBAT| = bat tery voltage magn itude.
VOH = overhead voltage. This is the di fference between
the battery voltage and the open loop tip/ring
voltage.
RL = loop res istance , not including protection resistors.
RP = protection resistor value.
Rdc = SLIC internal dc feed resistance.
Note: VBAT = –48 V; ILIM = 22 mA; Rdc1 = 115 Ω.
12-3050.i (F)
Figure 13. Loop Current vs. Loop V olt age
Starting from the on-hook condition and going through
to a short circuit, the curve passes through two regions:
Region 1: On-hook and low-loop current s. The slope
corresponds to the dc resistance of the SLI C, Rdc1
(default is 72 Ω typical). The open circuit voltage is
the battery voltage less the overhead voltage of the
devic e, VOH (de fault is 6.5 V ty pical). These values are
suitable for most applications, but can be adjusted if
needed.
Region 2: Current limit. The dc cu rrent is limited to a
starting value determined by external resistor RPROG,
an internal current source, and the gai n from tip/ring t o
pin VITR. Current l i mit wi t h a 100 Ω load is set by t he
equation:
0.637 RPROG (kΩ) + 2 mA = ILIM x (mA)
Overhead Vol ta ge
In order to drive an on-hook ac signal, the SLI C must
set up the tip and ring volt age to a value less than the
battery voltage. The amount that the open loop voltage
is decreased relative to the battery is referred to as t he
overhead voltage. This is expressed as an equation:
VOH = |VBAT| – (V PT – VPR)
W ithout this buffer voltage, amplifier saturation will
occur and the sign al will be c lipped. In modes wit hout
PPM , the L9217 is set to allow undistorted on-hook
transm ission of a 3.17 dBm signal into a 900 Ω loop
impe dance.
In high overhead and PPM modes, overhead is auto-
mati call y increased to accommodat e on-hook t ransmis-
sion of meter pulse signals. The increase in overhead
is set by a resi stor from pin OVH to ground. Thi s is
expressed as an equation:
VOVH (V ) = 6.37 + 0.09535 x ROVH (kΩ)
ILVBAT VOH–
RL2RPRdc++
----------------------------------
=
VT/R VBAT VOH–()R×L
RL2RPRdc++
---------------------------------------------
=
01020 50
0
20
30
40
50
LOOP VOLT AGE (V)
30 40
10
LOOP CURRENT (mA)
1
12.5 kΩ
–1
Rdc1
ILIM TESTED ILIM ONSET
Agere Systems In c. 21
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applications (continued)
Rate of B attery Reversa l
The rate o f battery reversal is controlled or ramp ed by
capacitors FB1 and FB2. A c hart showing FB1/FB2 val-
ues versus typical ramp rate is given below. Leave
FB1/FB2 open if it is not desired to ramp the rate of
battery reve rsal.
Tab le 13. FB1/ FB2 Va lu es vs. Ty pi cal Ramp Time
Loop Range
The equat ion below can be rear ranged to provi de the
loop range for a requir ed loop current:
Off-Hook Detection
The loop closure det ection threshold is set by re sistor
RLCTH. The supervision output bit NSTAT is high in an
on-hook condition. The of f-hook comparator goes low
during an off-hook conditon:
12-2553fm (F)
Figu re 14. Of f-Hook Dete ct i on Circuit
CFB1/CFB2 Transition Time
0.01 µF 20 ms
0.1 µF 220 ms
0.22 µF 440 ms
0.47 µF 900 ms
1.0 µF 1.8 s
1.22 µF2.25 s
1.3 µF 2.5 s
1.4 µF 2.7 s
1.6 µF 3.2 s
RLVBAT VOH–
IL
---------------------------- 2RP–RDC–=
ITR (mA) = 0. 4 167 RLTCH (kΩ) –1. 9 mA
ACTI VE off-hook to on-hook
ITR (mA) = 0. 4 167 RLTCH (kΩ) + 2.7 mA
SCA N on-hook to off-hook
RLITR
RP
RP
RING
–
+
–
+
DCOUT
RLCTH
LCTH
NSTAT
TIP
0.125 V/mA
0.05 mA
22 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applications (continued)
Ring Trip Detection
The ring trip circuit is a comparator that has a speci al input section optimized for this application. The equivalent
circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing.
Fi gure 15 . Ring Trip Eq uiva lent Cir cuit an d E quivalent Appl ication
Ring trip detection threshold is gi ven by the following equat ion:
ITH (m A) =
+
–
RTSP
RLOOP
15 kΩ
8.4 V
IP = IN
RTSN
3.32 MΩ/3.40 MΩ
CRTS1
0.015 µF
PHONE
HOOK SWITCH
RC PHONE
VRINGVBAT
NSTAT
RTSP
IN
RTSN
–
+
2.94 M Ω
RS
402 Ω/510 Ω
RTSN MΩ()0.015 RTSP MΩ()–+[]VBAT 8.4–[]×1000×
RTSN MΩ()0.015+[]RS×
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Agere Systems In c. 23
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Longitudinal Balance
The SLIC is graded to certain longitudinal balance
specifications . The numbers are guaranteed by testing
(Figure 5 and Figure 8). However, for specific applica-
tions, the longitudinal balance may also be determined
by termination impedan ce , protection resistance, and
especially by the mismatch between prot ec tion resis-
tors at tip and ring. This can be illustrated by the equa-
tion:
LB = 20 x log
where:
LB: longitudinal balance.
RP: protection resi stor value in Ω.
ZT: magnitude of the termination impedance in Ω.
ε: protection resi stor mismatc h in Ω.
∆: SLIC internal tip/rin g sensing mismat ch.
The ∆ can be calculated using the above equation with
these exceptions: ε = 0, ZT = 600 Ω, RP = 100 Ω, and
the longi tudinal balance specification on a specific
code.
Now with ∆ av ailable, the eq ua ti on w ill pr ed i ct the
actual longitudinal balance for RP, ZT, and ε.
Be aware that ZT may vary with frequency f or complex
impedance appl icat ions.
Periodic Pulse Metering (PPM)
Periodic pulse metering (PPM), also referred to as
TTX, i s input to the PPMIN input of t he L9217. Upon
application of appropriate logic control, this signal is
presented to the tip/ring subscriber loop. The state of
the L9217 may be changed whi le applying PPM sig-
nals. The L9217 assumes that a shaped PPM signal i s
applied to the PP M IN inpu t.
Suffi cient drive curr ent is avail able in the tip and ring
drive amplifiers to support 3.5 Vrms PPM signals into a
200 Ω load with a 45 mA dc curren t limit.
PPM signals are i nput to a separate PPMIN input. This
input is controlle d via the logic table. PPMIN is off dur-
ing all st ates except the forward/reverse PP M act i ve
state. Thus, PPM signals may be present at all times,
even during non-PP M act i ve times. To apply PPM to
tip/ring, from a normal overhead state first switch to a
high overhead s tate without PPM; the overhead volt-
age at tip/ring will increase to 7 V t o 13 V. The ramp up
time of the overhead increase is on the order of hun-
dreds of milliseconds. Thus, wait 1 s before a pplying
the PPM signal by going t o a PPM active high over-
head state. Once in a high overhead, t here is no timing
requirem ent in switching in and out of a PPM active
mode. Without the inital 1 s delay, AT/AR will get int o
saturation and PPM signal at T/R will get distorted, pro-
ducing crosstalk in the handset.
PPM input signals may be a maxim um 0.525 Vrm s at
PPMIN. The gain from PPMIN tip/ring is 10. Thus, for
2.5 Vrm s at tip and ring, apply a 0.375 Vrms signal at
PPMIN. The PPM signal should be ac coupled to
PPMIN through a 0.01 µF capacitor.
W hen appli ed to tip and ring, the PPM signal w ill also
be returned through the SLIC and will appear at the
SLIC V ITR output. The concern is that this high-voltage
signal can ove rload the codec input and cause distor-
tion of the (desired) ac sign al. Therefore, some sort of
PPM rejection scheme must be employed, see Figure
1, Functional Diagram. The L9217 outputs on the
PPM OUT pin, which is the out put of the PPM input
ampl ifier. Connec ting a resistor, RPPM, from PPMOU T
to node TG will provide a path for a hybrid reject of the
returned mete r pulse signal. The return path from tip
and ring to VITR for the PPM signal is through the
internal AX am plifier. TG is the input to this amplifier.
Through RPPM, by applying a PPM signal equal in mag-
nitud e, but 180 degrees o ut of phase to the returned
PPM signal at TG, the PPM signal is cancelled, pre-
venting overload at the codec input. Even if the cancel-
lation is not perfect, the idea is to reduce the PP M
signal so as not to overload the codec. Codecs typi-
cally have a low-pass filter at their input to reject any
residual me ter pulse signal.
The value of RPPM i s se lected b y:
RPPM = [{(VPPMIN x 10)/(RPPMLOAD + RDC + 2RP)}/201.2]–1
For undistorted transmissio n of meter pulse signals,
incre ase the overhead as described in the Overhe ad
Voltage section of this dat a sheet.
368 RP
+()368 ZT RP–+()×
368 2 ZT 2–RP×[]×∆ε+×()×
-------------------------------------------------------------------------------------------
2424 Ag e re Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design
Codec Typ es
At this point in the des ign, the codec needs to be
selected. The interface network bet ween the SLIC and
codec can then be designe d. There are four key ac
design parameters. Term i na ti on i m pe d a nce is the
impedance loo king into the 2-wire port of the line card.
It is set to match the impedance of the telephone loop
in order to minimize echo return to the telephone set .
Tran smit gain is measured from the 2-wire port to the
PCM highway, while receive gain is done from the
PCM highway to the transmit port. Finally, the hybrid
balance netwo rk cancels the unwanted amount of the
receive signal that appears at the transmit port.
Below is a brief codec feature summary.
First-Generatio n Codecs. The se perform the basic
filtering, A/D (transm it), D/A (receive), and µ-law/A-law
companding. They all have an op amp in front of the
A/D convert er for transm it gain sett i ng and hybrid bal-
ance (cancellation at the summing node). Depen ding
on the type, some have dif ferential analog input stages,
different ial analog out put stages, 5 V only or ±5 V oper-
ation, and µ-law/A-law selectability. These are avail-
able in single and quad designs. This type of codec
requires continuous time anal og filtering via external
resistor/capacitor networks to set the ac design param-
eters. An example of this type of codec is the Agere
T7504 quad 5 V only codec.
This type of codec tends to be the mos t econ omica l in
terms of piece part price, but tend s to require more
external compon ents than a third-generation codec.
Further, ac parameters are fixed by t he external R/C
network, so sof tware control of ac parameters i s diff i -
cult.
Third-Generation Codecs. Thi s class of devices
includes all ac parameters set digit ally under micropro-
cessor cont rol. Dependi ng on t he device, it may or may
not hav e data control latches. Additional functionality
sometimes offered includes tone plant gene ration and
reception, TTX generati on, test algorit hms, and echo
cancellation. Again, this type of codec may be 5 V
only or ±5 V operation, single quad or 16-channel, and
µ-law/A-law or 16-bit linear coding select abl e. Exam-
ples of this type of codec are the Agere T853 5/6 (5 V
only, quad, standard features), T8533/4 (5 V only , quad
with echo cancellation), and the T8531/36 (5 V only
16-channel with self-test).
ac Interface Network
The ac interface netwo rk between the L9217 and the
code c will vary depending on the codec selected. With
a first-generatio n codec, the interface betwee n the
L9217 and codec ac tually sets the ac parameters . Wit h
a third-gene ration codec, all ac parameters are set dig-
itally, i nternal to the codec; thus, the interface between
the L9217 and this type of codec is d esigned to avoid
overload at the codec input in the transmit direction,
and to optimize signal-to-noise ratio (S/N) in the
receive direction.
Rece ive Inte rface
Because th e design requirements are very different
with a first- or third-generation codec, the L9217 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9217
and codec.
Wi th a first-generation codec, the term i nation imped-
ance is set by pr oviding gain shap ing through a feed-
back network from the SLIC VITR output to th e SLIC
RCVN/RCVP inputs. The L9217 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single ended to differential gain in the receive direc-
tion from either RCVN or RCVP to T/R. Assuming a
short from VITR t o RCVN or RCVP, the maximum
impe dance that is seen looking into the SLIC is the
produc t of the SLIC transconduc tance times the SLIC
receive gain, plus the protection resistors. The various
speci fied termination impedanc e can range ov er the
voiceband as low as 300 Ω up to over 1000 Ω. Thus, if
the SLIC gains are too low, it will be imposs ib le to syn-
thesize the higher termination imped ances . Further-
more, the termination that is achiev ed will be far less
than what is calculat ed by assuming a short for SLIC
output to SLIC input. In the receive direction, in order to
control echo, the gain i s typically a loss, which requires
a loss network at the SLIC RCVN/RCVP inpu ts, w hich
will reduce the amount of gain that is availa ble for te r-
minat i on impedance. For this reason a high-gain SLIC
is required with a first-generat ion codec.
Agere Systems In c. 25
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Receive Interface (continued)
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer mus t first decide upon all termination imped-
ance, hybrid balances, and transm ission level points
(TLP) requirements that the line card must meet. In the
transmit directi on, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that i s being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequenc y, must ensure that the
codec is not overloaded. With a given TLP and a gi ven
SLIC gain, if t he signal wi l l cause a codec overload, the
desi gn er must i n se rt so me sort of loss, typica lly a resis-
tor divider, between the SLIC output and codec input.
In the re ceive direction, the issue is to optimize S/N.
Again, the designer must consider all the considered
TLPs. The idea is, for all desired TLPs, to run the codec
at or as close as possi ble to it s m axim um output signal,
to optimize the S /N. Remember noise floor is constant,
so the hotter th e signal from the codec, the better the
S/N. The problem is, if the codec is feeding a high-gain
SLIC , either an external resistor divider is n eeded t o
knock the gain down to meet the TLP requirements, or
the codec is not operat ing near maximum signal levels,
thus comp romi sing the S/N.
It appears the solution is to have a SLIC with a low
g ain , especially in the rec e iv e d ire c t ion . This w ill al lo w
the codec to operate near its maximum output signal
(to optimize S/N), without an external resistor divid er
(to minimize cost).
N ote also that some third-generation co decs require
the design er to provide an inherent resistive termina-
tion vi a external net works. The codec will then provide
gain shaping, as a function of frequency to meet the
return loss requirements. Further stability issues may
add external components or excessive ground plane
requirem ents to the design.
To m eet the unique requirem ents of both types of
cod ecs, the L9217 offers two receive gain choices.
These rec eive gains are mask program mab le at the
factory and are off ered as two diff erent code variations.
For interface with a first- generation codec, the L9217A
is offered wit h a receive gai n of 7.86. For interface with
a third-generation cod ec, the L9217G is offered with a
receive gain of 2. In ei ther case, the transconductance
in the transmit direction, or the transmit gain is 403 Ω.
Example 1: Real Termination ( First-Generation Codec)
ac equi valent circuits for real termination usi ng a T 7504 codec is shown in Figure 15.
12-3581Cm (F)
Figure 16. ac Equivalen t Circuit
RP
ZT+
–
RP
VT/R
IT/R
VS
ZT/R
+
–
RING AV = –1
AV = 1
VITR
–
+
+
–
CURRENT
SENSE
TIP
+
–
RT1
RRCV
RHB1
RT2
RCVN
RCVP
RXVGSX
VFXIN
VFR
1/4 T75 04 CODEC
RG
2.4 V
–0.403 V/mA
AV =
L9217 SLIC
VFXIP
3.93
26 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Example 1: Real Termin ation (Fir st-Gen eration Co dec) (continued)
The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination imped-
ance.
Term i n ation Imp edan ce:
ZT =
Receive Gain:
grcv =
grcv =
Tran smit Gain:
gtx =
gtx = x
Hybrid Balance:
hbal = 20l og
To optimize the hyb rid balance, the sum of the c urrents at the VFX input of the codec op amp should be set to 0.
The fol lowing express ions assume the test network is the same as the t ermination impedance.
RHB =
hbal = 20l og
VTR⁄
ITR⁄–
--------------
ZT2RP3168
1RT3
RGP
---------RT3
RRCV
------------
++
-----------------------------------
+=
VTR⁄
Vfr
--------------
7.86
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
1ZT
ZT/R
-------------
+
-------------------------------------------------------------------------------------
VGSX
VTR⁄
---------------
RX
RT6
---------- 403
ZT
-----------
VGSX
VTR⁄
---------------
RX
gtx grcv×
-------------------------
RX
RHB
------------gtx–grcv×
Agere Systems In c. 27
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Example 2: Complex Ter mination (First-Gen eration Codec)
Below are design equations for complex termination (see Figure 17 and Figure 18).
RTGP || R TGS
RTGP || R TGS
gtx =
grcv =
hbal = 20log
where:
ZT/R = R1 + R2 || C
ZTG = RTGP || (RTGS + CG)
RTGP = 8.06 kΩ
RTGS = RTGP
CG = x C
and
CNRN2 = CG RTGP
RN1 = RN2
The equations above do not include the blocking capacitors.
RT1 2RP7.86
201.2
------------ 1
1RT3
RGP
---------RT3
RRCV
------------
++
----------------------------------- 1
1RN1
RN2
--------
+
------------------
–
•+=
RT2 7.86
201.2
------------RTGP RTGS⁄
1RT3
RGP
---------RT3
RRCV
------------
++
----------------------------------- 1
1RN1
RN2
--------
+
------------------
+
+=
1
CT
-------7.86
201.2
---------------- 1
CN1
-----------RN2
RN1 RN2+()
2
-------------------------------------RTGP RTGS
|| 1
CTG
----------- RTGP
RTGP RTGS+
-------------------------------------
2•• 1
1RT3
RGP
------------RT3
RRCV
---------------
++
---------------------------------------------- 1
1RN1
RN2
-----------
+
---------------------
–
+
=
RX
RT6
---------- 1
201.2
---------------- ZTG
ZT
-----------
7.86
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
------------------------------------------------1
1ZT
ZTR⁄
-------------
+
------------------------
×
RX
RHB
------------gtx–grcv×
R1
R2
-------
R22
RTGP R1R2+()
------------------------------------------
2RP
3167
-------------
3167
2RP
-------------RTGS
RTGP
--------------
1–
28 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Example 2: Complex Termina tion (First-Gene ration Codec) (continued)
5-6401L(F)
Figure 17. In terface Circuit Using First-Gen erati on Codec (±5 V Codec)
5-6400o(F)
Figure 18. Interface Circuit Using First-Ge nera tion Code c (+5 V Only Codec)
RTGS
RTGP = 8.06 kΩRT6
RX
RT3
CODEC
OP AMP
–
+
CN
RN1
RN2 RGP
RRCV
RCVN
RCVP
–IT/R
201.2
CGS
CB1
RTGS
RT6
RT3
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
CN
RN1
RRCV
RCVN
RCVP
–IT/R
CGS
AX
RTGS
CB1
RTGP = 8.06 kΩRT6
Rx
RT3
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
CN
RN1
RN2RGP
RRCV
RCVN
RCVP
–IT/R
201.2
CG
AX
–2.4 V
CB2
Agere Systems In c. 29
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Power Derating
Operating temperature range, maximum current limit ,
maximu m battery voltage, minimum dc loop, and pro-
tection resistor values wi ll influence the overal l thermal
performance . This section sho ws the relevant design
equation s and consideration s in evaluating the SLIC
thermal performance.
Consider the L9217 SLIC in a 28-pin PLCC package.
The thermal resista nce on a 2-layer board with natural
convection is 43 °C/W.
The SLIC will enter the thermal shutdown state at a
minimum of 150 °C. The thermal shutdown design
should ensure that the SLIC temperature does not
reach 150 °C under normal operating condition s.
Assume a maximum ambient operating temperature of
85 °C, a design current limit of 25 mA, and a maximum
battery of –52 V. Further, assume a (worst-case) mini-
mum dc loop of 200 Ω, and that 50 Ω protection resis-
tors are use d at both tip and ring.
1. TTSD – TAMBIENT(max) = a llow ed therm a l ris e .
150 °C – 85 °C = 65 °C
2. A llowed thermal rise = package thermal
impeda nce • SLIC power dissipation.
65 °C = 43 °C/W • SLIC pow er dissipation
SLIC power dissipation (P DISS) = 1.51 W
Thus, if th e total power dissipated in the SLIC is less
than 1.51 W, it will not enter the thermal shutdown
state. To tal SLIC power is calcu lated as:
Total PDISS = Maximum battery • maximum
current limit (including e ffects of accuracy)
+ SLIC quiescen t power
For the L9217, SLIC quiescent power (PQ) is maximum
at 0.175 W. Thus,
Total PDISS = (–52 V • [25 mA • 1.08]) + 0.175 W
Total PDISS = 1.404 W + 0.175 W
Total PDISS = 1.579 W
The power dis si pated in the SLIC is the total power dis-
sipation less t he power that is dissipated in the loop.
SLIC PDISS = Total power – loop power
Loop power = (ILIM)2 • (RdcLOOP min + 2RP)
Loop power = (25 mA • 1.08)2 •
(200 Ω + 100 Ω)
Loop power = 0.21 9 W
SLIC power = 1.579 W – 0.219 W = 1.36
SLIC power = 1.36 W < 1.51 W
Thus, in this exampl e, the thermal design ensures that
the SLIC will not enter the thermal shutdown st ate.
Pin-for-Pin Compatibility with L9218 /L9219
The L9217 can be a pin-for-pin replacem ent for the
L9218/ L9219. The except ions are as follows: L9217
has 3 logic control inputs: B0, B1, and B2. The L9218
has only 2 logic control inputs: B0 and B1 . Pin 13 in
L9218 is NC, so a connection between the controller
and pin 13 will not affect L9218 operation. In L9217, pin
28 is PPMOUT, pin 21 i s PPMI N, and pin 27 is OVH. In
L9218/ 9, pin 28 is NC, pin 21 is NC, and pin 27 is TSD
PCB Layout Information
Make the l eads to BGND and VBAT as wide as possible
for thermal and electrical reasons. Also, maximize the
amount of PCB copper in the area of—and specifically
on—t he leads connec t ed to this device for the lowest
operating temperat ure.
W hen powering the device, ensure that no external
potent ial creates a v oltage on any pin of the device that
exceeds the device ratings. In this application, some of
the conditions th at cause such potentials during pow-
erup are the following:
1. A n indu ctor connecte d to PT and PR (this can force
an overvolt age on VBAT through the protection
devic es if the VBAT connect ion chatters).
2. Inductance in the VBAT lead (this could resonate with
the VBAT filter capacitor to cause a dest ructive over-
voltage).
This device is normally used on a circuit card that is
subject ed to hot plug-in, meaning the card is plugged
into a biased backplane connector. In order to prevent
damage to the IC, all ground connect i ons must be
applied before, and removed after, all other connec-
tions.
30 Agere Systems In c.
Preliminary Data Sheet
October 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Outline Diagram
28- Pin P LCC
Dim e ns ion s ar e in millimet e r s .
5-2506r.8(F)
1.27 TYP
0.330/0.533
0.10
SEATING PLANE
0.51 MIN
TYP
4.572
MAX
12 18
11
5
4126
25
19
12.446 ± 0.127
PIN #1 IDENTIFIER
ZONE
11.506 ± 0.076
11.506
± 0.076
12.446
± 0.127
Agere Systems In c. 31
Preliminary Data Sheet
October 2001 with Reverse Batt ery and PPM
L9217A/G Low-Cost Line Interface
Ordering Information
Device Package Comcode
LUCL9217AAR-DT 28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 8
108760737
LUCL9217AAR-D 28-P in PLCC
(Dry-bagged)
Gain of 8
108760729
LUCL9217GA R-DT 28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 2
108760760
LUCL9217GA R-D 28-Pin PLCC
(Dry-bagged)
Gain of 2
108760752
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
Oct ob er 20 01
DS02-002ALC (Replaces DS01 -253ALC)
For additio nal information, contact your A ger e Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Agere Systems Inc., 555 Union Bo ulev ar d, Room 30L- 15P-BA, Allent own, PA 18109-3286
1-800-372-2447, FAX 610-712- 4106 (In CANADA: 1-800-553-2448, F A X 610- 712- 4106)
ASIA P ACIFIC: Agere Systems Singapore Pte . Lt d., 77 Science Par k Dr iv e, #03-18 Cint ec h III, Sing apor e 118256
Tel. (65) 778 88 33, FA X ( 65) 777 7495
CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Bou lev ar d P udong, S hanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN : Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, S hinagawa-ku, Tokyo 141, Japa n
Tel. (81) 3 5421 16 00, FA X ( 81) 3 5421 1700
EUROP E : Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technic al Inquiries: GE RM AN Y: (49) 89 95086 0 ( M unic h) , UNITED K ING DOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND : (358) 9 3507670 (Helsinki),
ITALY: (39) 02 66081 31 ( Mi lan) , SPAIN: (34) 1 807 1441 (Madrid)
