R5105N Series
Compact Watchdog Timer with VD
No.EK-159-091101 CMOS Microprocessor Supervisory
The R5105N Series are CMOS-b ased s ystem pow er ICs with a voltage detector (VD) and watchdog timer (WDT ) integrated in a single
chip. R5105N monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset
signal when a malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted high
accuracy with an external capacitor.
FEATURES
• Supply Current (ISS)························Typ. 11μA (VDD=-VDET+0.5V,
Clock pulse input)
• Operating Voltage Range (VDD)······0.9V to 6.0V
(VD Section)
•
Detector Th res hol d Range (-V
DET
)
···1.5V to 5.5V (internally fixed)
•
Detector Threshold Accuracy
··········± 1%
•
Temp. coeff. of Detector Threshold
···Typ. ± 100ppm/°C
• Output Delay Time (tPLH)·················Typ. 370ms (CD=0.1μF)
• Output Delay Time Accuracy··········± 16% (-40°C
<
=
Topt
<
=
105°C)
(WDT Section)
• Watchdog Timeout Period (tWD)······ Typ. 310ms (CTW=0.1μF)
• Reset Hold Time of WDT (tWR) ······· Typ. 34ms (CTW=0.1μF)
•
W atchdog Timeout Period Accuracy
····± 33% (-40°C
<
=
Topt
<
=
105°C)
• Package·········································SOT-23-6
(The above shows specification at Topt=25°C. Design assurance value at -40°C
<
=
Topt
<
=
105°C is also available. For details, please refer to the datasheet.)
BLOCK DIAGRAMS
TYPICAL APPLICATION
R5105Nxx1A
(Nch. open drain output)
VDD
GND
SCK
RESETB
CD
CTW
WATCHDOG
TIMER CLOCK
DETECTOR
3
6
2
4
5
1
Vref2 Vref1
R5105Nxx1C
(CMOS output)
VDD
GND
SCK
RESETB
CD
CTW
3
6
2
4
5
1
WATCHDOG
TIMER CLOCK
DETECTOR
Vre
f
2Vref1
CD
VDD
RESET
I/O
R
CTW
GND
VDD
CD
RESETB
SCK
CTW
3
6 5 2
4
1
Microprocessor
R5105Nxx1A
Series
Power Sup ply
SELECTION GUIDE
Package Quantity per Reel Part No.
SOT-23-6 3,000 pcs R5105N
.
xx
.
1
.
∗
-TR-F
.
xx
.
: S pecify the detector threshold within the range 1.5V (
.
15
.
)
to 5.5V
(
.
55
.
)
in 0.1V steps.
.
∗
: Select the output type from (
.
A
.
) Nch. open drain or (
.
C
.
) CMOS.
PACKAGE (Top View) TIMING CHART
SOT-23-6
6 5 4
1 2 3
1 SCK Watchdog timer clock input pin
2 CTW Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
3 VDD Power supply pin
4 RESETB Output pin for Reset "L" signal
5 GND Ground pin
6 CD Ext. Cap. pin for setting output
delay time of VD
APPLICATION
• Monitoring of the power system of devices equipped with microprocessors
-VDET
+VDET
V
RESETB
tWR
V
CTW
V
SCK
V
DD
Vref2H
Vref2L
tPLH
V
CD
tPHL tPHL
tPLH
tWDItWD
-VTCD
+VTCD
∗tPHL : Output delay time
∗tWDI : tWD/10 (SCK pulses input during this period are ignored.)
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