CAT34WC02JATE13 - Catalyst Semiconductor, Inc.

PIN FUNCTIONS

Pin Name Function

A0, A1, A2 Device Address Inputs

SDA Serial Data/Address

SCL Serial Clock

WP Write Protect

VCC 1.7 V to 5.5 V Power Supply

VSS Ground

CAT34WC02

2-kb I2C Serial EEPROM, Serial Presence Detect

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

PIN CONFIGURATION BLOCK DIAGRAM

DIP Package (P, L)

24CXX F03

TSSOP Package (U, Y)

SOIC Package (J, W)

FEATURES

■400 kHz (5 V) and 100 kHz (1.7 V) I2C bus

compatible

■1.7 to 5.5 volt operation

■Low power CMOS technology

– zero standby current

■16-byte page write buffer

■Industrial and automotive temperature ranges

■Self-timed write cycle with auto-clear

■Software write protection for lower 128 bytes

■1,000,000 program/erase cycles

■100 year data retention

■8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages

- “Green” package option available

■256 x 8 memory organization

■Hardware write protect

DESCRIPTION

The CAT34WC02 is a 2-kb Serial CMOS EEPROM

internally organized as 256 words of 8 bits each. Catalyst’s

advanced CMOS technology substantially reduces

device power requirements. The CAT34WC02 features

a 16-byte page write buffer. The device operates via the

I2C bus serial interface and is available in 8-pin DIP,

8-pin SOIC or 8-pin TSSOP packages.

Characteristics subject to change without notice Doc No. 1003, Rev. I

DOUT

ACK

SENSE AMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

STATE COUNTERS

SLAVE

ADDRESS

COMPARATORS

E2PROM

VCC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGH V OL TA GE/

TIMING CONTROL

VSS

SCL

SDA

VSS

A0VCC

SCL

SDA

VSS

VCC

SCL

SDA

VCC

SCL

SDA

VSS

CAT34WC02

Doc. No. 1003, Rev. I

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5.0 V

Symbol Test Conditions Min Typ Max Units

CI/O(3) Input/Output Capacitance (SDA) VI/O = 0 V 8 pF

CIN(3) Input Capacitance (A0, A1, A2, SCL) VIN = 0 V 6 pF

RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Typ Max Units

NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(3)(4) Latch-up JEDEC Standard 17 100 mA

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground(1) ............–2.0 V to VCC + 2.0 V

VCC with Respect to Ground ............. –2.0 V to +7.0 V

Package Power Dissipation

Capability (Ta = 25°C).................................. 1.0 W

Lead Soldering Temperature (10 seconds)...... 300 °C

Output Short Circuit Current(2) ....................... 100 mA

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Note:

(1) The minimum DC input voltage is - 0.5 V. During transitions, inputs may undershoot to - 2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC + 1 V.

(5) Standby Current, ISB = 0 µA (<900 nA).

D.C. OPERATING CHARACTERISTICS

VCC = + 1.7 V to + 5.5 V, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

ICC Power Supply Current (Read) fSCL = 100 kHz 1 mA

ICC Power Supply Current (Write) fSCL = 100 kHz 3 mA

ISB(5) Standby Current (VCC = 5.0 V) VIN = GND or VCC 0µA

ILI Input Leakage Current VIN = GND to VCC 1µA

ILO Output Leakage Current VOUT = GND to VCC 1µA

VIL Input Low Voltage –1 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 1.0 V

VOL1 Output Low Voltage (VCC = 3.0 V) IOL = 3 mA 0.4 V

VOL2 Output Low Voltage (VCC = 1.7 V) IOL = 1.5 mA 0.5 V

CAT34WC02

3Doc No. 1003, Rev. I

Write Cycle Limits

Symbol Parameter Min Typ Max Units

tWR Write Cycle Time 4 10 ms

A.C. CHARACTERISTICS

VCC = 1.7 V to 5.5 V, unless otherwise specified.

Read & Write Cycle Limits

Symbol Parameter 1.7 V 4.5 V - 5.5 V

Min Max Min Max Units

FSCL Clock Frequency 100 400 kHz

TI(1) Noise Suppression Time 200 200 ns

Constant at SCL, SDA Inputs

tAA SCL Low to SDA Data Out 3.5 1 µs

and ACK Out

tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start

tHD:STA Start Condition Hold Time 4 0.6 µs

tLOW Clock Low Period 4.7 1.2 µs

tHIGH Clock High Period 4 0.6 µs

tSU:STA Start Condition Setup Time 4.7 0.6 µs

(for a Repeated Start Condition)

tHD:DAT Data In Hold Time 0 0 ns

tSU:DAT Data In Setup Time 50 50 ns

tR(1) SDA and SCL Rise Time 1 0.3 µs

tF(1) SDA and SCL Fall Time 300 300 ns

tSU:STO Stop Condition Setup Time 4 0.6 µs

tDH Data Out Hold Time 100 100 ns

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Power-Up Timing(1)(2)

Symbol Parameter Min Typ Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

CAT34WC02

Doc. No. 1003, Rev. I

FUNCTIONAL DESCRIPTION

The CAT34WC02 supports the I2C Bus data transmis-

sion protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a re-

ceiver. Data transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT34WC02

operates as a Slave device. Both the Master and Slave

devices can operate as either transmitter or receiver, but

the Master device controls which mode is activated. A

maximum of 8 devices may be connected to the bus as

determined by the device address inputs A0, A1, and A2.

PIN DESCRIPTIONS

SCL: Serial Clock

The CAT34WC02 serial clock input pin is used to clock

all data transfers into or out of the device. This is an input

pin.

SDA: Serial Data/Address

The CAT34WC02 bidirectional serial data/address pin

is used to transfer data into and out of the device. The

SDA pin is an open drain output and can be wire-ORed

with other open drain or open collector outputs.

A0, A1, A2: Device Address Inputs

These inputs set device address when cascading mul-

tiple devices. A maximum of eight devices can be

cascaded when using the device.

WP: Write Protect

This input, when tied to GND, allows write operations to

the entire memory. For CAT34WC02 when this pin is

tied to VCC, the entire array of memory is write protected.

When left floating, memory is unprotected.

START BIT

SDA

STOP BIT

SCL

5020 FHD F05

Figure 3. Start/Stop Timing

5020 FHD F04

Figure 2. Write Cycle Timing

tWR

STOP

CONDITION START

CONDITION ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tFtLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

5020 FHD F03

Figure 1. Bus Timing

CAT34WC02

5Doc No. 1003, Rev. I

I2C BUS PROTOCOL

The following defines the features of the I2C bus proto-

col:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT34WC02 monitor the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master then sends the address of the

particular slave device it is requesting. The four most

significant bits of the 8-bit slave address are fixed

(except when accessing the Write Protect Register) as

1010 for the CAT34WC02 (see Fig. 5). The next three

significant bits (A2, A1, A0) are the device address bits

and define which device the Master is accessing. Up to

eight CAT34WC02 may be individually addressed by

the system. The last bit of the slave address specifies

whether a Read or Write operation is to be performed.

When this bit is set to 1, a Read operation is selected,

and when set to 0, a Write operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT34WC02 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT34WC02 then performs a Read or a Write operation

depending on the state of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledg-

ing device pulls down the SDA line during the ninth clock

cycle, signaling that it received the 8 bits of data.

The CAT34WC02 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation,

it responds with an acknowledge after receiving each

byte.

When the CAT34WC02 begins a READ mode, it trans-

mits 8 bits of data, releases the SDA line, and monitors

the line for an acknowledge. Once it receives this ac-

knowledge, the CAT34WC02 will continue to transmit

data. If no acknowledge is sent by the Master, the device

terminates data transmission and waits for a STOP

condition.

34WC02 F07

Figure 4. Acknowledge Timing

Figure 5. Slave Address Bits

5020 FHD F06

ACKNOWLEDGE

START

SCL FROM

MASTER 89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

DEVICE ADDRESS

0 1 0 A2 A1 A0 R/W

01 1 0 A2 A1 A0 R/W

Normal Read and Write

Programming the Write

Protect Register

CAT34WC02

Doc. No. 1003, Rev. I

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

the byte address that is to be written into the address

pointer of the CAT34WC02. After receiving another

acknowledge from the Slave, the Master device trans-

mits the data byte to be written into the addressed

memory location. The CAT34WC02 acknowledges once

more and the Master generates the STOP condition, at

which time the device begins its internal programming to

nonvolatile memory. While this internal cycle is in

progress, the device will not respond to any request from

the Master device.

Page Write

The CAT34WC02 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The Page

Write operation is initiated in the same manner as the

Byte Write operation, however instead of terminating

after the initial word is transmitted, the Master is allowed

to send up to 15 additional bytes. After each byte has

been transmitted the CAT34WC02 will respond with an

acknowledge, and internally increment the low order

address bits by one. The high order bits remain un-

changed.

If the Master transmits more than 16 bytes prior to

sending the STOP condition, the address counter ‘wraps

around’, and previously transmitted data will be overwrit-

ten.

Once all 16 bytes are received and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point all received data is written to

the CAT34WC02 in a single write cycle.

Acknowledge Polling

The disabling of the inputs can be used to take advan-

tage of the typical write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation, the CAT34WC02 initiates the internal write

cycle. ACK polling can be initiated immediately. This

involves issuing the start condition followed by the slave

address for a write operation. If the CAT34WC02 is still

busy with the write operation, no ACK will be returned.

If the CAT34WC02 has completed the write operation,

an ACK will be returned and the host can then proceed

with the next read or write operation.

WRITE PROTECTION

The CAT34WC02 is designed with a hardware protect

pin that enables the user to protect the entire memory.

The CAT34WC02 also has a software write protection

feature. By programming the software write protection

software and hardware protection features of the

CAT34WC02 are designed into the part to provide

added flexibility to the design engineers.

Hardware

The write protection feature of CAT34WC02 allows the

user to protect against inadvertent programming of the

memory array. If the WP pin is tied to Vcc, the entire

5020 FHD F09

Figure 7. Page Write Timing

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS ACTIVITY :

MASTER

SDA LINE

5020 FHD F08

BUS A CTIVITY :

MASTER

SDA LINE

DATA n+P

BYTE

ADDRESS (n)

DATA n

DATA n+1

SLAVE

ADDRESS

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

Figure 6. Byte Write Timing

CAT34WC02

7Doc No. 1003, Rev. I

memory array is protected and becomes read only. The

entire memory becomes write protected regardless of

whether the write protect register has been written or

not. When WP pin is tied to Vcc, the user cannot program

the write protect register. If the WP pin is left floating or

tied to Vss, the device can be written into (except the first

128 bytes if the write protect register is programmed).

Software

The software protection on the CAT34WC02 protects

the first 128 bytes of the memory array permanently.

Software write protect is implemented by programming

the write protect register. A user can write only once to

the write protect register and once written it is irrevers-

ible (even if you reset the CAT34WC02).

The write protection register is written by sending a

regular byte write command with the slave address set

to 0110 instead of 1010. After the initial access to the

access to this register.

READ OPERATIONS

The READ operation for the CAT34WC02 is initiated in

the same manner as the write operation with the one

exception that the R/W bit is set to a one. Three different

READ operations are possible: Immediate Address

READ, Selective READ and Sequential READ.

Immediate Address Read

The CAT34WC02’s address counter contains the ad-

dress of the last byte accessed, incremented by one. In

other words, if the last READ or WRITE access was to

address N, the READ immediately following would ac-

cess data from address N + 1. If N = 255 for 34WC02,

then the counter will ‘wrap around’ to address 0 and

continue to clock out data. After the CAT34WC02 re-

ceives its slave address information (with the R/W bit set

to one), it issues an acknowledge, then transmits the 8-

bit byte requested. The master device does not send an

acknowledge but will generate a STOP condition.

Selective Read

Selective READ operations allow the Master device to

select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte address of the location it wishes to

read. After the CAT34WC02 acknowledge the word

address, the Master device resends the START condi-

tion and the slave address, this time with the R/W bit set

to one. The CAT34WC02 then responds with its ac-

knowledge and sends the 8-bit byte requested. The

master device does not send an acknowledge but will

generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT34WC02 sends the initial 8-bit

data requested, the Master will respond with an ac-

knowledge which tells the device it requires more data.

The CAT34WC02 will continue to output a byte for each

acknowledge sent by the Master. The operation will

terminate operation when the Master fails to respond

with an acknowledge, thus sending the STOP condition.

The data being transmitted from the CAT34WC02 is

outputted sequentially with data from address N fol-

lowed by data from address N + 1. The READ operation

address counter increments all of the CAT34WC02

address bits so that the entire memory array can be read

during one operation. If more than the 256 bytes are read

out, the counter will “wrap around” and continue to clock

out data bytes.

5020 FHD F10

Figure 8. Immediate Address Read Timing

SLAVE

ADDRESS

KDATA N

BUS ACTIVITY :

MASTER

SDA LINE

SCL

SDA 8TH BIT

STOPNO ACKDATA OUT

CAT34WC02

Doc. No. 1003, Rev. I

Figure 11. Selective Read Timing

Figure 12. Sequential Read Timing

5020 FHD F12

5020 FHD F11

Figure 10. Software Write Protect

Figure 9. Memory Array

Software Write Protectable

(by programming the write

protect register)

FFH

00H

7FH

Hardware Write Protectable

(by connecting WP pin to

Vcc)

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS A CTIVITY :

MASTER

SDA LINE

XXXXXXX XXXXXXX

X = Don't Care

SLAVE

ADDRESS

BUS A CTIVITY :

MASTER

SDA LINE

BYTE

ADDRESS (n)

KDATA n

SLAVE

ADDRESS

BUS A CTIVITY :

MASTER

SDA LINE

DATA n+xDATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

CAT34WC02

9Doc No. 1003, Rev. I

ORDERING INFORMATION

Notes:

(1) The device used in the above example is a 34WC02JI-TE13 (SOIC, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating

Voltage, Tape & Reel)

Prefix Device # Suffix

34WC02 JITE13

Product

Number Tape & Reel

TE13: 2000/Reel

Package

P: PDIP

J: SOIC (JEDEC)

U: TSSOP

Operating V oltage

Blank: 1.7 V - 5.5 V

CAT

Temperature Range

I = Industrial (-40˚C to +85˚C)

A = Automotive (-40˚ - 105˚C)*

* -40˚ to +125˚C is available upon request

Optional

Company ID

L: PDIP (Lead free, Halogen free)

W: SOIC (JEDEC), (Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

CAT34WC02

Doc. No. 1003, Rev. I

REVISION HISTORY

Date Rev. Reason

9/22/2003 H Eliminated commercial temperature range

Updated marking

12/9/2003 I Changed Industrial Temp to “I” from “Blank” in ordering information

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Publication #: 1003

Revison: I

Issue date: 12/9/03

Type: Final

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