LTC4420
1
4420fa
For more information www.linear.com/LTC4420
TYPICAL APPLICATION
FEATURES DESCRIPTION
18V Dual Input Micropower
PowerPath Prioritizer with
Backup Supply Monitoring
The LT C
®
4420 is a dual input monolithic PowerPath™
prioritizer, with low operating current, that provides
backup switchover for keeping critical circuitry alive dur-
ing brownout and power loss conditions. Unlike diode-OR
products, little current is drawn from the inactive supply
even if its voltage is greater than the active supply.
Internal 2Ω, current limited PMOS switches provide
power path selection from a primary input (V1) or a backup
input (V2) to the output. Tw o adjustable voltage monitors
set via external resistive dividers provide flexibility in set-
ting V1 to V2 switchover and V2 undervoltage thresholds.
V1 is monitored continuously while V2 supply monitoring
includes controllable low duty cycle UV monitoring. When
primary input V1 drops, the ADJ monitor causes OUT to
be switched to V2. When V2 drops, it is disconnected from
OUT if V2DIS is low. Fast non-overlap switchover circuitry
prevents reverse and cross conduction while minimizing
output droop.
Auxiliary voltage monitor CMP1 provides flexible voltage
monitoring and output V2OK provides V2 undervoltage
status. Freshness seal mode prevents V2 battery discharge
during storage or shipment.
APPLICATIONS
n Selects Highest Priority Valid Supply from Tw o
Inputs
n Wide 1.8V to 18V Operating Range
n Internal Dual 2Ω, 0.5A Switches
n Low 3.6µA Operating Current
n Low 320nA V2 Current When V1 Connected to OUT
n Blocks Reverse and Cross Conduction Currents
n Reverse Supply Protection to –15V
n Built-In V2 Test with Optional V2 Disconnect
n V2 Freshness Seal/Ship Mode
n ±1.5% Accurate Adjustable Switchover Threshold
n ±2.3% Accurate V2 Monitor and Comparator
n Overcurrent and Thermal Protection
n Thermally Enhanced 12-Pin 3mm × 3mm
DFN and 12-Lead Exposed Pad MSOP Packages
n Low Power Battery Backup
n Portable Equipment
n Point-of-Sale (POS) Equipment
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners.
Typical Switchover Waveforms
SWITCHOVER
THRESHOLD
COUT = 10µF
ILOAD = 100mA
V2 MONITORING
INTERVAL
V2 UNDERVOLTAGE
AND DISCONNECT
OUT
20ms/DIV
V1
4420 TA01b
+
V1
ADJ V1UV
V2OK
TYPICAL VALUES:
SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
CMP1
V2
V2UV
GNDSW
1M 1M 1M
OUT
237k
121k
OUT
5V WALL
ADAPTER
CMPOUT1
V2OK
V2DIS
V2TEST
LTC4420
GND 4420 TA01a
4.02M
V1UV
THRESHOLD: V1 < 4.4V (V1 FALLING)
V2OK THRESHOLD: V2 < 6V (V2 FALLING)
7.4V
Li-Ion
280k
10µF
LTC4420
2
4420fa
For more information www.linear.com/LTC4420
ABSOLUTE MAXIMUM RATINGS
Terminal Voltages
V1, V2 ......................................................–15V to 24V
OUT ....................................................... –0.3V to 24V
OUT – V2 .................................................–24V to 39V
OUT – V1 .................................................–24V to 39V
Input Voltages
ADJ, CMP1, V2UV, V2TEST, V2DIS
(Note 3) ................................................ –0.3V to 24V
Output Voltages
CMPOUT1, GNDSW, V2OK (Note 3) ...... –0.3V to 24V
(Notes 1, 2)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4420CDD#PBF LTC4420CDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4420IDD#PBF LTC4420IDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4420CMSE#PBF LTC4420CMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP 0°C to 70°C
LTC4420IMSE#PBF LTC4420IMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted.
TOP VIEW
13
GND
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
12
11
8
9
10
4
5
3
2
1V2
V2DIS
V2UV
OUT
V2OK
GNDSW
V1
V2TEST
CMP1
ADJ
GND
CMPOUT1 67
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
V1
V2TEST
CMP1
ADJ
GND
CMPOUT1
12
11
10
9
8
7
V2
V2DIS
V2UV
OUT
V2OK
GNDSW
TOP VIEW
13
GND
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
Pin Currents (Note 2)
ADJ, CMP1, V2UV, CMPOUT1, GNDSW .............–1mA
V2TEST, V2DIS, V2OK ......................................–1mA
Operating Ambient Temperature Range
LTC4420C ................................................ 0°C to 70°C
LTC4420I .............................................–40°C to 85°C
Junction Temperature (Notes 4, 5) ........................ 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP Package ................................................. 300°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage and Currents
V1, V2 Operating Voltage Range l1.8 18 V
IV1 V1 Current, V1 Powering OUT
V1 Current, V2 Powering OUT
IOUT = 0, V1 = 8.4V, V2 = 3.6V
V1 = 8.4V, V2 = 3.6V
l
l
3.6
500
6.3
800
µA
nA
ORDER INFORMATION
http://www.linear.com/product/LTC4420#orderinfo
LTC4420
3
4420fa
For more information www.linear.com/LTC4420
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: These pins can be tied to voltages down to –5V through a resistor
that limits the current to less than –1mA.
Note 4: The LTC4420 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC4420 is tested under pulsed load conditions such that
TJ ≈ TA. The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) according to
the formula:
TJ = TA + (PD • θJA)
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IV2 V2 Current, V2 Powering OUT
V2 Current, V1 Powering OUT
V2 Current in Freshness Seal Mode
IOUT = 0, V1 = 3.6V, V2 = 8.4V
V1 = 3.6V, V2 = 8.4V
V1 = GND, V2 = 5V
l
l
l
3.3
320
120
6
650
220
µA
nA
nA
RON Switch Resistance V1 = V2 = 5V, IOUT = –100mA l1 2 5 Ω
tVALID(V1) Input Qualification Time V1 Rising, ADJ Rising l 34 64 94 ms
Input Comparators
VTHA ADJ Threshold ADJ Falling l1.032 1.047 1.062 V
VHYSTA ADJ Comparator Hysteresis ADJ Rising l30 50 70 mV
VTHC CMP1, V2UV Threshold CMP1, V2UV Falling l0.378 0.387 0.396 V
VHYSTC CMP1, V2UV Comparator Hysteresis CMP1, V2UV Rising l7.5 10 12.5 mV
tPDA ADJ Comparator Falling Response Time 10% Overdrive l4 7.3 12 µs
tPDC CMP1, V2UV Comparator Response Times 20% Overdrive l30 65 µs
Power Path Function
ILIM Output Current Limit V1, V2 = 8.4V l 0.5 1.1 1.6 A
VREV Reverse Comparator Threshold (V1, V2) – VOUT for Power Path Turn-On l25 50 75 mV
tSWITCH Break-Before-Make Switchover Time V1 = V2 = 5V, IOUT = –100mA l1 2.5 5 µs
V2 Monitoring
tMONL Longest Possible V2UV Monitor Duration V2TEST ≥ VIH l 88 128 168 ms
tMONS Shortest Possible V2UV Monitor Duration V2TEST ≥ VIH l 1 2 3 ms
tLTEST Time Between V2UV Monitoring Events V2TEST ≥ VIH l 80 132 180 s
tHV2T Minimum Allowed V2TEST High Time V2TEST Driven Externally l10 ms
tLV2T Minimum Allowed V2TEST Low Time V2TEST Driven Externally l10 ms
I/O Specifications
VOL Output Voltage Low, CMPOUT1, GNDSW and V2OK I = 100µA
I = 1mA
l
l
15
120
50
250
mV
mV
VOH V2OK Output High Voltage I = –1µA, V2 = 5V l1.05 1.65 2.3 V
IOH V2OK, GNDSW, CMPOUT1 Output High Leakage CMPOUT1, GNDSW, V2OK = 18V l±50 ±150 nA
VIL V2DIS, V2TEST Input Low Voltage V1 = V2 = 5V l0.2 V
VIH V2DIS, V2TEST Input High Voltage V1 = V2 = 5V l0.9 V
IV2X(IN,Z) V2DIS, V2TEST Allowable Leakage in Open State l0.5 µA
IPU(V2OK) V2OK Pull-Up Current V2 = 5V, ADJ = 0V, V2OK = 0V l–2.7 –5 –8 µA
ILEAK ADJ, CMP1, V2UV Leakage Current ADJ, CMP1, V2UV = 0V, 1.5V l±1 ±5 nA
LTC4420
4
4420fa
For more information www.linear.com/LTC4420
TYPICAL PERFORMANCE CHARACTERISTICS
V1 Current, V1 Powers OUT
(IOUT = 0)
V2 Current, V2 Powers OUT
(IOUT = 0) V2 Current, V1 Powers Out
(TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated)
V1 Current, V2 Powers Out
Normalized Falling ADJ
Threshold vs Temperature
Normalized CMP1 and
V2UV Falling Thresholds vs
Temperature
ADJ Hysteresis vs Temperature ADJ Leakage vs Temperature
Open-Drain (CMPOUT1, GNDSW,
V2OK) VOL vs Pull-Down Current
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.990
0.995
1.000
1.005
1.010
NORMALIZED V
THC
4420 G06
V1 = 1.8V
V1 = 3.6V
V1 ≥ 6V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.5
3.0
3.5
4.0
4.5
V1 CURRENT (µA)
4420 G01
V1 = V2
–40°C
25°C
90°C
V2 VOLTAGE (V)
0
5
10
15
20
150
200
250
300
350
400
450
V2 CURRENT (nA)
4420 G03
V1 = V2
–40°C
25°C
90°C
V2 VOLTAGE (V)
0
5
10
15
20
300
350
400
450
500
550
4420 G04
V1 CURRENT (nA)
PULL-DOWN CURRENT (mA)
0
0.5
1
1.5
2
0
50
100
150
200
250
V
OL
(mV)
4420 G05
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.990
0.995
1.000
1.005
1.010
NORMALIZED V
THA
4420 G07
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
30
40
50
60
70
ADJ HYSTERESIS (mV)
4420 G08
V
ADJ
= 0V, 1.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.5
1.0
1.5
2.0
2.5
3.0
ADJ LEAKAGE (nA)
4420 G09
V2 = 1.8V
V2 = 3.6V
V2 ≥ 6V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.5
3.0
3.5
4.0
V2 CURRENT (µA)
4420 G02
LTC4420
5
4420fa
For more information www.linear.com/LTC4420
V1 Reverse Voltage Blocking
with V2 Powering Out
TYPICAL PERFORMANCE CHARACTERISTICS
Switch RON vs Temperature
IOUT vs VOUT for Different Input
Supply VoltagesOutput Current Limit vs Temperature
Switchover from a Higher to a
Lower Voltage
Freshness Seal Current vs
V2 Voltage and Temperature
Output Voltage and Current
Waveforms During Switchover
Output Current IOUT Response for
Different Shorting Impedances
(TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated)
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.80
0.90
1.00
1.10
1.20
1.30
1.40
CURRENT LIMIT (A)
4420 G10
OHMIC
CURRENT
LIMIT
FOLDBACK
VIN = 1.8V
VIN = 3.6V
VIN = 5V
V
OUT
(V)
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1.0
1.2
I
OUT
(A)
4419 G12
5V
3.6V
2V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1
2
3
4
5
R
ON
(Ω)
4419 G13
V1 = 0V
1.8V
3.6V
5V
≥6V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
0
50
100
150
200
250
V2 CURRENT (nA)
4420 G14
COUT = 10µF
IOUT = 200mA
DISCONNECT FROM V1
CONNECT TO V2
3ms/DIV
V1
OUT
2V/DIV
V2
4419 G15
C
OUT
= 10µF
I
LOAD
= 50mA
C1= C2 = 10µF
OUT
10V
6V
10µs/DIV
V2
I
OUT
0.5A/DIV
V1
4420 G16
ILOAD = 50mA
6V
–10V
10V
20ms/DIV
V2
V1
10V/DIV
I
OUT
0.5A/DIV
4420 G17
1.2Ω
2.2Ω
3.3Ω
3.9Ω
5Ω
40µs/DIV
0
0.5
1.0
1.5
2.0
2.5
3.0
IOUT (A)
4419 G11
LTC4420
6
4420fa
For more information www.linear.com/LTC4420
PIN FUNCTIONS
ADJ: Adjustable Switchover Threshold Input. ADJ is the
noninverting input to the switchover threshold comparator.
If V1 ≥ 1.55V and ADJ ≥ 1.097V for at least 64ms, OUT
is switched internally to the primary V1 input. When the
ADJ input voltage is lower than 1.047V, OUT is switched
internally to V2 if conditions in Table 1 of the Applica-
tions Information section are met. Otherwise, OUT stays
unpowered. Tie ADJ via a resistive divider to V1, in order
to set the V1 to V2 switchover voltage. Do not leave open.
CMP1: Auxiliary Comparator 1 Monitor Input . CMP1 is the
noninverting input to an auxiliary comparator. The invert-
ing input is internally connected to a 0.387V reference.
Connect CMP1 to GND when it is not used.
CMPOUT1: Auxiliary Comparator Output 1. This open-drain
comparator output is pulled low when CMP1 is below
0.387V and during power-up, otherwise it is released.
Once released, connecting a resistor between CMPOUT1
and a desired supply voltage up to 18V causes this pin to
be pulled high. Leave open if unused.
GNDSW: Pulsed GND Output. This open-drain output is
pulled low when V2UV is being monitored, otherwise it
is released high. Connect a resistive divider between V2,
V2UV and GNDSW to set V2 undervoltage threshold.
Leave open if unused.
Exposed Pad: The exposed pad is ground and must be
soldered to the PCB ground plane.
GND: Device Ground.
OUT: Output Voltage Supply. OUT is a prioritized voltage
output that is either connected to V1, V2 or is unpowered
as indicated in Table 1 of the Applications Information sec-
tion. Additionally, OUT must be at least 50mV below the
input supply for a connection to that supply to be activated.
Bypass with a capacitor of 1µF or greater. See Applica-
tions Information for bypass capacitor recommendations.
V1: Primary Power Supply. OUT is internally switched to
V1 if V1 ≥ 1.55V and ADJ ≥ 1.097V. When in freshness
seal, applying V1 ≥ 1.55V and ADJ ≥ 1.097V for 32ms
disables freshness seal. Bypass with 1µF or greater. Tie
to GND if unused.
V2: Backup Power Supply. OUT is internally switched to
V2 if ADJ < 1.047V or V1 < 1.55V, provided other condi-
tions listed in Table 1 in Applications Information are met.
Bypass with 1µF or greater. Tie to GND if unused.
V2DIS: V2 Power Path Disable Input. When driven low,
this pin disables the V2 to OUT power path if input V2UV
drops below 0.387V. Connect a resistor between V2 or
OUT and this pin to provide additional pull-up. Leave open
if unused. This pin is initialized high during power-up.
V2OK: V2OK Logic Output. V2OK is an output that is driven
high with a 5µA pull-up if V2UV > 0.387V at the end of
the V2UV monitoring period. Otherwise it is driven low.
Connect a resistor between OUT and this pin to provide
additional pull-up. As this pin is used to enable freshness
seal, do not force low or connect a pull-down resistor to
this pin. Leave open if unused.
V2TEST: V2 Undervoltage Test Enable Input. This pin sets
the duty cycle of V2 undervoltage monitoring. When V1
is valid, driving V2TEST low disables V2 monitoring while
driving it high enables V2 monitoring with a maximum
duty cycle of ~0.1%. When V1 is invalid or not present,
V2 is always monitored with V2TEST setting the duty
cycle between 0.0015% and 0.1% depending on its own
state and previously determined V2 validity. Refer to the
state diagram and waveforms in the Applications Informa-
tion section for details. Leave open or connect a resistor
between V2 or OUT and this pin to provide additional
pull-up. Connect to GND if unused. This pin is initialized
high on power-up.
V2UV: V2 Undervoltage Monitor Input. V2UV is the non-
inverting input to a comparator whose inverting input is
internally connected to a 0.387V reference. Connect a
resistive divider between V2, V2UV and GNDSW to set V2
undervoltage threshold. See the Applications Information
section for details on V2 monitoring. Connect a pull-up
resistor to V2 if unused. Do not leave open.
LTC4420
7
4420fa
For more information www.linear.com/LTC4420
FUNCTIONAL DIAGRAM
+
–
+
–
+
–
+–
0.397V/
0.387V
CP1
CMP1
V2
V1
EN1
CUV1
CUV2
1.55V/
1.52V
EN2
50mV
CREV2
5µA
2.5V
OUT
CMPOUT1
V2OK
CONTROL LOGIC
GNDSW
EN_GNDSW
+
–
+–
50mV
CREV1
+
–
6
3
1
12
9
8
7
FRESHNESS
SEAL
+
–
1.097V/
1.047V
1M
CADJ 64ms
7.3µs
ADJ
4
+
–
0.397V/
0.387V
CV2UV
V2UV
10
V2DIS
11
1M
V2TEST
2
GND
5
D Q
E
4420 BD
LTC4420
8
4420fa
For more information www.linear.com/LTC4420
OPERATION
The Functional Diagram shows the major blocks of the
LTC4420. The LTC4420 is a PowerPath prioritizer that
switches output OUT between primary (V1) and backup
(V2) sources depending on their validity and priority with
V1 having the highest priority. A resistive divider between
V1, ADJ and GND and comparators CUV1 and CADJ are
used to monitor V1’s voltage to establish validity. V1 is
valid if V1 ≥ 1.55V and ADJ ≥ 1.097V for 64ms after V1
rises above 1.55V. Otherwise V1 is invalid. A resistive
divider between V2, V2UV and GNDSW and comparators
CUV2 and CV2UV are used to monitor V2’s voltage to
establish validity. V2 voltage is monitored periodically in
order to minimize current consumption in the divider. V2
is valid if V2 ≥ 1.55V and V2UV ≥ 0.4V at the end of the
V2 monitoring period. Otherwise it is invalid. If neither
supply is valid, OUT stays unpowered if V2DIS is low. If
V2DIS is high and V2 > 1.55V, OUT is connected to V2.
Refer to Table 1 in the Applications Information section
for details. Switchover threshold is independent of relative
V1 and V2 voltages, permitting V1 to be lower or higher
than V2 when V1 powers OUT and vice versa.
Power connection to the output is made by enhancing back-
to-back internal P-channel MOSFETs. Current passed by
the MOSFETs is limited to typically 1.1A if OUT is greater
than 1V. Otherwise it is limited to 250mA. When switching
from V1 to V2, the V1 to OUT power path is first disabled
and comparator CREV2 is enabled. After the OUT voltage
drops 50mV below V2, as detected by CREV2, OUT is
then connected to V2. This break-before-make strategy
prevents OUT from backfeeding V2. Switchover back to V1
occurs in a similar manner once V1 has been revalidated.
The LTC4420 blocks reverse voltages up to –15V when
a reverse condition occurs on an inactive channel. The
LTC4420 also disables a channel if the corresponding
input supply falls below 1.52V. A small ~3µA current is
drawn from either the prioritized input supply, or the high-
est supply if both input supplies are below 1.55V. Very
little current (~320nA) is drawn from the unused supply.
Pins V2TEST and V2DIS provide flexibility in monitoring
and disconnecting the V2 power path using the V2UV
monitor input. V2 is monitored by activating the V2-V2UV-
GNDSW resistive divider. V2TEST allows for adjustability
of GNDSW duty cycle to trade off V2 quiescent current with
V2 monitoring frequency. When low, V2DIS disables the
V2 to OUT power path, if V2 is found to be invalid. Refer
to the Applications Information section for details. If V2 is
valid at the end of a V2 monitoring interval, output V2OK
is latched high. Otherwise it is latched low. V2OK retains
its state until the end of the next V2 monitoring interval
when it gets updated. V2 monitoring is disabled if V2 <
1.55V or during thermal shutdown. During initial power-
up V2 monitoring is disabled and V2OK is initialized low.
The LTC4420 provides an additional comparator, CP1,
whose open-drain output pulls low either when the CMP1
pin voltage falls below 0.387V or during initial power up.
This comparator can be used to monitor supplies to provide
early power failure warning and other useful information.
The LTC4420 can be put into a V2 freshness seal mode
to prevent battery discharge during storage or shipment.
The Applications Information section lists the steps to
engage and disengage V2 freshness seal.
LTC4420
9
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For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
The LTC4420 is a low quiescent current 2-channel priori-
tizer that powers both its internal circuitry and its output
OUT from a prioritized valid input supply. Unlike an ideal
diode-OR, the LTC4420 does not necessarily draw current
from the highest supply as long as one supply is greater
than 1.8V. Table 1 lists the input supply from which the
LTC4420 draws its internal quiescent current ICC and the
supply to which OUT is connected after input supplies
have been qualified.
A typical battery backup application is shown in Figure 1.
V1 is powered by a 2-cell Li-Ion battery pack whose safe
discharge limit is between 5.6V and 6V. V2 is powered by
a low self discharge 7.6V Li-Thionyl Chloride (Li-SOCl2)
hold-up battery which is completely discharged when its
voltage drops to 6V. Li-SOCL2 battery life is maximized
as very little current is drawn from V2 during normal
operation due to the low duty cycle of V2 monitoring and
the LTC4420’s low V2 standby current. To protect the
2-cell Li-Ion battery on V1, switchover threshold is set
to be ~5.6V. After switchover to V2, the Li-Ion battery
primarily supplies only divider R1-R3’s current as the
LTC4420 draws only a small standby current from V1.
Monitor CMP1 is configured to provide V1 power failure
warning by driving V1UV low when V1 falls below 6V.
Monitor input V2UV is configured to set V2’s UV threshold
to 6V and V2DIS is tied low to disconnect the V2 to OUT
power path when V2 falls below 6V. V2TEST is tied high
to monitor V2 once every 132s. Relevant equations used
to calculate these component values are discussed in the
following subsections.
Figure 1. The LTC4420 Protecting 2-Cell Lithium Battery Packs
on V1 and V2 from Discharge Below Their Safe Minimum Voltage
Setting Switchover and V2 Undervoltage Thresholds
Several factors affect switchover voltage and should be
taken into account when calculating resistor values. These
include resistor tolerance, 1.5% ADJ comparator threshold
error, divider impedance and worst-case ADJ pin leakage.
These factors also apply to resistive dividers connected
to monitor inputs CMP1 and V2UV. Referring to Figure
1 and the Electrical Characteristics table, the typical V1
switchover threshold:
VSW1 =
V
THA
R1+R2
• R1+R2+R3
( )
(1)
Table 1. OUT and LTC4420 ICC Power
INPUT VOLTAGES
V1 > 1.55V ADJ > 1.097V V2 > 1.55V V2DIS > 0.9V V2UV > 0.397* ICC SOURCE OUT CONNECTION
Y†Y†X X X V1 V1
Y N Y Y X V2 V2
Y N Y N Y V2 V2
Y N Y N N V1 Hi-Z
Y N N X X V1 Hi-Z
N X Y N N V2 Hi-Z
N X Y N Y V2 V2
N X Y Y X V2 V2
N X N X X VMAX** Hi-Z
*Note: Refers to V2UV voltage at the end of the V2 monitoring period.
**Note: VMAX = higher of V1 and V2.
† For 64ms.
+
V1
ADJ
CMP1 V2UV
V1UV
V2
V2UV
GNDSW
4420 F01
R3
1M
V1UV: V1 < 6V (V1 FALLING)
V2UV: V2 < 6V (V2 FALLING)
R6
1M
R7
1M
R8
1M
COUT
10µF
R2
150k
R1
78.7k
OUT
OUT
V2TEST
V2OK
CMPOUT1
V2DIS
LTC4420
GND
R5
4.02M
SWITCHOVER
THRESHOLD: V1 < 5.6V (V1 FALLING)
+
2-CELL
Li-Ion
7.4V
2-CELL
Li-SOCl2
7.4V R4
280k
C1
4.7µF
C2
4.7µF
LTC4420
10
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
Typical V1 undervoltage threshold is:
VV1UV =
V
THC
R1
• R1+R2+R3
( )
(2)
Worst-case VOL due to current flow into the GNDSW pin
must be taken into account while calculating values for
the V2 undervoltage resistive divider:
VV2UV =VTHC
R4+VOL
100µA
• R4+R5+VOL
100µA
(3)
Equations 1-3 assume ADJ and CMP1 pin leakages are
negligible. To account for pin leakage, equations 1-3 must
be modified by an ILEAK • REQ term where equivalent
resistance REQ must be calculated on a case-by-case ba-
sis. Worst-case component values and reference voltage
tolerances must be used to calculate the maximum and
minimum threshold voltages. For example, to calculate
minimum falling switchover threshold voltage VSW1(MIN),
use VTHA(MIN), (R2+R1)(MAX), R3(MIN) in equation 1.
Figure 2. ADJ Comparator Propagation Delay as a
Function of Slew Rate; tPDA vs dVADJ/dt
where IOUT is the current supplied by COUT during non-
overlap or dead time, tNOV. Choosing:
COUT ≥
t
NOV
•I
OUT
∆VOUT
(5)
limits output droop to less than ∆VOUT.
In order to estimate tNOV and IOUT, first consider a scenario
where power supplies are present on V1 and V2, and their
voltages are changing slowly compared to the ADJ com-
parator propagation delay tPDA. For such cases, IOUT is
ILOAD and tNOV is tSWITCH. COUT can be sized according to
equation 5 with IOUT = ILOAD(MAX) and tNOV = tSWITCH(MAX)
to limit maximum output droop when switching to a higher
supply. When switching to a lower supply, switchover is
initiated only after OUT falls VREV below the supply that
is being switched in. In such cases, total output droop is
∆VOUT + VREV.
Next consider a scenario where the input power source
powering OUT is unplugged. OUT backfeeds circuitry
connected to the input supply pin. Both input and output
droop at the same rate. Referring to Figure 1, assume
the battery on V1 is unplugged when OUT is connected
to V1. IOUT is the sum of ILOAD and the back fed current
IBACK, which in this example is IR3. As OUT and V1, since
the two are connected, droop below the ADJ threshold,
switchover occurs to V2 with a dead time
tNOV = tPDA + tSWITCH (6)
where tPDA is an overdrive dependent ADJ comparator
delay. As an approximation, use tPDA from the Electrical
Characteristics table to estimate tNOV. Use this tNOV and:
IOUT = (IBACK + ILOAD) (7)
in equation 5 to size COUT:
COUT ≥tPDA +tSWITCH
( )
•IOUT
∆VOUT
(8)
Refer to Figure 2 for a more accurate estimate of tPDA vs
dVOUT/dt. If ADJ is filtered with capacitor CADJ, its discharge
time via divider R1 – R3 increases tPDA. This results in a
higher output droop than estimated by equation (8).
Selecting Output Capacitor COUT
COUT can be selected to control either output voltage droop
during switchover or output rising slew rate during initial
power-up or when switching to a higher supply.
In general, output droop, ΔVOUT, can be calculated by:
VOUT =
t
NOV
•I
OUT
C
OUT
(4)
dV
ADJ
/dt (V/s)
10
100
1k
10k
100k
0
25
50
75
100
125
t
PDA
(µs)
4420 F02
LTC4420
11
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
In order to limit output rising slew rate dVOUT/dt, size:
COUT ≥
I
LIM
dVOUT
dt
(9)
as the LTC4420 limits OUT charging current to ILIM until
OUT approaches the input supply to within ILIM • RON,
where RON is the channel switch resistance. Refer to the
Thermal Protection and Maximum COUT section to deter-
mine maximum allowed COUT.
Inductive Effects
Parasitic inductance and resistance can impact circuit
performance by causing overshoot and undershoot of input
and output voltages when the LTC4420 turns off. Parasitic
inductance in the power path causes positive-going
overshoot on the input and a negative-going undershoot
on the output. Another cause of positive input overshoot is
R-L-C tank ringing during hot plug of an input supply. Input
overshoot is most pronounced when the total resistance
of the input tank is low. Care must be taken to ensure over
voltage transients do not exceed the Absolute Maximum
ratings of the LTC4420. Additionally, parasitic resistance
and inductance can cause input undershoot (droop)
during power path turn on. If severe enough, undershoot
can temporarily invalidate a supply and cause repeated
power up cycles (motorboating) or unwanted switchover
between sources.
The first step to avoid these issues is to minimize parasitic
inductance and resistance in the power path. Guidelines
are given in the layout section for minimizing parasitic
inductance on the printed circuit board (PCB). External
to the PCB, twist the power and ground wires together to
minimize inductance.
Second, use a bypass capacitor at the input to limit input
voltage overshoot during LTC4420 power path turn off. A
few micro farads is sufficient for most applications. When
hot plugging supplies with large parasitic inductances, it
is possible for the R-L-C tank to ring to more than twice
the nominal supply voltage. Wall adapters and batteries
typically have enough loss (i.e. series resistance) to prevent
ringing of this magnitude. However, if this is a problem,
snub input capacitor CSN1 with resistor RSN1, typically
0.5Ω. Place this network close to the supply pin.
Third, if an input capacitor is not permissible, use a TVS
(such as SMAJ16CA) in applications when supply pin
transients can exceed 24V. Use a bidirectional TVS in
applications requiring reverse input protection. Note that
a TVS does not address droop and motorboating, which
are solved only by input bypassing.
During normal operation, the LTC4420 limits power path
current to < 1.6A and internal circuitry prevents OUT from
ringing below ground during power path turn off. This is
also true for output shorts when the short is close to the
LTC4420’s OUT pin. However, if the output is shorted
through a long wire, current in the wire inductance (LPAR2
in Figure 3) builds up due to the discharge of COUT1 and
can be much higher than 1.6A. This current causes the
OUT pin to ring below its −0.3V absolute maximum rating
once COUT1 has been fully discharged. For this special
case, split the output capacitor between COUT1 and COUT2
and make COUT1 small. Snub COUT1 with resister RSN2 to
damp R-L-C ringing if required. Size COUT2 to obtain the
required total output capacitance. Also add a diode between
OUT and ground close to the LTC4420 to clamp negative
ringing if the OUT pin rings below –0.3V.
Figure 3. Recommended Inductive Transient Suppression Circuitry
V1 OUT
4420 F03
COUT1
1µF
D1
1N5818
CSN1
5µF
RSN1
0.5Ω
LPAR1
OPTIONAL
LPAR2
OUT
V1
LTC4420
RSN2
1Ω
OPTIONAL
C
OUT2
10µF
LTC4420
12
4420fa
For more information www.linear.com/LTC4420
V2 Monitoring and Control
The LTC4420 monitors V2 voltage through an external
resistive divider connected between V2, V2UV and GNDSW.
When V2 is being monitored, open-drain output GNDSW
is pulled low to activate the resistive divider, otherwise
it is released high. V2UV is monitored by comparator
CV2UV, whose output is latched at the end of the moni-
toring period. This latched output establishes V2 validity
and is used in Table 1.
APPLICATIONS INFORMATION
Figure 4. State Diagram Describing V2 Monitoring
V2 monitoring duration and time between monitoring
events are set by input V2TEST, V1 validity and V2 validity
as determined previously. Complete behavior is described
by the state diagram shown in Figure 4. This implementa-
tion was chosen for the following reasons,
1. To provide flexibility in monitoring and disconnect-
ing the backup battery as required by the application,
while minimizing current draw through the V2 resistive
divider. V2TEST and V2DIS need to be actively driven
to achieve this.
V1 VALID
V2TEST
HIGH
AND AND
V2 NOT
VALID
V1
VALID
V2TEST
HIGH
AND AND V2 NOT
VALID
V2 NOT VALID AND V1 NOT VALID
V2TEST
HIGH AND V2
VALID
V2TEST
LOW
AND
V1
VALID
AND
V2
NOT VALID
V1
NOT VALID
V2TEST
LOW AND V1
VALID
V2TEST
HIGH AND V2
VALID
V2TEST
HIGH AND V2 NOT
VALID
V2TEST
HIGH
AND
V2
VALID
DISABLE
V2 MONITORING
SWITCHOVER
TO V2
EXIT THERMAL
SHUTDOWN
OR
V1 NOT VALID AND (V2TEST LOW AND V2 NOT VALID)
V1 VALID AND V2TEST LOW
V2 VALID OR V2TEST HIGH
V2
NOT VALID
ORAND V2TEST
LOW
V1
NOT VALID
POWER
UP
THERMAL
SHUTDOWN
V2 < 1.55V
V2 NOT UV
OR OR
128ms
V2 MONITORING
2ms
V2 MONITORING
WHEN V1 IS
VALID
WAIT FOR RISING
V2TEST OR
OVERRIDE CONDITION
2ms
V2 MONITORING
WHEN V1 IS
INVALID
V1 VALID AND (VTEST HIGH AND V2 NOT VALID)
V2TEST LOW AND V1 VALID
4420 F04
( )
LTC4420
13
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
2. To provide default battery backup monitoring and dis-
connect in systems where V2TEST and V2DIS are not
actively driven. V2TEST and V2DIS are either tied high
or low in these applications.
3. To allow a system powered by OUT to shut itself down
if there is no valid input supply.
4. To support backup battery charging without having to
disconnect the battery from the system.
5. Handling exceptions such as initial power up, recov-
ery from thermal shutdown and switchover after long
intervals when V2 was not being monitored.
Configuring V2TEST and V2DIS
V2TEST controls the duration of and the time between
V2 monitoring events. It can either be tied high, low or
actively driven based on the application. The following
section explores common scenarios.
In applications where primary supply V1 is going to be
valid for long periods of time and where V2TEST can be
actively driven, V2TEST should generally be driven low and
only pulsed high when V2 status is needed. This minimizes
V2-V2UV-GNDSW divider current. This scenario also
applies when V2 is a battery that slowly discharges over
time, making a V2 status update every 132s superfluous.
When operating off V2, V2TEST may be pulsed at intervals
shorter than 131s to check V2’s validity especially after
large load current spikes.
If V2TEST cannot be actively driven, it should be tied to
either V2 or OUT through a pull-up resistor. If V2 can be
reversed, tie V2TEST to OUT. Tying V2TEST high ensures
that V2 is monitored every 132s as long as V2 > 1.55V.
V2 monitoring duration is 128ms when V2 is valid and
reduces to 2ms if V2 becomes invalid. Use smaller resis-
tors in the V2-V2UV-GNDSW divider if V2 is a battery that
can develop a passivation layer when it is not being used.
Larger V2 current helps break the passivation whenever
the V2 divider is active.
In special cases where V2 needs to be monitored only
when V1 goes invalid and when battery passivation is not
an issue, tie V2TEST low.
If automatic V2 disconnect is desired when a V2 UV event
occurs, tie V2DIS low. Otherwise leave open or tie to either
OUT or V2 through a pull up resistor. If V2 can be reversed,
tie V2DIS to OUT. If V2DIS can be actively driven, driving
it low some time after a V2 UV event (output V2OK goes
low) allows systems powered by OUT to finish active tasks,
backup data and initiate shutdown proceedings.
Actively Driving V2TEST
In Figure 5, V2TEST is actively driven. When V1 powers up
above switchover threshold VSW1, it is qualified for 64ms
after which the V1 to OUT power path is activated. When
V2 rises above 1.55V, GNDSW is pulsed low for 128ms
and V2UV is monitored, even though V2TEST is low. V2
is found to be valid resulting in V2OK being driven high.
As long as V1 remains valid, V2 is monitored only when
V2TEST is driven high with V2 monitoring time being the
lower of either the V2TEST high time or 128ms. Figure 5
shows two such monitoring events of durations t1 and
t2 where t1 and t2 are less than 128ms. When V1 drops
below VSW1, OUT is switched to V2 and V2 validity is
refreshed by monitoring it once for 128ms independent
of the state of V2TEST. Following this, since V2 is the
only valid supply, V2 is monitored for 2ms every 132s
if V2TEST is low or for 128ms every 132s if V2TEST is
high. If V2 becomes invalid and V2DIS is low, the V2 to
OUT power path gets disabled.
V2TEST Tied Low
Figure 6 shows voltage waveforms for the case where
V2TEST is tied low. When V2 powers up above 1.55V,
GNDSW is pulsed low and V2 is monitored once for 128ms.
Simultaneously, the V2 to OUT power path is activated in
order to allow a system powered by OUT to power itself
up and drive V2DIS to a desired state. V2 is determined
to be valid causing V2OK to be driven high and the V2
power path to remain activated. If V2 was determined to
be invalid and V2DIS was low, V2’s power path would have
been disabled and V2OK pulled low after 128ms. Since
both V1 and V2TEST are low, V2 is monitored for 2ms
every 132s. When V1 becomes valid, OUT is switched to
V1 and V2 monitoring is halted until V1 becomes invalid.
LTC4420
14
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
Figure 6. V2 Monitoring When V2TEST Is Low
Figure 5. V2 Monitoring by Actively Driving VTEST. Note That t1 and t2 are < 128ms
t1
t1
t2
t2
VSW1
V1
V2
V2TEST
GNDSW
V2OK
OUT
1.55V
VUV2
VSW1
TIME
4420 F05
~64ms V1 POWER PATH ACTIVE V2 POWER PATH ACTIVE
2ms131s128ms128ms
GNDSW
V2OK
OUT
V2
1.55V
V2 POWER PATH ACTIVE V1 POWER
PATH ACTIVE
128ms
VUV2
VSW1
V1
131s 131s2ms
TIME
4420 F06
2ms
~64ms
LTC4420
15
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
INCREASING CMP1 HYSTERESIS
In some applications, built in CMP1 hysteresis may be
insufficient. In such cases, CMP1 hysteresis can be in-
creased as shown in Figure 7. Hysteresis at the monitored
input VMON with R8 present and assuming R9 << R8, is
given by:
VHYST =VHYSTC
R3
R1||R3||R8 +VPU
R3
R8
(10)
where VHYSTC is found in the electrical table and is typi-
cally 10mV. Account for supply VPU and resistor R8 when
calculating rising and falling thresholds of monitored
input VMON.
Referring to Figure 1, in order to prevent switchover when
COUT is being initially charged add input capacitor C1.
Ideally, if V1 is greater than switchover threshold VSW1
by ∆V, size:
C1>
VSW1 •COUT • 1– ∆V
2•ILIM •RESR
∆V
(13)
to ensure no switchover occurs when COUT is initially be-
ing charged. If the resulting C1 value causes large inrush
current, is physically too big or requires a large snubber
resistor when V1 is plugged (refer to the Typical Applications
section), select C1 to be as high a value as the application
can tolerate. A filter capacitor CADJ can also be added to
ADJ, to ride through the initial output charge up time. CADJ
should be minimized as it slows ADJ response, resulting
in a larger output droop when the input supply powering
V1 is either unplugged or drops quickly.
Input Shorts and Supply Brownout
The LTC4420 temporarily turns off its active power path
during input shorts or brownout conditions if the input
supply falls below OUT by 0.7V. If the primary input supply
becomes invalid, switchover to the backup supply occurs.
The power path is reactivated when the input recovers to
within 0.7V of the output.
Figure 8 shows the response of the LTC4420 to a brown-
out and recovery on V1 where switchover to V2 does not
occur as V1 stays above 1.8V. When V1 falls, OUT gets
disconnected from V1 and is slowly discharged by load
resistance ROUT. When V1 recovers, the power path is
reactivated and OUT tracks V1. In Figure 9, when V1 falls,
OUT gets disconnected from V1 as V1 drops below the
switchover threshold. When V1 recovers, it needs to be
qualified for 64ms before it is reconnected to OUT. OUT
gets discharged by ROUT and is connected to V2 once its
voltage is 50mV less than V2.
Figure 7. Increasing COMP1 Hysteresis
CMP1
VPU
4420 F07
R3
R1
R8
CMPOUT1
VMON
LTC4420
R9
Supply Impedance and ADJ Comparator Hysteresis
In some applications, V1 could be supplied by a battery
pack with high ESR or through a long cable with appreciable
series resistance. Load current, IOUT, flowing through this
resistance reduces the monitored V1 voltage by:
∆V1 = IOUT • RESR (11)
The drop can be as high as:
ΔV1 = ILIM • RESR (12)
when COUT is initially being charged. Voltage droop at the
V1 pin can result in repeated switchover between V1 and
V2 if built-in V1 (ADJ) hysteresis is insufficient.
LTC4420
16
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
Reverse Voltage Blocking
The LTC4420 blocks reverse voltages on supply pins V1
and V2 up to –15V relative to GND and up to –39V relative
to OUT. Transient voltage suppressors (TVS) connected to
V1 and V2 must be bidirectional and capacitors connected
to these pins must be rated to handle reverse voltages. A
reverse voltage on V2 does not disrupt V1 operation and
vice-versa.
Freshness Seal Mode
Freshness seal mode prevents V2 battery discharge by
keeping V2 disconnected from OUT even if V1 is absent
or invalid. Very little current is drawn from V2—typically
just 120nA. The following sequence (refer to Figure 10)
puts the LTC4420 in freshness seal mode:
1. Power up V2 and V2UV.
2. Once V2OK is asserted high, drive it below 50mV.
3. Power up V1 and ADJ for at least 94ms. Complete steps
2 and 3 within 80s of V2OK asserting high. Freshness
seal is enabled.
Figure 9. Voltage Waveforms When a Brownout on V1
Results in Switchover to V2. Switchover Threshold = 3V
Figure 8. Voltage Waveforms During a Brownout on V1
That Does Not Result in Switchover to V2. Switchover
Threshold = 1.8V
Figure 10. Freshness Seal Engage Procedure
COUT = 10µF
ROUT = 100Ω
100µs/DIV
V1
5V/DIV
V2
5V/DIV
OUT
5V/DIV
4420 F08
100µs/DIV
V1
5V/DIV
V2
5V/DIV
OUT
5V/DIV
4420 F09
COUT = 10µF
ROUT = 100Ω
Engage this mode if V2 is a backup battery either during
storage or during shipment. Once freshness seal has been
engaged, if V1 is disconnected, V2 stays disconnected
from OUT. Freshness seal is automatically disabled the
next time V1 is revalidated. Limit V2OK pin capacitance
to less than 10nF in order to prevent freshness seal mode
from accidentally being engaged.
Design Example
In Figure 11, the LTC4420 prioritizes between a 5V supply
connected to V1 and a 7.4V 2-cell Li-Ion battery con-
nected to V2. The system is designed to switch OUT to
V2 when V1 drops below 4V, provide early power failure
warning when V1 drops below 4.5V and disconnect the
backup battery voltage when it drops below 6V. Maximum
anticipated load current is 100mA and maximum allowed
output droop is 100mV. Output rising slew rate is limited to
<0.1V/µs and V1 and V2 input capacitances are limited to
10µF to avoid large inrush current. 1% tolerance resistors
are used ADJ, CMP1 and V2UV pin leakages and GNDSW
VOL are ignored as their design impact is small.
V2UV
V2OK
V1
ADJ
V2
1.8V
0.48V
1.8V
1.116V
4420 F10
94ms FSEAL
ENABLED
DRIVEN LOW
EXTERNALLY
< 80s
1 2 3
LTC4420
17
4420fa
For more information www.linear.com/LTC4420
Figure 11. Design Example
APPLICATIONS INFORMATION
R
1=
V
THC
•R1+R2+R3
( )
V
PFV1
(18)
R1=
0.387V
4.5V
• 500kΩ
( )
(19)
Solving equations 16 and 19 results in R1= 43.3kΩ and
R2 = 87.6kΩ. Using the nearest 1% resistors results in
R2 = 88.7kΩ. Recalculating equation 1 using calculated
R2 and R3 values and using standard 1% resistor values
close to 43.3kΩ for R1 results in R1= 44.2kΩ.
A similar procedure is used to calculate R4 and R5 using
equation 3 and total divider current. Resistance of the
GNDSW pull-down, typically 120Ω, is neglected as it is
small compared to R4 and R5. The design equations are
shown below.
R4+R5=
7.4V
5µA =1.48MΩ
(20)
as desired current in the divider is 5µA.
Rewriting equation 3 neglecting pin leakage and assuming
R5>>R4 results in:
R4 =
V
THC
• R4+R5
( )
VV2UV
(21)
R4 =
0.387V •1.48MΩ
6V
(22)
Solving equations 20 and 22 results in R4 = 96.2kΩ and
R5 = 1.38MΩ. Choosing the nearest 1% resistor results
in R4 = 95.3kΩ and R5 = 1.37MΩ.
COUT affects both OUT droop during switchover as de-
termined by equation 4 and OUT rising slew rate as de-
termined by equation 9. Calculate minimum COUT required
to meet desired output droop and slew rate specifications
using equations 8 and 9 and size COUT to be the larger of
the two values.
First choose total resistive divider current to be ~10µA for
V1 and 5µA for V2. Since the V2 divider is pulsed with a
maximum duty cycle of 0.1%, average V2 divider current
is negligible. For the 5V supply, this results in:
R1+R2+R3=
5V
10µA =500kΩ
(14)
Since desired switchover threshold, VSW1, and total divider
impedance are known, use equation 1 to first calculate R3.
Using R3 and equation 2, calculate R1 and R2. Rewriting
equation 1 results in:
R1+R2
( )
=
V
THA
• R1+R2+R3
( )
VSW1
(15)
Using (R1+R2+R3) = 500kΩ from equation 14, results in:
R1+R2
( )
=
1.047V •500kΩ
4V
=130.9kΩ
(16)
R3 ~ (500kΩ – 130.9kΩ) = 369.1kΩ (17)
Using the nearest 1% resistor value yields R3 = 365kΩ.
Rearranging equation 2, results in:
V1
ADJ
CMP1
V2UV
PFV1
V2
V2UV
GNDSW
GND 4420 F11
R3
365k
5V
INPUT
2-CELL
Li-Ion
7.4V
RSN1
0.5Ω
R6
1M
R7
1M
COUT
15µF
R2
88.7k
R1
44.2k
OUT
OUT
V2TEST
V2OK
CMPOUT1
V2DIS
LTC4420
R5
1.37M
R4
95.3k
C1
2.2µF
C2
2.2µF
+
LTC4420
18
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
COUT required to limit OUT droop to < 100mV is given by
equation 8,
COUT ≥tPDA +tSWITCH
( )
•ILOAD
100mV
(23)
COUT ≥
7.3µs+2.5µs
( )
•0.1A
100mV
=9.8µF
(24)
COUT required to limit OUT slew rate to < 0.1V/µs is given
by equation 9,
COUT ≥
I
LIM
0.1V/µs =11µF
(25)
Choose a COUT capacitor whose minimum value is 11µF
accounting for voltage and temperature coefficients. Do
this for other capacitors as well. Assuming correct PCB
Figure 12. Recommended 12-Lead MSE Layout for a 2-Layer PCB
GND
V1 V2
OUT
LTC4420
COUT
GND GND
C1 C2
4419 F12
layout, choose C1 to be 2.2µF, which is ~1/5th of COUT to
suppress inductive transients. Also snub C1 with a 0.5Ω
resistor to prevent ringing.
Layout Consideration
Make power and ground traces as wide as possible. Place
bypass capacitors, snubbers and TVS devices as close to
the pin as possible to reduce power path resistance and
parasitic inductance. These result in smaller overvoltage
transients and improved overvoltage protection. Place
resistive dividers close to the pins to improve noise im-
munity. Use a 4-layer board if possible with layer 2 as
dedicated GND and solder the exposed pad to a large PCB
GND trace for better heat dissipation. A partial layout for
a 2-layer PCB is shown in Figure 12.
LTC4420
19
4420fa
For more information www.linear.com/LTC4420
APPLICATIONS INFORMATION
Figure 13. Maximum Allowed COUT vs Input
Voltage for Different TA
TYPICAL APPLICATIONS
Battery Backup with Interface to Low Voltage Logic
THERMAL PROTECTION AND MAXIMUM COUT
Depending on the difference between input and output
voltages, the LTC4420’s internal power dissipation can be
high when operating in current limit mode. This usually
occurs when a large COUT is being charged either during
initial power up or when OUT switches over to a higher
supply. The situation is worsened if there is a DC load on
OUT, as this reduces the current available to charge COUT.
In such cases, self heating can cause power path turn-off
due to activation of the thermal protection circuitry. The
power path is reactivated when die temperature drops to
a safe value. This process can repeat indefinitely if COUT is
discharged fully by load current IOUT in the interval when
the power path is off.
Maximum allowed COUT to prevent activation of the thermal
protection circuit depends on several factors such as input
supply and output voltages, starting ambient temperature,
heat dissipation in the PCB and DC output current. Choose
COUT < 500µF if possible. If a larger COUT is necessary,
use Figure 13 to choose COUT. Also follow PCB layout
guidelines to improve heat dissipation.
ILOAD = 0
–40°C
25°C
85°C
V
IN
(V)
5
10
15
20
100
1k
10k
60k
C
OUT
(µF)
4420 F13
R3
365k
RSN1
0.5Ω
5V TO 18V
WALL ADAPTER
3.6V TO 18V
BACKUP
SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
V1UV THRESHOLD: V1 < 4.5V (V1 FALLING)
V2OK THRESHOLD: V2 < 3V (V2 FALLING)
COUT
10µF
R2
88.7k
R6
1M
R7
1M
R8
1M
R1
44.2k
R4
150k
R5
1M
V1 OUT
V2TEST
V2DIS
CMPOUT1
V2OK
4420 TA02
ADJ
CMP1
V2UV
GNDSW
GND
LTC4420
V2
C1
10µF
C3
10µF
C2
10µF
IN OUT
LTC1763-3.3V
SHDN GND
V2OK
V1UV
3.3V
SYSTEM
RSN2
0.5Ω
LTC4420
20
4420fa
For more information www.linear.com/LTC4420
TYPICAL APPLICATIONS
Triple Voltage Monitor
SuperCap Backup with SuperCap Charging
R3
1M
R7
1M
R8
1M
R6
1M
COUT
10µF
R2
237k
R1
121k
R11
1.87M
R12
301k
R14
127k
R13
12.1k
1.7V TO 5.5V
INPUT
R4
127k
R5
1M
V1
V2
OUT OUT
V2OK
V1UV
V2TEST
V2DIS
L1 3.3µH
4.2V
V2OK
CMPOUT1
V2UV
ADJ
GNDSW
4420 TA03
GND
LTC4420
CMP1
C2
940mF
940mF
C1
10µF
C3
120pF
C2: MURATA DMF325R5H474M3DTA0
SW2SW1
LTC3128
GND
VOUT
RSENP
RSENS
MID
IN
PROG
MAXV FB
RUN
SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
V1UV THRESHOLD: V1 < 4.4V (V1 FALLING)
V2OK THRESHOLD: V2 < 3.5V (V2 FALLING)
+
R3
2M
R10
2M
R7
1M
R8
1M
COUT
10µF
R1
191k
R5
1M
R4
59k
9V
ALKALINE
R9
113k
+
14.8V
Li-Ion
V1 OUT OUT
V2OK
OUTUV
CMP1
CMPOUT1
V2DIS
V2OK
ADJ
V2UV
GNDSW
4420 TA04
SWITCHOVER THRESHOLD: V1 < 12V (V1 FALLING)
V2OK THRESHOLD: V2 < 7V (V2 FALLING)
OUTUV THRESHOLD: OUT < 7.5V (OUT FALLING)
GND
LTC4420
V2
C1
10µF
C2
10µF
V2TEST
LTC4420
21
4420fa
For more information www.linear.com/LTC4420
TYPICAL APPLICATIONS
Early Power Failure Warning with Low Battery Indication
R3
1M COUT
10µF
PFV1
V2OK
OUT
R2
75k
R1
41.2k
L1, 10µH
V1
ADJ
4420 TA05
GND
LTC4420
CMP1
V2
SW2SW1
BST2BST1
VOUT
VIN
COMP
FBRUN
VCC
SNSGND
PWM
LTC3111
C3
1µF
C5
0.1µF
12V
TO OTHER
CIRCUITS
C4
0.1µF
R13
1M
R14
137k
C8
10µF
5V TO 15V
INPUT
C6
39pF
C7, 1nF R12, 44.2k C1
22µF
R8
20k
R10
2.21M
R6
1M
R7
1M
R8
1M
R11
158k
C9
18pF
R5
2M
V2UV
R4
66.5k
GNDSW
OUT
V2TEST
V2DIS
CMPOUT1
V2OK
C2
10µF
4-CELL
14.8V
Li-ION
PFV1, V1 POWER FAILURE THRESHOLD: V1 < 10.6V (V1 FALLING)
SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING)
V2OK THRESHOLD: V2 < 12V (V2 FALLING)
+
LTC4420
22
4420fa
For more information www.linear.com/LTC4420
Prioritization with Failsafe Backup Supply
V1
ADJ
CMP1 V2UV
PFV1
V2
V2UV
GNDSW
4420 TA06
R3
1M
R7
1M
R8
1M
COUT
10µF
R2
75k
R1
41.2k
OUT OUT
DS
BAT54
V2TEST
V2OK
CMPOUT1
V2DIS
LTC4420
GND
R5
1.37M
PFV1 THRESHOLD: V1 < 10.6V (V1 FALLING)
SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING)
V2UV THRESHOLD: V2 < 6V (V2 FALLING)
12V
WALL
ADAPTER
COIN
CELL
3V
2-CELL
Li-Ion
7.4V R4
95.3k
C1
10µF
C2
10µF
+
RSN1
0.5Ω
TYPICAL APPLICATIONS
LTC4420
23
4420fa
For more information www.linear.com/LTC4420
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
0.75 ±0.05
R = 0.115
TYP
16
127
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD12) DFN 0106 REV A
0.23 ±0.05
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
2.38 ±0.10
2.25 REF
0.45 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.25 ±0.05
2.25 REF
2.38 ±0.05
1.65 ±0.05
2.10 ±0.05
0.70 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.45 BSC
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
LTC4420
24
4420fa
For more information www.linear.com/LTC4420
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings.
MSOP (MSE12) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
16
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
0.42 ±0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
LTC4420
25
4420fa
For more information www.linear.com/LTC4420
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/17 Updated tSWITCH test condition
Updated pin function for Exposed Pad
3
6
LTC4420
26
4420fa
For more information www.linear.com/LTC4420
LINEAR TECHNOLOGY CORPORATION 2016
LT 0917 REV A • PRINTED IN USA
www.linear.com/LTC4420
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R3
1M
R7
1M
R8
1M
COUT
10µF
C3
2.2µF
R2
237k
R1
121k
R5
1.37M
R4
95.3k
5V
WALL
ADAPTER
2-CELL
7.4V
Li-Ion
R12
1.1M
R11
1.05M
V1 OUT
V2TEST
V1UV
V2UV
CMPOUT1
V2OK
V2DIS
RUN
5V
ADJ
CMP1
V2UV
GNDSW
4420 TA07
GND
LTC4420
V2
C6
10µF
C2
10µF
C1
10µF
RUN
MPPC
VS1
VS2
VCC
BST1 BST2SW1
PWM GND PGND
LTC3129-1
VS3
SW2
C4
22nF
C5
22nF
L1
3.3µH
VIN OUT
SYSTEM
R13
1M SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING)
V1UV THRESHOLD: V1 < 4.4V (V1 FALLING)
V2UV THRESHOLD: V2 < 6V (V2 FALLING)
RSN1
0.5Ω
+