DATA SH EET
Product specification
File under Integrated Circuits, IC24 1999 Aug 05
INTEGRATED CIRCUITS
74LVC162374A; 74LVCH162374A
16-bit edge triggered D-type
flip-flopwith30 Ωseriestermination
resistors; 5 V input/output tolerant;
3-state
1999 Aug 05 2
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
FEATURES
•ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
•5 V tolerant input/output for
interfacing with 5 V logic
•Wide supply voltage range of
1.2 to 3.6 V
•Complies with JEDEC standard
no. 8-1A
•CMOS low power consumption
•MULTIBYTE flow-through
standard pin-out architecture
•Lowinductancemultiplepowerand
ground pins for minimum noise and
ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold
(74LVCH162374A only)
•High impedance when VCC =0
•Power off disables outputs,
permitting live insertion.
DESCRIPTION
The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate
D-typeinputsforeachflip-flopand3-stateoutputsforbusorientedapplications.
The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.
A clock (CP) input and an output enable (OE) are provided for each octal.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
The flip-flops will store the state of their individual D-inputs that meet the set-up
and hold time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
The74LVCH162374A bus hold datainputs eliminates the needfor external pull
up resistors to hold unused inputs.
The 74LVC(H)162374A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
↑= LOW-to-HIGH CP transition.
OPERATION MODES INPUTS INTERNAL
FLIP-FLOPS OUTPUTS
nOE nCP nDnQ0to Q7
Load and read register L↑lL L
L↑hH H
Latch register and disable outputs H↑lL Z
H↑hH Z
1999 Aug 05 3
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
∑(CL×VCC2×fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in Volts.
ORDERING INFORMATION
PINNING
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay CP to QnCL= 50 pF; VCC = 3.3 V 3.8 ns
fmax maximum clock frequency 150 MHz
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per
flip-flop VCC = 3.3 V; note 1 30 pF
OUTSIDE NORTH
AMERICA NORTH AMERICA PACKAGE
TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE
74LVC162374ADL VC162374A DL −40 to +85 °C 48 SSOP plastic SOT370-1
74LVC162374ADGG VC162374A DGG 48 TSSOP plastic SOT362-1
74LVCH162374ADL VCH162374A DL 48 SSOP plastic SOT370-1
74LVCH162374ADGG VCH162374A DGG 48 TSSOP plastic SOT362-1
PIN SYMBOL DESCRIPTION
11
OE output enable input (active LOW)
2, 3, 5, 6, 8, 9, 11, 12 1Q0to 1Q73-state flip-flop outputs
4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V)
7, 18, 31, 42 VCC DC supply voltage
13, 14, 16, 17, 19, 20, 22, 23 2Q0to 2Q73-state flip-flop outputs
24 2OE output enable input (active LOW)
25 2CP clock input
36, 35, 33, 32, 30, 29, 27, 26 2D0to 2D7data inputs
47, 46, 44, 43, 41, 40, 38, 37 1D0to 1D7data inputs
48 1CP clock input
1999 Aug 05 4
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
Fig.1 Pin configuration.
handbook, halfpage
162374A
MNA433
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2CP
1OE 1CP
Fig.2 Logic symbol.
handbook, halfpage
MNA434
1Q0
1Q1
1CP 2CP
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
1999 Aug 05 5
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
Fig.3 Logic diagram.
handbook, full pagewidth
MNA435
2CP
D
CP
Q
2OE
to 7 other channels
FF2
2Q0
2D0
1CP
D
CP
Q
1OE
to 7 other channels
FF1
1Q0
1D0
Fig.4 IEC logic symbol.
handbook, halfpage
23
MNA436
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 2EN
1OE 11EN
1CP
2OE
2CP
48 C3
C2
1D 1
2D 2
2D7
2D62Q7
2Q6
Fig.5 Bus hold circuit.
handbook, halfpage
to internal circuit
MNA428
VCC
input
1999 Aug 05 6
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL PARAMETER CONDITIONS LIMITS UNIT
MIN. MAX.
VCC DC supply voltage
for max. speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIDC input voltage range 0 5.5 V
VODC output voltage range
output HIGH or LOW state 0 VCC V
3-state 0 5.5 V
Tamb operating ambient temperature see DC and AC characteristics per
device −40 +85 °C
tr, tfinput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC DC supply voltage −0.5 +6.5 V
IIK DC input diode current VI<0 −−50 mA
VIDC input voltage note 1 −0.5 +5.5 V
IOK DC output diode current VO>V
CC or VO<0 −±50 mA
VODC output voltage
output HIGH or LOW note 1 −0.5 VCC + 0.5 V
output 3-state note 1 −0.5 +6.5 V
IODC output diode current VO=0toV
CC −±50 mA
IGND, ICC DC VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation plastic shrink
mini-pack (SSOP and TSSOP) above 60 °C derate linearly with
5.5 mW/K −500 mW
1999 Aug 05 7
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground=0V).
Notes
1. All typical values are at VCC = 3.3 V and Tamb =25°C.
2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH162374A) only.
4. For data inputs only, control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
SYMBOL PARAMETER
TEST CONDITIONS Tamb (°C)
UNIT
OTHER VCC (V) −40 to +85
MIN. TYP.(1) MAX.
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8
VOH HIGH-level output voltage VI=V
IH or VIL; IO=−6 mA 2.7 VCC −0.5 −−V
V
I
=V
IH or VIL;
IO=−100 µA3.0 VCC −0.2 VCC −
VI=V
IH or VIL;
IO=−12 mA 3.0 VCC −0.8 −−
V
OL LOW-level output voltage VI=V
IH or VIL; IO= 6 mA 2.7 −−0.40 V
VI=V
IH or VIL;
IO= 100 µA3.0 −−0.20
VI=V
IH or VIL; IO= 12 mA 3.0 −−0.55
IIinput leakage current VI= 5.5 Vor GND; note 2 3.6 −±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 Vor GND 3.6 −0.1 ±5µA
Ioff power off leakage supply VIor VO= 5.5 V 0.0 −0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −0.1 20 µA
∆ICC additional quiescent supply
current per control pin VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −5 500 µA
IBHL bus hold LOW sustaining
current VI= 0.8 V; notes 3,
4 and 5 3.0 75 −−µA
I
BHH bus hold HIGH sustaining
current VI= 2.0 V; notes 3,
4 and 5 3.0 −75 −−µA
I
BHLO bus hold LOW overdrive
current VI= 0.8 V; notes 3,
4 and 6 3.6 500 −−µA
I
BHHO bus hold HIGH overdrive
current VI= 0.8 V; notes 3,
4 and 6 3.6 −500 −−µA
1999 Aug 05 8
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns; Tamb =−40 to +85 °C.
Note
1. Typical values at VCC = 3.3 V and Tamb =25°C.
SYMBOL PARAMETER WAVEFORMS
LIMITS
UNITVCC = 3.3 V ±0.3 V VCC = 2.7 V
MIN. TYP.(1) MAX. MIN. MAX.
tPHL/tPLH propagation delay
nCP to nQn
see Figs 6 and 9 1.5 3.8 6.2 1.5 7.2 ns
tPZH/tPZL 3-state output enable
time nOE to nQn
see Figs 8 and 9 1.5 4.1 7.1 1.5 8.1 ns
tPHZ/tPLZ 3-state output disable
time nOE to nQn
see Figs 8 and 9 1.5 3.7 5.2 1.5 6.2 ns
tWnCP pulse width HIGH or
LOW see Fig.6 3 1.5 −3.0 −ns
tsu set-up time nDnto nCP see Fig.7 2.0 0.3 −2.0 −ns
thhold time nDnto nCP see Fig.7 +1.5 −0.3 −1.5 −ns
fmax maximum clock pulse
frequency see Fig.6 100 −−80 −MHz
1999 Aug 05 9
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
AC WAVEFORMS
Fig.6 Clock input (nCP) to output (nQn) propagation delay, the clock pulse width and the maximum clock pulse
frequency.
handbook, full pagewidth
MNA437
nCP INPUT
nQn OUTPUT
tPHL tPLH
tW
VM
VOH
VI
GND
VOL
VMVM
1/fmax
Fig.7 Data set-up and hold times for the nDn input to the nCP input.
The shaded areas indicate when the input is permitted to change for predictable output performance.
handbook, full pagewidth
MNA438
GND
GND
th
tsu th
tsu
VM
VM
VM
VI
VOH
VOL
VI
nQn OUTPUT
nCP INPUT
nDn INPUT
1999 Aug 05 10
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
Fig.8 3-state enable and disable times.
handbook, full pagewidth
MNA432
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
nQn OUTPUT
LOW-to-OFF
OFF-to-LOW
nQn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
nOE INPUT
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.9 Load circuitry for switching times.
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA296
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Definitions for test circuit:
RL= Load resistor; see Chapter “AC Characteristics”.
CL= Load capacitance including jig and probe capacitance
(see Chapter “AC Characteristics”).
RT= Termination resistance should be equal to the output
impedance Zo of the pulse generator.
VCC VI
<2.7 V VCC
2.7 - 3.6 V 2.7 V
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
1999 Aug 05 11
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
PACKAGE OUTLINES
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 93-11-02
95-02-04
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118AA
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
1999 Aug 05 12
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywvθ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 93-02-03
95-02-10
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153ED
1999 Aug 05 13
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboard by screen printing, stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurface mount devices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackages with leadsonfoursides, the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Aug 05 14
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Aug 05 15
Philips Semiconductors Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A;
74LVCH162374A
NOTES
© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
1999 67
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Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Aug 05 Document order number: 9397 750 05975
Philips Semiconductors - PIP - 74LVC162374A; 74LVCH162374A; 16-bit edge triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
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74LVC162374A;
74LVCH162374A; 16-
bit edge triggered D-
type flip-flop with
30 Ohm series
termination
resistors; 5 V
input/output
tolerant; 3-state
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Philips Semiconductors - PIP - 74LVC162374A; 74LVCH162374A; 16-bit edge triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
General description
The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and
an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs
can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-
HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
The 74LVCH162374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.
The 74LVC(H)162374A is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce line
noise.
Features
● ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
● 5 V tolerant input/output for
interfacing with 5 V logic
● Wide supply voltage range of
1.2 to 3.6 V
● Complies with JEDEC standard
no. 8-1A
● CMOS low power consumption
● MULTIBYTE flow-through
standard pin-out architecture
● Low inductance multiple power and
ground pins for minimum noise and
ground bounce
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Philips Semiconductors - PIP - 74LVC162374A; 74LVCH162374A; 16-bit edge triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
● Direct interface with TTL levels
● All data inputs have bus hold
(74LVCH162374A only)
● High impedance when VCC =0
● Power off disables outputs,
permitting live insertion.
Applications
Download
PDF
File
AN240: Interfacing 3 Volt and 5 Volt Applications
Datasheet
Type number Title Publication
release date Datasheet status Page
count File
size
(kB)
Datasheet
74LVC162374A;
74LVCH162374A 16-bit edge
triggered D-type
flip-flop with 30
Ohm series
termination
resistors; 5 V
input/output
tolerant; 3-state
8/5/1999 Product
specification 16 94
Download
PDF
File
Download
Blockdiagram(s)
Block diagram of
74LVCH162374ADL
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Philips Semiconductors - PIP - 74LVC162374A; 74LVCH162374A; 16-bit edge triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
Parametrics
Type number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74LVCH162374ADGG SOT362-1
(TSSOP48)
3.3V 16-Bit
D-Type Flip-
Flop; Postive-
Edge Trigger
with Bus
Hold and 30
Ohm
Termination
Resistors (3-
State)
6~10 Low 48 Low Power or
Battery
Applications TTL Low
74LVCH162374ADL SOT370-1
(SSOP48)
3.3V 16-Bit
D-Type Flip-
Flop; Postive-
Edge Trigger
with Bus
Hold and 30
Ohm
Termination
Resistors (3-
State)
6~10 Low 48 Low Power or
Battery
Applications TTL Low
Products, packages, availability and ordering
Type number North American type
number Ordering code
(12NC) Marking/Packing
Download
PDF
File
IC packing info Package Device
status Buy online
74LVCH162374ADGG 74LVCH162374ADG 9352 387 70112 Standard Marking
* Tube
SOT362-1
(TSSOP48)
Full production
order this
product
online
-
74LVCH162374ADG-
T 9352 387 70118 Standard Marking
* Reel Pack,
SMD, 13"
SOT362-1
(TSSOP48)
Full production
order this
product
online
-
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Philips Semiconductors - PIP - 74LVC162374A; 74LVCH162374A; 16-bit edge triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374ADL 74LVCH162374ADL 9352 387 60112 Standard Marking
* Tube SOT370-1
(SSOP48) Full production
order this
product
online
-
74LVCH162374ADL-
T 9352 387 60118 Standard Marking
* Reel Pack,
SMD, 13"
SOT370-1
(SSOP48) Full production
order this
product
online
-
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74LVCH162374A
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