*Index 05.09.1997 10:59 Uhr Page 1 General Purpose Microcomputer Data Sheet HD404019R Series HD404054 Series/HD404094 Series Compact Microcomputer H42xx Family Data Sheet HD404202 Series/HD404222 Series A/D Converter On-Chip H43xx Family Data Sheet HD404304 Series HD404318 Series HD404328 Series HD404339 Series HD404358 Series HD404369 Series HD404344 Series/HD404394 Series Improved Timers, System Control H44xx Family Data Sheet HD404439 HD404449 Series HD404459 Series Preface The HMCS400 Series is made up of the microcomputer families listed below, each with functions geared for applications in specific fields. The Hitachi 4-bit Single-Chip Microcomputer Databook is divided into two separate databooks, no. 1 and no. 2. Databook no. 1 includes information from general purpose microcomputers to the H44XX family, while no. 2 includes information from the H46XX family to the H48XX family. Use databooks no. 1 and no. 2 accordingly. HMCS400 Series General purpose microcomputer H42XX Family 28 pin compact microcomputer H43XX Family Built-in A/D converter H44XX Family Enhanced timer function H46XX Family Built-in DTMF generator/receiver No. 1 No. 2 H47XX Family VFD display controller/driver H48XX Family LCD display controller/driver Contents General Information Function Overview........................................................................................................................... Introduction of Packages .............................................................................................................. Reliability and Quality Assurance .............................................................................................. Reliability Test Data of Microcomputer ................................................................................... Programmable ROM (ZTATTM) Microcomputer ....................................................................... Program Development Procedure and Support Systems.................................................... Instruction Set .................................................................................................................................. 2 22 36 44 66 71 77 Data Sheets General Purpose Microcomputer HD404019R............................................................................................................................................ HD40L4019R.......................................................................................................................................... HD4074019 ............................................................................................................................................ HD407L4019 .......................................................................................................................................... HD404052 .............................................................................................................................................. HD404054 .............................................................................................................................................. HD4074054 ............................................................................................................................................ HD404092 .............................................................................................................................................. HD404094 .............................................................................................................................................. HD4074094 ............................................................................................................................................ H42XX Family HD404201 .............................................................................................................................................. HD40L4201 ............................................................................................................................................ HD404202 .............................................................................................................................................. HD40L4202 ............................................................................................................................................ HD404222 .............................................................................................................................................. HD40L4222 ............................................................................................................................................ HD4074224 ............................................................................................................................................ H43XX Family HD404302R............................................................................................................................................ HD404304 .............................................................................................................................................. HD4074308 ............................................................................................................................................ HD404314 .............................................................................................................................................. HD404316 .............................................................................................................................................. HD404318 .............................................................................................................................................. HD4074318 ............................................................................................................................................ HD404324 .............................................................................................................................................. HD404324U............................................................................................................................................ HD404326 .............................................................................................................................................. HD404326U............................................................................................................................................ HD404328 .............................................................................................................................................. HD404328U............................................................................................................................................ HD4074329 ............................................................................................................................................ HD4074329U.......................................................................................................................................... HD404334 .............................................................................................................................................. HD404336 .............................................................................................................................................. HD404338 .............................................................................................................................................. HD4043312 ............................................................................................................................................ HD404339 .............................................................................................................................................. HD4074339 ............................................................................................................................................ HD404354 .............................................................................................................................................. HD404356 .............................................................................................................................................. 248 248 248 248 368 368 368 368 368 368 461 461 461 461 461 461 461 579 579 579 632 632 632 632 696 696 696 696 696 696 696 696 775 775 775 775 775 775 845 845 HD404358 .............................................................................................................................................. 845 HD40A4354 ............................................................................................................................................ 845 HD40A4356 ............................................................................................................................................ 845 HD40A4358 ............................................................................................................................................ 845 HD407A4359 .......................................................................................................................................... 845 HD404364 .............................................................................................................................................. 939 HD404368 .............................................................................................................................................. 939 HD4043612 ............................................................................................................................................ 939 HD404369 .............................................................................................................................................. 939 HD40A4364 ............................................................................................................................................ 939 HD40A4368 ............................................................................................................................................ 939 HD40A43612 .......................................................................................................................................... 939 HD40A4369 ............................................................................................................................................ 939 HD407A4369 .......................................................................................................................................... 939 HD404341 ..............................................................................................................................................1043 HD404342 ..............................................................................................................................................1043 HD404344 ..............................................................................................................................................1043 HD4074344 ............................................................................................................................................1043 HD404391 ..............................................................................................................................................1043 HD404392 ..............................................................................................................................................1043 HD404394 ..............................................................................................................................................1043 HD4074394 ............................................................................................................................................1043 H44XX Family HD404439 ..............................................................................................................................................1194 HD404448 ..............................................................................................................................................1295 HD404449 ..............................................................................................................................................1295 HD4074449 ............................................................................................................................................1295 HD404458 ..............................................................................................................................................1405 HD404459 ..............................................................................................................................................1405 HD4074459 ............................................................................................................................................1405 General Information Function Overview Introduction of Packages Reliability and Quality Assurance Reliability Test Data of Microcomputer Programmable ROM (ZTATTM) Microcomputer Program Development Procedure and Support Systems Instruction Set Function Overview General-purpose products: H40XX Family Series No. Type No. HD404054 Mask HD404052 ROM HD404094 ZTAT Mask ROM HD404019 ZTAT Mask ROM ROM (byte) 2k RAM (digit) 512 Max. operating Freq (MHz) f OSC =4 4.0-6.0 0.5 f OSC =8 8-bit timer (channels) 3 SCI (channels) - I/O port 35 Comparator Package 2 DP-42S, FP-44A HD404054 HD40A4052 HD40A4054 HD4074054 HD404092 4k 2k 4k 4k 2k 512 2.7-5.5 1.8-6.0 1 1 f OSC =4 f OSC =4 3 - 35 2 DP-42S, FP-44A HD404094 HD4074094 HD404019R 4k 4k 16k 992 2.7-5.5 3.5-6.0 1 0.89 f OSC =4 f OSC =4.5 2 1 58 - DP-64S, FP-64A, FP-64B 3.5-6.0 0.89 f OSC =4.5 2.7-6.0 4.5-5.5 1.12 0.89 f OSC =3.58 f OSC =4.5 4.5-5.5 0.89 f OSC =4.5 3.0-5.5 1.12 f OSC =3.58 HD40L4019R ZTAT Min. Supply operation voltage (V) (s) 1.8-6.0 1 HD4074019 16k HD407L4019 DP-64S, FP-64A DP-64S, FP-64A, FP-64B, DC-64S DP-64S, FP-64A *: Under development Compact products: H42XX Family Series No. Type No. HD404202 Mask HD404201 ROM HD404222 Mask ROM ZTAT ROM (byte) 1k HD40L4201 HD404202 HD40L4202 HD404222 2k HD40L4222 HD4074224 4k RAM (digit) 64 Min. Supply operation voltage (V) (s) 3.5-6.0 0.89 Max. operating Freq (MHz) f OSC =4.5 8-bit timer (channels) 1 SCI (channels) - I/O port 22 128 2.5-6.0 3.5-6.0 2.5-6.0 3.5-6.0 3.55 0.89 3.55 0.89 f OSC =1.125 f OSC =4.5 f OSC =1.125 f OSC =4.5 2 1 22 2.5-6.0 3.5-5.5 2.5-5.5 3.55 0.89 3.55 f OSC =1.125 f OSC =4.5 f OSC =1.125 2k Comparator Package - DP-28S, FP-28DA, FP-30D 2 DP-28S, FP-28DA, FP-30D Function Overview Built-in A/D converter products: H43XX Family Min. Max. Supply opera- operating ROM RAM voltage tion Freq (byte) (digit) (V) (s) (MHz) 2k 160 4.5-5.5 1.78 f OSC =4.5 8-bit timer (channels) 2 SCI (chan- I/O A/D connels) port verter - 33 4 High voltage terminal 25 Medium voltage Input terminal capture - - HD404304 HD4074308 HD404314 4k 8k 4k 384 4.0-5.5 0.89 f OSC =4.5 3 1 34 8 21 - Available - HD404316 HD404318 HD4074318 HD404324 6k 8k 8k 4k 280 2.7-6.0 1.78 f OSC =4.5 3 1 35 4 - - - HD404324U* HD404326 6k HD404326U* HD404328 8k HD404328U* HD4074329 16k 536 2.9-5.5 HD4074329U* HD404334 4k 512 4.0-5.5 0.89 f OSC =4.5 3 1 54 12 30 - Available - DP-64S, FP-64B HD404336 HD404338 HD4043312 HD404339 HD4074339 HD404354 6k 8k 12k 16k 16k 4k 384 2.7-6.0 0.8 f OSC =5 3 1 34 8 - 4 Available - DP-42S, FP-44A HD404356 HD404358 HD40A4354 HD40A4356 HD40A4358 HD407A4359 HD404364 6k 8k 4k 6k 8k 16k 4k 4.5-5.5 0.47 f OSC =8.5 2.7-6.0 0.8 f OSC =5 3 1 54 12 - 8 Available - DP-64S, FP-64B, FP-64A HD404368 HD4043612 HD404369 HD40A4364 HD40A4368 HD40A43612 HD40A4369 HD407A4369 HD404341 8k 12k 16k 4k 8k 12k 16k 16k 1k 4.5-5.5 0.47 f OSC =8.5 256 2.7-5.5 0.89 f OSC =4.5 2 1 22 4 - - - - DP-28S, FP-28DA, FP-30D HD404342 HD404344 HD4074344 HD404391 2k 4k 4k 1k 256 2.7-5.5 0.89 f OSC =4.5 2 1 21 3 - 3 - - DP-28S, FP-28DA, FP-30D HD404392 HD404394 HD4074394 2k 4k 4k Series No. Type No. HD404304 Mask HD404302R ROM ZTAT HD404318 Mask ROM ZTAT HD404328 Mask ROM ZTAT HD404339 Mask ROM ZTAT HD404358 Mask ROM ZTAT HD404369 Mask ROM ZTAT HD404344 Mask ROM ZTAT HD404394 Mask ROM ZTAT *: External LCD voltage divider type 2 512 512 LCD controller Package - DP-42, DP-42S, FP-54 24seg x 4com DP-42S, FP-44A DP-64S, FP-64B, FP-64A DP-64S, FP-64B Function Overview Improved timer functionality products: H44XX Family ROM (byte) 16k Min. RAM Supply operation (digit) voltage (V) (s) 960 3.5-6.0 0.89 HD404448 8k 1152 3.0-6.0 2.7-6.0 1.78 1 f OSC =2.25 f OSC =4 4 2 64 4 - FP-80A, TFP-80F HD404449 HD4074449 HD404458 16k 16k 8k 512 2.7-5.5 1.8-3.6 1 f OSC =4 4 1 56 - Available FP-64A HD404459 HD4074459 16k 16k 2.2-2.7 2.7-3.6 2 1 f OSC =2 f OSC =4 Series No. Type No. HD404439 Mask HD404439 ROM HD404449 HD404459 Mask ROM ZTAT Mask ROM ZTAT Max. operating 8-bit timer SCI I/O Freq (MHz) (channels) (channels) port 5 2 70 f OSC =4.5 A/D converter Comparator Package 8 - FP-80A, FP-80B 768 Built-in DTMF circuit products: H46XX Family Series No. Type No. HD404618 Mask HD404612 ROM ZTAT HD404629R Mask ROM HD404614 HD404616 HD404618 HD4074618 HD404628R Min. Max. 8-bit Supply opera- operating timer ROM RAM voltage tion Freq (chan(byte) (digit) (V) (s) (MHz) nels) 2k 1184 2.7-6.0 5 f OSC =0.8 3 SCI (chan- I/O nels) port 1 30 DTMF genera- DTMF LCD A/D Comparator receiver controller converter tor Package Available - 32seg x - Available FP-80A, 4com FP-80B, TFP-80 4k 6k 8k 8k 8k 1876 3.0-5.5 3.0-6.0 1 f OSC =4 4 1 44 Available - 52seg x 4com 4 - FP-100A, FP-100B, TFP-100B 1152 2.7-6.0 3.0-6.0 2.7-6.0 3.0-6.0 2.7-6.0 3.5-5.5 2.7-5.5 2.7-6.0 f OSC =2 f OSC =4 f OSC =2 f OSC =4 f OSC =2 f OSC =4 f OSC =2 f OSC =4 4 2 68 Available - - - Available FP-80B HD4046212R 12k HD404629R 16k ZTAT HD404639R Mask ROM ZTAT HD404654 HD404669 Mask ROM ZTAT Mask ROM ZTAT HD404678 Mask ROM HD4074629 16k HD404638R 8k HD404639R 16k HD40A4638R 8k HD40A4639R 16k HD407A4639R 16k 2 1 2 1 2 1 2 1 4.0-6.0 0.5 f OSC =8 f OSC =4 3 1 32 Available - - - Available DP-42S, FP-44A 3 1 52 Available - - - Available FP-64A 4 2 48 - Available - - - FP-64A HD404652 2k 512 2.7-5.5 1 4.0-5.5 0.5 1.8-6.0 1 HD404654 HD4074654 HD404668 4k 4k 8k 1152 2.7-5.5 1 1.8-5.5 1 f OSC =4 HD4046612 HD404669 HD40A4668 HD40A46612 HD40A4669 HD407A4669 12k 16k 8k 12k 16k 16k 4.0-5.5 0.5 f OSC =8 HD404676 6k 2.2-5.5 1 4.0-5.5 0.5 4.5-5.5 1.91 f OSC =4 f OSC =8 f OSC =4.2 HD404678 HD4074678 8k 512 3 Function Overview VFD controller/driver products: H47XX Family Series No. Type No. HD404719 Mask HD404719 ROM ZTAT HD4074719 HD404729 Mask HD404728 ROM ZTAT HD404729 HD4074729 Supply Min. ROM RAM voltage opera-tion (byte) (digit) (V) (s) 16k 960 3.0-6.0 0.89 Max. operating 8-bit timer SCI Freq (MHz) (channels) (channels) I/O port 5 2 70 f OSC =4.5 High voltage terminal 36 16k 8k f OSC =4.5 32 576 16k 16k 3.0-5.5 3.0-6.0 0.89 3 2 56 A/D VFD converter controller Package 8 - FP-80A, FP-80B - Available DP-64S, FP-64A, FP-64B 3.0-5.5 LCD controller/driver products: H48XX Family Series No. Type No. HD404818 Mask HD404812 ROM ZTAT HD404829R Mask ROM HD404849 ZTAT Mask ROM ZTAT HD404889* Mask ROM ZTAT HD40L4812 HD404814 HD40L4814 HD404816 HD40L4816 HD404818 HD40L4818 HD4074818 HD407L4818 HD404828R 8k 1876 HD4048212R HD404829R HD4074829 HD404848 12k 16k 16k 8k 512 2.7-5.5 2.7-6.0 0.89 f OSC =4.5 4 1 35 32seg x 4com 8 - FP-80A, FP-80B, TFP-80C HD4048412 HD404849 HD4074849 HD404888 12k 16k 16k 8k 2.7-5.5 1.8-5.5 0.89 f OSC =4.5 4 1 46 32seg x 4com 6 - FP-80A, TFP-80C HD4048812 HD404889 HD4074889 12k 16k 16k 4k 6k 8k 8k 4.45 0.95 4.45 0.95 4.45 0.95 4.45 0.95 4.45 1 Max. operating 8-bit timer SCI I/O LCD A/D Freq (MHz) (channels) (channels) port controller converter ComparatorPackage 3 1 30 32seg x - Available FP-80A, f OSC =4.2 4com FP-80B, TFP-80 f OSC =0.9 f OSC =4.2 f OSC =0.9 f OSC =4.2 f OSC =0.9 f OSC =4.2 f OSC =0.9 f OSC =4.2 f OSC =0.9 f OSC =4.2 4 1 44 52seg x 4 - FP-100A, 4com FP-100B, TFP-100B 2.7-6.0 4.0-6.0 2.7-6.0 4.0-6.0 2.7-6.0 4.0-6.0 2.7-6.0 4.0-5.5 3.0-5.5 2.7-6.0 *: Under development 4 Supply Min. ROM RAM voltage opera-tion (byte) (digit) (V) (s) 2k 1184 4.0-6.0 0.95 1184 1344 2.0-5.5 Introduction of Packages Hitachi microcomputer devices include various types of packages which meet the requirements of the ever smaller, thinner, and more versatile electric appliances. When selecting a suitable package for use, please refer to this introduction for Hitachi microcomputer packages. 1. Package Classification Pin insertion types, surface mounting types, and multifunction types are applicable for each kind of mounting method. Also plastic and ceramic packages are offered. Figure 1 shows the package classification according to the mounting types onto the printed circuit board (PCB) and the package materials. Lead type package DIP (Dual In-line Package) Insertion type S-DIP (Shrink DIP) Area array package PGA (Pin grid array) Gull wing lead package Two-directionale type SOP (Small Outline Package) IC package SSOP (Shrink SOP) Four directionale type QFP (Quad Flat Package) TQFP (Thin QFP) Surface mount type J-lead package Four directionale type QFJ (PLCC) (Quad Flat J-leaded package) Non-lead package Four directionale type QFN (LCC) (Quad Flat Non-leaded package) Figure 1 Package Classification by Material and by Printed Circuit Board Mounting Method Introduction of Packages 2. Type Number and Package Code Indication The type number of Hitachi's 4-bit single-chip microcomputers is followed by the package material and outline specifications, as shown below. The package type used for each chip is identified by code as follows, illustrated on its data sheet. When placing an order, please write the package code beside the type number. Type Number Indication HDXXXXXXS HMCS400 series F: QFP FS: QFP H: QFP P: Plastic DIP S: Shrink-type plastic DIP C: Ceramic DIP TF: TQFP FT: SSOP FP: SOP Package Code Indication DP-64SA Additional outline 2 Number of pins Outline D: Dual in-line F: Flat TF: Flat with a mounting height of 1.27 mm or less 2 Materials P: Plastic C: Ceramic G: Glass-sealed ceramic Additional outline 1 S: Shrink type D: Dual lead type Introduction of Packages 3. Package Dimensional Outline Hitachi's 4-bit single-chip microcomputer devices employ the package types shown in table 1 according to the mounting method onto the PCB. Table 1 Package List Mounting Method Package Classification Package Material Package code Insertion type Standard package (DIP) Plastic DP-42 Shrink package (S-DIP) Plastic DP-28S DP-42S DP-64S Ceramic DC-64S Plastic FP-28DA FP-30D Plastic FP-44A, FP-54, FP-64A, FP-64B, FP-80A, FP-80B, FP-100A, FP-100B Surface mounting type Gullwing lead type Dual lead type (SOP) Quad lead type (QFP) Thin quad lead type Plastic (TQFP) TFP-80, TFP-80C TFP-80F, TFP-100B 3 Introduction of Packages Plastic DIP Unit: mm DP-42 21 0.48 0.10 Dimension including the plating thickness Base material dimension 4 0.51 Min 1.3 Max 2.54 0.25 15.0 Max 1.2 13.4 1 22 2.54 Min 5.06 Max 42 52.8 53.8 Max 15.24 + 0.11 0.25 - 0.05 0 - 15 Hitachi Code JEDEC Code EIAJ Code Weight DP-42 -- SC-512-42D 6.0 g Introduction of Packages Shrink type plastic DIP Unit: mm DP-28S 27.1 27.9 Max 28 8.8 14 0.48 0.10 0.51 Min 2.41 Max 1.78 0.25 10.16 5.10 Max 1.0 2.54 Min 1 10.8 Max 15 + 0.11 0.25 - 0.05 0 - 15 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC Code EIAJ Code Weight DP-28S -- SC-548-28B 1.9 g 5 Introduction of Packages Unit: mm DP-42S 37.3 38.6 Max 22 14.0 14.6 Max 42 21 1.0 2.54 Min 5.10 Max 1 1.78 0.25 0.48 0.10 0.51 Min 1.38 Max Dimension including the plating thickness Base material dimension 15.24 0.10 0.25 +- 0.05 0 - 15 Hitachi Code JEDEC Code EIAJ Code Weight DP-42S -- SC-551-42 4.8 g DP-64S 57.6 58.5 Max 33 17.0 18.6 Max 64 32 1.0 1.78 0.25 0.48 0.10 Dimension including the plating thickness Base material dimension 6 0.51 Min 1.46 Max 2.54 Min 5.08 Max 1 19.05 + 0.11 0.25 - 0.05 0 - 15 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) DP-64S -- SC-553-64A 8.8 g Introduction of Packages Shrink type ceramic DIP Unit: mm DC-64S 57.30 64 18.92 33 32 0.9 1.78 0.25 0.48 0.10 Dimension including the plating thickness Base material dimension 0.51 Min 1.50 Max 2.54 Min 5.60 Max 1 19.05 0.11 0.25 +- 0.05 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) DC-64S -- SC-553-64A 9.7 g 7 Introduction of Packages Small outline package (SOP) FP-28DA 18.00 18.75 Max 15 14 1.27 0.15 0.40 0.08 0.38 0.06 0.15 0.20 +- 0.10 1.27 Max 0.20 M Dimension including the plating thickness Base material dimension 8 0.17 0.05 0.15 0.04 1 3.00 Max 8.40 28 11.80 0.30 1.70 0 - 10 1.00 0.20 Introduction of Packages Unit: mm FP-30D 11.0 11.2 Max 16 1 15 8.0 30 0.65 0.32 0.08 0.30 0.06 0.10 0.10 0.10 1.05 Max 0.17 0.05 0.15 0.04 2.00 Max 0.10 M Dimension including the plating thickness Base material dimension 10.0 0.2 1.0 0 - 8 0.5 0.10 Hitachi Code JEDEC Code EIAJ Code Weight FP-30D -- -- -- 9 Introduction of Packages Quad flat package (QFP) Unit: mm FP-44A 17.2 0.3 14 23 33 22 44 12 0.8 17.2 0.3 34 0.15 M 3.0 0.10 Dimension including the plating thickness Base material dimension 10 0.17 0.05 0.15 0.04 0.37 0.08 0.35 0.06 2.70 3.05 Max 11 0.10 +0.15 -0.10 1 1.6 0 - 8 0.8 0.3 Hitachi Code JEDEC Code EIAJ Code Weight FP-44A -- ED-7404A 1.2 g Introduction of Packages Unit: mm FP-54 25.6 0.4 20 33 49 32 1.0 54 1 5 23 0.15 M 0 Min 2.0 Dimension including the plating thickness Base material dimension 2.8 0.17 0.05 0.15 0.04 0.37 0.08 0.35 0.06 3.10 Max 22 6 2.70 14 19.6 0.4 50 2.0 0 - 10 2.0 1.7 0.3 Hitachi Code JEDEC Code EIAJ Code Weight FP-54 -- -- 1.7 g 11 Introduction of Packages Unit: mm FP-64A 17.2 0.3 14 33 48 32 0.8 17.2 0.3 49 64 17 1 0.10 Dimension including the plating thickness Base material dimension 12 0.17 0.05 0.15 0.04 1.0 2.70 0.15 M 3.05 Max 16 0.10 +0.15 -0.10 0.37 0.08 0.35 0.06 1.6 0 - 8 0.8 0.3 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) FP-64A -- EDR-7311 1.2 g Introduction of Packages Unit: mm FP-64B 24.8 0.4 20 33 32 64 20 1.0 0.15 Dimension including the plating thickness Base material dimension 0.17 0.05 0.15 0.04 0.20 M 2.70 19 0.20 +0.10 -0.20 1 0.37 0.08 0.35 0.06 3.10 Max 1.0 52 14 18.8 0.4 51 2.4 1.0 0 - 10 1.2 0.2 Hitachi Code JEDEC Code EIAJ Code Weight FP-64B -- -- 1.7 g 13 Introduction of Packages Unit: mm FP-80A 17.2 0.3 14 60 41 40 80 21 0.65 17.2 0.3 61 1 0.10 Dimension including the plating thickness Base material dimension 14 0.17 0.05 0.15 0.04 0.83 2.70 0.12 M 3.05 Max 20 0.10 +0.15 -0.10 0.32 0.08 0.30 0.06 1.6 0 - 8 0.8 0.3 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) FP-80A -- EDR-7311 1.2 g Introduction of Packages Unit: mm FP-80B 24.8 0.4 20 41 65 40 80 25 0.15 Dimension including the plating thickness Base material dimension 2.70 0.8 0.17 0.05 0.15 0.04 24 0.15 M 0.20 +0.10 -0.20 1 0.37 0.08 0.35 0.06 3.10 Max 0.8 14 18.8 0.4 64 2.4 1.0 0 - 10 1.2 0.2 Hitachi Code JEDEC Code EIAJ Code Weight FP-80B -- -- 1.7 g 15 Introduction of Packages Unit: mm FP-100A 24.8 0.4 20 51 50 100 31 M 0.58 0.15 Dimension including the plating thickness Base material dimension 16 2.70 0.13 0.17 0.05 0.15 0.04 30 0.20 +0.10 -0.20 1 0.32 0.08 0.30 0.06 3.10 Max 0.65 81 14 18.8 0.4 80 2.4 0.83 0 - 10 1.2 0.2 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) FP-100A -- -- 1.7 g Introduction of Packages Unit: mm FP-100B 16.0 0.3 14 75 51 50 100 26 0.10 Dimension including the plating thickness Base material dimension 0.17 0.05 0.15 0.04 0.08 M 1.0 2.70 25 0.12 +0.13 -0.12 1 0.22 0.05 0.20 0.04 3.05 Max 0.5 16.0 0.3 76 1.0 0 - 8 0.5 0.2 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) FP-100B -- EDR-7311 1.2 g 17 Introduction of Packages Thin quad flat package (TQFP) Unit: mm TFP-80 15.6 0.3 14 60 41 40 80 21 0.65 15.6 0.3 61 0.10 Dimension including the plating thickness Base material dimension 18 0.17 0.05 0.15 0.04 0.83 1.00 0.13 M 1.20 Max 20 0.10 0.10 1 0.32 0.08 0.30 0.06 0.8 0-8 0.5 0.1 Hitachi Code JEDEC Code EIAJ Code Weight TFP-80 -- -- 0.5 g Introduction of Packages Unit: mm TFP-80C 14.0 0.2 12 60 41 40 80 21 0.5 14.0 0.2 61 0.10 Dimension including the plating thickness Base material dimension 0.10 0.10 1.25 1.00 0.10 M 0.17 0.05 0.15 0.04 20 1.20 Max 1 0.22 0.05 0.20 0.04 1.0 0 - 8 0.5 0.1 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) TFP-80C -- EDR-7311 0.4 g 19 Introduction of Packages Unit: mm TFP-80F 16.0 0.2 14 60 41 40 80 21 0.65 16.0 0.2 61 0.10 Dimension including the plating thickness Base material dimension 20 0.10 0.10 0.17 0.05 0.15 0.04 0.83 1.00 0.13 M 1.20 Max 20 1 0.32 0.08 0.30 0.06 1.0 0.5 0.1 Hitachi Code JEDEC Code EIAJ Code Weight 0 - 8 TFP-80F -- ED-7404A 0.5 g Introduction of Packages Unit: mm TFP-100B 16.0 0.2 14 75 51 50 100 26 1.0 0.10 Dimension including the plating thickness Base material dimension 1.00 0.08 M 0.17 0.05 0.15 0.04 25 0.10 0.10 1 0.22 0.05 0.20 0.04 1.20 Max 0.5 16.0 0.2 76 1.0 0 - 8 0.5 0.1 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) TFP-100B -- EDR-7311 0.5 g 21 Reliability and Quality Assurance Microcomputer devices are advancing rapidly in terms of functional capabilities and level of integration, and are being used in an increasingly wide range of applications. At the same time there are demands for significantly higher quality and reliability. Hitachi has made a commitment to meeting users' requirements through the establishment of an integrated quality and reliability system, covering all stages from planning and development through to after-sales service, with the goal of raising the level of technology in design, manufacturing, and inspection departments. The following describes Hitachi's semiconductor quality and reliability system, and presents reliability data for 4-bit single-chip microcomputer devices. Quality Assurance 1. Views on Quality and Reliability At Hitachi the basic views on quality are meeting the individual user's purchase needs and required quality, and to be at the satisfied quality level as considered for general marketability. The quality required by the users can be clearly specified by the contract specifications. If not, the quality required is not always definite. For both cases, efforts are made to assure the reliability so that the delivered semiconductor devices can perform their ability in actual operating conditions. To realize such quality in the manufacturing process, the key points should be: to establish a quality control system in the process, and to enhance morale for quality. In addition, the quality of the semiconductor devices required by the users is moving toward higher levels as the performance of electronic systems on the market is also moving higher and is expanding its size and application fields. To meet this situation, Hitachi bases its performance on the follow: 1. 2. 3. 4. Build in reliability with the design at the new product development stage. Build in quality at the manufacturing process sources. Execute tougher inspections and reliability confirmations of final products. Increase quality levels with field data feedback. In order to achieve a major improvement in quality, all departments work together with Hitachi's research laboratories in the pursuit of semiconductor device quality and reliability. With the views and methods mentioned above, utmost efforts are made to meet the users' requirements. Reliability and Quality Assurance 2. Reliability Design of Semiconductor Devices 2.1 Reliability Targets A reliability target is an important factor in manufacturing and sales as well as performance and price. It is not practical to rate the reliability target with failure rate at certain common test conditions. The reliability target is determined by taking the corresponding characteristics of the equipment such as design, manufacture, inner process quality control, screening and test method, etc., into consideration; other considerations in which the operating conditions of the equipment in which the semiconductor device is used in, reliability target of the system, derating applied in the design, operating conditions, and maintenance. 2.2 Reliability Design To achieve the reliability required based on reliability targets, design standardization, device design (including process design and structure design), design review, and reliability test are essential. 1. Design standardization The establishment of design rules and the standardization of parts, materials, and processes are necessary. As for the design rules, critical items on quality and reliability are always analyzed at the circuit design, device design, layout design, etc. Therefore, as long as the standardized processes and materials are used, the reliability failure risk is extremely small even in newly development devices, except for the case of including special requirements in functions. 2. Device design It is important in device design to consider the total balance of process design, structure design, and circuit and layout design. Especially for cases where new processes and new materials are employed, technical analysis is thoroughly executed prior to device development. 3. Reliability evaluation by test vehicle A test vehicle is sometimes called a test pattern. This is a useful method for the design and process reliability evaluation of ICs and LSIs which have complicated functions. * Purposes of the test vehicle are as follows: Verification of fundamental failure mode Analysis of the relationship between failure mode and manufacturing process conditions Search of failure mechanism analysis Establishment of QC points in manufacturing * Effectiveness of evaluation by the test vehicle are as follows: Common fundamental failure mode and failure mechanism in devices can be evaluated. Factors dominating failure mode can be categorized, and comparisons can be made with processes having been experienced in field. Ability to analyze the relationship between failure causes and manufacturing factors. Easy to run tests, etc. 2 Reliability and Quality Assurance 2.3 Design Review Design review is an organized method that confirms the design has satisfied the required performance including the specifications of the users and design work, and whether or not technical improvements accumulated in both the test data of major individual fields and field data are effectively built in. In addition, from the standpoint of enhancing competitive power in products, the major purpose of design review is to ensure the quality and reliability of the products. At Hitachi, design review is first performed from the planning stage of new products and design-modified products. The items considered and determined at design review are as follows: 1. Description of the products based on specified design documents. 2. From the view of individual specialties, execution of subprogram calculations, experiments, and investigations are carried out accordingly for any ambiguous information found within the design documents. 3. Determination of the contents of reliability and the methods based on the design document and drawings. 4. Checking the process ability of the manufacturing line to achieve the design goal. 5. Discussion on the preparation for production. 6. Planning and execution of subprograms: for any design changes proposed by the individual specialists; and for tests, experiments, and calculations to confirm the design change. 7. Reference of past failure experiences with similar devices, confirmation of prevention methods and planning and execution of test programs for their confirmation. These analyses and decisions are made using separate checklists created depending on the devices. 3. Quality Assurance System of Semiconductor Devices 3.1 Activity of Quality Assurance The general views of overall quality assurance at Hitachi are as follows: 1. Problems in individual processes should be solved during the process. Therefore, at the final product stage, potential failure factors have already been eliminated. 2. Feedback of information is needed to ensure satisfied levels of process capabilities. 3. The purpose of quality assurance is to assure the required reliability as a result of the above mentioned. The following are regards to device design, quality approval at mass production, inner process quality control, product inspection, and reliability tests. 3 Reliability and Quality Assurance 3.2 Quality Approval To ensure the quality and required reliability quality approval is executed at the trial production stage of the device design and the mass production stage based on the reliability design described in section 2. The views on quality approval are as follows: 1. 2. 3. 4. 5. The third party performs the approval objectively from the standpoint of the customers. Past failure experiences and on-field information are fully considered. Approval is necessary for any changes in design and work. Intensive approval is executed on parts, material, and process. Process capabilities and fluctuation factors are analyzed, and control points are setup at the mass production stage. Considering the views mentioned above, quality approval is performed as shown in figure 1. 3.3 Quality and Reliability Control at Mass Production For quality assurance of products in mass production, quality control is executed with essential division of function in manufacturing department, quality assurance department (major functions), and other related departments. The total function flow is shown in figure 2, and the main points are described below. 3.3.1 Quality Control of Parts and Material As the performance and the reliability of semiconductor devices are increasing the importance in quality control for materials and parts also increases; for example, crystals, lead frames, fine wires for wire bonding, and packages for IC production, and materials used in the manufacturing process such as mask patterns and chemicals. Besides quality approval on parts and materials as stated in section 3.2, the incoming inspection is also significant in the quality control of parts and materials. The incoming inspection is performed according to its specifications following purchase specifications and drawings, and the sampling inspection is executed based mainly on MIL-STD-105D. The other activities of quality assurance are as follows: 1. An outside-vendor technical information meeting 2. Approval on outside vendors, and guidance of outside vendors 3. Physical chemical analysis and testing The typical checkpoints of parts and materials are shown in table 1. 4 Reliability and Quality Assurance Step Contents Target specifications Design trial production Purpose Design review Characteristics of materials and parts: Appearance Dimension Heat resistance Mechanical Electrical Other Confirmation of characteristics and reliability of materials and parts Electrical characteristics: Function Voltage Current Temperature Other Appearance and dimension Confirmation of target specifications mainly on electrical characteristics Quality approval (1) Reliability test: Life test Thermal stress Moisture resistance Mechanical stress Other Confirmation of quality and reliability in design Quality approval (2) Reliability test: Process check same as quality approval (1) Confirmation of quality and reliability in mass production Materials and parts approval Characteristics approval Mass production Figure 1 Flowchart of Quality Approval 3.3.2 Inner Process Quality Control Inner process quality control is a very important function in quality assurance of semiconductor devices. The following is a description about the control of semifinal products, final products, manufacturing facilities, measuring equipment, and manufacturing conditions and submaterials. The quality control in the manufacturing process is shown in figure 3. 1. Quality control of semifinal products and final products Potential failure factors of semiconductor devices should be removed in the manufacturing process. To achieve this, check points are setup in each process, and products which have potential failure factors are not transferred to the next process. Especially for high reliability semiconductor devices, the manufacturing line is rigidly selected, and the quality control in the manufacturing process is strictly executed--rigid checks in each process and lot, 100% inspection to remove failure factors caused by manufacturing fluctuation, and screening methods such as high temperature aging and temperature cycling. The considerations of inner process quality control are as follows: 5 Reliability and Quality Assurance Process Quality Control Method Materials and parts Materials and parts Inspection of materials and parts Manufacturing Inspection of materials and parts for semiconductor devices Lot sampling and confirmation of quality level Manufacturing equipment, environment, submaterials and worker supervision Confirmation of quality level Screening In-process quality control Lot sampling and confirmation of quality level 100% inspection 100% inspection appearance and electrical characteristics Testing and inspection product inspection Sampling inspection on appearance and electrical characteristics Lot sampling Reliability test Confirmation of quality level Products Lot assurance test Receiving Feedback information Shipment Customer Quality information: Claim Field experience General quality Report Figure 2 Flowchart of Quality Control in Manufacturing Process * * * * * * 6 Condition control of individual equipment and workers, and sampling checks of semifinal products. Proposal and execution of work improvements. Education of workers Maintenance and improvement of yield Recognizing quality problems, and executing countermeasures Reports on quality Reliability and Quality Assurance Process Control Point Purpose of Control Purchase of material water Wafer Surface oxidation Inspection on surface oxidation Photoresist Oxidation Appearance; thickness of oxide film Scratches, removal of crystal Defective wafers Assurance of resistance Pinholes; scratches Photoresist Dimension; appearance Inspection on photoresist PQC level check Diffusion Characteristics; appearance Diffusion Inspection on diffusion PQC level check Diffusion depth; sheet resistance Gate width Characteristics of oxide film Evaporation Breakdown voltage Inspection on evaporation PQC level check Wafer inspection Evaporation Wafer Thickness of vapor film; Scratches; contamination Thickness; VTH characteristics Inspection on chip electrical characteristics Chip scribe Inspection on chip appearance PQC lot judgement Chip Electrical characteristics Assembling Assembling Dimension level check of photoresist Diffusion status Control of basic parameters (VTH, etc.); cleanness of surface; Prior check VIH breakdown voltage check Assurance of standard thickness Crack; prevention quality assurance of scribe Appearance of chip Frame PQC level check Package Inspection after assembling PQC lot judgement Sealing Sealing PQC level check Final electrical inspection Failure analysis Marking Appearance after chip bonding Appearance after wire bonding Pull strength; compression width; shear strength Appearance after assembling Quality check of chip bonding Appearance after sealing Outline; dimension Marking strength Guarantee of appearance and dimension Analysis of failures; failure mode; mechanism Feedback of analysis information Quality check of wire bonding Prevention of open and short circuits Appearance inspection Sampling inspection on products Receiving Shipment Figure 3 Example of Inner Process Quality Control 7 Reliability and Quality Assurance 2. Quality control of manufacturing facilities and measuring equipment The equipment for manufacturing semiconductor devices, which are important factors in determining quality and reliability, have been remarkably developed to produce the necessary high performance devices along with improvements in production. At Hitachi, the automation of manufacturing equipment promotes improvements in manufacturing fluctuation, and regulations have been established for maintaining the proper operation of high performance equipment and performance of required functions. As for the maintenance inspection for quality control, both daily inspections based on related specifications and periodical inspections are performed. During inspection, the specified inspection points are systematically checked off without allowing any exceptions to pass. For the calibration and control of measuring equipment, maintenance numbers, specifications, and calibration history are clearly indicated, and calibration interval control carried out. In inspection, standard equipment approved by public institutions is used, and the inspection points specified in the standards are checked in sequence to maintain and improve quality. 3. Quality control of manufacturing conditions and submaterials The quality and reliability of semiconductor devices are highly affected by the manufacturing process. Therefore, regulating the manufacturing conditions (i.e., temperature, humidity, and dust) and submaterials (i.e., gas and pure water) used in the manufacturing process are intensively carried out. Dust control is described in more detail below. Dust control is essential for realizing a higher degree of integration and higher reliability of the devices. At Hitachi, the maintenance and improvement of cleanness within the manufacturing site are executed by paying intensive attention to buildings, facilities, air-conditioning systems, materials delivered-in, clothes, work, etc., and including periodical inspections on floating dust within room, falling dust, and floor dirt. 3.3.3 Final Product Inspection and Reliability Assurance 1. Final product inspection Lot inspection is done by the quality assurance department for products which were judged as 100% good after testing, which is the final process in the manufacturing department. Although 100% is expected of the products sampling inspection is executed to prevent any mixture of failed products by mistake. The inspection is executed not only to confirm that the products meet the users' requirements, but to consider the potential factors. Lot inspection is executed based on MIL-STD-105D. 2. Reliability assurance tests To assure the reliability of semiconductor devices, periodical reliability tests and reliability tests on individual manufacturing lots required by the user are performed. 8 Reliability and Quality Assurance Table 1 Quality Control Checkpoints of Material and Parts (Example) Material/Parts Control Items Checkpoints Wafer Appearance Damage and contamination on surface Dimension Flatness Sheet resistance Resistance Defect density Number of defects Crystal axis Mask Appearance Number of defects Scratches Dimension Dimension level Resistoration Fine wire for wire bonding Gradation Uniformity of gradation Appearance Contamination; scratches; bendings; twists Dimension Frame Purity Purity level Elongation ratio Mechanical strength Appearance Contamination; scratches Dimension Dimension level Processing precision Ceramic package Plating Bondability; solderability Mounting characteristics Heat resistance Appearance Contamination; scratches Dimension Dimension level Leak resistance Airtightness Plating Bondability; solderability Mounting characteristics Heat resistance Electrical characteristics Plastic Mechanical strength Mechanical strength Composition Characteristics of plastic material Electrical characteristics Thermal characteristics Molding performance Molding performance Mounting characteristics Mounting characteristics 9 Reliability and Quality Assurance Customer Claim (failures and information) Sales dept. Sales engineering dept. Failure analysis Quality assurance dept. Design dept. Manufacturing dept. Countermeasures and execution of countermeasures Report Quality assurance dept. Follow-up and confirmation of countermeasure execution Report Sales engineering dept. Reply Customer Figure 4 Process Flowchart of Field Failure 10 Reliability and Quality Assurance 4. Reliability Design Major advances are being made in IC and LSI design and process technologies in the pursuit of higher reliability. Specific examples are the setting of target characteristics, reliability design for circuits and devices, process technologies such as crystal processing, epitaxial growth, impurity diffusion, ion implantation, auto-etching, surface stabilization, electrodes, bonding, and sealing, manufacturing process control techniques, as well as techniques for inspection, reliability evaluation, failure analysis, and so on. Higher reliability can only be achieved by raising the overall level of these technologies. Reliability design and its advantages with regard to processes are discussed below. 4.1 Surface Stabilization Technology Surface degradation, one of the major failure modes for semiconductor devices, is of two kinds, according to the degradation parameters and mechanism. In one case, the effects are due to the conductivity of the SiSiO 2 surface phase, as with PN junction reverse withstand voltage degradation, and changes over time in the threshold voltage (VTH) and mutual conductance in MOS devices, while in the other case, the effects are due to surface carrier recombination, as with current amplification factor degradation or low-frequency noise degradation. There are considered to be four major causes of surface degradation, as follows (see figure 5): Crackinter-layer shorting Coating defect, crack, pin holeAl corrosion PSG: P elutionA1 corrosion, characteristic deterioration 2nd passivation Poly-Si wiring (polysilicon) Al wiring Inter-layer insulating film SiO2 Diffusion layer Surface peeling 1st passivation Si substrate Pin holes penetration by contaminants Na contamination Figure 5 Surface Protective Film Divisions and Problems * Mobile ions (such as Na+) that infiltrate the first passivation film from the manufacturing process or the sealing material * The surface charge (Qss) and surface level at the Si-SiO 2 boundary * Pin hole flaws in the passivation film * A leakage charge on the second passivation film due to an electric field 11 Reliability and Quality Assurance There may also be a problem with mobile ion contamination at levels not previously a problem due to the high degree of integration and sophistication of the devices, and cases of extremely localized contamination, such as passivation flaws, that may result in fatal defects. To achieve Si surface stabilization, therefore, it is necessary to improve the getter effect with respect to mobile ions in the first passivation film, create a flawless film with surface stability and precision by means of a clean process, and have a threshold voltage (VTH) capable of withstanding a leakage charge. Meanwhile, the second passivation film plays an extremely important role in improving the reliability (moisture resistance) of the plastic sealing material, and requires the following characteristics. * The ability to prevent the penetration of moisture and contaminants from outside, and contaminating ions from the resin material itself * Passivation film quality capable of withstanding thermal stress in the resin material * A low flaw density In this regard, Hitachi is undertaking research and development in the areas of first and second passivation films and inter-layer insulating film, to improve the reliability of various semiconductor devices. Some of these improvements are described below. 65C 95% RH1000hr Al Corrosion Defect Rate (Relative Values) 1. PSG (phospho-silicate glass) for use as first and second passivation and inter-layer insulating film has been improved to provide better prevention of external contamination (improving the getter effect with respect to NA + ions) and moisture resistance (see figure 6). Sample plastic-packaged ICs (Specification A) 103 102 (Specification B) 10 (Specification C) 1 1 10 102 103 104 Second Passivation Flaw Density (Relative Values) Figure 6 Passivation Flaw Density and Moisture Resistance 2. Clean, flaw-free process: This is especially important for the first passivation film, and the aim is to develop cleaner processing, including higher purity of process materials such as the photoresist, cleaning agent, and vapor deposition Al, cleaner oxidization oven silica tubes, and also a flaw-free process, including improved vapor deposition methods, higher photomask quality, improved wafer handling methods, and the prevention of dust in the process. 12 Reliability and Quality Assurance 3. Leakage charge countermeasures: The design threshold voltage (VTH) is increased by the formation of channel stopper layer using ion implantation technology, or the use of a thicker passivation film. 4. Process control: In addition to the BT (bias-temperature) method of process control relating to mobile ions, Hitachi also carries out [INPURA ??] quantity control using special MOS elements, and automatic film thickness measurement by optical means during polysilicon film creation. 4.2 Electrode Formation and Assembly Technology These processes are represented in chip electrode formation, die bonding which fixes the chip in the package, and wire bonding which connects the chip electrodes to the leads. The technical level of these processes has a great effect on reliability. The main failure modes that occur in these processes are summarized below. * Disconnection or shorting due to electromigration in the Al vapor deposition wiring, or disconnection in areas with a level difference * Bonding disconnection, semi-disconnection, or shorting * Chip cracking * Increased resistance or disconnection due to a compound between the Au and Al metals * Bonding wire fatigue and disconnection due to repeated thermal stress * Increased thermal resistance and chip separation with soft solder die bonding Hitachi is engaged in appropriate structural design to cope with these causes of defects, and incorporates reliability into the manufacturing process. As regards bonding, for example, Hitachi was quick to develop a computer-controlled, fully automatic thermocompression wire bonding system, which is being used on the production line to ensure stable quality. Regarding process quality control, in addition to the conventional visual inspection used in pre-sealing inspection, Hitachi carries out contour control of the fine wiring in the chip, and bonding contour control, using a scanning electron microscope. 4.3 Plastic Sealing Technology Semiconductor device sealing methods consist of hermetic sealing using metal, ceramic, or low-meltingpoint glass, and plastic sealing using plastic material. Hermetic sealing has a long history, and there are no particular problems regarding materials or sealing technology. Leak tests have also been established, and airtightness is guaranteed by conducting major and minor leak tests. Plastic-packaged semiconductor devices, meanwhile, which came about in the pursuit of lower cost, have come to play a major role in extending the range of areas in which semiconductors are used, and are now the mainstream type. The features of plastic-packaged semiconductor devices in terms of reliability are outlined below. The main failure modes of plastic-packaged semiconductor devices are disconnection due to corrosion of the aluminum used in electrode wiring, and wire bonding disconnection. 13 Reliability and Quality Assurance The main cause of the former is moisture that penetrates via the interface between the plastic and the lead frame, or moisture that permeates the plastic material itself. This moisture penetration is accelerated by impurity ions extracted from the plastic, voltages between electrode wires, and humidity, corroding the electrode wiring and, if there is a large amount of penetrating moisture, finally leading to disconnection. With the latter failure mode, temperature variations result in internal stress because of the different coefficients of thermal expansion and elastic coefficients of the materials of which the device is composed (Si chip, bonding wire, lead frame, and plastic). If the weakest point, the pointing wire, cannot withstand this stress, disconnection will result. Various improvements have been adopted from a system standpoint which combines improvements that affect the electrical characteristics of the device with improvements in plastic materials, mold technology, structural design, and surface stabilization film, in addition to In dealing with the two main failure modes described above. 14 Reliability Test Data of Microcomputer Reliability of Microcomputer Devices 1. Structure Four-bit single-chip microcomputer devices are available in plastic and ceramic packages. Figure 1 shows examples of the package structure. The structure of COMS 4-bit single-chip microcomputer devices varies depending on the manufacturing process and circuit configuration. There are generally two kinds of gates, Al gates and Si gates. Hitachi mainly uses devices with an Si gate structure, because the alignment of the gate parts is comparatively precise and easy to implement, allowing high reliability to be achieved. Plastic DIP Flat Plastic Package Bonding wire Chip Chip Bonding wire Plastic Plastic Tab Lead Lead Figure 1 Package Structure Si-Gate CMOS PSG Gate Al S G P-channel EMOS FET1 P+ N+ N+ D D P+ P-Well SiO2 Source Drain FET2 N-channel EMOS G S (FET2 only) Figure 2 Chip Structure and Basic Circuit Reliability Test Data of Microcomputer 2. Reliability Data 2.1 HMCS400 Series Reliability Test Result The reliability test results of HMCS400 Series are shown in table 1 to table 4. The data is classified by package type, DIP and QFP. Table 1 Operation Life (Mask ROM): (Condition: VCC = 6.0 V, Ta = 125C) Chip Package Samples Component Hours (C.H.) Failures HD404019R DIP 45 45,000 0 QFP 45 45,000 0 HD404304 DIP 45 45,000 0 HD404439 QFP 45 45,000 0 HD404618 QFP 45 45,000 0 TQFP 45 45,000 0 HD404678 QFP 45 45,000 0 HD404719 QFP 45 45,000 0 HD404729 DIP 45 45,000 0 QFP 45 45,000 0 DIP 45 45,000 0 SOP 45 45,000 0 DIP 45 45,000 0 QFP 45 45,000 0 DIP 45 45,000 0 QFP 45 45,000 0 HD404339 DIP 45 45,000 0 HD404449 QFP 45 45,000 0 TQFP 45 45,000 0 HD404459 QFP 45 45,000 0 HD404629R QFP 45 45,000 0 TQFP 45 45,000 0 QFP 45 45,000 0 TQFP 45 45,000 0 QFP 45 45,000 0 TQFP 45 45,000 0 HD404222 HD404318 HD404328 HD404818 HD404829R 2 Reliability Test Data of Microcomputer Table 2 Moisture Resistance (Mask ROM): (Condition: 65C, 95%RH) High Temperature High Humidity Storage Chip Package 168 Hours 500 Hours 1000 Hours HD404019R DIP 0/116 0/116 0/116 QFP 0/77 0/77 0/77 HD404304 DIP 0/116 0/116 0/116 HD404618 QFP 0/77 0/77 0/77 TQFP 0/45 0/45 0/45 DIP 0/116 0/116 0/116 QFP 0/77 0/77 0/77 DIP 0/45 0/45 0/45 SOP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD404339 DIP 0/45 0/45 0/45 HD404449 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 HD404459 QFP 0/45 0/45 0/45 HD404629R QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 HD404729 HD404222 HD404318 HD404328 HD404818 HD404829R 3 Reliability Test Data of Microcomputer Table 2 Moisture Resistance (Mask ROM) (cont): Pressure Cooker Test (Condition: 121C, 202.65 kPa (2 atm)) Chip Package 40 Hours 60 Hours 100 Hours HD404019R DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 SOP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD404339 DIP 0/22 0/22 0/22 HD404449 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404459 QFP 0/22 0/22 0/22 HD404629R QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404618 HD404729 HD404222 HD404318 HD404328 HD404818 HD404829R 4 Reliability Test Data of Microcomputer Table 2 Moisture Resistance (Mask ROM) (cont): High Temperature, High Humidity Bias (Condition: 85C, 85%RH, VCC = 5.5 V) Chip Package 168 Hours 500 Hours 1000 Hours HD404618 QFP 0/22 0/22 0/22 TQFP 0/32 0/32 0/32 HD404729 DIP 0/22 0/22 0/22 HD404019R DIP 0/32 0/32 0/32 QFP 0/32 0/32 0/32 DIP 0/32 0/32 0/32 SOP 0/32 0/32 0/32 DIP 0/32 0/32 0/32 QFP 0/32 0/32 0/32 DIP 0/32 0/32 0/32 QFP 0/32 0/32 0/32 HD404339 DIP 0/32 0/32 0/32 HD404449 QFP 0/32 0/32 0/32 TQFP 0/32 0/32 0/32 HD404459 QFP 0/32 0/32 0/32 HD404629R QFP 0/32 0/32 0/32 TQFP 0/32 0/32 0/32 QFP 0/32 0/32 0/32 TQFP 0/32 0/32 0/32 QFP 0/32 0/32 0/32 TQFP 0/32 0/32 0/32 HD404222 HD404318 HD404328 HD404818 HD404829R 5 Reliability Test Data of Microcomputer Table 3 Temperature Cycling (Mask ROM): (Condition: -55C to +150C) Chip Package 10 Cycles 100 Cycles 200 Cycles HD404019R DIP 0/135 0/45 0/45 QFP 0/90 0/45 0/45 HD404304 DIP 0/135 0/45 0/45 HD404618 QFP 0/135 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/90 0/45 0/45 HD404678 HD404729 HD404222 HD404318 HD404328 DIP 0/215 0/45 0/45 QFP 0/90 0/45 0/45 DIP 0/45 0/45 0/45 SOP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD404339 DIP 0/45 0/45 0/45 HD404449 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD404459 HD404629R HD404818 HD404829R 6 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 Reliability Test Data of Microcomputer Table 4 High Temperature, Low Temperature, Storage (Mask ROM): High Temperature Storage (Condition: +150C) Chip Package 168 Hours 500 Hours 1000 Hours HD404019R DIP 0/22 0/22 0/22 HD404304 DIP 0/22 0/22 0/22 HD404618 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404678 QFP 0/22 0/22 0/22 HD404729 DIP 0/22 0/22 0/22 HD404222 DIP 0/22 0/22 0/22 SOP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD404339 DIP 0/22 0/22 0/22 HD404449 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404459 QFP 0/22 0/22 0/22 HD404629R QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404318 HD404328 HD404818 HD404829R 7 Reliability Test Data of Microcomputer Table 4 High Temperature, Low Temperature, Storage (Mask ROM) (cont): Low Temperature Storage (Condition: -55C) Chip Package 168 Hours 500 Hours 1000 Hours HD404618 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404729 DIP 0/22 0/22 0/22 HD404019R DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 SOP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD404339 DIP 0/22 0/22 0/22 HD404449 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404459 QFP 0/22 0/22 0/22 HD404629R QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD404222 HD404318 HD404328 HD404818 HD404829R 8 Reliability Test Data of Microcomputer 2.2 4-Bit ZTAT Microcomputer Reliability Test Result The reliability test results of four-bit ZTAT microcomputer are shown in table 5 to table 10. Table 5 Operation Life (ZTAT): (Condition: VCC = 5.5 V, Ta = 125C) Chip Package Samples Component Hours (C.H.) Failures HD4074019 DIP 45 45,000 0 QFP 32 32,000 0 HD4074308 DIP 45 45,000 0 HD4074618 QFP 45 45,000 0 TQFP 45 45,000 0 HD4074719 QFP 45 45,000 0 HD4074729 DIP 45 45,000 0 HD4074224 DIP 45 45,000 0 SOP 45 45,000 0 DIP 45 45,000 0 QFP 45 45,000 0 DIP 45 45,000 0 QFP 45 45,000 0 HD4074339 DIP 45 45,000 0 HD4074449 QFP 45 45,000 0 HD4074629 QFP 45 45,000 0 HD4074818 QFP 45 45,000 0 TQFP 45 45,000 0 QFP 45 45,000 0 HD4074318 HD4074329 HD4074829 9 Reliability Test Data of Microcomputer Table 6 Moisture Resistance (ZTAT): (Condition: 65C, 95%RH) High Temperature, High Humidity Storage Chip Package 168 Hours 500 Hours 1000 Hours HD4074308 DIP 0/116 0/116 0/116 HD4074618 QFP 0/77 0/77 0/77 TQFP 0/45 0/45 0/45 HD4074719 QFP 0/77 0/77 0/77 HD4074729 DIP 0/116 0/116 0/116 QFP 0/77 0/77 0/77 DIP 0/45 0/45 0/45 SOP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD4074339 DIP 0/45 0/45 0/45 HD4074449 QFP 0/45 0/45 0/45 HD4074629 QFP 0/45 0/45 0/45 HD4074818 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD4074224 HD4074318 HD4074329 HD4074829 10 Reliability Test Data of Microcomputer Table 6 Moisture Resistance (ZTAT) (cont): Pressure Cooker Test (Condition: 121C, 202.65 kPa (2 atm)) Chip Package 40 Hours 60 Hours 100 Hours HD4074019 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD4074308 DIP 0/22 0/22 0/22 HD4074618 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD4074719 QFP 0/22 0/22 0/22 HD4074729 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 SOP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD4074339 DIP 0/22 0/22 0/22 HD4074449 QFP 0/22 0/22 0/22 HD4074629 QFP 0/22 0/22 0/22 HD4074818 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD4074224 HD4074318 HD4074329 HD4074829 11 Reliability Test Data of Microcomputer Table 7 Temperature Cycling (ZTAT): (Condition: -55C to +150C) Chip Package 10 Cycles 100 Cycles 200 Cycles HD4074019 DIP 0/115 0/45 0/45 QFP 0/90 0/45 0/45 HD4074308 DIP 0/135 0/45 0/45 HD4074618 QFP 0/90 0/45 0/45 TQFP 0/45 0/45 0/45 HD4074719 QFP 0/90 0/45 0/45 HD4074729 DIP 0/135 0/45 0/45 QFP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 SOP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 DIP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD4074339 DIP 0/45 0/45 0/45 HD4074449 QFP 0/45 0/45 0/45 HD4074629 QFP 0/45 0/45 0/45 HD4074818 QFP 0/45 0/45 0/45 TQFP 0/45 0/45 0/45 QFP 0/45 0/45 0/45 HD4074224 HD4074318 HD4074329 HD4074829 12 Reliability Test Data of Microcomputer Table 8 High Temperature, Low Temperature, Storage (ZTAT): High Temperature Storage (Condition: +150C) Chip Package 48 Hours 168 Hours 500 Hours 1000 Hours HD4074308 DIP 0/160 0/22 0/22 0/22 HD4074408 DIP (ceramic) 0/255 0/104 0/104 0/104 DIP 0/260 0/44 0/44 0/44 QFP 0/103 0/32 0/32 0/32 QFP 0/160 0/22 0/22 0/22 TQFP 0/100 0/22 0/22 0/22 HD4074719 QFP 0/140 0/22 0/22 0/22 HD4074729 DIP 0/240 0/22 0/22 0/22 HD4074224 DIP 0/100 0/22 0/22 0/22 SOP 0/100 0/22 0/22 0/22 DIP 0/100 0/22 0/22 0/22 QFP 0/100 0/22 0/22 0/22 DIP 0/100 0/22 0/22 0/22 QFP 0/100 0/22 0/22 0/22 HD4074339 DIP 0/100 0/22 0/22 0/22 HD4074449 QFP 0/100 0/22 0/22 0/22 HD4074629 QFP 0/100 0/22 0/22 0/22 HD4074818 QFP 0/100 0/22 0/22 0/22 TQFP 0/100 0/22 0/22 0/22 QFP 0/100 0/22 0/22 0/22 HD4074618 HD4074318 HD4074329 HD4074829 13 Reliability Test Data of Microcomputer Table 8 High Temperature, Low Temperature, Storage (ZTAT) (cont): Low Temperature Storage (Condition: -55C) Chip Package 168 Hours 500 Hours 1000 Hours HD4074019 DIP 0/22 0/22 0/22 HD4074308 DIP 0/22 0/22 0/22 HD4074618 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 HD4074719 QFP 0/22 0/22 0/22 HD4074729 DIP 0/22 0/22 0/22 HD4074224 DIP 0/22 0/22 0/22 SOP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 DIP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD4074339 DIP 0/22 0/22 0/22 HD4074449 QFP 0/22 0/22 0/22 HD4074629 QFP 0/22 0/22 0/22 HD4074818 QFP 0/22 0/22 0/22 TQFP 0/22 0/22 0/22 QFP 0/22 0/22 0/22 HD4074318 HD4074329 HD4074829 14 Reliability Test Data of Microcomputer Table 9 Mechanical and Environment Test Results DIP QFP TQFP SOP Test Test Conditions Samples Failures Samples Failures Samples Failures Samples Failures Thermal shock 0C to 100C 10 cycles 210 0 Soldering heat 260C, 10 sec 246 0 Solderability 230C, 5 sec, rosin flux 132 0 88 0 22 Salt water spray 35C, NaCl 5%, 110 0 66 0 Drop test 75 cm, maple board 44 0 40 60 0 160 0 150 0 22 0 22 0 0 22 0 22 0 22 0 0 22 0 22 0 40 0 22 0 22 0 22 0 22 0 22 0 Refer table 11 24 hours 3 times Lead integrity Stretching 500 g, 10 sec (DIP) 250 g, 10 sec (QFP, TQFP, SOP) Bending 250 g, 90, 3 times (DIP) 250 g, 90, 1 time (QFP, TQFP, SOP) 15 Reliability Test Data of Microcomputer Table 10 Soldering Heat Resistance Infrared Reflow (Conditions: 235C, 10 Seconds) and Solder Dip (Conditions: 260C, 10 Seconds) Chip Package Pre Conditions Hours Samples Failures HD404019R QFP 85C, 85%RH 24 hours 22 0 HD404439 QFP 85C, 85%RH 48 hours 22 0 HD404618 QFP 85C, 85%RH 48 hours 22 0 TQFP 85C, 85%RH 48 hours 22 0 HD404729 QFP 85C, 85%RH 48 hours 22 0 HD404222 SOP 85C, 85%RH 96 hours 22 0 HD404449 QFP 85C, 85%RH 48 hours 22 0 TQFP 85C, 85%RH 48 hours 22 0 QFP 85C, 85%RH 48 hours 22 0 TQFP 85C, 85%RH 48 hours 22 0 QFP 85C, 85%RH 48 hours 22 0 TQFP 85C, 85%RH 24 hours 22 0 HD4074224 SOP 85C, 85%RH 24 hours 22 0 HD4074449 QFP 85C, 85%RH 24 hours 22 0 TQFP 85C, 85%RH 24 hours 22 0 QFP 85C, 85%RH 24 hours 22 0 TQFP 85C, 85%RH 24 hours 22 0 HD404629 HD4074618 HD4074629 3. Precaution 3.1 Storage The following lists preferable measures for storing semiconductor devices to prevent the possibility of breakage and the deterioration of its electrical characteristics, solderability, and appearance. 1. 2. 3. 4. 5. Store at an ambient temperature of 5 to 30C with a relative humidity of 40% to 60%. Store in an environment of clean air, free from dust and active gases. Store the devices within containers which do not induce static electricity. Keep the devices free of any physical loads. If the devices are to be stored for a long period of time, store the devices of which the leads have not yet been bent. The bent leads of these devices will corrode at the areas of bending during its storage. 6. If the device is not in a sealed container, store it in a cool, dry, dark, and ductless area. Assemble the devices within 5 days after they have been unpacked. Storing devices in nitrogen gas is desirable. Using dry nitrogen gas with a dew point at -30C or lower allows the devices to be stored for up to 20 days. Unpacked devices must not be stored for more than 3 months. 16 Reliability Test Data of Microcomputer Be particularly careful when surface mount packages are soldered by a process that heats the entire packages, because the packages may crack due to absorption of moisture. Care must be taken to not allow condensation to occur during storage due to rapid temperature changes. 3.2 Transportation As with storage methods, general precautions for other electronic component parts are applicable for the transportation of semiconductors, mounted semiconductor units, and other similar systems. In addition, the following considerations must also be given: 1. Use containers or jigs which will not induce static electricity as the result of vibration during transportation. It is preferable to use an electrically conductive container or aluminium foil. 2. In order to prevent the devices from being damaged by static-electricity-induced clothes, workers should be properly grounded with a resistor while handling the devices. A resistor of about 1 M must be provided for the worker to protect the devices from electric shock. Figure 3 illustrates measured data concerning static electricity on a human body. 3. When transporting the printed circuit boards of the mounted semiconductor devices, preventive measures against static electricity must be taken; for example, voltage buildup is prevented by shorting the terminal circuits. When a conveyor belt is used, prevent the conveyor belt from being electrically charged by applying some surface conduction. 4. When transporting semiconductor devices or printed circuit boards, mechanical vibration and shock must be minimizied. Electric charges on the body and clothing varies greatly depending on the type of clothing, footwear, build, ambient temperature and humidity, and so on. Some actual examples are given below. Actual Examples of Body Charges Conditions a Shirt, 100% cotton a, b: Clothing c, d: Metal tub c a b b d Max. Voltage Ambient Conditions + 4,900V (1) b Shirt, PVC synthetic fiber - 13,000V a Shirt, PVC synthetic fiber - 3,500V b Shirt, 100% cotton + 7,200V (2) a Bare skin - 410V (3) b Shirt, 100% cotton + 980V a Bare skin + 3,200V b Shirt, PVC synthetic fiber + 7,000V (4) Insulating material Ambient temperature: 20C Relative humidity: 40% Steel sheet Static capacitance between steel sheet and metal tub: 50 pF Insulation resistance: 1.5 x 1012 Method of Measuring Body Charge Article a is put on over the bare skin, and article b over this. During this operation, the subject is grounded. The ground wire is removed, then article b is taken off and thrown into tub b. In these examples, the potential at this point is measured. The "bare skin" case, a, in (3) and (4) in the table refers to the case where one article of clothing is worn and friction occurs directly between the body and the clothing. Figure 3 Examples of Body Charge Measurements 17 Reliability Test Data of Microcomputer 3.3 Handling during Measurement Avoid static electricity, noise, and surge voltages when measuring semiconductor devices. During transportation or storage, damage to devices can be prevented by shorting their terminal circuits to equalize their electrical potential. However, when the devices are to be measured or mounted, these shorted terminals are left open to introduce the possibility of accidentally being touched by someone or by measuring equipment, work benches, soldering irons, conveyor belts, etc. The devices will fail if they come in contact with something which leaks current or carries a static charge. Be careful not to allow curve tracers, synchroscopes, pulse generator, dc stabilizing power supply units, etc., to leak current from their terminals or housings to the devices. While the devices are being tested, take special care to not apply a surge voltage from the tester, to attach a clamping circuit to the tester, and to not allow any abnormal voltages through bad contacts from the current source. During measurement, avoid miswirings and short circuits. When inspecting a printed circuit board, make sure that no soldering bridges or foreign matter exist before turning on the power switch. Since these precautions depend upon the types of semiconductor devices, contact Hitachi for further details. 3.4 Special handling precautions 1. Be sure to observe the absolute maximum ratings and to use a device under derated conditions, if possible. 2. Be sure to minimize any thermal stress as well as humidity stress. 3. Do not apply excessive force between the leads and the chip housing when forming leads. 4. Be sure to avoid applying static electricity while handling, transporting or storing a device. Ensure complete grounding. 5. Avoid introducing surge from a tester to a chip during measurement. 6. No specification should be exceeded by applying a surge voltage/current or static electricity to a chip, even after system assembly is completed. 7. Take countermeasures, such as fail-safe provisions, according to the application when designing a microcomputer system. 8. Be sure to carry out system debugging using a parts-mounted test. 9. Refer to any application notes described in the respective data sheets when using a microcomputer device with on-chip EPROM. 10. Placing a device of the plastic package type in a high electric field may cause surface leakage due to charging, resulting in incorrect operation. Avoid using a device where there is a high electric field. Be sure to cover the package surface with a conductive shield plate if a device is used in a high electric field. 11. Contact our technical engineers beforehand when using a device under special operating conditions. 18 Reliability Test Data of Microcomputer Table 11 No.1 Solderability Defects in Storage Type of defect Solderability defects during storage Table 12 Description Remedy Classification A cardboard magazine and black rubber were used for storing devices, causing the color of the leads to change as well as defective solderability. The surface of the lead formed sulfides due to sulfurous compounds in the magazine used for storage. Be sure to use a storage case and magazine for storing devices which do not react with lead materials. Especially, avoid any sulfurous compounds. Other (storage) No.2 Static Discharge Breakdown during Transportation and Storage Type of defect Description Remedy Classification Static discharge breakdown during transportation and storage During the production process of a device, a normal device became defective after board assembly before being mounted. Devices were stacked, and the device was destroyed by the application of the charge accumulated on a capacitor facing the device. (1) Be sure to insert insulation between the device boards before transportation. Other (storage, transportation) Table 13 (2) Discharge capacitors before transportation. (3) Separate the device boards. No.3 Static Discharge Breakdown during Measurement Type of defect Description Remedy Classification Static discharge breakdown during measurement During automatic device measurement, a static electrical charge accumulated on the plastic guide rails while sliding the devices. This charge was discharged by the measuring head, destroying the input circuit of the device. This failure occurred when the humidity was low; it did not occur at high humidity. (1) The plastic rails were replaced with metallic rails, which would not cause static electricity. Other (measurement) (2) The guide rails were grounded. 19 Reliability Test Data of Microcomputer Table 14 No.4 Breakdown during Measurement Type of defect Breakdown during measurement Description Remedy Classification (1) While measuring output voltage VOL from the bus driver, applying a constant input current, IOL , (100 to 300 mA) destroyed a device. (1) Use voltage application instead of current application. Other (measurement) (2) While measuring the withstand voltage (for ICs with a strength of 70 V or more), applying a current (1 mA) generated a similar failure. (2) Apply a voltage equivalent to the withstand voltage for current measurement. (3) While measuring the withstand voltage, noise was superimposed on the constant-current source. This caused current to enter the negative range, which also destroyed the device. 3.5 Application Notes for the Surface-Mount Packages 1. Temperature distribution on the package The infrared reflow method is most generally used for surface mounting. Since the package is made of black epoxy resin, the area directly exposed to infrared radiation is most likely to absorb heat, which will increase the temperature locally compared to other areas, if no countermeasures are taken. In the example shown in figure 4, the temperature of the area exposed to infrared radiation is 20 to 30 C higher than the soldered leads, and 40 to 50 C higher than the bottom surface of the package. Performing solder mounting under such conditions may cause cracks in the package. 20 Reliability Test Data of Microcomputer Infrared (Epoxy resin) (Thermocouple) 300 Temperature (C) T3 250 T2 T1 (Solder) T1 T2 200 T3 150 60s 100 30s Time (sec) Figure 4 Typical Temperature Profile when Mounting Solder with Infrared Heating 2. Humidity absorption of the package Humidity absorption by the epoxy resin used for a plastic package is difficult to avoid in a highhumidity environment. A large amount of absorbed water rapidly vaporizes during the solder mounting process. This could cause detachment at the surface between the resin and the lead frame. In the worst case, it may cause the package to crack. Therefore, devices, especially of the thin-package type, should be stored in a dry box. To remove any water absorbed during transportation, storage or handling, we recommend baking at 125 C for 16 to 24 hours before performing the solder mounting process. 3. Temperature increase and refrigeration The solder dip method is one of the solder mounting procedures used for electronic parts. The heattransfer coefficient with this method is of an order greater than with the reflow method, causing a larger thermal shock to plastic products. As this may cause package cracking and decreased humidity resistance, use of this method is limited to certain products. Note that rapid temperature increases and refrigeration should also be avoided even if the reflow method is used. Be sure to set an appropriate condition at a target of 4 C/sec or less. 4. Contamination around the package A rosin-type flux is recommended for use in soldering. A chlorine-type flux is likely to remain on the package, which can reduce the reliability of the product. Avoid using flux of this type. If any flux, including rosin-type flux, remains on the package, leads can become corroded. Therefore, thorough cleaning and removal are required. Note that some detergents may erase marks printed on the package if in contact with the package for a long period of time. 21 Reliability Test Data of Microcomputer General precautions have been outlined above. Note that the reflow conditions may vary with the shape of the package and printed-circuit board, the type of reflow and equipment. For reference, Figure 5 shows reflow conditions using a QFP infrared reflow chamber. The numbers in this figure refer to the temperatures at the package resin. Be sure to limit the temperature at the lead section to a maximum of 260 C for no longer than 10 seconds. Also ensure that the temperature difference between the surface and reverse side of the resin is 10 C or less. Although the infrared reflow method is most typically used, the vapor-phase reflow method is also used. Figure 6 shows the recommended reflow conditions when using a vapor-phase reflow chamber. Whether the solder dip method can be used depends on the product type; contact our sales engineers for details. Figure 7 shows the recommended conditions for the solder dip method. For small and thin packages of the surface-mount type, refer to the separate manuals for the mounting procedure. Contact our sales engineers for details. Temperature 235 C (max.) 10 sec. (max.) 140 to 160 C Approx. 60 sec. 1 to 4 C/sec. 1 to 5 C/sec. Time Figure 5 Recommended Infrared Reflow Conditions Temperature 215 C 30 sec. (max.) 140 to 160 C Approx. 60 sec. 1 to 5 C/sec. Time Figure 6 Recommended Vapor-Phase Reflow Conditions 22 Reliability Test Data of Microcomputer Baking (1 to 3 min.) Dipping Cooling (2 to 4 sec.) Surface temperature of the substrate 80 to 150 C Tmax = 260 C Solder melting point Natural air cooling or forced air cooling Time Figure 7 Recommended Solder Dip Conditions 23 Programmable ROM (ZTAT) Microcomputer ZTATTM Microcomputer with Built-in Programmable ROM 1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-V CC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n Programmable ROM (ZTAT) Microcomputer connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. 2. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. For details on the procedure for setting up PROM mode, see the PROM mode schematic for the individual product actually being used. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 1. 2 Programmable ROM (ZTAT) Microcomputer Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 2. If it is programmed erroneously to an address given in table 2 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product employs a V PP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258 specifications. Table 1 Selection of Mode (Example of HD404829R Series) Mode CE OE VPP O0 - O7 Write "Low" "High" VPP Data input Verify "High" "Low" VPP Data output Prohibition of programming "High" "High" VPP High impedance Table 2 PROM Writer Program Address (Example of HD404829R Series) ROM size Address 8k $0000 - $3FFF 12k $0000 - $5FFF 16k $0000 - $7FFF Writing/verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure 1 and a timing chart in figure 2. For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATT M Microcomputer's Built-in Programmable ROM and precautions for its Applications." 3 Programmable ROM (ZTAT) Microcomputer $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . $1FFF $2000 . . . . . . . . . . . . . 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 Program (16,384 words) JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B, INT2 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to A/D, serial routine) $3FFF $7FFF Upper three bits are not to be used (fill them with 111) Figure 1 Memory Map in PROM Mode (Example of HD404829R Series) 4 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Programmable ROM (ZTAT) Microcomputer Start Set write/verify modes VCC = 6.0 0.25 V, VPP = 12.5 0.3V Address = 0 n=0 n + 1 n Yes No Program t PW =1 ms 5% n < 25? Address + 1 Address Verification OK? Go Program t OPW = 3n ms Last address? No Yes VCC Reject Set read mode = 5.0 0.5 V, VPP = VCC 0.6 V No Read all addresses Yes End Figure 2 Flowchart of High-Speed Programming 5 Programmable ROM (ZTAT) Microcomputer Programming Electrical Characteristics DC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0V, T a = 25C 5C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Input high voltage level VIH O0 to O7, A0 to A14, OE, CE 2.2 -- VCC + 0.3 V Input low voltage level VIL O0 to O7, A0 to A14, OE, CE -0.3 -- 0.8 V Output high voltage level VOH O0 to O7 2.4 -- -- V IOH = -200 A Output low voltage level VOL O0 to O7 -- -- 0.4 V IOL = 1.6 mA O0 to O7, A0 to A14, OE, CE -- -- 2 A Vin = 5.25 V/0.5 V Input leakage IIL current Unit VCC current ICC -- -- 30 mA VPP current IPP -- -- 40 mA Test Condition AC Characteristics (VCC = 6.0 V 0.25 V, V PP = 12.5 V 0.3 V, T a = 25C 5C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Condition Address setup time tAS 2 -- -- s See figure 3 OE setup time tOES 2 -- -- s Data setup time tDS 2 -- -- s Address hold time tAH 0 -- -- s Data hold time tDH 2 -- -- s Data output disable time tDF -- -- 130 ns VPP setup time tVPS 2 -- -- s Program pulse width tPW 0.95 1.0 1.05 ms CE pulse width during overprogramming tOPW 2.85 -- 78.75 ms VCC setup time tVCS 2 -- -- s Data output delay time tOE 0 -- 500 ns 6 Programmable ROM (ZTAT) Microcomputer Input pulse level: 0.8 V to 2.2 V Input rise/fall time: 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Write Verify Address t AH t AS Data Data in Stable t DS V PP V CC V PP V CC V CC GND Data out Valid t DH t DF t VPS t VCS CE t PW OE t OES t OE t OPW Figure 3 PROM Write/Verify Timing 7 Programmable ROM (ZTAT) Microcomputer Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTATT M microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 1). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: * Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. * Heat excites trapped electrons, allowing them to escape. * High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate Control gate SiO2 SiO2 Floating gate Floating gate Drain Source N+ N+ Write (0) Drain Source N+ N+ Erasure (1) Figure 1 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT TM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: * Check that the socket adapter is firmly mounted on the PROM programmer. * Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. 8 Programmable ROM (ZTAT) Microcomputer PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT TM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 2. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi. Programming, verification Exposure to high temperature, without power 150C 10C, 48 h +8 h * -0 h Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150C. Figure 2 Recommended Screening Procedure Normal programming rate: The normal programming rate is guaranteed to be 95% or higher. 2. Handling window-package product Glass erase window: Rubbing the glass erase window with a plastic object or attaching any electrically charged material to it may generate static electricity on the window surface, resulting in faulty chip operation. In this case, apply ultraviolet light to the window for a short time to neutralize the electrical charge, then return to the normal condition. This procedure, however, also reduces the charge accumulated on the floating gate at the same time; thus, a re-programming operation is recommended. Since the basic cause of the problem is the electrical charge on the window, the remedy is to avoid any charge. The following countermeasures are similar to those against static discharge breakdown for general ICs: * Ground the human body when handling the product. Do not use gloves which can cause static electricity. 9 Programmable ROM (ZTAT) Microcomputer * Do not rub the glass window with a plastic object which is likely to generate static electricity. * Take care when using a refrigerant spray, since some products may include a few undesirable ions. * Use an ultraviolet shielding label (especially one containing conductive material), since it effectively equalizes the surface charge. Handling after programming the EPROM: Since a small amount of ultraviolet light is emitted by a fluorescent lamp or sunlight, exposing a chip to such light for a long time may cause memory information to invert. In addition, the device may malfunction if exposed to strong light due to the effect of a photoelectric current. It is therefore advisable to attach a light-proof label (e.g. ultraviolet shielding label) to cover the glass erase window before using the device. Special labels for this purpose are commercially available. In general, any label that contains metal can effectively absorb ultraviolet light. The following should be considered when selecting a shielding label. 1. Adhesive property (mechanical strength) Re-attaching the same label or using a label with attached dust should be avoided since it reduces adhesive strength. Since static electricity may be generated when detaching a label, it is recommended that erasure using ultraviolet light and re-programming be performed after detaching any label (when replacing a label, use a method such as attaching the new label over the old one, for instance). 2. Allowable temperature range Take care concerning the shielding-label requirements for the allowable temperature range as well as the ambient temperature used. The use of a label under conditions exceeding the allowable temperature range may harden the adhesive, which can cause the label to peel off easily. This also causes the adhesive to stick to the glass window, and to remain on the glass window after detaching the label. 3. Moisture-proof property Take care concerning the shielding-label requirements for the allowable humidity range as well as the ambient humidity. It is very difficult to find a shielding label which can be used in any ambient conditions allowed for all currently released MCU models. Therefore, an appropriate shielding label should be selected according to the application. 10 Program Development Procedure and Support Systems 1. General Description Hitachi provides cross assemblers and emulators as a support environment for user program development. User developed programs can then be downloaded into ZTATTM memory and the microcomputer can be installed in the user system, either for sample production or for mass production. Hitachi also supports ROM mask programming and the delivery of mask ROM microcomputers with user software in ROM as ICs. Figure 1 shows the typical design procedure. Procedure Description (1) When a user constructs a system using an HMCS400 Series microcomputer, before designing the rogram, the user first designs the system and allocates I/O pins and RAM to the required functions according to the system design. (2)To implement the required functions, the user then designs the algorithms using flowcharts. Then the user codes the program in HMCS400 assembler language based on those flowcharts. (3)The software coded according to the flowcharts is then written to a floppy disk, completing the creation of the program. (4)The source program is assembled and linked on a host computer to create a load module. At this time the user also checks for and corrects errors in the program. (5)Hardware simulation is used to verify program operation. Hitachi provides a wide range of hardware emulators for this purpose. (6)The program is then delivered to Hitachi either as an EPROM or as a ZTATTM microcomputer. The user also submits two forms, the Single-Chip Microcomputer Request Specifications form and the Mask Option List form. (7)Hitachi creates a mask program from the ROM and the mask options, fabricates ICs, and presents sample ICs to the user. The user evaluates the samples, and mass production starts when the user has verified that the ICs are programmed correctly. Program Development Procedure and Support Systems EPROM or ZTATTM Start Allocation of RAM and I/O (1) Flowchart (2) (6) EPROM Artwork M/T (3) Source program Pattern generator tape Editor (4) Assemble list Assemble/link Cross assembler system Mask OK? Test production EPROM Yes Load module program Sample Sample evaluation Yes (5) Hardware simulation (7) OK? OK? No No No Emulator, EPROM microcomputer, PROM microcomputer Yes Masked ROM Mass production ZTAT Mass production Figure 1 Program Design Procedure 2. Emulation The Hitachi emulators for 4-bit single-chip microcomputers provide powerful support for both the hardware and software aspects of system development. The emulation system consists of a combination of an emulator unit (the HS400EUA02H), one or more of a wide range of target probes, the E400 emulator itself (the HS400EPI01H), and user system interface cables. 2 Program Development Procedure and Support Systems 2.1 Emulator unit Features The HS400EUA02H has the following features: * A wide range of emulation commands for efficient development. * Support for a wide range of target chips by exchanging the target probe and the user system interface cables. * Is provided in its own case and, since it operates on 100 VAC line power, does not require a separate power supply. * Small footprint (92 x 353 mm) that does not require much bench space. Functions The HS400EUA02H provides the following functions: * Executes user programs in real time. * Sets breakpoints Combination breakpoints: Up to four breakpoints can be set based on arbitrary values of the program counter, address/data bus, data memory content, external probe signals, pass count, and other aspects. PC breakpoint: The entire memory area can be specified according to the program counter. * Displays trace results without stopping program execution using trace stop mode. * Real-time trace: Records and displays up to 2000 steps of bus information and external signals before and after a breakpoint. Also displays data memory R/W signals, data, the stack level, and other information. * Symbolic debugging: Supports debugging using symbolic information for breaking, tracing, and other operations. * Execution time measurement: Measure program execution time in microseconds for run times of up to one hour. * Line assembler: Allows the contents of memory to be modified in assembler language. * Disassembler * Single-step trace: Traces the user program and displays the contents of MCU registers and data memory at a specified address after each inspection execution cycle. * Register display and modification * Program and data memory display and modification * Coverage function * Self-diagnostics function 3 Program Development Procedure and Support Systems Dedicated target probe Host Emulator unit Dedicated target probe User cable User system Common target probe or E400 Emulator Evaluation chip-set Host Emulator unit Common target probe User cable User system User cable User system Evaluation chip-set Host E400 Emulator Evaluation chip-set * 4 E400 Emulator Structure of HMCS400 Series Emulator Set Program Development Procedure and Support Systems Table 1 Emulator Commands Category Command Function Object program management L Loads object program and symbol information V Verifies object program P Saves object program Execution G Executes user program S Traces user program in single steps Setting break conditions BP Sets, displays, and cancels program counter (PC) break TR Sets, displays, and cancels combination break conditions BR1 BR2 BR3 Management of memory and registers Support of debugging I Displays and modifies program memory contents ID Dumps program memory contents IMAP Sets and displays the program memory area T Transfers object program C Compares object program M Displays and modifies data memory contents MD Dumps data memory contents MMAP Sets and displays data memory area DEF Sets address to display data memory contents during the halt of user program execution R Displays and modifies register values IO Displays and modifies I/O port contents CONT Restarts realtime trace from subcommand wait Q Displays realtime trace results HE Displays all emulator commands A Line assemble DA Disassemble O Searches for bit pattern CO Displays and clears coverage data F Sets and displays MCU clock mode TIM Sets and displays MCU timer operation N Designates transfer rate SYM Defines, clears, and displays symbols, and selects the attribute of the symbols to be loaded 5 Program Development Procedure and Support Systems 2.2 General-purpose target probe While we at Hitachi have provided target probes for each IC product, we have also released a general-purpose target probe that can support a wide range of ICs when the evaluation chip and/or the data ROM in a system is exchanged. This product will increase the efficiency of our customers' investments. We intend to make all possible efforts to assure that new products will also be compatible with this general-purpose target probe. However, there are certain microcomputers that this target probe cannot support due to the functions provided by those microcomputers. Emulator structural units An emulator system consists of four components: the emulator unit, the general-purpose target probe, the chip set, and the user system interface cables. Alternatively, the E400 emulator, which combines the emulator unit and the general-purpose target probe in a single unit, can be used. * Either the HS400EUA02H, which is provided in a case, or the earlier HS400EUA01H can be used. * The model number of the general-purpose target probe is HS400ETA01H. * The chip set consists of the evaluation chip and data ROM, and is selected according to the microcomputer for which debugging is to be performed. * The model number has the form HS4xx(x)ERSvrH, where 4xx(x) is the three or four digit abbreviated product name, and vr indicates the product version number. * The user system interface cable is selected according to the microcomputer package. Note that the user system interface cables used with the earlier target probes cannot be used with the general-purpose target probe. 2.3 E400 emulator The emulator unit and the general-purpose target probe have been miniaturized and combined in a single B5-sized unit to support an even wider range of development environments. Features The E400 emulator (HS4000EPI01H) has the following features: * The same functions previously provide by two products, an emulator unit and a target probe. * Support for high-speed operation (Example: 8 MHz with the HD404639R Series) * Development using a source code debugger. * Bus monitor mode connection, which allows display of internal RAM data in LEDs in real time during user program execution. (Function expansion option: under development) 6 Program Development Procedure and Support Systems 2.4 Source code debugger HS4000ISIW1SF Runs under the Windows*1 operating system on IBM PC*2 compatible personal computers. * Source level debugging functions: Source display Setting and clearing breakpoints in the source code Display and modification of symbol contents in the source code * Multiwindow display Wide range of information reference and manipulation functions (source, memory, register, trace, break settings, and other information) * Menu format Manipulations using menu selection * Test support functions Coverage display Command chain execution Execution result acquisition * Help functions Online help Guideline messages Notes: 1. Windows is a registered trademark of Microsoft. 2. IBM PC is a registered trademark of International Business Machines, Inc. 7 Program Development Procedure and Support Systems 3. System Software Development Standards for Single-Chip Microcomputer Applications 3.1 Basics of application system development As shown in figure 2, single-chip microcomputer application system development consists of hardware and software development. In principle, the customer is responsible for all aspects of system development. However, if for one of the following reasons, * Insufficient software development staff, * Lack of experience in software development, or * Inadequate debugging tools, when the customer is considering developing system software for a single-chip microcomputer application, they feel they are not able to develop the required software, Hitachi will undertake the development of the required software for a fee. Single-chip microcomputer application system development Hardware development Software development Figure 2 Single-Chip Microcomputer Application System Development 3.2 When requesting application system software development Table 2 lists the division of labor and responsibilities when Hitachi accepts a request for single-chip microcomputer application system software development. Program development request: The customer must prepare in advance the following documents, which are created as items 1, 2, 3, and 4 in table 2 when a customer requests software development from Hitachi. 1. System functional description document 2. Peripheral circuit design diagrams 3. Program specifications document (Including general flowcharts.) 4. System development planning documents and production planning documents Furthermore, we strongly recommend extensive discussions between the customer and Hitachi in advance concerning details of the software production. Hitachi cannot accept modifications to the above items once a request for program development has been accepted. However, in the event of unavoidable changes, contact Hitachi as quickly as possible. 8 Program Development Procedure and Support Systems Table 2 Division of Responsibility in Software Development No. Item 1 Production of system functional description documents 2 Production of peripheral circuit design diagrams 3 Production of a program specifications document 4 Production of system development planning documents and production planning documents 5 Production of detailed program flowcharts 6 Production of program code listings 7 Assembling and debugging the program 8 Writing the program to EEPROM and installing it in an evaluation board 9 Production of test units 10 Debugging in the test units 11 Debugging in an actual system 12 Production of mask ROM tapes or EEPROMs 13 Production of a program design document Two copies will be delivered 14 Program approval One copy returned to Hitachi after approval Notes: Customer Hitachi Notes Including general flowcharts : Handled by the person in charge at the corresponding company. : Indicates joint operations. The numbers in the No. column correspond to the numbers in parentheses in figure 3. 9 Program Development Procedure and Support Systems Start System functional specifications selection (1) Microcomputer selection Rough design if peripheral circuits (2) Program specifications design (Including general flowcharts) (3) System production planning (Production planning document) (4) NG Check 1 OK [Hardware] [Software] Detailed peripheral circuit design (2) Detailed flowchart production (5) Evaluation unit production (9) Coding (6) Assembly and debugging Debugging in evaluation units (10) Debugging in actual systems (11) (7), (8) NG Check 2 OK Mask ROM code production (12) Program design specifications document production (13) Program acceptance (14) End Items in parentheses refer to the No. column in table 2. Figure 3 Software Development Procedure 10 Program Development Procedure and Support Systems Program development: Hitachi will develop the program according to the program specifications document provided by the customer. The fee for this development effort will depend on the size of the program developed. (Consult your Hitachi sales representative for details of the fee schedule.) The program will be developed so that it meets the program specifications document, but note that it will not meet any specifications not explicitly stated in the program specifications document. If the size of the developed program exceeds the capacity of the on-chip ROM, Hitachi will request, based on consultations with the customer, the removal of requirements from the program specifications document. Program debugging: In program debugging, what is checked is whether or not the developed program meets the requirements of the program specifications document. The customer must provide an evaluation unit that includes the required peripheral circuits for this process. The program will be debugged by connecting the evaluation unit to an evaluation board provided by Hitachi. A representative from the customer should be present during this process. When we have completed this debugging process, we will present the evaluation unit and the evaluation board to the customer for a final check. If required, the customer should install the evaluation board in an actual system and test the software in an actual system. If the result of this check is that the program does not meet the specifications in the program specifications document, the customer should request corrections from Hitachi. Completion of program development: After the final checks using the evaluation unit and the provided evaluation board have been completed, the customer will receive the following items: * Program design document (Includes a program acceptance form) ... Two copies This includes a description of the program, flowcharts, and a program listing. * Mask ROM paper tape or EEPROM ... One set will be provided. After you have verified the program and have accepted it, please return one copy of the program design document (which includes a program acceptance form) to Hitachi. This completes the program development procedure. After service: Hitachi makes all possible efforts to develop programs without errors. However, it is not possible to say either that all program errors will be discovered in the debugging stage, or that the customer's final check will have revealed all program errors. If any errors remain, Hitachi will correct the program. However, the procedures used and the charges for those corrections shall be determined by a separate agreement between Hitachi and the customer. 11 Instruction Set The MCU has 101 instructions, classified into the following ten groups: * * * * * * * * * * Immediate instructions Register-to-register instructions RAM address instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM address instructions Input/output instructions Control instructions The functions of these instructions are listed in tables 1 to 10, and an opcode map is shown in table 11. Symbols and Abbreviations AB Transfer from A to B A B Exchange between A and B X Logical negation (NOT) 1 High level 0 Low level NZ Not Zero* NB No borrow* OVF Overflow* AND OR Exclusive OR Not equals Less than or equal to % Denotes binary number $ Denotes hexadecimal number i, m, p 1-digit hexadecimal number ($0-$F) d 3-digit hexadecimal number ($000-$FFF) n 2-bit binary number a 6-bit binary number b 8-bit binary number u Combination of p (1-digit hexadecimal number) and d (3-digit hexadecimal number) y, x 1 or 0 * Status goes high with NZ, NB or OVF. Instruction Set Table 1 Immediate Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from Immediate LAI i 1 0 0 0 1 1 i3 i2 i1 i0 i A 1/1 Load B from Immediate LBI i 1 0 0 0 0 0 i3 i2 i1 i0 i B 1/1 Load Memory from Immediate 0 1 1 0 1 0 i3 i2 i1 i0 i M d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2/2 LMID i, d Load Memory from LMIIY i Immediate, Increment Y Table 2 1 0 1 0 0 1 i3 i2 i1 i0 i M, Y+1Y NZ 1/1 Register-to-Register Instructions Function Words/ Status Cycles Operation Mnemonic Operation Code Load A from B LAB 0 0 0 1 0 0 1 0 0 0 BA 1/1 Load B from A LBA 0 0 1 1 0 0 1 0 0 0 AB 1/1 Load A from W LAW* 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WA 2/2*1 Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 YA 1/1 Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX A 1/1 Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY A 1/1 Load A from MR LAMR m 1 0 0 1 1 1 m3 m2 m1 m0 MR(m) A 1/1 Exchange MR and A XMRA m 1 0 1 1 1 1 m3 m2 m1 m0 MR(m) A 1/1 2 Notes: 1. The assembler automatically provides an operand for the second word of the LAW instruction. 2. This instruction is not available for the following: * HD404222 * HD40L4222 * HD404201 * HD404202 * HD40L4201 * HD40L4202 * HD4074224 2 Instruction Set Table 3 RAM Address Instructions Operation Mnemonic Operation Code Function Words/ Status Cycles Load W from Immediate LWI i*3 0 0 1 1 1 1 0 0 i1 i0 i W 1/1 Load X from Immediate LXI i 1 0 0 0 1 0 i3 i2 i1 i0 i X 1/1 1 0 0 0 0 1 i3 i2 i1 i0 i Y 1/1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 AW 2/2*1 Load Y from Immediate LYI i 2 Load W from A LWA* Load X from A LXA 0 0 1 1 1 0 1 0 0 0 AX 1/1 Load Y from A LYA 0 0 1 1 0 1 1 0 0 0 AY 1/1 Increment Y IY 0 0 0 1 0 1 1 1 0 0 Y + 1 Y NZ 1/1 Decrement Y DY 0 0 1 1 0 1 1 1 1 1 Y - 1 Y NB 1/1 Add A to Y AYY 0 0 0 1 0 1 0 1 0 0 Y + A Y OVF 1/1 Subtract A from Y SYY 0 0 1 1 0 1 0 1 0 0 Y - A Y NB 1/1 Exchange X and SPX XSPX 0 0 0 0 0 0 0 0 0 1 X SPX 1/1 Exchange Y and SPY XSPY 0 0 0 0 0 0 0 0 1 0 Y SPY 1/1 Exchange X and SPX, Y and SPY XSPXY 0 0 0 0 0 0 0 0 1 1 X SPX, Y SPY 1/1 Notes: 1. The assembler automatically provides an operand for the second word of the LAW instruction. 2. This instruction is not available for the following: * HD404222 * HD40L4222 * HD404201 * HD404202 * HD40L4201 * HD40L4202 * HD4074224 3. This instruction is not available for the compact microcomputers: HD404222, HD40L4222, HD4074224, HD404201, HD404202, HD40L4201 and HD40L4202. 3 Instruction Set Table 4 RAM Register Instructions Status Words/ Cycles Operation Mnemonic Operation Code Function Load A from Memory LAM(XY) 0 0 1 0 0 1 0 0 y x M A, (X SPX, Y SPY) 1/1 Load A from Memory LAMD d 0 1 1 0 0 1 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 MA 2/2 Load B from Memory LBM(XY) 0 0 0 1 0 0 0 0 y x M B, (X SPX, Y SPY) 1/1 Load Memory from A LMA(XY) 0 0 1 0 0 1 0 1 y x A M, (X SPX, Y SPY) 1/1 Load Memory from A LMAD d 0 1 1 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AM 2/2 Load Memory from A, Increment Y LMAIY(X) 0 0 0 1 0 1 0 0 0 x A M, Y+1Y (X SPX) NZ 1/1 Load Memory from A, Decrement Y LMADY(X) 0 0 1 1 0 1 0 0 0 x A M, Y-1Y (X SPX) NB 1/1 Exchange Memory and A XMA(XY) 0 0 1 0 0 0 0 0 y x M A, (X SPX, Y SPY) 1/1 Exchange Memory and A XMAD d 0 1 1 0 0 0 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M A 2/2 Exchange Memory and B XMB(XY) 0 0 1 1 0 0 0 0 y x M B, (X SPX, Y SPY) 1/1 Note: (XY) and (X) have the following meanings: Each instruction with (XY) has four mnemonics, each with different object codes. For example, different values of X and Y of the opcode of the LAM(XY) instruction are given below. Mnemonic LAM LAMX LAMY LAMXY y 0 0 1 1 x 0 1 0 1 Function None X SPX Y SPY X SPX, Y SPY Each instruction with (X) has two mnemonics, each with different object codes. For example, different values of X of the opcode of the LMAIY(X) instruction are given below. Mnemonic LMAIY LMAIYX 4 X 0 1 Function None X SPX Instruction Set Table 5 Arithmetic Instructions Function Words/ Status Cycles i0 A+iA OVF 1/1 1 0 0 B+1B NZ 1/1 1 1 1 1 B-1B NB 1/1 0 0 1 1 0 1/1 1 0 1 0 1 0 1/1 1 1 0 0 0 0 0 A+1A 1/1 1 0 0 0 0 0 0 B B 1/1 0 1 0 1 0 0 0 0 0 1/1 0 0 1 0 1 0 0 0 0 1 1/1 SEC 0 0 1 1 1 0 1 1 1 1 1 CA 1/1 Reset Carry REC 0 0 1 1 1 0 1 1 0 0 0 CA 1/1 Test Carry TC 0 0 0 1 1 0 1 1 1 1 Add A to Memory AM 0 0 0 0 0 0 1 0 0 0 Add A to Memory AMD d Add A to Memory with Carry AMC Operation Mnemonic Operation Code Add Immediate to A AI i 1 0 1 0 0 0 i3 i2 i1 Increment B IB 0 0 0 1 0 0 1 Decrement B DB 0 0 1 1 0 0 Decimal Adjust for Addition DAA 0 0 1 0 1 Decimal Adjust for Subtraction DAS 0 0 1 0 Negate A NEGA 0 0 0 Complement B COMB 0 1 0 Rotate Right A with Carry ROTR 0 Rotate Left A with Carry ROTL Set Carry CA 1/1 M+AA OVF 1/1 0 1 0 0 0 0 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M+AA OVF 2/2 0 M+A+ CA A OVF CA OVF 1/1 0 0 0 0 1 1 0 0 0 Add A to Memory with AMCD d Carry 0 1 0 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M+A+ CA A OVF CA OVF 2/2 Subtract A from Memory with Carry SMC 0 M-A- CA A NB CA NB 1/1 Subtract A from Memory with Carry SMCD d 0 1 1 0 0 1 1 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M-A- CA A NB CA NB 2/2 OR A and B OR 0 1 0 1 0 0 0 1 0 0 A B A AND Memory with A ANM 0 0 1 0 0 1 1 1 0 0 AM A NZ 1/1 AND Memory with A ANMD d 0 1 1 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AM A NZ 2/2 OR Memory with A ORM 0 A M A NZ 1/1 OR Memory with A ORMD d 0 1 0 0 0 0 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A M A NZ 2/2 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 1/1 5 Instruction Set Operation Mnemonic Operation Code EOR Memory with A EORM 0 EOR Memory with A EORMD d Note Function Status Words/ Cycles A M NZ A 1/1 0 1 0 0 0 1 1 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A M NZ A 2/2 Function Words/ Status Cycles iM NZ 1/1 0 0 0 0 1 1 1 0 0 : Logical AND : Logical OR : Exclusive OR Table 6 Compare Instructions Operation Mnemonic Operation Code Immediate Not Equal to Memory INEM i 0 Immediate Not Equal to Memory INEMD i,d 0 1 0 0 1 0 I3 I2 I1 I0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 iM NZ 2/2 A Not Equal to Memory ANEM 0 AM NZ 1/1 A Not Equal to Memory ANEMD d 0 1 0 0 0 0 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AM NZ 2/2 B Not Equal to Memory BNEM 0 0 0 1 0 0 0 1 0 0 BM NZ 1/1 Y Not Equal to Immediate YNEI i 0 0 0 1 1 1 i3 i2 i1 i0 Yi NZ 1/1 Immediate Less than or Equal to Memory ILEM i 0 0 0 0 1 1 i3 i2 i1 i0 iM NB 1/1 Immediate Less than or Equal to Memory ILEMD i,d 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 iM NB 2/2 A Less than or Equal to Memory ALEM 0 AM NB 1/1 A Less than or Equal to Memory ALEMD d 0 1 0 0 0 1 0 1 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AM NB 2/2 B Less than or Equal to Memory BLEM 0 0 1 1 0 0 0 1 0 0 BM NB 1/1 A Less than or Equal to Immediate ALEI i 1 0 1 0 1 1 i3 i2 i0 Ai NB 1/1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 i3 0 0 i2 i1 1 0 1 0 i1 i0 0 0 Instruction Set Table 7 RAM Bit Manipulation Instructions Mnemonic Operation Code Set Memory Bit SEM n 0 1 n1 n0 1 M(n) 1/1 Set Memory Bit SEMD n,d 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 M(n) 2/2 Reset Memory Bit REM n 0 0 n1 n0 0 M(n) 1/1 Reset Memory Bit REMD n,d 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 M(n) 2/2 Test Memory Bit TM n 0 1 n1 n0 M(n) 1/1 Test Memory Bit TMD n,d 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M(n) 2/2 Table 8 0 0 0 1 1 0 0 1 0 0 0 0 Function Words/ Status Cycles Operation 0 0 0 0 1 1 ROM Address Instructions Mnemonic Operation Code Branch on Status 1 BR b 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1/1 Long Branch on Status 1 BRL u 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Long Jump Unconditionally JMPL u 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Subroutine Jump on Status 1 CAL a 0 a5 a4 a3 a2 a1 a0 1 1/2 Long Subroutine Jump on Status 1 CALL u 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Table Branch TBR p 0 0 1 0 1 1 p3 p2 p1 p0 1/1 Return from Subroutine RTN 0 0 0 0 0 1 0 0 0 0 1/3 Return from Interrupt RTNI 0 0 0 0 1 0 0 0 1 1 1 1 1 0 Function Words/ Status Cycles Operation 2/2 1 I/E ST CA recovery 1/3 7 Instruction Set Table 9 Input/Output Instructions Operation Mnemonic Operation Code Function Set Discrete I/O Latch SED 0 0 1 1 1 0 0 Set Discrete I/O Latch Direct SEDD m 1 0 1 1 1 0 Reset Discrete I/O Latch RED 0 0 0 1 1 Reset Discrete I/O Latch Direct REDD m 1 0 0 1 Test Discrete I/O Latch TD 0 0 Test Discrete I/O Latch Direct TDD m 1 Load A from R-Port Register LAR m Load B from R-Port Register Words/ Status Cycles 1 D(Y) 1/1 m3 m2 m1 m0 1 D(m) 1/1 0 0 0 D(Y) 1/1 1 0 m3 m2 m1 m0 0 D(m) 1/1 1 1 1 0 0 0 1 0 1 0 m3 m2 m1 m0 1 0 0 1 0 1 m3 m2 m1 m0 R(m) A 1/1 LBR m 1 0 0 1 0 0 m3 m2 m1 m0 R(m) B 1/1 Load R-Port Register from A LRA m 1 0 1 1 0 1 m3 m2 m1 m0 A R(m) 1/1 Load R-Port Register from B LRB m 1 0 1 1 0 0 m3 m2 m1 m0 B R(m) 1/1 Pattern Generation Pp 0 1 1 0 1 1 p3 p2 p1 p0 Table 10 1 0 1 0 0 0 0 0 0 D(Y) 1/1 D(m) 1/1 1/2 Control Instructions Mnemonic Operation Code No Operation NOP 0 0 0 0 0 0 0 0 0 0 1/1 Start Serial STS 0 1 0 1 0 0 1 0 0 0 1/1 Stand-by Mode/ Watch Mode SBY 0 1 0 1 0 0 1 1 0 0 1/1 Stop Mode/ Watch Mode STOP 0 1 0 1 0 0 1 1 0 1 1/1 8 Function Words/ Status Cycles Operation Instruction Set Table 11 Opcode Map 1 RTN RTNI 7 8 LBM(XY) AYY LASPY RED LASPX YNEI 9 A XMA(XY) SEM n(2) LAM(XY) LMA(XY) B C 1 2 3 4 5 SYY LYA E TD SED LXA 8 COMB ALEMD TC XMAD LAMD ANM F i(4) SBY STOP JMPL CALL p(4) p(4) REMD n(2) SMCD LMID E EORMD p(4) LMAD C D ORMD *3 STS SEMD n(2) LAY B i(4) BRL TM n(2) A AMCD OR IY 9 AMD ANEMD p(4) D LMADY(X) 7 ILEMD DAS LBA 6 INEMD IB SMC BLEM F 0 *1 LAW *1 LWA EORM REM n(2) TBR XMB(XY) F i(4) DAA ROTR ROTL E i(4) 6 8 C D ORM LAB BNEM 7 B i(4) 5 LMAIY(X) NEGA A AMC ILEM 4 9 AM INEM 3 1 6 ALEM 2 0 1 0 R8 R9 H L 0 1 2 3 4 5 0 NOP XSPX XSPY XSPXY ANEM TMD n(2) ANMD i(4) P p(4) CAL a(6) BR b(8) DB DY REC SEC LWI i*2 (2) 0 LBI i(4) 1 LYI i(4) 2 LXI i(4) 3 LAI 4 LBR m(4) 5 LAR m(4) 6 REDD m(4) 7 LAMR m(4) 8 AI 9 LMIIY A TDD i(4) i(4) i(4) m(4) B ALEI i(4) C LRB m(4) D LRA m(4) E SEDD m(4) F XMRA m(4) ... 1-word/2-cycle instruction ... 1-word/3-cycle ... RAM direct address instruction instruction (2-word/2-cycle) ... 2-word/2-cycle instruction Notes: 1. This instruction is not available for the following: * HD404222 * HD40L4222 * HD404201 * HD404202 * HD40L4201 * HD40L4202 * HD4074224 9 Instruction Set 2. This instruction is not available for the compact microcomputers, HD404222, HD40L4222, HD4074224, HD404201, HD40L4201, HD404202 and HD40L4202. 3. The STS instruction is not available for the HD404201, HD40L4201, HD404202 and HD40L4202. 10 General Purpose Microcomputer HD404019R Series Rev. 5.0 March 1997 Description The HD404019R series are HMCS400-series CMOS 4-bit single-chip microcomputers. Each device incorporates a ROM, RAM, I/O, serial interface, and two timer/counters, and contains high-voltage I/O pins including high-current output pins to directly drive fluorescent displays. The HD404019R series includes four chips. The HD404019R and HD40L4019R are Mask ROM versions. The HD4074019 and HD407L4019 are PROM versions. The HD40L4019R and HD407L4019 are lowvoltage operation versions. Features * 16,384-word x 10-bit ROM Mask ROM: HD404019R, HD40L4019R PROM: HD4074019, HD407L4019 * 992-digit x 4-bit RAM * 58 I/O pins, including 26 high-voltage I/O pins (40 V max.) * Two timer/counters 8-bit free-running timer 8-bit auto-reload timer/counter * Clock synchronous 8-bit serial interface * Five interrupt sources Two by external sources Two by timer/counters One by serial interface * Subroutine stack, up to 16 levels including interrupts * Minimum instruction execution time: 0.89 s * Low-power dissipation modes Standby: Stops instruction execution while allowing clock oscillation and interrupt functions to operate Stop: Stops instruction execution and clock oscillation while retaining RAM data HD404019R Series * On-chip oscillator Crystal or ceramic oscillator External clock * Packages 64-pin shrink type plastic DIP 64-pin flat plastic package 64-pin shrink type ceramic DIP with window Ordering Information Type Product Name Model Name Package Mask ROM HD404019R HD404019RS DP-64S HD404019RH FP-64A HD404019RFS FP-64B HD40L4019RS DP-64S HD40L4019RH FP-64A HD4074019S DP-64S HD4074019H FP-64A HD4074019FS FP-64B HD4074019C DC-64S HD407L4019S DP-64S HD407L4019H FP-64A HD40L4019R ZTAT HD4074019 HD407L4019 ZTAT: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd. 2 HD404019R Series Differences between ZTAT and Mask ROM Version ZTAT Mask ROM Version Item HD4074019 HD407L4019 HD404019R HD40L4019R Power supply voltage (V) 4.5 to 5.5 V 3.0 to 5.5 V 3.5 to 6.0 V 2.7 to 6.0 V Instruction cycle time (tcyc ) 0.89 to 20 s 1.12 to 20 s 0.89 to 10 s 1.12 to 10 s ROM (word) 16,384 x 10-bit 16,384 x 10-bit 16,384 x 10-bit 16,384 x 10-bit 992 x 4-bit 992 x 4-bit 992 x 4-bit 992 x 4-bit RAM 1 I/O pin circuit* Oscillator stabilization*2 Package Standard pins NMOS open drain NMOS open drain Each pin can be without pull-up MOS (NMOS open drain), with pull-up MOS, or CMOS High voltage pins PMOS open drain PMOS open drain Each pin can be without pull-down MOS (PMOS open drain) or with pull-down MOS Crystal Available Available Available Available Ceramic Available Available Available Available DP-64S Available Available Available Available FP-64A Available Available Available Available FP-64B Available -- Available -- DC-64S Available -- -- -- --: Not available Notes: 1. See table 17. 2. See table 20. 3 HD404019R Series 17 50 DP-64S DC-64S 49 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 42 11 41 12 40 13 39 14 38 15 37 16 36 17 35 18 34 19 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 FP-64A Top view 4 52 43 FP-64B 10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 53 44 9 R51 R52 R53 R60 R61 R62 R63 VCC R40/SCK R41/SI R42/SO R43 R70 R71 R72 R73 R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50 54 45 8 32 16 46 7 31 15 55 51 47 6 30 52 14 56 13 48 5 29 53 57 12 49 4 28 54 58 11 3 27 55 59 10 50 26 56 60 9 51 2 25 57 61 58 8 1 24 7 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50 R51 62 59 23 60 6 22 61 5 63 62 4 64 3 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80 R73 R72 R71 R70 R43 R42/SO R41/SI R40/SCK 21 63 20 64 2 R52 R53 R60 R61 R62 R63 VCC R40/SCK R41/SI R42/SO R43 R70 R71 1 R02 R01 R00 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D11 D12 D13 D14 D15 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50 R51 R52 R53 R60 R61 R62 R63 VCC R00 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Pin Arrangement D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80 D3 D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80 R73 R72 R8 R7 R6 R5 R83 R82 R81 R80 R73 R72 R71 R70 R63 R62 R61 R60 R53 R52 R51 R50 B PC D port A R0 CA R1 ALU ST Instruction decoder 16,384 x 10-bit ROM R10 R11 R12 R13 R2 SPY Y SP System control R00 R01 R02 R03 R20 R21 R22 R23 R3 SPX X 992 x 4-bit RAM RESET D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R30 R31 R32/INT0 R33/INT1 R4 W R33/INT1 External interrupt R32/INT0 Interrupt control Timer B GND VCC indicates highvoltage I/O pins R9 R44/SO R41/SI R40/SCK R93 R92 R91 R90 Timer A TEST Serial interface OSC1 RA OSC2 RA1/Vdisp RA0 HD404019R Series Block Diagram R40/SCK R41/SI R42/SO R43 5 HD404019R Series Pin Functions Power Supply VCC: Apply the power supply voltage to this pin. GND: Connect to ground. Vdisp: Power supply pin (multiplexed with RA1) for high-voltage I/O pins with a maximum voltage of 40 V (V CC - 40 V). For details, see the Input/Output section. TEST: For test purposes only. Connect it to VCC. RESET: Resets the MCU. For details, see the Reset section. Oscillators OSC 1, OSC 2: OSC1 and OSC 2 can be connected to a crystal resonator, ceramic resonator or an external oscillator circuit. For details, see the Internal Oscillator Circuit section. Ports D0 to D15 (D Port): An input/output port addressed by bits. These 16 pins are all input/output pins. D0 to D3 are standard pins and D4 to D15 are high-voltage pins. The circuit type for each pin can be selected using a mask option. For details, see the Input/Output section. R0 to RA 1 (R Ports): R0 to R9 are 4-bit I/O ports. Only RA is a 2-bit port. R9 and RA are input ports, and R0 to R8 are I/O ports. R0, R1, R2, and RA are high-voltage ports, and R3 to R9 are standard ports. Each pin has a mask option which selects its circuit type. The pins R32, R33, R40, R4 1, and R42 are multiplexed with INT0, INT 1, SCK, SI, and SO, respectively. For details, see the Input/Output section. Interrupts INT0, INT1: External interrupts for the MCU. INT1 can be used as an external event input pin for timer B. INT 0 and INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section. Serial Interface SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO) are used for serial interface. SCK, SI, and SO are multiplexed with R40, R41, and R4 2, respectively. For details, see the Serial Interface section. 6 HD404019R Series Memory Map ROM Memory Map The MCU contains a 16,384-word x 10-bit ROM (mask ROM or PROM). It is described in the following paragraphs and by the ROM memory map in figure 1. Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL instructions to branch to the starting address of the initialization program and of the interrupt programs. After reset or an interrupt routine is processed, the program is executed from the vector address. Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for subroutines. The CAL instruction branches to subroutines. Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P instruction can refer to the ROM data as a pattern. Program Area ($0000 to $3FFF): Locations from $0000 to $3FFF can be used for program code. 0 $0000 Vector address $000F $0010 15 16 Zero-page subroutine (64 words) 63 64 $003F $0040 Pattern (4096 words) 4095 4096 $0FFF $1000 Program (16,384 words) 16383 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (jump to reset routine) JMPL instruction (jump to INT0 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to serial routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $3FFF Figure 1 ROM Memory Map 7 HD404019R Series RAM Memory Map The MCU also contains a 992-digit x 4-bit RAM as the data and stack area. In addition to these areas, interrupt control bits and special function registers are also mapped on the RAM memory space. The RAM memory map (figure 2) is described in the following paragraphs. Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag cannot be set by software. The RSP bit is used only to reset the stack pointer. Special Function Registers Area ($004 to $00B): The special function registers are the mode or data registers for the external interrupt, the serial interface, and the timer/counters. These registers are classified into three types: write-only, read-only, and read/write as shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions. Data Area ($020 to $3BF): The 16 digits, $020 through $02F, of the data area are called memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL instruction, CALL instruction) or interrupts are processed. This area can be used as a 16-level nesting stack in which one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is available as a data area. 8 HD404019R Series 0 $000 RAM-mapped registers 31 32 Memory registers (MR) 47 48 $01F $020 $02F $030 Data (928 digits) 959 960 0 1 2 3 4 5 6 7 8 9 10 11 12 Interrupt control bits area (PMR) Port mode register (SMR) Serial mode register Serial data register lower (SRL) Serial data register upper (SRU) (TMA) Timer mode register A (TMB) Timer mode register B (TCBL/TLRL) Timer B* (TCBU/TLRU) $3BF $3C0 Stack (64 digits) W W R/W R/W W W R/W R/W Not used $01F 31 1023 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $3FF *: Two registers are mapped on the same address. R: Read only W: Write only R/W: Read/write 10 Timer counter B lower (TCBL) R Timer load register B lower (TLRL) W $00A 11 Timer counter B upper (TCBU) R Timer load register B upper (TLRU) W $00B Figure 2 RAM Memory Map 9 HD404019R Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 Not used Not used IMTB (IM of timer B) IFTB (IF of timer B) $002 3 Not used Not used IMS (IM of serial) IFS (IF of serial) $003 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Note: Each bit of the interrupt control bit area is set by the SEM/SEMD instruction, reset by the REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other instructions. Furthermore the interrupt request flag is not affected by the SEM/SEMD instruction. The value of the status flag becomes invalid when the unusable bits are tested. Figure 3 Interrupt Control Bits Area Configuration Memory registers Stack area 32 MR (0) $020 960 Level 16 $3C0 33 MR (1) $021 Level 15 34 MR (2) $022 Level 14 35 MR (3) $023 Level 13 36 MR (4) $024 Level 12 37 MR (5) $025 Level 11 38 MR (6) $026 Level 10 39 MR (7) $027 Level 9 40 MR (8) $028 Level 8 41 MR (9) $029 Level 7 42 MR (10) $02A Level 6 43 MR (11) $02B Level 5 44 MR (12) $02C Level 4 45 MR (13) $02D Level 3 46 MR (14) $02E Level 2 47 MR (15) $02F 1023 Level 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC12 PC11 $3FC 1021 PC10 PC9 PC8 PC7 $3FD 1022 CA PC6 PC5 PC4 $3FE 1023 PC3 PC2 PC1 PC0 $3FF PC13 to PC0: Program counter ST: Status flag CA: Carry flag Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position 10 HD404019R Series Functional Description Registers and Flags The MCU has nine registers and two flags for the CPU operations (figure 5). 3 0 A Accumulator 3 0 B B register 1 0 W 3 W register 0 X 3 X register 0 Y 3 Y register 0 SPX 3 SPX register 0 SPY SPY register 0 CA Carry flag 0 ST 13 Status flag 0 PC Program counter 9 1 5 1 1 1 0 SP Stack pointer Figure 5 Registers and Flags Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the arithmetic logic unit (ALU), and transfer data to/from memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): The 2-bit W register, and the 4-bit X and Y registers indirectly address RAM. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY assist the X and Y registers, respectively. Carry Flag (CA): The carry flag (CA) stores the overflow from the ALU generated by an arithmetic operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions. 11 HD404019R Series During an interrupt, a carry is pushed onto the stack. It is restored by the RTNI instruction, but not by the RTN instruction. Status Flag (ST): The status flag (ST) holds the ALU overflow, ALU non-zero, and the results of a bit test instruction for the arithmetic or compare instructions. It is a branch condition of the BR, BRL, CAL, or CALL instruction. The value for the status flag remains unchanged until the next arithmetic, compare, or bit test instruction is executed. The status becomes a 1 after the BR, BRL, CAL, or CALL instruction is either executed or skipped. During an interrupt, the status is pushed onto the stack. It is restored back from the stack by the RTNI instruction, but not by the RTN instruction. Program Counter (PC): The program counter is a 14-bit binary counter which controls the sequence in which the instructions stored in ROM are executed. Stack Pointer (SP): The stack pointer (SP) points to the address of the next stack area (up to 16 levels). The stack pointer is initialized to RAM address $3FF. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is restored from it. The stack can only be used up to 16 levels deep because the high-order four bits of the stack pointer are fixed at 1111. The stack pointer is initialized to $3FF by either MCU reset or by the RSP bit reset from the REM/REMD instruction. 12 HD404019R Series Interrupts Five interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A and B), and serial port (serial). For each source, an interrupt request flag (IF) interrupt mask (IM), and interrupt vector addresses control and maintain the interrupt request. The interrupt enable flag (IE) also controls interrupt operations. Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped on $000 through $003 of the RAM space. They are accessible by RAM bit manipulation instructions. (The interrupt request flag (IF) cannot be set by software.) The interrupt enable flag (IE) and IF are cleared to 0, and the interrupt mask (IM) is set to 1 by MCU reset. Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source. An interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be activated and vector addresses will be generated from the priority PLA corresponding to the interrupt source. Table 1 Vector Addresses and Interrupt Priority Reset/Interrupt Priority Vector Addresses RESET -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Serial 5 $000C Table 2 Interrupt Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer B Serial IE 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 IF1 * IM1 * 1 0 0 0 IFTA * IMTA * * 1 0 0 IFTB * IMTB * * * 1 0 IFS * IMS * * * * 1 Note: * Indicates don't care 13 HD404019R Series Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed onto the stack. In the third cycle, the instruction is re-executed after jumping to the vector address. At each vector address, program the JMPL instruction to branch to the starting address of the interrupt program. The IF which caused the interrupt must be reset by software in the interrupt program. $000,0 IE Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $000,2 IF0 $000,3 IM0 Priority control logic $001,0 IF1 $001,1 IM1 $001,2 IFTA $001,3 IMTA $002,0 IFTB $002,1 IMTB $003,0 IFS $003,1 IMS Note: $m, n is RAM address $m, bit number n. Figure 6 Interrupt Control Circuit Block Diagram 14 Vector address HD404019R Series Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 7 Interrupt Processing Sequence 15 HD404019R Series Power on RESET = 1? No Yes Interrupt request? Yes No No IE = 1? Yes Reset MCU Execute instruction Accept interrupt IE 0 PC (PC) + 1 Stack (PC) Stack (CA) Stack (ST) PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer A interrupt? No PC $0008 Yes Timer B interrupt? No PC $000C (serial interrupt) Figure 8 Interrupt Processing Flowchart 16 HD404019R Series Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests as shown in table 3. It is reset by an interrupt and set by the RTNI instruction. Table 3 Interrupt Enable Flag IE Interrupt Enable/Disable 0 Disabled 1 Enabled External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by the port mode register (PMR: $004). Setting bit 3 and bit 2 of PMR causes the R3 3/INT1 and R32/INT0 pins to be used as INT 1 and INT0, respectively. The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs. (Refer to table 4.) The INT1 input can be used as a clock signal input to timer B in which timer B counts up at each falling edge of the INT1 input. When INT1 is used as the timer B external event input, the external interrupt mask (IM1) has to be set so that the interrupt request by INT1 will not be accepted. (Refer to table 5.) Table 4 External Interrupt Request Flags IF0, IF1 Interrupt Request 0 No 1 Yes Table 5 External Interrupt Masks IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (masked) External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs, respectively. External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the external interrupt requests. Port Mode Register (PMR: $004): The port mode register is a 4-bit write-only register which controls the R3 2/INT0 pin, R33/INT1 pin, R41/SI pin, and R42/SO pin as shown in table 6. The port mode register will be initialized to $0 by MCU reset. These pins are therefore initially used as ports. 17 HD404019R Series Table 6 Port Mode Register PMR3 R33/INT1 Pin 0 Used as R33 port input/output pin 1 Used as INT1 input pin PMR2 R32/INT0 Pin 0 Used as R32 port input/output pin 1 Used as INT0 input pin PMR1 R41/SI Pin 0 Used as R41 port input/output pin 1 Used as SI input pin PMR0 R42/SO Pin 0 Used as R42 port input/output pin 1 Used as SO output pin 18 HD404019R Series Serial Interface The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register, the serial mode register, the octal counter, and the multiplexer as illustrated in figure 9. Pin R40/SCK and the transmit clock signal are controlled by the serial mode register. The contents of the serial data register can be written into or read out by software. The data in the serial data register can be shifted synchronously with the transmit clock signal. The STS instruction initiates serial interface operations and resets the octal counter to $0. The counter starts to count at the falling edge of the transmit clock (SCK) signal and increments by one at the rising edge of SCK. When the octal counter is reset to $0 after eight transmit clock signals, or a transmit/receive operation is discontinued, the serial interrupt request flag will be set. OC (3 bits) Octal counter Prescaler (11 bits) SROF IFS Serial interface interrupt request flag /2 /8 / 32 / 128 / 512 / 2048 System clock /2 Serial MPX Internal bus line (S1) MPX 4 SCK 3 4 SMR (4 bits) Serial mode register Internal bus line (S2) 4 SR (8 bits) Serial data register 4 4 4 Internal bus-line (S2) PMR (4 bits) Port mode register SCK 2 R40/SCK port SCK R41/SI port R42/SO port SI SO Figure 9 Serial Interface Block Diagram Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R4 0/SCK pin, prescaler divide ratio, and transmit clock source as shown in table 7. The write signal to the serial mode register controls the operating state of the serial interface. The write signal to the serial mode register stops the serial data register and octal counter from accepting the transmit clock, and it also resets the octal counter to $0 simultaneously. Therefore, when the serial interface is in the transfer state, the write signal causes the serial mode register to cease the data transmit and to set the serial interrupt request flag. 19 HD404019R Series The contents of the serial mode register will be changed on the second instruction cycle after the serial mode register has been written to. Therefore, the STS instruction must be executed after the data in the serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU reset. Table 7 Serial Mode Register SMR3 R40/SCK 0 Used as R40 port input/output pin 1 Used as SCK input/output pin Transmit Clock SMR2 SMR1 SMR0 R40/SCK Port Clock Source Prescaler Divide System Clock Ratio Divide Ratio 0 0 0 SCK output Prescaler / 2048 / 4096 1 SCK output Prescaler / 512 / 1024 0 SCK output Prescaler / 128 / 256 1 SCK output Prescaler / 32 / 64 0 SCK output Prescaler /8 / 16 1 SCK output Prescaler /2 /4 0 SCK output System clock -- /1 1 SCK input External clock -- -- 1 1 0 1 Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a loworder digit (SRL: $006) and a high-order digit (SRU: $007). The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the falling edge of the transmit clock signal. At the same time, external data is input from the SI pin to the serial data register, MSB first, synchronously with the rising edge of the transmit clock. Figure 10 shows the I/O timing chart of the transmit clock signal and the data. The read/write operations of the serial data register should be performed after the completion of data transmit/receive. Otherwise the data may not be guaranteed. Transmit clock 1 Serial output data 2 3 4 5 6 LSB Serial input data latch timing Figure 10 Serial Interface I/O Timing 20 7 8 MSB HD404019R Series Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag will be set when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal counter. Refer to table 8. Table 8 Serial Interrupt Request Flag IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request. Refer to table 9. Table 9 Serial Interrupt Mask IMS Interrupt Request 0 Enabled 1 Disabled (masked) Selection and Change of the Operation Mode: Table 10 shows the serial interface operation modes which are determined by a combination of the value in the port mode register and in the serial mode register. Initialize the serial interface by a write signal to the serial mode register when the operation mode has changed. Table 10 Serial Interface Operation Mode SMR3 PMR1 PMR2 Serial Interface Operating Mode 1 0 0 Clock continuous output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Operating State of Serial Interface: The serial interface has three operating states: the STS waiting state, transmit clock wait state, and transfer state, as shown in figure 11. The STS waiting state is the initialization state of the serial interface. The serial interface enters this state in one of two ways: either by the operation mode changing through a change in the data in the port mode register, or by data being written into the serial mode register. In this state, the serial interface does not operate even if the transmit clock is applied. If the STS instruction is executed, the serial interface shifts to the transmit clock wait state. 21 HD404019R Series In the transmit clock wait state the falling edge of the first transmit clock causes the serial interface to shift to the transfer state. The octal counter then counts up and the serial data register shifts simultaneously. As an exception, if the clock continuous output mode is selected, the serial interface stays in the transmit clock wait state while the transmit clock outputs continuously. The octal counter becomes 000 again after 8 transmit clocks or the execution of the STS instruction, so the serial interface returns to the transmit clock wait state and the serial interrupt request flag is set simultaneously. When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the STS instruction, and stops after 8 clocks. STS waiting state octal counter = 000 transmit clock disable Change PMR * Write to SMR Change PMR* Write to SMR STS instruction (IFS 1) Transmit clock Transmit clock wait state (octal counter = 000) 8 transmit clocks, STS instruction (IFS 1) Transfer state (octal counter 000) Note: * Change PMR means the operation mode changes as shown below. Clock continuous output mode * Transmit mode * Receive mode * Transmit/receive mode Figure 11 Serial Interface Operation State Transmit Clock Error Detection Example: The serial interface functions abnormally when the transmit clock is disturbed by external noise. Transmit clock errors can be detected by the procedure shown in figure 12. If more than 8 transmit clocks occur in the transfer state, the state of the serial interface shifts as follows: transfer state, transmit clock wait state, and transfer state. The serial interrupt flag should be reset before entering into the STS state by writing data to SMR. This procedure sets the IFS again. 22 HD404019R Series Transmit/receive (IFS 1) Interrupt disable IFS 0 Write to SMR IFS = 1? Yes Transmit clock error processing No Normal end Figure 12 Transmit Clock Error Detection Example 23 HD404019R Series Timers The MCU contains a prescaler and two timer/counters (timers A and B). See figure 13. The prescaler is an 11-bit binary counter, timer A an 8-bit free-running timer, and timer B is an 8-bit auto-reload timer/event counter. Internal bus line (S1) Timer mode register B 4 TMB (4 bits) INT1 TL (4 bits) Timer latch register 3 CPTB 4 Prescaler (11 bits) Timer A MPX TBOF TCB (8 bits) Timer counter B IFTB Interrupt request flag of timer B TLR (8 bits) Timer load register B 4 Internal bus line (S2) /2 /4 /8 /32 /128 /512 /1024 /2048 System clock /2048 /2 /4 /8 /32 /128 /512 Timer B MPX 4 CPTA TCA (8 bits) Timer counter A TAOF 3 TMA (3 bits) IFTA Interrupt request flag of timer A Timer mode register A Figure 13 Timer/Counter Block Diagram Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $0000 by MCU reset, and it starts to count up with the system clock signal as soon as RESET input goes to logic 0. The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals to timer A, timer B, and the serial interface. The prescaler divide ratio is selected by timer mode register A (TMA), timer mode register B (TMB), or the serial mode register (SMR). Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input signal. When the next clock signal is applied after timer A becomes $FF, it generates an overflow and becomes $00. This overflow causes the timer A interrupt request flag (IFTA: $001, bit 2) to go to 1. This timer can function as an interval timer periodically generating overflow output at every 256th clock signal input. The clock input signals to timer A are selected by timer mode register A (TMA: $008). Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock source, and the prescaler divide ratio of timer B. When the external event input is used as an input clock signal to timer B, select R33/INT1 as INT1 and set the external interrupt mask (IM1) to prevent an external interrupt request from occurring. 24 HD404019R Series Timer B is initialized according to the data written into timer load register B by software. Timer B counts up at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will generate an overflow output. In this case, if the autoreload function is selected, timer B is initialized according to the value of timer load register B. If it is not selected, timer B goes to $00. The timer B interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output. Timer Mode Register A (TMA: $008): Timer mode register A is a 3-bit write-only register. The TMA controls the prescaler divide ratio of timer A clock input as shown in table 11. Timer mode register A is initialized to $0 by MCU reset. Table 11 Timer Mode Register A TMA2 TMA1 TMA0 Prescaler Divide Ratio 0 0 0 / 2048 1 / 1024 0 / 512 1 / 128 0 / 32 1 /8 0 /4 1 /2 1 1 0 1 Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in table 12. Timer mode register B is initialized to $0 by MCU reset. The operation mode of timer B changes at the second instruction cycle after timer mode register B is written to. Timer B should be initialized by writing data into timer load register B after the contents of TMB are changed. The configuration and function of timer mode register B is shown in figure 14. Table 12 Timer Mode Register B TMB3 Auto-Reload Function 0 No 1 Yes 25 HD404019R Series TMB2 TMB1 TMB0 Prescaler Divide Ratio, Clock Input Source 0 0 0 / 2048 1 / 512 0 / 128 1 / 32 0 /8 1 /4 0 /2 1 INT1 (external event input) 1 1 0 1 PMR: $004 SMR: $005 PMR3 PMR2 PMR1 PMR0 SMR3 SMR2 SMR1 SMR0 Transmit clock selection R40/SCK pin mode selection R42/SO pin mode selection R41/SI pin mode selection R32/INT0 pin mode selection R33/INT1 pin mode selection TMA: $008 TMA2 TMA1 TMA0 TMB: $009 TMB3 TMB2 TMB1 TMB0 Timer B input clock selection Auto-reload function selection Timer A input clock selection Figure 14 Mode Register Configuration and Function Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit writeonly timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL: $00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B). (Refer to figure 2.) Timer counter B can be initialized by writing data into timer load register B. Write the low-order digit first, and then the high-order digit. The timer counter is initialized when the high-order digit is written. The timer load register is initialized to $00 by the MCU reset. 26 HD404019R Series The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when the high-order digit is read. Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the overflow output of timer A (table 13). Table 13 Timer A Interrupt Request Flag IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request from being generated by the timer A interrupt request flag (table 14). Table 14 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the overflow output of timer B (table 15). Table 15 Timer B Interrupt Request Flag IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request from being generated by the timer B interrupt request flag (table 16). Table 16 Timer B Interrupt Mask IMTB Interrupt Request 0 Enabled 1 Disabled (masked) 27 HD404019R Series Input/Output The MCU has 58 I/O pins, 32 standard and 26 high voltage. One of three circuit types can be selected by the mask option for each standard pin: CMOS, with pull-up MOS, and without pull-up MOS (NMOS open drain); and one of two circuit types can be selected for each high-voltage pin: with pull-down MOS and without pull-down MOS (PMOS open drain). Since the pull-down MOS is connected to the internal Vdisp line, the RA 1/Vdisp pin must be selected as V disp via the mask option when the option with pull-down MOS is selected for at least one high-voltage pin. See table 17 for I/O pin circuit types. When every input/output pin is used as an input pin, the mask option and output data must be selected in the manner specified in table 18. Output Circuit Operation of With Pull-Up MOS Standard Pins: In the standard pin option with pull-up MOS, the circuit shown in figure 15 is used to shorten the rise time of the output. When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this instruction. This pulse will switch the PMOS (B) on and shorten the rise time. The write pulse keeps the PMOS in the on state for one-eighth of the instruction cycle time. While the write pulse is 0, a high output level is maintained by the pull-up MOS (C). When the HLT signal becomes 0 in the stop mode, MOS (A), (B), and (C) turn off. D Port: I/O port D has 16 discrete I/O pins, each of which can be addressed independently. It can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD instructions. See tables 17 and 18 for the classification of standard pin, high-voltage pin, and the I/O pin circuit types. R Ports: The eleven R ports are composed of 36 I/O pins and 6 input-only pins. Data is input through the LAR and LBR instructions and output through the LRA and LRB instructions. The MCU will not be affected by writing into the input-only and/or non-existing ports, while invalid data will be read when the output-only and/or non-existing ports are read. The R3 2 , R33 , R40 , R4 1 , and R42 pins are multiplexed with the INT0 , INT1 , SC K, SI, and SO pins, respectively. See tables 17 and 18 for the classification of standard pins, high-voltage pins and selectable circuit types of these I/O pins. Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction because of noise. The I/O pins should be fixed as follows to prevent malfunction. High-voltage pins: Select without pull-down MOS (PMOS open drain) via the mask option and connect to VCC on the printed circuit board. Standard pins: Select without pull-up MOS (NMOS open drain) via the mask option and connect to GND on the printed circuit board. R4 0/SCK and R42/SO should be used as R40 and R42 by the serial mode register and port mode register, respectively. 28 HD404019R Series Table 17 I/O Pin Circuit Types Standard Pins Without Pull-Up MOS (NMOS Open Drain) (A) With Pull-Up MOS (B) I/O common pins HLT D0-D3, Input data HLT Input data VCC VCC HLT Write pulse HLT HLT Applicable Pins CMOS (C) Input data R30-R33, VCC R40-R43, HLT Output data R50-R53, R60-R63, Output data Output data R70-R73, R80-R83 VCC Input pins HLT Input data HLT -- HLT R90-R93 Input data High Voltage Pins Without Pull-Down MOS (PMOS Open Drain) (D) I/O common pins Applicable Pins With Pull-Up MOS (E) VCC VCC D4-D15 , HLT Output data HLT HLT Output data VCC Vdisp Input data HLT Input data R10-R13, R20-R23 HLT HLT Input pins R00-R03, Input data Input data RA0 VCC Vdisp Input pins HLT Input data -- RA1 29 HD404019R Series Standard Pins Without Pull-Up MOS (NMOS Open Drain) or CMOS (A or C) With Pull-Up MOS (B) I/O common pins Applicable Pins SCK SCK HLT HLT VCC HLT + mode select VCC HLT + mode select VCC Internal SCK VCC Output pins HLT SCK* (output mode) Internal SCK VCC SO VCC HLT SO SO INT0, INT1 Input pins Input data HLT Input data SI, SCK HLT (input mode) Notes: In the stop mode, HLT is 0, HLT is 1 and I/O pins are in high impedance. * If the MCU is interrupted by the serial interface in the external clock input mode, the SCK terminal becomes input only. Table 18 Data Input from Common Input/Output Pins I/O Pin Circuit Type Standard pins High voltage pins 30 Input Possible Input Pin State CMOS No -- Without pull-up MOS (NMOS open drain) Yes 1 With pull-up MOS Yes 1 Without pull-down MOS (PMOS open drain) Yes 0 With pull-down MOS Yes 0 HD404019R Series VCC VCC PMOS (B) Write pulse (output instruction) HLT Pull-up MOS (C) NMOS (A) Data MOS Buffer On-Resistance Value A Approximately 250 B Approximately 1 k C Approximately 30 k to 160 k (VCC = 5 V) 1 instruction cycle Output instruction execution Write pulse Figure 15 Output Circuit Operation of With Pull-Up MOS Standard Pins 31 HD404019R Series Reset Pulling the RESET pin high resets the MCU. At power-on or when cancelling the stop mode, the reset must satisfy tRC for the oscillator to stabilize. In all other cases, at least two instruction cycles are required for the MCU to be reset. Table 19 shows the components initialized by MCU reset, and the status of each. Table 19 Initial Values After MCU Reset Item Initial Value by MCU Reset Contents Program counter (PC) $0000 Execute program from the top of ROM address Status flag (ST) 1 Enable branching with conditional branch instructions Stack pointer (SP) $3FF Stack level is 0 (A) Without pull-up MOS 1 Enable to input (B) With pull-up MOS 1 Enable to input (C) CMOS 1 -- 0 Enable to input 0 Enable to input Interrupt enable flag (IE) 0 Inhibit all interrupts Interrupt request flag (IF) 0 No interrupt request Interrupt mask (IM) 1 Mask interrupt request Port mode register (PMR) 0000 See Port Mode Register section Serial mode register (SMR) 0000 See Serial Mode Register section Timer mode register A (TMA) 000 See Timer Mode Register A section Timer mode register B (TMB) 0000 See Timer Mode Register B section Prescaler $000 -- Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- Timer load register (TLR) $00 -- Octal counter 000 -- I/O pins, output Standard register pins High-voltage (D) Without pullpins down MOS (E) With pull- down MOS Interrupt flags Mode registers Timer/counters 32 HD404019R Series After MCU Reset to Recover from After MCU Reset to Recover from Stop Mode Other Modes Item Carry flag (CA) The contents of the items before MCU reset are not retained. It is necessary to initialize them by software. Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SR) RAM The contents of the items before MCU reset are not retained. It is necessary to initialize them by software. The contents of RAM before MCU Same as above for RAM reset (just before STOP instruction) are retained Internal Oscillator Circuit Figure 16 outlines the internal oscillator circuit. A crystal oscillator or ceramic oscillator can be selected as the oscillator type. Refer to table 20 to select the oscillator type. In addition, see figure 17 for the layout of the crystal or ceramic oscillator. OSC1 Oscillator 1/4 divider circuit Timing generator circuit System clock OSC2 Figure 16 Internal Oscillator Circuit ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, GND ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, OSC,,,,,,,,,,,,,,,,,,,,,,,, 2 ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, OSC,,,,,,,,,,,,,,,,,,,,,,,, 1 ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, TEST,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, RESET,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, D,,,,,,,,,,,,,,,,,,,,,,,, 0 ,,,,,,,,,,,,,,,,,,,,,,,, Figure 17 Layout of Crystal or Ceramic Oscillator 33 HD404019R Series Table 20 Examples of Oscillator Circuits Circuit Configuration External clock operation (OSC1, OSC2) Circuit Constants Oscillator OSC1 Open OSC2 Ceramic oscillator (OSC1, OSC2) Ceramic oscillator C1 OSC1 Ceramic oscillator CSA4.00MG (Murata) Rf: 1 M 20% Rf C1: 30 pF 20% OSC2 C2 C2: 30 pF 20% GND Crystal oscillator (OSC1, OSC2) Rf: 1 M 20% C1 C1: 10 pF to 22 pF 20% OSC1 Crystal C2: 10 pF to 22 pF 20% Rf Crystal: Equivalent circuit shown at bottom left OSC2 C2 GND Co: 7 pF max. Rs: 100 max. AT-cut parallel resonance crystal OSC1 L C1 RS f: 1.0 MHz to 4.5 MHz OSC2 C0 Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal, ceramic resonator, and the floating capacitance when designing the board. When using the resonator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and other elements should be as short as possible, and avoid crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator. Refer to figure 17. 34 HD404019R Series Operating Modes The MCU has two low-power dissipation modes, standby mode and stop mode (table 21). Figure 18 is a mode transition diagram for these modes. Standby Mode: Executing the SBY instruction puts the MCU into standby mode. In standby mode, the oscillator circuit is active, and the interrupts, timer/counters, and serial interface remain working. On the other hand, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and I/O pins retain the states they were in just before the MCU went into standby mode. Table 21 Low-Power Dissipation Modes Condition Standby Mode Stop Mode Instruction SBY instruction STOP instruction Oscillator circuit Active Stopped Instruction execution Stopped Stopped Registers, flags Retained Reset*1 Interrupt function Active Stopped RAM Retained Retained 2 Input/output pins Retained* High impedance Timer/counters, serial interface Active Stopped Cancellation method RESET input, interrupt request RESET input Notes: 1. The MCU recovers from the stop mode by RESET input. Refer to table 19 for the contents of flags and registers. 2. When I/O circuits are active, an I/O current may flow in the standby mode, depending on the state of the I/O pins. This is an additional current added to the standby mode current dissipation. Active mode SBY instruction STOP instruction Interrupt request Standby mode RESET = 1 RESET = 0 RESET = 1 Stop mode RESET = 1 Reset Figure 18 MCU Operating Mode Transition 35 HD404019R Series Standby mode may be cancelled by inputting RESET or by asserting an interrupt request. In the former case the MCU is reset. In the later case, the MCU becomes active and executes the next instruction following the SBY instruction. If the interrupt enable flag is 1 when an interrupt request is asserted, the interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution continues. Figure 19 shows the flowchart of the standby mode. Standby Oscillator: Active Peripheral clocks: Active All other clocks: Stop RESET = 1? Yes No IF0 = 1? No Yes IM0 = 0? IF1 = 1? No Yes IFTA = 1? No Yes IM1 = 0? No Yes No Yes IMTA = 0? IFTB = 1? No No Yes IFS = 1? No Yes IMTB = 0? Yes No Yes IMS = 0? Yes Restart processor clocks Restart processor clocks Execute next instruction (active mode) No Reset MCU Execute instruction IE = 1? Yes Accept interrupt Figure 19 MCU Operating Flowchart in Standby Mode 36 No HD404019R Series Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit and every function of the MCU stop. The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 20, reset input must be applied for at least tRC for oscillation to be stabilized. (Refer to the AC Characteristics table.) After the stop mode is cancelled, RAM retains the state it was in just before the MCU went into stop mode, but the accumulator, B register, W register, X/SPX registers, Y/SPY registers, carry flag, and serial data register will not retain their contents. Stop mode Oscillator Internal clock RESET tres STOP instruction execution tres tRC (stabilization time) Figure 20 Timing of Stop Mode Cancellation 37 HD404019R Series PROM Mode Pin Description Table 22 describes the pin functions in PROM mode. Table 22 PROM Mode Signals Pin Number MCU Mode PROM Mode DC-64S, DP-64S FP-64B FP-64A Symbol I/O Symbol 1 59 57 D11 I/O VCC 2 60 58 D12 I/O 3 61 59 D13 I/O 4 62 60 D14 I/O 5 63 61 D15 I/O 6 64 62 P00 I/O A1 I 7 1 63 R01 I/O A2 I 8 2 64 R02 I/O A3 I 9 3 1 R03 I/O A4 I 10 4 2 R10 I/O A5 I 11 5 3 R11 I/O A6 I 12 6 4 R12 I/O A7 I 13 7 5 R13 I/O A8 I 14 8 6 R20 I/O A0 I 15 9 7 R21 I/O A10 I 16 10 8 R22 I/O A11 I 17 11 9 R23 I/O A12 I 18 12 10 RA0 I VCC 19 13 11 RA1/Vdisp I 20 14 12 R30 I/O A13 I 21 15 13 R31 I/O A14 I 22 16 14 R32/INT0 I/O 23 17 15 R33/INT1 I/O 24 18 16 R50 I/O 25 19 17 R51 I/O 26 20 18 R52 I/O 27 21 19 R53 I/O 28 22 20 R60 I/O 29 23 21 R61 I/O 38 I/O HD404019R Series Pin Number MCU Mode PROM Mode DC-64S, DP-64S FP-64B FP-64A Symbol I/O 30 24 22 R62 I/O 31 25 23 R63 I/O 32 26 24 VCC 33 27 25 R40/SCK I/O O4 I/O 34 28 26 R41/SI I/O O5 I/O 35 29 27 R42/SO I/O O6 I/O 36 30 28 R43 I/O O7 I/O 37 31 29 R70 I/O CE I 38 32 30 R71 I/O OE I 39 33 31 R72 I/O 40 34 32 R73 I/O O4 I/O 41 35 33 R80 I/O O3 I/O 42 36 34 R81 I/O O2 I/O 43 37 35 R82 I/O O1 I/O 44 38 36 R83 I/O O0 I/O 45 39 37 R90 I VPP 46 40 38 R91 I A9 I 47 41 39 R92 I M0 I 48 42 40 R93 I M1 I 49 43 41 RESET I RESET I 50 44 42 TEST I TEST I 51 45 43 OSC1 I 52 46 44 OSC2 53 47 45 GND 54 48 46 D0 I/O O0 I/O 55 49 47 D1 I/O O1 I/O 56 50 48 D2 I/O O2 I/O 57 51 49 D3 I/O O3 I/O 58 52 50 D4 I/O 59 53 51 D5 I/O Symbol I/O VCC GND 39 HD404019R Series Pin Number MCU Mode PROM Mode DC-64S, DP-64S FP-64B FP-64A Symbol I/O 60 54 52 D6 I/O 61 55 53 D7 I/O 62 56 54 D8 I/O 63 57 55 D9 I/O 64 58 56 D10 I/O Symbol I/O VCC Notes: 1. I/O: Input/output pins I: Input pins O: Output pins 2. Connect each pair of O4, O3, O2, O1, and O0. Hitachi supplies the socket adapter on which these pairs are internally connected. 40 HD404019R Series Programmable ROM Operation The on-chip PROM of HD4074019 and HD407L4019 are programmed in PROM mode. The PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 21. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a 64-to-28-pin socket adapter. Table 24 lists the recommended PROM programmers and socket adapters. Since the instruction of the HMCS400 series consists of 10 bits, the HMCS400-series microcom puter incorporates a conversion circuit used as a general-purpose PROM programmer. By this circuit, an instruction is read or programmed using 2 addresses, the low-order 5 bits and the high-order 5 bits. For example, if 8 kwords of an on-chip PROM are programmed by a general purpose PROM programmer, 16 kbytes of addresses ($0000 to $3FFF) should be specified. Programming and Verification The HD4074019 and HD407L4019 can be programmed at high-speed without causing voltage stress or affecting data reliability. Table 23 shows how programming and verification modes are selected. Erasing PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits become 1s. The erasing specifications are as follows: ultraviolet (UV) light with wavelength 2537 A with a minimum irradiation of 15 W sec/cm2. These conditions are satisfied by exposing the LSI to a 12,000-W/cm2 UV source for 15 to 20 minutes at a distance of 1 inch. Precautions 1. Addresses $0000 to $7FFF should be specified if the PROM is programmed by a PROM programmer. Note that the plastic package type cannot be erased and reprogrammed. (Only ceramic window packages can be erased and reprogrammed.) 2. Make sure that the PROM programmer, socket adapter, and LSI match properly. Using the wrong programmer for the socket adapter may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed to the programmer. 3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the HD4074019 and HD407L4019, the LSI may be permanently damaged. 12.5 V is the voltage for VPP of Intel's 27256. 41 HD404019R Series Table 23 PROM Modes Selection Pin Mode CE OE VPP O0 to O7 Programming Low High VPP Data input Verify High Low VPP Data output Programming inhibited High High VPP High impedance Table 24 Recommended PROM Programmers and Socket Adapters PROM Programmer* Socket Adapter Maker Type Name Package Type Type Name Maker DATA I/O 280 DP-64S HS409ESS11H Hitachi 201 DC-64S 29B + UniPak2B FP-64B HS409ESF01H S22 FP-64A HS409ESH01H PKW-1000 DP-64S HS409ESS21H PKW-1100 DC-64S PKW-1600 FP-64B HS409ESF01H PKW-3100 FP-64A HS409ESH01H AVAL DATA Corp. Hitachi Note: * Since the address pins of the HD4074019 and HD407L4019 are high voltage pins, errors may occur in device insertion tests if a PROM programmer other than those listed above is used. 42 HD404019R Series VCC VCC RESET VCC TEST M0 M1 VPP R90/VPP O0 to O7 Data O0 to O7 A0 to A14 Address A0 to A14 OE OE CE CE GND Figure 21 PROM Mode Function Diagram 43 HD404019R Series Addressing Modes RAM Addressing Modes As shown in figure 22, the MCU has three RAM addressing modes: register indirect addressing, direct addressing, and memory register addressing. W register W1 W0 X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing Instruction 1st word Instruction 2nd word Opcode d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Direct Addressing Instruction Opcode 0 0 0 0 m3 m2 m1 1 m0 0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing Figure 22 RAM Addressing Modes Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits) are used as the RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits) following the opcode used as the RAM address. Memory Register Addressing Mode: The memory registers (16 digits from $020 to $02F) are accessed by executing the LAMR and XMRA instructions. 44 HD404019R Series ROM Addressing Modes and the P Instruction The MCU has four kinds of ROM addressing modes as shown in figure 23. [JMPL] [BRL] [CALL] Instruction 1st word Opcode p3 Instruction 2nd word p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 Program counter PC13 PC12 PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A 3 A 2 A1 A0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 23 ROM Addressing Modes 45 HD404019R Series Direct Addressing Mode: The program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC 13 to PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. By executing the BR instruction, the program can branch to an address on the current page. This instruction replaces the low-order eight bits of the program counter (PC7 to PC0) with 8-bit immediate data. When the BR instruction is on a page boundary (256n + 255) (figure 24), executing it transfers the PC contents to the next page, due to the hardware architecture. Consequently, the program branches to the next page when the BR instruction is used on a page boundary. The HMCS400-series cross macroassembler has an automatic paging facility for ROM pages. Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page subroutine area, which is located at $0000 to $003F. When the CAL instruction is executed, 6 bits of immediate data are placed in the low-order six bits of the program counter (PC 5 to PC0) and 0s are placed in the high-order eight bits (PC13 to PC6). Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address determined by the contents of the 4-bit immediate data, accumulator, and B register. P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure 25). When bit 8 in the referred ROM data is 1, 8 bits of ROM data are written into the accumulator and B register. When bit 9 is 1, 8 bits of ROM data are written into the R1 and R2 port output registers. When both bits 8 and 9 are 1, ROM data are written into the accumulator and B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 46 HD404019R Series BR AAA 256(n - 1) + 255 256n AAA NOP BR AAA BR BBB 256n + 254 256n + 255 256(n + 1) BBB NOP Figure 24 BR Instruction Branch Destination on a Page Boundary 47 HD404019R Series Instruction [P] Opcode p3 0 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R2 2 R21 R2 0 R13 R12 R11 R10 If RO 9 = 1 Pattern Figure 25 P Instruction 48 HD404019R Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14 V 10 Pin voltage VT -0.3 to VCC + 0.3 V 1 VCC - 45 to VCC + 0.3 V 2 Total permissible input current Io 50 mA 3 Maximum input current Io 15 mA 5, 6 Maximum output current -Io 4 mA 6, 7 6 mA 7, 8 30 mA 7, 9 4 Total permissible output current -Io 150 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation should be under the conditions of the electrical characteristics. If these conditions are exceeded, it may cause a malfunction or affect the reliability of the LSI. All voltages are with respect to GND. 1. Standard pins. 2. High voltage pins. 3. Total permissible input current is the total sum of input currents which flow in from all I/O pins to GND simultaneously. 4. Total permissible output current is the total sum of the output currents which flow out from VCC to all I/O pins simultaneously. 5. Maximum input current is the maximum amount of input current from each I/O pin to GND. 6. D0 to D3 and R3 to R8. 7. Maximum output current is the maximum amount of output current from V CC to each I/O pin. 8. R0 to R2. 9. D4 to D15 . 10. Applied to HD4074019 and HD407L4019. 49 HD404019R Series Electrical Characteristics DC Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified) Item Symbol Pin Input high voltage VIH VCC + 0.3 V HD404019R, HD4074019 0.9 VCC -- VCC + 0.3 V HD40L4019R 0.8 VCC -- VCC + 0.3 V HD407L4019: VCC = 4.5 V to 5.5 V 0.9 VCC -- VCC + 0.3 V HD407L4019 0.7 VCC -- VCC + 0.3 V HD404019R, HD4074019 0.8 VCC -- VCC + 0.3 V HD40L4019R 0.7 VCC -- VCC + 0.3 V HD407L4019: VCC = 4.5 V to 5.5 V 0.9 VCC -- VCC + 0.3 V HD407L4019 VCC -0.5 -- VCC + 0.3 V HD404019R, HD4074019, HD407L4019 VCC -0.3 -- VCC + 0.3 V HD40L4019R RESET, -0.3 SCK, INT0, INT1 -- 0.2 VCC V HD404019R, HD4074019 -0.3 -- 0.1 VCC V HD40L4019R -0.3 -- 0.2 VCC V HD407L4019: VCC = 4.5 V to 5.5 V -0.3 -- 0.1 VCC V HD407L4019 -0.3 -- 0.3 VCC V HD404019R, HD4074019 -0.3 -- 0.2 VCC V HD40L4019R -0.3 -- 0.3 VCC V HD407L4019: VCC = 4.5 V to 5.5 V -0.3 -- 0.1 VCC V HD407L4019 -0.3 -- 0.5 V HD404019R, HD4074019, HD407L4019 -0.3 -- 0.3 V HD40L4019R SCK, SO VCC -1.0 -- -- V -IOH = 1.0 mA VCC -0.5 -- -- V -IOH = 0.5 mA SI Input low voltage VIL Output high VOH voltage 50 Unit Test Conditions -- OSC1 VIL Typ Max RESET, 0.8 VCC SCK, INT0, INT1 SI Input low voltage Min OSC1 Note HD404019R Series Item Symbol Pin Min Typ Max Unit Test Conditions Output low voltage VOL SCK, SO -- -- 0.4 V IOL = 1.6 mA Input/output | IIL | leakage current RESET, -- SCK, INT0, INT1, SI, SO, OSC1 -- 1 A Vin = 0 V to VCC 1 Current dissipation in active mode VCC -- -- 8.0 mA HD404019R, HD4074019: VCC = 5 V, f OSC = 4 MHz, divide by 4 2, 5 -- -- 8.0 mA HD40L4019R, HD407L4019: VCC = 5 V, fOSC = 4 MHz, divide by 4 2, 5 -- -- 3.0 mA HD40L4019R, HD407L4019: VCC = 3 V, fOSC = 3.58 MHz, divide by 4 2, 5 3, 5 ICC Notes Current dissipation in standby mode ISBY VCC -- -- 2.0 mA VCC = 5 V, fOSC = 4 MHz, divide by 4 Current dissipation in stop mode ISTOP VCC -- -- 10 A HD404019R, HD40L4019R: 4 Vin (TEST, R90) = VCC - 0.3 V to VCC, Vin (RESET) = 0 V to 0.3 V -- -- 10 A HD4074019, HD407L4019: Vin (TEST, R90) = VCC - 0.3 V to VCC, Vin (RESET) = 0 V to 0.3 V 2 -- -- V Stop mode retaining voltage VSTOP VCC Notes: 1. Excluding pull-up MOS current and output buffer current (HD404019R, HD40L4019R) Excluding output buffer current (HD4074019, HD407L4019) 2. The MCU is in the reset state. Input/output current does not flow. * MCU in reset state, operation mode * RESET, TEST: VCC * D0 to D3, R3 to R9: VCC * D4 to D15 , R0 to R2, RA0, RA1: Vdisp 3. The timer/counter operates with the fastest clock. Input/output current does not flow. * MCU in standby mode * Input/output in reset state * Serial interface: stop * RESET: GND * TEST: VCC * D0 to D3, R3 to R9: VCC * D4 to D15 , R0 to R2, RA0, RA1: Vdisp 4. Excluding pull-down MOS current. 5. When fOSC = x MHz, estimate the current dissipation as follows: maximum value at x MHz = x/4 x (maximum value at 4 MHz) 51 HD404019R Series Input/Output Characteristics for Standard Pins (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Input high voltage VIH D0 to D3, R3 to R9 0.7 VCC -- VCC + 0.3 V HD404019R, HD4074019 0.8 VCC -- VCC + 0.3 V HD40L4019R 0.7 VCC -- VCC + 0.3 V HD407L4019: Note VCC = 4.5 V to 5.5 V Input low voltage VIL D0 to D3, R3 to R9 0.8 VCC -- VCC + 0.3 V HD407L4019 -0.3 -- 0.3 VCC V HD404019R, HD4074019 -0.3 -- 0.2 VCC V HD40L4019R -0.3 -- 0.3 VCC V HD407L4019: VCC = 4.5 V to 5.5 V -0.3 Output high VOH voltage D0 to D3, R3 to R8 -- VCC - 1.0 -- 0.2 VCC V HD407L4019 -- V HD404019R, HD40L4019R: 1 -IOH = 1.0 mA VCC - 0.5 -- -- V HD404019R, HD40L4019R: 1 -IOH = 0.5 mA Output low VOL voltage D0 to D3, R3 to R8 -- -- 0.4 V IOL = 1.6 mA Input/output | IIL | leakage current D0 to D3, R3 to R9 -- -- 1 A HD404019R, HD40L4019R: 2 Pull-up MOS current Notes: 1. 2. 3. 4. 52 -IPU Vin = 0 V to VCC 1 A D0 to D3, -- R3 to R8, R91 to R93 -- R90 -- -- 20 A D0 to D3, R3 to R9 30 -- 150 A HD4074019, HD407L4019: 3 Vin = 0 V to VCC HD404019R, HD40L4019R: 4 VCC = 5 V, Vin = 0 V Applied to I/O pins selected as CMOS output by mask option. Excluding pull-up MOS current and output buffer current. Excluding output buffer current. Applied to I/O pins selected as with pull-up MOS by mask option. HD404019R Series Input/Output Characteristics for High Voltage Pins (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Input high voltage VIH D4 to D15 , R0 to R2, RA0, RA1 0.7 VCC -- VCC + 0.3 V HD404019R, HD4074019 0.8 VCC -- VCC + 0.3 V HD40L4019R: Note VCC = 3.5 V to 6.0 V 0.7 VCC -- VCC + 0.3 V HD407L4019: VCC = 4.5 V to 5.5 V Input low voltage VIL D4 to D15 , R0 to R2, RA0, RA1 0.8 VCC -- VCC + 0.3 V HD407L4019 VCC - 40 -- 0.3 VCC V HD404019R, HD4074019 VCC - 40 -- 0.2 VCC V HD40L4019R: VCC = 3.5 V to 6.0 V VCC - 40 -- 0.3 VCC V HD407L4019: VCC = 4.5 V to 5.5 V VCC - 40 Output high voltage VOH -- D4 to D15 VCC - 3.0 -- 0.2 VCC V HD407L4019 -- V HD404019R, HD40L4019R: -IOH = 15 mA, VCC = 5 V 20% VCC - 2.0 -- -- V HD404019R, HD40L4019R: -IOH = 10 mA, VCC = 5 V 20% VCC - 1.0 -- -- V HD404019R, HD40L4019R: -IOH = 4 mA VCC - 3.0 -- -- V HD4074019: -IOH = 15 mA VCC - 2.0 -- -- V HD4074019: -IOH = 10 mA VCC - 1.0 -- -- V HD4074019: -IOH = 4 mA VCC - 3.0 -- -- V HD407L4019: -IOH = 15 mA, VCC = 4.5 V to 5.5 V VCC - 2.0 -- -- V HD407L4019: -IOH = 10 mA VCC - 1.0 -- -- V HD407L4019: -IOH = 4 mA 53 HD404019R Series Item Symbol Output high VOH voltage Pin Min Typ Max Unit Test Conditions R0 to R2 VCC - 3.0 -- V -- Note HD404019R, HD40L4019R: -IOH = 3 mA, VCC = 5 V 20% VCC - 2.0 -- -- V HD404019R, HD40L4019R: -IOH = 2 mA, VCC = 5 V 20% VCC - 1.0 -- -- V HD404019R, HD40L4019R: -IOH = 0.8 mA VCC - 3.0 -- -- V HD4074019: -IOH = 3 mA VCC - 2.0 -- -- V HD4074019: -IOH = 2 mA VCC - 1.0 -- -- V HD4074019: -IOH = 0.8 mA VCC - 3.0 -- -- V HD407L4019: -IOH = 3 mA, VCC = 4.5 V to 5.5 V Output low VOL voltage D4 to D15 , VCC - 2.0 -- -- V HD407L4019: -IOH = 2 mA VCC - 1.0 -- -- V HD407L4019: -IOH = 0.8 mA -- -- VCC - 37 V HD404019R, HD40L4019R: 1 Vdisp = VCC - 40 V R0 to R2 -- -- VCC - 37 V HD404019R, HD40L4019R: 2 150 k at VCC - 40 V -- -- VCC - 37 V HD4074019, HD407L4019: 150 k at VCC - 40 V Input/output | IIL | leakage current D4 to D15 , -- -- 20 A HD404019R, HD40L4019R: 3 Vin = VCC - 40 V to VCC R0 to R2, RA0, RA1 -- -- 20 A HD4074019, HD407L4019: 4 Vin = VCC - 40 V to VCC Pull-down MOS current Notes: 1. 2. 3. 4. 54 IPD D4 to D15 , R0 to R2, 125 -- 900 A HD404019R, HD40L4019R: Vdisp = VCC - 35 V, Vin = VCC RA0, RA1 Applied to I/O pins selected as with pull-up MOS by mask option. Applied to I/O pins selected as with pull-up MOS (PMOS open drain) by mask option. Excluding pull-down MOS current and output buffer current. Excluding output buffer current. 1 HD404019R Series AC Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Oscillation frequency fOSC OSC1, OSC2 0.4 4 4.5 MHz HD404019R: divide by 4 0.4 4 4.5 MHz HD40L4019R: Note VCC = 3.5 V to 6.0 V, divide by 4 0.4 -- 3.58 MHz HD40L4019R: divide by 4 0.2 4 4.5 MHz HD4074019: divide by 4 0.2 4 4.5 MHz HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4 Instruction cycle time tcyc 0.2 -- 3.58 MHz HD407L4019 0.89 1 20 s HD404019R 0.89 1 10 s HD40L4019R: VCC = 3.5 V to 6.0 V 1.12 -- 10 s HD40L4019R 0.89 1 20 s HD4074019: divide by 4 0.89 1 20 s HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4 Oscillation stabilization time tRC OSC1, OSC2 1.12 -- 20 s HD407L4019 -- -- 20 ms HD404019R, HD4074019 1 -- -- 20 ms HD40L4019R: 1 VCC = 3.5 V to 6.0 V -- -- -- -- 40 20 ms ms HD40L4019R 1 HD407L4019: 1 VCC = 4.5 V to 5.5 V -- -- 40 ms HD407L4019 1 Notes: 1. The oscillator stabilization time is the period from when V CC reaches its minimum allowable voltage (HD404019R/HD40L4019R: 3.5 V, HD4074019: 4.5 V, HD407L4019: 3.0 V (3.5 V when VCC = 3.5 V to 6.0 V)) at power-on until when the oscillator stabilizes, or after RESET goes high by MCU reset to quit stop mode. At power-on or when recovering from stop mode, apply the RESET input for more than tRC to meet the necessary time for oscillator stabilization. When using a crystal or ceramic oscillator, consult with the crystal oscillator manufacturer since the oscillator stabilization time depends on the circuit constants and stray capacitance. (See figure 26.) 55 HD404019R Series Item Symbol Pin Min Typ Max Unit Test Conditions Note External clock high width tCPH OSC1 92 -- -- ns HD404019R, HD4074019: divide 1 by 4 92 -- -- ns HD40L4019R: 1 VCC = 3.5 V to 6.0 V, divide by 4 120 -- -- ns HD40L4019R: divide by 4 1 92 -- -- ns HD407L4019: 1 VCC = 4.5 V to 5.5 V, divide by 4 External clock low width tCPL OSC1 115 -- -- ns HD407L4019 1 92 -- -- ns HD404019R, HD4074019: divide by 4 1 92 -- -- ns HD40L4019R: 1 VCC = 3.5 V to 6.0 V, divide by 4 120 -- -- ns HD40L4019R: divide by 4 1 92 -- -- ns HD407L4019: 1 VCC = 4.5 V to 5.5 V, divide by 4 115 -- -- ns HD407L4019 1 External clock rise time tCPr OSC1 -- -- 20 ns 1 External clock fall time tCPf OSC1 -- -- 20 ns 1 INT0 high width tIH INT0 2 -- -- tcyc 2 INT0 low width tIL INT0 2 -- -- tcyc 2 INT1 high width tIH INT1 2 -- -- tcyc 2 INT1 low width tIL INT1 2 -- -- tcyc 2 RESET high width tRSTH RESET 2 -- -- tcyc 3 Input capacitance Cin All pins -- -- 30 pF RESET fall time f = 1 MHz, V in = 0 V tRSTf Notes: 1. See figure 26. 2. See figure 27. 3. See figure 28. 56 HD404019R, HD40L4019R: All pins -- except R90 -- 30 pF R90 -- -- 180 pF -- -- 20 ms HD4074019, HD407L4019: f = 1 MHz, V in = 0 V 3 HD404019R Series Serial Interface Timing Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Notes Transmit clock tScyc cycle time SCK output 1 -- -- tcyc Load shown in figure 30 1, 2 Transmit clock tSCKH high widths SCK output 0.4 -- -- tcyc 1, 2 Transmit clock tSCKL low widths SCK output 0.4 -- -- tcyc 1, 2 Transmit clock tSCKr rise time SCK output -- -- 40 ns HD404019R, HD4074019, HD407L4019 1, 2 -- -- 40 ns HD40L4019R: 1, 2 VCC = 3.5 V to 6.0 V Transmit clock tSCKf fall time SCK output -- -- 200 ns HD40L4019R 1, 2 -- -- 40 ns HD404019R, HD4074019, HD407L4019 1, 2 -- -- 40 ns HD40L4019R: 1, 2 VCC = 3.5 V to 6.0 V -- -- 200 ns HD40L4019R 1, 2 Transmit clock tScyc cycle time SCK input 1 -- -- tcyc 1 Transmit clock tSCKH high width SCK input 0.4 -- -- tcyc 1 Transmit clock tSCKL low width SCK input 0.4 -- -- tcyc 1 Transmit clock tSCKHD completion detect time SCK input 1 -- -- tcyc 3 Transmit clock tSCKr rise time SCK input -- -- 40 ns 1 Transmit clock tSCKf fall time SCK input -- -- 40 ns 1 Notes: 1. See figure 29. 2. See figure 30. 3. Transmit clock completion detect time is the high level period after 8 pulses of transmit clock are input. The serial interrupt request flag is not set when the next transmit clock is input before the transmit clock completion detect time has passed. 57 HD404019R Series Item Symbol Serial output tDSO data delay time Pin Min Typ Max Unit Test Conditions Notes SO -- -- 300 ns HD404019R 1, 2 -- -- 300 ns HD40L4019R: 1, 2 VCC = 3.5 V to 6.0 V -- -- 500 ns HD40L4019R 1, 2 -- -- 200 ns HD4074019 1, 2 -- -- 200 ns HD407L4019: 1, 2 VCC = 4.5 V to 5.5 V Serial input tSSI data setup time SI -- -- 400 ns HD407L4019 1, 2 100 -- -- ns HD404019R 1 100 -- -- ns HD40L4019R: 1 VCC = 3.5 V to 6.0 V Serial input tSSI data setup time Serial input data hold time tHSI SI SI 300 -- -- ns HD40L4019R 1 200 -- -- ns HD4074019, HD407L4019 1 200 -- -- ns HD404019R 1 200 -- -- ns HD40L4019R: 1 VCC = 3.5 V to 6.0 V 400 -- -- ns HD40L4019R 1 100 -- -- ns HD4074019 1 100 -- -- ns HD407L4019: 1 VCC = 4.5 V to 5.5 V 200 Notes: 1. See figure 29. 2. See figure 30. 58 -- -- ns HD407L4019 1 HD404019R Series HD404019R HD4074019 HD407L4019 1/fCP VCC - 0.5 tCPH 0.5 tCPr tCPL tCPf HD40L4019R 1/fCP VCC - 0.3 tCPH 0.3 tCPr tCPL tCPf Figure 26 Oscillator Timing HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) INT0, INT1 0.8 VCC 0.2 VCC tIH tIL tIH tIL HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) INT0, INT1 0.9 VCC 0.1 VCC Figure 27 Interrupt Timing HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) RESET 0.8 VCC 0.2 VCC tRSTH tRSTf HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) RESET 0.9 VCC 0.1 VCC tRSTH tRSTf Figure 28 Reset Timing 59 HD404019R Series HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) tScyc tSCKf SCK VCC - 2.0 V (0.8 VCC)* 0.8 V (0.2 VCC)* tSCKr tSCKL tSCKHD tSCKH tDSO VCC - 2.0 V SO 0.8 V tSSI tHSI 0.7 VCC 0.3 VCC SI Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output. 0.8 VCC and 0.2 VCC are the threshold voltages for transmit clock input. HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) tScyc tSCKf SCK VCC - 2.0 V (0.9 0.8 V (0.1 VCC)* VCC)* tSCKr tSCKL tSCKHD tSCKH tDSO VCC - 2.0 V SO 0.8 V tSSI tHSI 0.7 VCC 0.3 VCC SI Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output. 0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock input. Figure 29 Timing of Serial Interface VCC RL = 2.6 k Test point C 30 pF R 12 k 1S2074 H or equivalent Figure 30 Timing Load Circuit 60 HD404019R Series HD404019R Option List Date of order Customer Please check off the appropriate applications and enter the necessary information. Dept. Name 5 V operation: HD404019R ROM code name Low-voltage operation: HD40L4019R LSI type number (Hitachi's entry) Note: I/O options masked by 1. I/O option R1 R2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin E R3 R4 R5 R6 R7 R8 R9 RA R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 I/O Standard pins High voltage pins A High voltage pins R0 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 High voltage pins D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 I/O Standard pins Pin I/O option B C D A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I are not available. I/O option B C D E Please mark on RA1/Vdisp A: Without pull-up MOS (NMOS open drain) B: With pull-up MOS C: CMOS (not be used as input) D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS 61 HD404019R Series HD404019R Option List 2. RA1/Vdisp RA1: Without pull-down MOS (D) 3. Divider (DIV) Divide by 4 Vdisp Note: If even one high-voltage pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 4. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System oscillator (OSC1 and OSC2) Ceramic oscillator Crystal oscillator External clock 6. Stop mode Used Not used 7. Package HD404019R DP-64S FP-64A FP-64A FP-64B 62 HD40L4019R DP-64S HD404054 Series/HD404094 Series Rev. 5.0 March 1997 Description The HD404054 Series and HD404094 Series are HMCS400-series microcomputers designed to increase program productivity with large-capacity memory. Each microcomputer has three timers, one serial interface, comparator, input capture circuit. The HD404054 Series includes three chips: the HD404052 with 2-kword ROM; the HD404054 with 4kword ROM; and the HD4074054 with 4-kword PROM (ZTAT version). Also, the HD404094 Series includes three chips: the HD404092 with 2-kword ROM; the HD404094 with 4-kword ROM; and the HD4074094 with 4-kword PROM (ZTAT version). The HD4074054 and HD4074094 are PROM version (ZTAT microcomputers). Program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTATversion is 27256-compatible.) Features * The differences between HD404054 Series and HD404094 Series I/O pins * * * * * * * * HD404054 Series HD404094 Series 10 large-current output pins: Six 15-mA sinks and four 10-mA sources * 6 largecurrent output pins: Two 15-mA sinks and four 10-mA sources * 4 intermediate voltage output pins 27 I/O pins and 8 dedicated input pins Three timer/counters Eight-bit input capture circuit Two timer outputs (including two PWM outputs) One event counter inputs (including one double-edge function) One clock-synchronous 8-bit serial interface Comparator (2 channels) Built-in oscillators Main clock: Ceramic or crystal oscillator (an external clock is also possible) HD404054 Series/HD404094 Series * Six interrupt sources Two by external sources Four by internal sources * Subroutine stack up to 16 levels, including interrupts * Two low-power dissipation modes Standby mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time: 1 s (fOSC = 4 MHz at 1/4 division ratio) 1/4, or 1/32 division ratio can be selected by hardware * Two operating modes MCU mode MCU/PROM mode (HD4074054, HD4074094) Ordering Information Product Name Type HD404054 Series HD404094 Series ROM (words) RAM (digit) Package Mask ROM HD404052H HD404092H 2,048 512 FP-44A HD404052S HD404092S ZTAT HD40A4052H FP-44A HD40A4052S DP-42S HD404054H HD404094H HD404054S HD404094S 4,096 FP-44A DP-42S HD40A4054H FP-44A HD40A4054S DP-42S HD4074054H HD4074094H HD4074054S HD4074094S ZTAT: Zero Turn Around Time 2 DP-42S 4,096 ZTAT is a trademark of Hitachi, Ltd. FP-44A DP-42S HD404054 Series/HD404094 Series Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DP-42S 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VCC SEL R43 /SO1 R42 /SI 1 R41 /SCK1 R40 /EVND R33 R32 /TOD R31 /TOC R30 R23 R22 R21 R20 R13 R12 R11 R10 R00 /INT1 D13 /INT0 D12 /STOPC FP-44A 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 R40 /EVND R33 R32 /TOD R31 /TOC R30 R23 R22 R21 R20 R13 R12 D5 D6 D7 D8 D9 D12 /STOPC D 13 /INT0 R0 0 /INT1 R10 R11 NC RE0/VCref TEST OSC1 OSC2 RESET GND D0 D1 D2 D3 D4 44 43 42 41 40 39 38 37 36 35 34 NC RC0 RD3 RD2 RD1 /COMP1 RD0 /COMP0 VCC SEL R4 3 /SO 1 R4 2 /SI1 R4 1 /SCK 1 RD 0 /COMP0 RD 1 /COMP1 RD2 RD3 RC0 RE 0 /VCref TEST OSC1 OSC2 RESET GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Top view 3 HD404054 Series/HD404094 Series Pin Description Pin Number Item Symbol DP-42S FP-44A 42 38 Applies power voltage GND 11 6 Connected to ground Test TEST 7 2 I Used for factory testing only: Connect this pin to V CC Reset RESET 10 5 I Resets the MCU Oscillator OSC1 8 3 I OSC2 9 4 O D0-D9 12-21 7-16 I/O* Power supply VCC Port I/O Function Input/output pins addressed by individual bits; pins D0-D3 are high-current source pins that can each supply up to 10 mA. The HD404054 Series: pins D4-D9are high-current sink pins that can each supply up to 15mA. The HD404094 Series: D4-D7 are intermediate voltage (12 V) NMOS open-drain pins, and D 8, D9 are high-current sink pins that can each supply up to 15 mA. D12,D13 22, 23 17, 18 I Input pins addressable by individual bits R00-R43 24-40 19-36 I/O Input/output pins addressable in 4-bit units RD0-RD3, 1-6 39-43,1 I Input pins addressable in 4-bit units RC0, RE0 Interrupt INT0, INT1 23, 24 18, 19 I Input pins for external interrupts Stop clear STOPC 22 17 I Input pin for transition from stop mode to active mode Serial SCK 1 38 34 I/O Serial clock input/output pin SI1 39 35 I Serial receive data input pin SO1 40 36 O Serial transmit data output pin TOC, TOD 34, 35 30, 31 O Timer output pins EVND 37 33 I Event count input pins COMP0, 1, 2 39, 40 I Analog input pins for voltage comparator 6 1 41 37 Timer Comparator COMP1 VCref Division rate SEL Reference voltage pin for inputting the threshold voltage of the analog input pin. I Input pin for selecting system clock division rate after RESET input or after stop mode cancellation. 1/4 division rate: Connect it to VCC 1/32 division rate: Connect it to GND Note: * D4-D7 of the HD404094 Series are output pins. 4 HD404054 Series/HD404094 Series GND V CC SEL OSC 2 OSC 1 STOPC TEST RESET Block Diagram System control External interrupt RAM (512 x 4bit) Timer A D port INT0 INT1 W (2bit) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 High current source pins High current sink pins Intermediate voltage NMOS open-drain output pins* X (4bit) SI1 SO1 SCK1 VCref COMP0 COMP1 Y (4bit) Timer D Serial 1 Comparator SPY (4bit) ALU CPU ST CA (1bit) (1bit) A (4bit) Internal data bus TOD SPX (4bit) Internal address bus EVND Timer C Internal data bus TOC RE port RC port RD port R4 port R3 port R2 port R1 port R0 port D 12 D 13 R0 0 R10 R11 R12 R13 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 RD0 RD1 RD2 RD3 RC0 RE 0 B (4bit) SP (10bit) Instruction decoder PC (14bit) ROM (4,096 x 10bit) (2,048 x 10bit) Note: * Only HD404094 Series : Data bus : Signal line 5 HD404054 Series/HD404094 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$07FF (HD404052, HD40A4052, HD404092), $0000-$0FFF (HD404054, HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding. 0 $0000 Vector address $000F 15 $0010 16 Zero-page subroutine (64 words) $003F 63 64 2047 Program & Pattern 2048 words (HD404052, HD40A4052, HD404092) $0040 $07FF 4096 words (HD404054, HD40A4054, HD4074054,HD404094, HD4074094) 4095 0 JMPL instruction 1 (Jump to RESET, STOPC routine) JMPL instruction 2 (Jump to INT0 routine) 3 JMPL instruction 4 (Jump to INT1 routine) 5 6 7 8 9 JMPL instruction (Jump to timer A routine) 10 11 12 13 14 15 JMPL instruction (Jump to timer C, routine) Not used JMPL instruction (Jump to timer D, routine) JMPL instruction (Jump to serial 1 routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0FFF Figure 1 ROM Memory Map RAM Memory Map The MCU contains a 512-digit x 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows. 6 HD404054 Series/HD404094 Series 0 $000 RAM-mapped registers 64 Memory registers (MR) 80 $040 $050 Not used $090 144 0 3 4 5 6 7 8 9 Interrupt control bits area (PMRA) W Port mode register A Serial mode register 1A (SM1A) W Serial data register 1 lower (SR1L) R/W Serial data register 1 upper (SR1U) R/W Timer mode register A (TMA) W $000 $003 $004 $005 $006 $007 $008 $009 Not used Data (432 digits) $240 576 Not used 960 $3C0 Stack (64 digits) $3FF 1023 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (MIS) Miscellaneous register Timer mode register C1 (TMC1) (TRCL/TWCL) Timer C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer D (TRDU/TWDU) Not used Timer mode register C2 (TMC2) Timer mode register D2 (TMD2) Not used Compare data register (CDR) (CER) Compare enable register W W R/W R/W W R/W R/W R/W R/W R W $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 Not used R: Read only W: Write only R/W: Read/Write 31 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Register flag area Port mode register B (PMRB) (PMRC) Port mode register C Not used W W Detection edge select register 2 (ESR2) (SM1B) W W (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) W W W W W Serial mode register 1B Not used Port D0 to D3 DCR Port D4 to D 7 DCR Port D8 and D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 Not used Two registers are mapped on the same area. 63 $03F 14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E 15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012 Figure 2 RAM Memory Map 7 HD404054 Series/HD404094 Series RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$018, $024-$034) This area is used as mode registers and data registers for external interrupts, serial interface 1, timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090-$23F): 432 digits from $090 to $23F. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 8 HD404054 Series/HD404094 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMTC (IM of timer C) IFTC (IF of timer C) Not used Not used $002 3 IMS1 (IM of serial interface 1) IFS1 (IF of serial interface 1) IMTD (IM of timer D) IFTD (IF of timer D) $003 Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 32 Not used Not used WDON (Watchdog on flag) Not used $020 33 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $021 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM IF ICSF ICEF RAME RSP WDON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Not executed Allowed Not executed Not executed Inhibited Inhibited Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. If the TM or TDM instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 9 HD404054 Series/HD404094 Series Bit 3 Bit 2 $000 $003 : Not used Interrupt control bits area R42/SI1 PMRA $004 SM1A $005 Bit 0 Bit 1 R41/SCK1 R43/SO1 Serial transmit clock speed selection 1 SR1L $006 Serial data register 1 (lower digit) SR1U $007 Serial data register 1 (upper digit) TMA $008 MIS $00C TMC1 $00D Clock source selection (timer A) *2 *1 SO 1 PMOS control Clock source selection (timer C) TRCL/TWCL $00E Timer C register (lower digit) TRCU/TWCU $00F Timer C register (upper digit) TMD1 $010 *1 Clock source selection (timer D) TRDL/TWDL $011 Timer D register (lower digit) TRDU/TWDU $012 Timer D register (upper digit) $013 Timer-C output mode selection TMC2 $014 TMD2 $015 *3 Timer-D output mode selection $016 CDR $017 CER $018 *4 Result of each analog input comparison *5 $020 Register flag area $023 R00/INT1 PMRB $024 PMRC $025 D13/INT0 D12/STOPC R40/EVND $026 ESR2 $027 EVND detection edge selection *6 SM1B $028 *7 DCD0 $02C Port D3 DCR Port D2 DCR Port D1 DCR Port D0 DCR DCD1 $02D Port D7 DCR Port D6 DCR Port D5 DCR Port D4 DCR DCD2 $02E Port D9 DCR Port D8 DCR DCR0 $030 Port R0 0 DCR DCR1 $031 Port R13 DCR Port R1 2 DCR Port R1 1 DCR Port R1 0 DCR DCR2 $032 Port R2 3 DCR Port R2 2 DCR Port R2 1 DCR Port R2 0 DCR DCR3 $033 Port R3 3 DCR Port R3 2 DCR Port R3 1 DCR Port R3 0 DCR DCR4 $034 Port R4 3 DCR Port R4 2 DCR Port R4 1 DCR Port R4 0 DCR $03F Notes: 1. Auto-reload on/off 2. Pull-up MOS control 3. Input capture selection 4. Comparator switch 5. Port/comparator selection 6. SO1 output level control in idle states 7. Serial clock source selection 1 Figure 5 Special Function Register Area 10 HD404054 Series/HD404094 Series Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC 12 PC11 $3FC 1021 PC 10 PC9 PC 8 PC7 $3FD 1022 CA PC6 PC 5 PC4 $3FE 1023 PC 3 PC2 PC 1 PC0 $3FF PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 11 HD404054 Series/HD404094 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 (ST) 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. 12 HD404054 Series/HD404094 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction-but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1. 13 HD404054 Series/HD404094 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Contents Interrupt Interrupt enable flag (IE) 0 Inhibits all interrupts flags/mask Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0 - All bits 0 Turns output buffer off (to high impedance) DCD2) I/O (DCR0- DCR4) All bits 0 Port mode register A (PMRA) - - 00 Refer to description of port mode register A Port mode register B (PMRB) ---0 Refer to description of port mode register B Port mode register C bits 3, 1, 0 (PMRC3, 000 PMRC1, PMRC0) Refer to description of port mode register C Detection edge select register 2 (ESR2) 00 - - Disables edge detection Timer/ Timer mode register A (TMA) - 000 Refer to description of timer mode register A counters, Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 serial Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 interface Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A Serial mode register 1B (SM1B) - - X0 Refer to description of serial mode register 1B Prescaler S (PSS) $000 -- Timer counter A (TCA) $00 -- Timer counter C (TCC) $00 -- Timer counter D (TCD) $00 -- Timer write register C (TWCU, TWCL) $X0 -- Timer write register D (TWDU, $X0 -- Octal counter TWDL) 000 -- 0 - 00 Refer to description of voltage comparator Comparator Compare enable register (CER) 14 HD404054 Series/HD404094 Series Item Bit register Others Abbr. Watchdog timer on flag Initial Value (WDON) 0 Contents Refer to description of timer C Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 00 - - Refer to description of operating modes, and oscillator circuit Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM RAM enable flag Status After Status After Cancellation of Stop Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Status After all Other Types of Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained (RAME) Port mode register 1 (PMRC12) bit 2 1 0 0 Pre-stop-mode values are retained 0 0 Interrupts The MCU has 6 interrupt sources: Two external signals (INT0, INT1), Three timer/counters (timers A, C, and D), and one serial interface (serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. 15 HD404054 Series/HD404094 Series A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Not used 4 $0008 Timer C 5 $000A Timer D 6 $000C Serial 1 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 16 HD404054 Series/HD404094 Series $ 000,0 IE INT0 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $ 000,2 IFO $ 000,3 IMO Vector address Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Not used Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC Timer D interrupt $ 003,0 IFTD $ 003,1 IMTD $ 003,2 Serial 1 interrupt IFS1 $ 003,3 IMS1 Note: $m,n is RAM address $m, bit number n. Figure 8 Interrupt Control Circuit 17 HD404054 Series/HD404094 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer C Timer D Serial 1 IE 1 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 0 IF1 * IM1 * 1 0 0 0 0 IFTA * IMTA * * 1 0 0 0 IFTC * IMTC * * * 1 0 0 IFTD * IMTD * * * * 1 0 IFS1 * IMS1 * * * * * 1 Note: * Can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution * Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 9 Interrupt Processing Sequence 18 Execution of instruction at start address of interrupt routine HD404054 Series/HD404094 Series Power on RESET = 0? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC) + 1 PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer-A interrupt? No PC $000A Yes Timer-C interrupt? No PC $000C Yes Timer-D interrupt? No PC $000E (serial 1 interrupt) Figure 10 Interrupt Processing Flowchart 19 HD404054 Series/HD404094 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input to INT0 and INT1 as listed in table 5. Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001) IF0, IF1 Interrupt Request 0 No 1 Yes External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 ExternalInterrupt Masks (IM0, 1M1: $000, $001) IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes 20 HD404054 Series/HD404094 Series Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 9. Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 10. Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 11. Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0 No 1 Yes 21 HD404054 Series/HD404094 Series Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 12. Table 12 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flags (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13 Serial Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 Interrupt Request 0 No 1 Yes Serial Interrupt Masks (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. Table 14 Serial Interrupt Mask (IMS1: $003, Bit 3) IMS1 Interrupt Request 0 Enabled 1 Disabled (masked) 22 HD404054 Series/HD404094 Series Operating Modes The MCU has Three operating modes as shown in table 15. The operations in each mode are listed in tables 16 and 17. Transitions between operating modes are shown in figure 11. Table 15 Operating Modes and Clock Status Mode Name Active Standby Stop Activation method SBY instruction RESET cancellation, interrupt request, STOPC cancellation in stop mode STOP instruction Status OP Stopped System oscillator OP RESET input, RESET input, interrupt RESET input, STOPC STOP/SBY instruction request input in stop mode Cancellation method Note: OP implies in operation Table 16 Operations in Low-Power Dissipation Modes Function Stop Mode Standby Mode CPU Reset Retained RAM Retained Retained Timer A Reset OP Timer C Reset OP Timer D Reset OP Serial interface 1 Reset OP Comparator Reset Stopped I/O Reset* Retained Note: OP implies in operation * Output pins are at high impedance. Table 17 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode Stop Mode Active Mode D0-D9 Retained High impedance Input enabled D12, D13 , RC0, -- -- Input enabled Retained or output of peripheral functions High impedance Input enabled RD0-RD3, RE0 R0-R4 23 HD404054 Series/HD404094 Series Reset by RESET input or by watchdog timer fOSC: Main oscillation frequency fcyc: f OSC/4 or or fOSC /32 (hardware selectable) o CPU: System clock o PER: Clock for other peripheral functions RAME = 0 RESET1 RESET2 STOPC Active mode Standby mode fOSC: Oscillate o CPU: Stop o PER: fcyc RAME = 1 SBY Interrupt Stop mode (TMA3 = 0) fOSC: Oscillate o CPU: fcyc o PER: fcyc STOP fOSC: o CPU: o PER: Stop Stop Stop Figure 11 MCU Status Transitions Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12. 24 HD404054 Series/HD404094 Series Stop Standby Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop No RESET = 0? Yes No RESET = 0? Yes IF0 * IM0 = 1? No No STOPC = 0? Yes IF1 * IM1 = 1? No Yes Yes IFTA * IMTA = 1? No Yes RAME = 1 RAME = 0 IFTC * IMTC = 1? Yes No IFTD * IMTD = 1? Yes No IFS1 * IMS1 = 1? No Yes Restart processor clocks Restart processor clocks Execute next instruction No Reset MCU IF = 1, IM = 0, and IE = 1? Execute next instruction Yes Accept interrupt Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. The MCU enters stop mode if the STOP instruction is executed in active mode. Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. 25 , HD404054 Series/HD404094 Series Stop mode Oscillator Internal clock STOP or RESET tres STOP instruction execution tres tRC (stabilization period) Figure 13 Timing of Stop Mode Cancellation Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 14 to 16. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. 26 HD404054 Series/HD404094 Series Power on RESET = 0? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 14 MCU Operating Sequence (Power On) 27 HD404054 Series/HD404094 Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 15 MCU Operating Sequence (MCU Operation Cycle) 28 HD404054 Series/HD404094 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Stop mode Standby mode No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle For IF and IM operation, refer to figure 12. Figure 16 MCU Operating Sequence (Low-Power Mode Operation) 29 HD404054 Series/HD404094 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 17. As shown in table 18, a ceramic oscillator can be connected to OSC 1 and OSC2. The system oscillator can also be operated by an external clock. After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be selected as 1/4 or 1/32 by setting the SEL pin level. * 1/4 division ratio: Connect SEL to VCC. * 1/32 division ratio: Connect SEL to GND. OSC2 OSC1 System fOSC oscillator 1/4 or 1/32 division circuit* fcyc tcyc Timing generator circuit CPU PER Note: * 1/4 or 1/32 division ratio can be selected by SEL pin. Figure 17 Clock Generation Circuit RE 0 TEST OSC 1 OSC 2 RESET GND GND Figure 18 Typical Layout of Ceramic Oscillator 30 CPU with ROM, RAM, registers, flags, and I/O Peripheral function interrupt HD404054 Series/HD404094 Series Table 18 Oscillator Circuit Examples Circuit Configuration External clock operation Ceramic oscillator (OSC1, OSC2) Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator: CSB400P22 (Murata), C1 OSC1 Ceramic oscillator CSB400P (Murata) Rf = 1 M 20% Rf C1 = C2 = 220 pF 5% OSC2 C2 GND Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 18). 31 HD404054 Series/HD404094 Series Input/Output The MCU has 27 input/output pins (D0-D9, R0 0-R4 3) and 8 input pins (D12, D13, RC0, RD0- RD3, RE 0). The features are described below. Some input/output pins have different features between the HD404054 Series and HD404094 Series. The differences between the HD404054 Series and HD404094 Series are listed in table 19. * A maximum current of 15 mA is allowed for each of the pins D 4 to D9 with a total maximum current of less than 105 mA. In addition, D0-D3 can each act as a 10-mA maximum current source. * Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R43/SO1 pin can be set to NMOS opendrain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Pins D0-D3 have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 19 programmable I/O circuits are listed in table 20, and I/O pin circuit types are shown in table 21. Table 19 The differences between HD404054 Series and HD404094 Series HD404054 Series HD404094 Series Large-current source pins (15 mA) D0-D3 D0-D3 Large-current sink pins (10 mA) D4-D9 D8, D9 Intermediate voltage NMOS open-drain pins (12 V) D4-D7 (output only) Pull-down MOS current pins D0-D3 D0-D3 Pull-up MOS current pins D4-D9, R0-R4 D8, D9, R0-R4 32 HD404054 Series/HD404094 Series Table 20-1 Programmable I/O Circuits (with pull-up MOS) MIS3 (Bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS 1 1 0 1 Note: -- indicates off status. Table 20-2 Programmable I/O Circuits (with pull-down MOS) MIS3 (Bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- On -- On -- CMOS buffer Pull-down MOS 1 1 0 1 Note: -- indicates off status. D4-D9, R port (HD404054 Series) D8, D9, R port (HD404094 Series) HLT Pull-up control signal VCC Pull-up MOS MIS3 VCC Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 19-1 I/O Buffer Configuration (with pull-up MOS) 33 HD404054 Series/HD404094 Series D0-D3 port Input control signal VCC Input data Buffer control signal DCD, DCR Output data PDR MIS3 Pull-down control signal HLT Figure 19-2 I/O Buffer Configuration (with pull-down MOS) 34 HD404054 Series/HD404094 Series Table 21 Circuit Configurations of I/O Pins Pins HD404054 Series HD404094 Series HLT D4-D9, D8, D9, MIS3 R0-R4 R0-R4 D0-D3 D0-D3 R43 R43 -- D4-D7 I/O Pin Type Circuit Input/output pins VCC Pull-up control signal Buffer control signal VCC DCD, DCR Output data PDR Input data Input control signal Input control signal VCC Input data Buffer control signal DCD, DCR Output data PDR MIS3 Pull-down control signal HLT VCC HLT VCC Pull-up control signal Buffer control signal Output data MIS3 DCR MIS2 PDR Input data Input control signal HLT Output pins DCD Output data PDR 35 HD404054 Series/HD404094 Series Pins I/O Pin Type Circuit Input data Input pins VCC Input data VCC SO1 SO1 TOC, TOD TOC, TOD HLT SI1, INT1, SI1, INT1, MIS3 EVND EVND MIS3 SCK1 SCK1 HLT VCC Pull-up control signal MIS3 PMOS control signal Output data VCC Pull-up control signal Output data Input pins MIS2 SO1 HLT VCC D12, D13 , RC0 SCK 1 Pull-up control signal Output data Output pins D12, D13 , RC0 SCK 1 HLT VCC HD404094 Series RD0-RD3, RE0 RD0-RD3, RE0 Input control signal Peripheral Input/ function output pins pins HD404054 Series VCC MIS3 TOC, TOD PDR Input data Input data SI1, INT1, EVND INT0, INT0, STOPC STOPC INT0, STOPC Note: The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. D Port (D0-D13): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0-D3 are highcurrent sources, and D12 and D 13 are input-only pins. D4-D9 of the HD404054 Series are high-current sinks. D4-D7 of the HD404094 Series are middle voltage output-only pins, and D8 and D9 are high-current sink pins. Pins D 0-D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions. 36 HD404054 Series/HD404094 Series The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 20). Pins D12 and D 13 are multiplexed with peripheral function pins S TOP C and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 22). R Ports (R0 0-RE0): 17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR4: $030-$034) that are mapped to memory addresses (figure 20). Pin R0 0 is are multiplexed with peripheral pin INT1 respectively. The peripheral function modes of these pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21). Pins R31-R32 are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function modes of these pins are selected by bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24). Pin R40 is multiplexed with peripheral pin EVND respectively. The peripheral function modes of these pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22). Pins R41-R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26. Ports RD0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively. The function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018) (figure 27). Port RE 0 is multiplexed with peripheral function pin VCref. While functioning as VC ref , do not use this pin as an R port at the same time, otherwise, the MCU may malfunction. Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS transistor is provided for each input/output pin other than input-only pins D 12 and D 13. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 20 and figure 28). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k or pulled down to GND by their pull-down MOS transistors. Note: *If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B register. 37 HD404054 Series/HD404094 Series Data control register (DCD0 to 2: $02C to $02E) (DCR0 to 4: $030 to $034) DCD0, DCD1 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name DCD03- DCD02- DCD01- DCD00- DCD13 DCD12 DCD11 DCD10 DCD2 Bit 3 2 1 0 Initial value -- -- 0 0 -- -- W Read/Write Bit name Not used Not used DCD21 W DCD20 DCR0 Bit 3 2 1 Initial value -- -- -- 0 Read/Write -- -- -- W Bit name 0 Not used Not used Not used DCR00 DCR1 to DCR4 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name DCR13- DCR12- DCR11- DCR10- DCR43 DCR42 DCR41 DCR40 All Bits CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 -- -- D9 D8 DCR0 -- -- -- R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 Figure 20 Data Control Registers (DCD, DCR) 38 HD404054 Series/HD404094 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value -- -- -- 0 -- -- -- W Read/Write Bit name Not used Not used Not used PMRB0 PMRB0 R00/INT1 mode selection 0 R00 1 INT1 Figure 21 Port Mode Register B (PMRB) Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 -- Read/Write W W W -- Bit name PMRC3 PMRC2* PMRC1 Not used PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D12/STOPC mode selection 0 D12 1 STOPC PMRC3 D13/INT0 mode selection 0 D13 1 INT0 Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value. Figure 22 Port Mode Register C (PMRC) 39 HD404054 Series/HD404094 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- R/W R/W R/W TMC21 TMC20 Bit name Not used TMC22 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 -- Inhibited TOC PWM output 1 1 0 R31/TOC mode selection 1 1 0 1 Figure 23 Timer Mode Register C2 (TMC2) 40 HD404054 Series/HD404094 Series Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 Bit name R32/TOD mode selection TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 -- Inhibited 1 TOD PWM output x R32 Input capture (R32 port) 1 1 0 1 1 x 1 0 x x : Don't care Figure 24 Timer Mode Register D2 (TMD2) Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used PMRA1 PMRA0 PMRA0 R43/SO1 mode selection 0 R43 1 SO1 PMRA1 R42/SI1 mode selection 0 R42 1 SI1 Figure 25 Port Mode Register A (PMRA) 41 HD404054 Series/HD404094 Series Serial mode register 1A (SM1A: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SM1A3 SM1A2 SM1A1 SM1A0 Bit name SM1A3 R41/SCK1 mode selection 0 R41 1 SCK1 Prescaler division ratio SM1A2 SM1A1 SM1A0 SCK1 Clock source 0 0 0 Output Prescaler / 2048 1 Output Prescaler / 512 0 Output Prescaler / 128 1 Output Prescaler / 32 0 Output Prescaler /8 1 Output Prescaler /2 0 Output System clock -- 1 Input External clock -- 1 1 0 1 Figure 26 Serial Mode Register 1A (SM1A) Compare enable register (CER: $018) Bit 3 2 1 0 Initial value 0 -- 0 0 Read/Write W -- W W CER3 Not used CER1 CER0 Bit name CER3 Digital/Analog selection CER1 CER0 Digital input mode: RD0 /COMP0 and RD1 /COMP1 operate as an R port. 0 0 COMP0 0 0 1 COMP1 1 0 Not used 1 Analog input mode: RD0 /COMP0 and RD 1 /COMP1 operate as analog input. 1 1 Not used Figure 27 Compare Enable Register 42 Analog input pin selection HD404054 Series/HD404094 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 -- -- W W -- -- MIS3 MIS2 Read/Write Bit name MIS3 Pull-up MOS on/off selection Not used Not used MIS2 CMOS buffer on/off selection for pin R43/SO1 0 Off 0 On 1 On 1 Off Figure 28 Miscellaneous Register (MIS) 43 HD404054 Series/HD404094 Series Prescalers The MCU has the following prescaler S. The prescaler operating conditions are listed in table 22, and the prescaler output supply is shown in figure 29. The timers A, C, D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset. Table 22 Prescaler Operating Conditions Prescaler Input Clock Reset Condition Stop Conditions Prescaler S System clock MCU reset MCU reset, stop mode Timer A Timer C System clock Prescaler S Timer D Serial 1 Figure 29 Prescaler Output Supply 44 HD404054 Series/HD404094 Series Timers The MCU has three timer/counters (A, C, and D). * Timer A: Free-running timer * Timer C: Multifunction timer * Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are listed in table 23. The operating modes are selected by software. Timer A Timer A Functions: Timer A has the following functions. * Free-running timer The block diagram of timer A is shown in figure 30. Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 31. 45 HD404054 Series/HD404094 Series Table 23 Timer Functions Functions Clock source Timer functions Timer outputs Timer A Timer C Timer D Prescaler S Available Available Available External event -- -- Available Free-running Available Available Available Event counter -- -- Available Reload -- Available Available Watchdog -- Available -- Input capture -- -- Available Toggle -- Available Available 0 output -- Available Available 1 output -- Available Available PWM -- Available Available Note: -- means not available. Timer A interrupt request flag (IFTA) Timer counter A (TCA) Overflow Internal data bus Clock System clock o PER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 30 Block Diagram of Timer A 46 HD404054 Series/HD404094 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- W W W Not used TMA2 TMA1 TMA0 Bit name Source Input clock TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc Timer A mode Note: Timer counter overflow output period (seconds) = input clock period (seconds) x 256. Figure 31 Timer Mode Register A (TMA) 47 HD404054 Series/HD404094 Series Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 32. System reset signal Watchdog on flag (WDON) TOC Timer C interrupt flag (IFTC) Watchdog timer control logic Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Timer counter C (TCC) Timer write register CU (TWCU) /2 /4 /8 /32 /128 /512 /1024 /2048 Selector System oPER clock Prescaler S (PSS) Overflow Free-running /reload control Timer write register CL (TWCL) 3 Timer mode register C1 (TMC1) 3 Timer mode register C2 (TMC2) Figure 32 Block Diagram of Timer C 48 Internal data bus Clock HD404054 Series/HD404094 Series Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer C has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 33. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 33. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is low. 49 HD404054 Series/HD404094 Series Toggle output waveform (timers C, and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 - N) clock cycles (256 - N) clock cycles PWM output waveform (timers C and D) T x (N + 1) TMC13 = 0 TMD13 = 0 T T x 256 TMC13 = 1 TMD13 = 1 T x (256 - N) Notes: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 34 and 41) N: The value of the timer write register Figure 33 Timer Output Waveform 50 HD404054 Series/HD404094 Series Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 34. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name TMC13 W W W W TMC13 TMC12 TMC11 TMC10 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period TMC12 TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 34 Timer Mode Register C1 (TMC1) 51 HD404054 Series/HD404094 Series * Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 35. It is reset to $0 by MCU reset. Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- R/W R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 -- Inhibited TOC PWM output Bit name 1 1 0 R31/TOC mode selection 1 0 1 1 Figure 35 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) as shown in figures 36 and 37. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer C is initialized by writing to timer write register C (TWCL: $00E, TWCU: $00F). In this case, the lower digit (TWCL) must be written to first, but writing only to the lower digit does not change the timer C value. Timer C is initialized to the value in timer write register C at the same time the upper digit (TWCU) is written to. When timer write register C is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer C. Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 36 Timer Write Register C Lower Digit (TWCL) 52 HD404054 Series/HD404094 Series Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 37 Timer Write Register C Upper Digit (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures 38 and 39. The upper digit (TRCU) must be read first. At this time, the count of the timer C upper digit is obtained, and the count of the timer C lower digit is latched to the lower digit (TRCL). After this, by reading TRCL, the count of timer C when TRCU is read can be obtained. Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 38 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 39 Timer Read Register C Upper Digit (TRCU) 53 HD404054 Series/HD404094 Series Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 40-1 and 40-2. Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-C's toggle output. 0 output: The operation is basically the same as that of timer-C's 0 output. 1 output: The operation is basically the same as that of timer-C's 1 output. 54 HD404054 Series/HD404094 Series PWM output: The operation is basically the same as that of timer-C's PWM output. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. 55 HD404054 Series/HD404094 Series Timer D interrupt request flag (IFTD) Timer output control logic TOD Timer read register DU (TRDU) Timer output control Timer read register DL (TRDL) Clock Timer write register DU (TWDU) System clock oPER /2048 Edge detection logic /2 /4 /8 /32 /128 /512 Selector EVND Overflow Free-running/ reload control Timer write register DL (TWDL) 3 Prescaler S (PSS) Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 40-1 Block Diagram of Timer D (Free-Running/Reload Timer) 56 Internal data bus Timer counter D (TCD) HD404054 Series/HD404094 Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Timer counter D (TCD) Overflow Selector /2 /4 /8 /32 /128 /512 /2048 3 System clock Timer mode register D1 (TMD1) Internal data bus Input capture timer control oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode) 57 HD404054 Series/HD404094 Series Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 41. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMD13 TMD12 TMD11 TMD10 Bit name TMD13 Free-running/reload timer selection TMD12 TMD11 TMD10 0 Free-running timer 0 0 0 2048tcyc 1 Reload timer 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R40/EVND (external event input) 1 1 0 1 Input clock period and input clock source Figure 41 Timer Mode Register D1 (TMD1) 58 HD404054 Series/HD404094 Series * Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 42. It is reset to $0 by MCU reset. Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 -- Inhibited 1 TOD PWM output x R32 Input capture (R32 port) 1 1 0 R32/TOD mode selection 1 0 1 1 x x x : Don't care Figure 42 Timer Mode Register D2 (TMD2) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) as shown in figures 43 and 44. The operation of timer write register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F). Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWDL3 TWDL2 TWDL1 TWDL0 Bit name Figure 43 Timer Write Register D Lower Digit (TWDL) 59 HD404054 Series/HD404094 Series Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 44 Timer Write Register D Upper Digit (TWDU) * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) as shown in figures 45 and 46. The operation of timer read register D is basically the same as that of timer read register C (TRCL: $00E, TRCU: $00F). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 45 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 46 Timer Read Register D Upper Digit (TRDU) 60 HD404054 Series/HD404094 Series * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 47. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 -- Read/Write W W W -- Bit name PMRC3 PMRC2 PMRC1 Not used PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D12/STOPC mode selection 0 D12 1 STOPC PMRC3 D13/INT0 mode selection 0 D13 1 INT0 Figure 47 Port Mode Register C (PMRC) * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 48. It is reset to $0 by MCU reset. Detection edge register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 -- -- W -- -- Read/Write W Bit name ESR23 ESR22 Not used Not used EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection * 1 Note: * Both falling and rising edges are detected. Figure 48 Detection Edge Select Register 2 (ESR2) 61 HD404054 Series/HD404094 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 24. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 24 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Reload Timer write register updated to value N T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 62 T x (N + 1) T HD404054 Series/HD404094 Series Serial Interface 1 The MCU has one channel of serial interface. The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Serial interface 1 * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of serial interface 1 is shown in figure 49. 63 HD404054 Series/HD404094 Series Serial interrupt request flag (IFS1) Octal counter (OC) Idle control logic SO1 Serial data register (SR1L/U) I/O control logic SCK1 Transfer control 1/2 /2 /8 /32 /128 /512 /2048 Selector System clock oPER 1/2 Selector SI1 3 Serial mode register 1A (SM1A) Prescaler S (PSS) Serial mode register 1B (SM1B) Figure 49 Block Diagram of Serial Interface 1 64 Internal data bus Clock HD404054 Series/HD404094 Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 25 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface 1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). Pins R42/SI 1 and R4 3/SO 1 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000 by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 is set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0-SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 26. Table 25 Serial Interface 1 Operating Modes SM1A PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 65 HD404054 Series/HD404094 Series Table 26 Serial Transmit Clock (prescaler output) SM1B SM1A Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Tranamit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 0 Operating States: Serial interface 1 has the following operating states; transitions between them are shown in figure 50. STS wait state Transmit clock wait state Transfer state Continuous transmit clock output state (only in internal clock mode) * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state. * Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. 66 HD404054 Series/HD404094 Series In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SM1A write 04 01 STS instruction 00 MCU reset 06 SM1A write (IFS1 1) 02 Transmit clock Transfer state (Octal counter 000) Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks 05 STS instruction (IFS1 1) Internal clock mode SM1A write 18 Continuous transmit clock output state (PMRA 0, 1 = 0, 0) SM1A write 14 STS wait state (Octal counter = 000, transmit clock disabled) 10 MCU reset 13 8 transmit clocks 11 STS instruction 16 SM1A write (IFS1 1) Transmit clock 17 12 Transmit clock Transfer state (Octal counter 000) Transmit clock wait state (Octal counter = 000) 15 STS instruction (IFS1 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 50 Serial Interface State Transitions Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output of serial output pin, SO1 can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the output level cannot be controlled in transfer state. 67 , HD404054 Series/HD404094 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SM1A write Output level control in idle states Dummy write for state transition Output level control in idle states SM1B write Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB MSB IFS1 External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SM1A write Output level control in idle states SM1B write Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin Undefined LSB MSB IFS1 Internal clock mode Flag reset at transfer completion Figure 51 Example of Serial Interface 1 Operation Sequence 68 HD404054 Series/HD404094 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 52. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag is set again, and therefore the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set. To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. 69 HD404054 Series/HD404094 Series Transfer completion (IFS1 1) Interrupts inhibited IFS1 0 SM1A write Yes IFS1 = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State SCK 1 pin (input) Transfer state Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. SM1A write IFS1 Flag set because octal counter reaches 000. Transmit clock error detection procedures Figure 52 Transmit Clock Error Detection 70 Flag reset at transfer completion. HD404054 Series/HD404094 Series Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. * * * * * Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Serial data register 1 (SR1L: $006, SR1U: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 53). * * * * R4 1/SCK 1 pin function selection Serial interface 1 transmit clock selection Serial interface 1 prescaler division ratio selection Serial interface 1 initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 71 HD404054 Series/HD404094 Series Serial mode register 1A (SM1A: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W SM1A3 SM1A2 SM1A1 SM1A0 Bit name SM1A3 R41/SCK1 mode selection 0 R41 1 SCK1 Prescaler division ratio SM1A2 SM1A1 SM1A0 SCK1 Clock source 0 0 0 Output Prescaler Refer to table 26 0 Output System clock -- 1 Input External clock -- 1 1 0 1 1 0 0 1 1 Figure 53 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 54). * Serial interface 1 prescaler division ratio selection * Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to. 72 HD404054 Series/HD404094 Series Serial mode register 1B (SM1B: $028) Bit 3 2 1 0 Initial value -- -- Undefined 0 Read/Write -- -- W W Bit name Not used Not used SM1B1 SM1B1 Output level control in idle states SM1B0 SM1B0 Serial clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 54 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 55 and 56) * Serial interface 1 transmission data write and shift * Serial interface 1 receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 57. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register 1(lower digit) (SR1L: $006) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR13 SR12 SR11 SR10 Figure 55 Serial Data Register 1 (SR1L) Serial data register 1(upper digit) (SR1U: $007) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR17 SR16 SR15 SR14 Figure 56 Serial Data Register 1 (SR1U) 73 HD404054 Series/HD404094 Series Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 57 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 58). * R4 2/SI 1 pin function selection * R4 3/SO 1 pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used PMRA1 PMRA0 PMRA0 R43/SO1 mode selection 0 R43 1 SO1 PMRA1 R42/SI1 mode selection 0 R42 1 SI1 Figure 58 Port Mode Register A (PMRA) 74 HD404054 Series/HD404094 Series Miscellaneous Register (MIS: $00C): This register has the following functions (figure 59). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 2-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 -- -- Read/Write W W -- -- MIS3 MIS2 Bit name Not used Not used MIS2 R43/SO1 PMOS on/off selection 0 On 1 Off MIS3 Pull-up MOS on/off selection 0 Off 1 On Figure 59 Miscellaneous Register (MIS) 75 HD404054 Series/HD404094 Series Comparator The block diagram of the comparator is shown in figure 60. The comparator compares input voltage with the reference voltage. COMP0 COMP1 Selector Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison. When an input voltage at COMP0, COMP1 is higher than the reference voltage, the TM or TMD command sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to COMP 0 and COMP1. On the other hand, when an input voltage at COMP0, COMP1 is lower, the TM or TMD command clears the ST to 0. + Comparator Comparator data register (CDR) Internal data bus - VCref Comparator enable register (CER) Figure 60 Block Diagram of Comparator 76 HD404054 Series/HD404094 Series Compare Enable Register (CER: $018): Three-bit write-only register which enables comparator operation, and selects the reference voltage and the analog input pin (figure 61). Compare enable register (CER: $018) Bit 3 2 Initial value 0 -- 0 0 Read/Write W -- W W Bit name CER3 0 1 CER3 1 Not used CER1 Digital/Analog selection 0 CER0 CER1 CER0 0 0 COMP0 1 COMP1 0 Not used 1 Not used Digital input mode: RD0 /COMP0, RD1 /COMP1 operate as R port 1 Analog input mode: RD0 /COMP0, RD1 /COMP1 operate as analog input Analog input pin selection Figure 61 Compare Enable Register Compare Data Register (CDR: $017): Two-bit read-only register which latches the result of the comparison between the analog input pins and the reference voltage. Bits 0 and 1 corresponds the results of comparison with COMP0 and COMP1, respectively. This register can be read only by the TM or TMD command. Only bit CER3 corresponds to the analog input pin which the input pin selection is made through pins CER0 and CER1. After a compare operation, the data in this register is not retained (figure 62). Compare data register (CDR: $017) Bit 3 2 Initial value -- -- Read/Write -- -- Bit name Not used Not used 1 0 Undefined Undefined R R CDR1 CDR0 Result of COMP0 comparison Result of COMP1 comparison Figure 62 Compare Data Register Note on Use: During the compare operation pins RD0/COMP0 and RD1/COMP1 operate as analog inputs and cannot operate as R ports. The comparator can operate in active mode but is disabled in other modes. RE0/VC ref cannot operate as an R port when the external input voltage is selected as the reference. 77 HD404054 Series/HD404094 Series Programmable ROM (HD4074054, HD4074094) The HD4074054 and HD4074094 are ZTAT microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode PROM Mode DP-42S FP-44A Pin Name I/O Pin Name I/O 1 39 RD0/COMP0 I CE I 2 40 RD1/COMP1 I OE I 3 41 RD2 I 4 42 RD3 I 5 43 RC0 I 6 1 RE0/VCref I M1 I 7 2 TEST I TEST I 8 3 OSC1 I VCC 9 4 OSC2 O 10 5 RESET I RESET 11 6 GND I GND 12 7 D0 I/O O 13 8 D1 I/O O 14 9 D2 I/O VCC 15 10 D3 I/O VCC 16 11 D4 I/O* O4 I/O 17 12 D5 I/O* O5 I/O 18 13 D6 I/O* O6 I/O 19 14 D7 I/O* O7 I/O 20 15 D8 I/O A13 I 21 16 D9 I/O A14 I 22 17 D12/STOPC I A9 I 23 18 D13/INT0 I VPP 24 19 R00/INT1 I/O M0 I 25 20 R10 I/O A5 I 26 21 R11 I/O A6 I 27 23 R12 I/O A7 I Note: I/O: Input/output pin, I: Input pin, O: Output pin * HD404054 Series: I/O, HD404094 Series: O 78 I HD404054 Series/HD404094 Series Pin No. MCU Mode PROM Mode DP-42S FP-44A Pin Name I/O Pin Name I/O 28 24 R13 I/O A8 I 29 25 R20 I/O A0 I 30 26 R21 I/O A10 I 31 27 R22 I/O A11 I 32 28 R23 I/O A12 I 33 29 R30 I/O A1 I 34 30 R31/TOC I/O A2 I 35 31 R32/TOD I/O A3 I 36 32 R33 I/O A4 I 37 33 R40/EVND I/O O0 I/O 38 34 R41/SCK 1 I/O O1 I/O 39 35 R42/SI1 I/O O2 I/O 40 36 R43/SO1 I/O O3 I/O 41 37 SEL I 42 38 VCC I - 22 NC - - 44 NC - VCC Note: I/O: Input/output pin, I: Input pin, O: Output pin 79 HD404054 Series/HD404094 Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET low as shown in figure 63. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD4074054 and HD4074094 are listed in table 27. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 4-kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 8-kbyte address space ($0000-$7FFF) must be specified. VCC VCC RESET TEST M0 VPP M1 O0 to O7 Data O0 to O7 A0 to A14 Address A0 to A14 VPP HD4074054 HD4074094 VCC OSC1 D2 D3 OE OE CE CE GND Figure 63 PROM Mode Connections Table 27 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Model Name Manufacturer DATA I/O Corp. 121B DP-42S HS4654ESS01H Hitachi AVAL Corp. PKW-1000 FP-44A HS4654ESH01H Hitachi 80 HD404054 Series/HD404094 Series Warnings 1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 28. Table 28 PROM Mode Selection Pin Mode CE OE VPP O0-O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 81 HD404054 Series/HD404094 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 64 and described below. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register direct addressing 1st word of Instruction 2nd word of Instruction Opcode d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory register addressing Figure 64 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. 82 HD404054 Series/HD404094 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 65 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 67. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 66. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 83 HD404054 Series/HD404094 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct addressing Instruction [BR] Program counter Opcode b6 b7 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current page addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero page addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table data addressing Figure 65 ROM Addressing Modes 84 B2 B1 Accumulator HD404054 Series/HD404094 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern output Figure 66 P Instruction 85 HD404054 Series/HD404094 Series 256 (n - 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 67 Branching when the Branch Destination is on a Page Boundary 86 HD404054 Series/HD404094 Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V Pin voltage VT -0.3 to VCC + 0.3 V Notes 1 -0.3 to +15.0 V 2 Total permissible input current Io 80 mA 3 Total permissible output current -Io 50 mA 4 Maximum input current Io 4 mA 5, 6 30 mA 5, 7 4 mA 8, 9 20 mA 8, 10 Maximum output current -Io Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D13 (VPP ) of HD4074054 and HD4074094. 2. Applies to D4 to D7 of HD404092, HD404094, and HD4074094. 3. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 4. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 5. The maximum input current is the maximum current flowing from each I/O pin to GND. 6. Applies to D0-D3, and R0-R4. 7. Applies to D4-D9 . 8. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 9. Applies to D4-D9 and R0-R4. 10. Applies to D0-D3. 87 HD404054 Series/HD404094 Series Electrical Characteristics DC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20 C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Input high voltage VIH RESET, STOPC, 0.9 VCC INT0, INT1, SCK 1, SI1, EVND OSC1 Input low voltage VIL Min Typ Max Unit -- VCC + 0.3 V VCC - 0.3 -- VCC + 0.3 V Test Condition Notes External clock RESET, STOPC, -0.3 INT0, INT1, SCK 1, SI1, EVND -- 0.10 VCC V OSC1 -0.3 -- 0.3 V External clock Output high voltage VOH SCK 1, SO1, TOC,TOD VCC - 1.0 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK 1, SO1, TOC,TOD -- -- 0.4 V IOL = 0.4 mA I/O leakage current | IIL | RESET, STOPC, -- INT0, INT1, SCK 1, SI1, SO1, EVND, OSC1, TOC, TOD -- 1 A Vin = 0 V to VCC 1 Current dissipation in active mode ICC1 VCC -- 5 -- mA VCC = 5 V, fOSC = 4 MHz Digital input mode 2, 4, 7 -- 5 10 mA VCC = 5 V, fOSC = 8 MHz Digital input mode 3, 4, 7 2, 4, 7 ICC2 VCC -- 0.6 1.8 mA VCC = 3 V, fOSC = 800 kHz Digital input mode ICMP1 VCC -- 9 -- mA VCC = 5 V, 2, 4, 7 fOSC = 4 MHz Analog comp. mode -- 9 15 mA VCC = 5 V, 3, 4, 7 fOSC = 8 MHz Analog comp. mode -- 3.1 4.3 mA VCC = 3 V, 2, 4, 7 fOSC = 800 kHz Analog comp. mode ICMP2 88 VCC HD404054 Series/HD404094 Series Item Symbol Pin(s) Current dissipation ISBY1 in standby mode VCC Min Typ Max Unit Test Condition Notes -- 1.2 -- mA VCC = 5 V, fOSC = 4 MHz 2, 6, 7 -- 3 6 mA VCC = 5 V, fOSC = 8 MHz 3, 6, 7 ISBY2 VCC -- 0.2 0.7 mA VCC = 3 V, fOSC = 800 kHz 2, 6, 7 Current dissipation ISTOP in stop mode VCC -- 1 5 A VCC = 3 V 2, 8 -- 1 10 A VCC = 5 V 3, 8 V Stop mode retaining voltage VSTOP VCC -- 1.3 -- Comparator input reference voltage scope VCref VCref 0 -- VCC - 1.2 V Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 9 Output buffer current is excluded. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094 and HD4074094. Applies to HD40A4052 and HD40A4054. ICC1 and ICC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at GND (0 V to 0.3V) TEST at VCC (VCC - 0.3 to VCC) RD0 and RD1 pins are analog input mode when no I/O current is flowing. Test conditions: MCU: Analog input mode Pins: RD0/COMP0 at GND (0 V to 0.3 V) RD1/COMP1 at GND (0 V to 0.3 V) RE0/VCref at GND (0 V to 0.3 V) ISBY1 and ISBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at VCC (VCC - 0.3 to VCC) TEST at VCC (VCC - 0.3 to VCC) The current dissipation is in proportion to fOSC while the MCU is operating or is in standby mode. The value of the dissipation on current when fOSC = F MHz is given by the following equation: Maximum value (fOSC = F MHz) = F/4 x maximum value (fOSC = 4 MHz) These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at VCC (VCC - 0.3 to VCC) TEST at VCC (VCC - 0.3 to VCC) D13* at VCC (VCC - 0.3 to VCC) Note: * Applies to HD4074054 and HD4074094 RAM data retention. 89 HD404054 Series/HD404094 Series I/O Characteristics for Standard Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: V CC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Input high voltage VIH Input low voltage Typ Max D12-D13 , 0.7 VCC R0-RD, RE0 -- VCC + 0.3 V VIL D12-D13 , -0.3 R0-RD, RE0 -- 0.3 VCC V Output high voltage VOH R0-R4 VCC - 1.0 -- -- V -IOH = 0.5 mA Output low voltage VOL R0-R4 -- -- 0.4 V IOL = 0.4 mA I/O leakage current | IIL | D12, R0-RD, -- RE0 -- 1 A Vin = 0 V to VCC 1 D13 -- -- 1 A Vin = 0 V to VCC 1, 2, 4 -- -- 1 A Vin = VCC - 0.3 V to VCC 1, 3 -- -- 20 A Vin = 0 V to 0.3 V 1, 3 -- 30 -- A VCC = 3 V, Vin = 0 V 2, 3 20 100 500 A VCC = 5 V, Vin = 0 V 4 Pull-up MOS -IPU current R0-R4 Min Unit Test Condition Notes Input high voltage VIHA COMP0, COMP1 -- VCref+0.0 5 -- V Analog compare mode 5 Input low voltage VILA COMP0, COMP1 -- VCref-0.05 -- V Analog compare mode 5 Notes: 1. 2. 3. 4. 5. 90 Output buffer current is excluded. Applies to HD404052, HD404054, HD404092, HD404094. Applies to HD4074054, HD4074094. Applies to HD40A4052, HD40A4054. The analog input reference voltage should be in the range 0 VCref VCC-1.2. HD404054 Series/HD404094 Series I/O Characteristics for High-Current Pins and Intermediate-Voltage Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified) Pin(s) Item Symbol HD404054 HD404094 Series Series Min Typ Max Unit Input high voltage VIH D0-D9 D0-D3, D8, D9 0.7 VCC -- VCC + 0.3 V Input low voltage VIL D0-D9 D0-D3, D8, D9 -0.3 -- 0.3 VCC V Output high voltage VOH D0-D9 D0-D3, D8, D9 VCC - 1.0 -- -- V -IOH = 0.5 mA D0-D3 D0-D3 2.0 -- -- V -IOH = 10 mA, VCC = 4.5 V to 6.0 V -- D4-D7 11.5 -- -- V 500 k at 12 V D0-D9 D0-D9 -- -- 0.4 V IOL = 0.4 mA D4-D9 D4-D9 -- -- 2.0 V IOL = 15 mA, VCC = 4.5 V to 6.0 V D0-D9 D0-D3, D8, D9 -- -- 1 A Vin = 0 V to VCC 1 -- D4-D7 -- -- 20 A Vin = 0 V to 12 V 1 D0-D3 D0-D3 -- 30 -- A VCC = 3 V, Vin = 3 V 3 -- 20 100 500 A VCC = 5 V, Vin = 5 V 4 D8, D9 -- 30 -- A VCC = 3 V, Vin = 0 V 3 -- 20 100 500 A VCC = 5 V, Vin = 0 V 4 Output low voltage I/O leakage current VOL | IIL | Pull-down IPD MOS current Pull-up MOS -IPU current Notes: 1. 2. 3. 4. D4-D9 Test Condition Notes 2 2 Output buffer current is excluded. When using HD4074054, HD4074094, VCC = 4.5 V to 5.5 V. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. Applies to HD40A4052, HD40A4054. 91 HD404054 Series/HD404094 Series AC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = -20 C to +75C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Clock oscillation frequency fOSC Instruction cycle time Oscillation stabilization time (ceramic) OSC1, OSC2 tcyc tRC OSC1, OSC2 Min Typ Max Unit Test Condition Notes 0.4 -- 4 MHz 1 0.4 -- 8.5 MHz 2 -- 8 -- s fOSC = 4 MHz, /32 1, 4 -- 3.76 -- s fOSC = 8.5 MHz, /32 2, 4 -- 1 -- s fOSC = 4 MHz, /4 1, 3 -- 0.47 -- s fOSC = 8.5 MHz, /4 2, 3 -- -- 7.5 ms VCC = 2.7 V to 5.5 V: 3, 4 HD4074054, HD4074094 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094 External clock high width tCPH External clock low width tCPL External clock rise time tCPr External clock fall time tCPf OSC1 OSC1 OSC1 OSC1 -- -- 60 ms VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 -- -- 7.5 ms VCC = 4.0 V to 6.0 V: 5, 6 HD40A4052,HD40A4054 105 -- -- ns 1, 7 49 -- -- ns 2, 7 105 -- -- ns 1, 7 49 -- -- ns 2, 7 -- -- 20 ns 1, 7 -- -- 10 ns 2, 7 -- -- 20 ns 1, 7 -- -- 10 ns 2, 7 INT0, INT1, EVND high width tIH INT0, INT1, 2 EVND -- -- tcyc 8 INT0, INT1, EVND low width tIL INT0, INT1, 2 EVND -- -- tcyc 8 RESET low width tRSTL RESET 2 -- -- tcyc 9 STOPC low width tSTPL STOPC 1 -- -- tRC 10 RESET rise time tRSTr RESET -- -- 20 ms 9 STOPC rise time tSTPr STOPC -- -- 20 ms 10 92 HD404054 Series/HD404094 Series Item Symbol Pin(s) Input capacitance Cin Analog comparator tCSTB stabilization time Min All pins except -- D13 D4-D7 Typ Max Unit Test Condition -- 15 pF f = 1 MHz, V in = 0 V Notes D4-D7 -- -- 30 pF f = 1 MHz, V in = 0 V D13 -- -- 15 pF f = 1 MHz, V in = 0 V: HD404052, HD404054, HD404092, HD404094, HD40A4052,HD40A4054 -- -- 180 pF f = 1 MHz, V in = 0 V: HD4074054, HD4074094 -- -- 2 tcyc VCC = 2.7 V to 5.5 V: 9 HD4074054, HD4074094 COMP0, COMP1 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094 -- -- 4 tcyc VCC = 4.0 V to 6.0 V: 11 HD40A4052,HD40A4054 -- -- 20 tcyc VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 Notes: 1. 2. 3. 4. 5. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. Applies to HD40A4052, HD40A4054. SEL = 1 SEL = 0 The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 2.7 (HD4074054, HD4074094)/1.8 (HD404052, HD404054, HD404092, HD404094) /4.0 (HD40A4052, HD40A4054)V at power-on, or after RESET input goes low or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 6. Applies to ceramic oscillator only. 7. Refer to figure 68. 8. Refer to figure 69. 9. Refer to figure 70. 10. Refer to figure 71. 11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering RD0/COMP0, RD1/COMP1 into analog input mode. 93 HD404054 Series/HD404094 Series Serial Interface Timing Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pin(s) Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 1 -- -- tcyc Load shown in figure 73 1 Transmit clock high width tSCKH SCK 1 0.5 -- -- tScyc Load shown in figure 73 1 Transmit clock low width tSCKL SCK 1 0.5 -- -- tScyc Load shown in figure 73 1 Transmit clock rise time tSCKr SCK 1 -- 100 -- ns Load shown in figure 73 1, 2 -- -- 80 ns -- 100 -- ns -- -- 80 ns -- -- 500 ns -- -- 200 ns 1, 3 300 -- -- ns 1, 2 150 -- -- ns 1, 3 300 -- -- ns 1, 2 150 -- -- ns 1, 3 Transmit clock fall time Serial output data delay time tSCKf tDSO Serial input data tSSI setup time Serial input data tHSI hold time Note: 94 SCK 1 SO1 SI1 SI1 1, 3 Load shown in figure 73 1, 2 1, 3 Load shown in figure 73 1. Refer to figure 72. 2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094. 3. Applies to HD40A4052, HD40A4054. 1, 2 HD404054 Series/HD404094 Series During Transmit Clock Input Item Symbol Pin(s) Min Typ Max Unit Transmit clock cycle time tScyc SCK 1 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 1 0.5 -- -- tScyc 1 Transmit clock low width tSCKL SCK 1 0.5 -- -- tScyc 1 Transmit clock rise time tSCKr SCK 1 -- 100 -- ns 1, 2 -- -- 80 ns 1, 3 -- 100 -- ns 1, 2 -- -- 80 ns 1, 3 -- -- 500 ns -- -- 200 ns 1, 3 300 -- -- ns 1, 2 150 -- -- ns 1, 3 300 -- -- ns 1, 2 150 -- -- ns 1, 3 Transmit clock fall time Serial output data delay time tSCKf tDSO Serial input data tSSI setup time Serial input data tHSI hold time Note: SCK 1 SO1 SI1 SI1 Test Condition Load shown in figure 73 Note 1, 2 1. Refer to figure72. 2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094. 3. Applies to HD40A4052, HD40A4054. 95 HD404054 Series/HD404094 Series OSC 1 1/fCP VCC - 0.3 V 0.3 V tCPL tCPH tCPr tCPf Figure 68 External Clock Timing RESET 0.9 VCC tRSTL 0.1 V CC tRSTr Figure 69 Interrupt Timing INT0 , INT1, EVND 0.9 VCC t IL t IH 0.1 VCC Figure 70 Reset Timing STOPC 0.9 VCC tSTPL 0.1 V CC tSTPr Figure 71 STOPC Timing 96 HD404054 Series/HD404094 Series t Scyc t SCKf SCK 1 VCC - VH (0.9 VCC )* 0.4 V (0.1 VCC )* t SCKr t SCKL t SCKH t DSO VCC - VH 0.4 V SO 1 t HSI t SSI 0.9 V CC 0.1 V CC SI 1 Note: * VCC - VH and 0.4 V are the threshold voltages for transmit clock output. VH = 1.0 V : HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094 VH = 2.0 V : HD40A4052, HD40A4054 0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock output. Figure 72 Serial Interface Timing VCC RL = 2.6 k Test point C 30 pF R 12 k 1S2074 H or equivalent Figure 73 Timing Load Circuit 97 HD404054 Series/HD404094 Series Notes On ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions (HD404054, HD404094 and HD40A4054). A 4-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 4-kword version. This limitation apply to the case of using EPROM and the case of using data base. ROM 2 kwords version: HD404052, HD404092, HD40A4052 Address $0800 to $0FFF $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern and program (2048 words) $07FF $0800 Not used $0FFF 98 Fill this area with all 1s HD404054 Series/HD404094 Series HD40(A)4052/HD40(A)4054 Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department 1. ROM size Name HD404052: 2-kword HD40A4052: 2-kword ROM code name HD404054: 4-kword HD40A4054: 4-kword LSI number 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 4. Stop mode Used Not used 5. Package DP-42S FP-44A 99 HD404054 Series/HD404094 Series HD404092/HD404094 Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department 1. ROM size Name HD404092: 2-kword ROM code name HD404094: 4-kword LSI number 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 4. Stop mode Used Not used 5. Package DP-42S FP-44A 100 H42xx Family HD404202 Series/HD404222 Series Rev. 5.0 March 1997 Description These MCU's are CMOS 4-bit single-chip microcomputers with the same architecture as the HMCS400 Series. Each microcomputers incorporate ROM, RAM, I/O, and peripheral functions such as one or two timer/counters. Also, HD404222 Series has two-channel comparators, and a serial interface. The HD404202 Series includes four chips: the HD404201 with 1-kword ROM and 5-V operation; HD40L4201 with 1-kword ROM and low-voltage operation; HD404202 with 2-kword ROM and 5-V operation; HD40L4202 with 2-kword ROM and low-voltage operation. The HD404222 Series includes three chips: HD404222 with 2-kword ROM and 5-V operation; HD40L4222 with 2-kword and low-voltage operation; HD4074224 with 4-kword PROM. The HD4074224, incorporating PROM, is a ZTAT microcomputer which can dramatically shorten system development period and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features * The differences between HD404202 Series and HD404222 Series. HD404202 Series HD404222 Series RAM (digits) 64 128 Timers 8-bit x 1 8-bit x 2 Serial interface -- Clock-synchronous 8-bit x 1 Comparators * * * * -- 2 channels HMCS400 CPU (software-compatible with the HMCS400 Series) 1024-word x 10-bit mask ROM (HD404201, HD40L4201) 2048-word x 10-bit mask ROM (HD404202, HD40L4202, HD404222, HD40L4222) 4096-word x 10-bit PROM (HD4074224) HD404202 Series/HD404222 Series * * * * * * * * * * * 2 64-digit x 4-bit RAM (HD404201, HD40L4201, HD404202, and HD40L4202) 128-digit x 4-bit RAM (HD404222, HD40L4222, and HD4074224) 22 I/O pins including 10 high-current pins Two timer/counters 8-bit free-running or watchdog timer (watchdog timer is selectable by mask option) (HD404222 Series) 8-bit auto-reloading timer/event counter Clock-synchronous 8-bit serial interface (HD404222 Series) Two-channel comparators (HD404222 Series) Two analog input pins Reference voltage pin One external interrupt Low-power dissipation modes Standby mode Stop mode Built-in oscillator Resistor or ceramic oscillator (an external clock is also possible) Minimum instruction cycle time 0.89 s (fOSC = 4.5 MHz, VCC = 3.5 V- 6.0 V) 3.55 s (fOSC = 1.125 MHz, VCC = 2.5 V- 6.0 V) 2.0 s (fOSC = 2.0 MHz, VCC = 2.5 V-6.0 V) for HD40L4222 Package 28 pin shrink-type plastic DIP (DP-28S) 28-pin SOP (FP-28DA) 30-pin SSOP (FP-30D) HD404202 Series/HD404222 Series Type of Product Device Mask ROM HD404201S HD40L4201S Options Package 1024 Selected by mask option DP-28S HD404201FP HD40L4201FP FP-28DA HD404201FT HD40L4201FT FP-30D HD404202S HD40L4202S ZTAT ROM Size 2048 DP-28S HD404202FP HD40L4202FP FP-28DA HD404202FT HD40L4202FT FP-30D HD404222S HD40L4222S DP-28S HD404222FP HD40L4222FP FP-28DA HD404222FT HD40L4222FT FP-30D HD4074224S01 4096 Timer A: Free-running timer Oscillator: Resistor HD4074224S02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224S03 Timer A: Watchdog timer Oscillator: Resistor HD4074224S04 Timer A: Watchdog timer Oscillator: Ceramic oscillator HD4074224FP01 Timer A: Free-running timer Oscillator: Resistor HD4074224FP02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224FP03 Timer A: Watchdog timer Oscillator: Resistor HD4074224FP04 Timer A: Watchdog timer Oscillator: Ceramic oscillator HD4074224FT01 Timer A: Free-running timer Oscillator: Resistor HD4074224FT02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224FT03 Timer A: Watchdog timer Oscillator: Resistor HD4074224FT04 Timer A: Watchdog timer Oscillator: Ceramic oscillator DP-28S FP-28DA FP-30D 3 HD404202 Series/HD404222 Series Differences between Mask ROM and ZTAT Microcomputers Mask ROM ZTAT Item HD404201 HD40L4201 HD404202 HD40L4202 HD404222 HD40L4222 HD4074224 Power supply voltage (VCC) 3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 5.5 V, Instruction cycle time (tcyc ) 0.89 to 4.0 s ROM 1024 x 10- 1024 x 10bit bit 2048 x 10- 2048 x 10bit bit 2048 x 10- 2048 x 10bit bit 4096 x 10-bit RAM 64 x 4-bit 64 x 4-bit 64 x 4-bit 64 x 4-bit 128 x 4-bit 128 x 4-bit 128 x 4-bit Watchdog timer/ free running timer -- -- -- -- 1 1 1 Serial interface -- -- -- -- 1 1 1 Comparator -- -- -- -- 2 ch 2 ch 2 ch Without Available pull-up MOS (NMOS open drain) (option A) Available Available Available Available Available -- With pullup MOS (option B) Available Available Available Available Available Available Available CMOS (option C) Available Available Available Available Available Available -- Clock Ceramic generation Available Available Available Available Available Available Available Resistor Available with -- Available with -- Available with -- Available only under I/O pin circuit (standard pins) 2.7 to 3.5 V 3.55 to 10.0 0.89 to 4.0 s s tcyc = 1.33 to 4.0 s External Package 4 3.55 to 10.0 0.89 to 4.0 s s tcyc = 1.33 to 4.0 s 2.0 to 10.0 s tcyc = 1.33 to 4.0 s 0.89 to 4.0 s, 2.0 to 10.0 s VCC = 3.5 to 5.5 V with t cyc = 1.33 to 4.0 s Available Available Available Available Available Available Available DP-28S DP-28S DP-28S DP-28S DP-28S DP-28S DP-28S FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-30D FP-30D FP-30D FP-30D FP-30D FP-30D FP-30D HD404202 Series/HD404222 Series PinArrangement HD404201, HD40L4201, HD404202, HD40L4202 GND 1 28 R23 NC 1 30 NC R10 2 27 R22 GND 2 29 R23 R11 3 26 R21 R10 3 28 R22 R12 4 25 R20 R11 4 27 R21 R13 5 24 D13 R12 5 26 R20 D0 6 23 D12 R13 6 25 D13 D1 7 DP-28S 22 TEST D0 7 24 D12 D2 8 FP-28DA 21 RESET D1 8 23 TEST D3 9 20 OSC2 D2 9 22 RESET D4 10 19 OSC1 D3 10 21 OSC2 D5 /INT 11 18 V CC D4 11 20 OSC1 D6 12 17 D11 D5 /INT 12 19 V CC D7 13 16 D10 D6 13 18 D11 D8 14 15 D9 D7 14 17 D10 D8 15 16 D9 FP-30D HD404222, HD40L4222, HD4074224 GND 1 28 R23 NC 1 30 NC R10 2 27 R22 GND 2 29 R23 R11 3 26 R21 R10 3 28 R22 R12 4 25 R20 R11 4 27 R21 R13 5 24 D13 R12 5 26 R20 D0 6 23 D12 R13 6 25 D13 D1 7 DP-28S 22 TEST D0 7 24 D12 D2 8 FP-28DA 21 RESET D1 8 23 TEST D3 9 20 OSC2 D2 9 22 RESET D4 10 19 OSC1 D3 10 21 OSC2 D5 /INT 11 18 V CC D4 11 20 OSC1 D6 /SCK 12 17 D11/COMP1 D5 /INT 12 19 V CC D7 /SI 13 16 D10/COMP0 D6 /SCK 13 18 D11/COMP1 D8 /SO 14 15 D9 /V ref D7 /SI 14 17 D10/COMP0 D8 /SO 15 16 D9 /V ref FP-30D 5 HD404202 Series/HD404222 Series BlockDiagram HD404201, HD40L4201, HD404202, HD40L4202 D5 / INT RESET TEST OSC1 OSC2 V CC GND External interrupt Timer B/event counter System control 1024 x 10-bit 2048 x 10-bit ROM Interrupt control Instruction decoder 64 x 4-bit RAM Stack pointer X (4) Y (4) ST CA A (4) B (4) Program counter ALU SPX (4) R2 R2 3 R2 2 R2 1 R2 0 High-current pins SPY (4) R1 D port R13 R12 R11 R10 D13 D12 D11 D10 D9 D8 D7 D6 D5 / INT D4 D3 D2 D1 D0 HD404222, HD40L4222, HD4074224 D 10 / Comp0 D 11 / D 9/ D 8/ D 7/ D 6/ Comp1 V ref SO SI SCK D5 / INT RESET TEST OSC1 OSC2 V CC GND Voltage Serial Timer B/ Timer A/ External watchdog interrupt comparator interface event counter timer Interrupt control System control 2048 x 10-bit 4096 x 10-bit ROM Instruction decoder 128 x 4-bit RAM Stack pointer X (4) Y (4) ST CA A (4) B (4) Program counter ALU SPX (4) R2 R2 3 R2 2 R2 1 R2 0 High-current pins 6 SPY (4) R1 R13 R12 R11 R10 D port D13 D12 D11 / D10 / D9 / D8 / COMP1 COMP0 Vref SO D7 / SI D6 / D5 / SCK INT D4 D3 D2 D1 D0 HD404202 Series/HD404222 Series Pin Description Pin Number Item Symbol Power supply VCC DP-28S FP-28DA FP-30D I/O Function 18 19 Power supply pin GND 1 2 Ground connection pin Test TEST 22 23 I Pin used for test purposes only. Connect it to ground. Reset RESET 21 22 I MCU reset pins Oscillator OSC1, 19 20 I Pins for the internal oscillator circuit. Connect them to a resistor or a ceramic oscillator, or connect OSC 1 to an external oscillator circuit. The internal oscillator is selected by mask option. OSC2 20 21 O D0-D13 6-17, 7-18, I/O 23, 24 24, 25 Input/output ports addressable by individual bits. Pins D12 and D13 can output 15 mA maximum. 2-5, 3-6, I/O 25-28 26-29 Input/output ports addressable in 4-bit units. These pins can output 15 mA maximum. Port R10-R23 Interrupt INT 11 12 I Input pin for external interrupt. It is also used as an external event input for timer B. It is multiplexed with pin D5. Serial interface* SCK 12 13 I/O Serial interface clock input/output pin. It is multiplexed with pinD6. SI 13 14 I Serial interface receive data input pin. It is multiplexed with pin D7. SO 14 15 O Serial interface transmit data output pin. It is multiplexed with pin D8. Comparator* Vref 15 16 I Reference voltage pin to input the threshold voltage of the analog input pins COMP0 16 17 I Analog input pins for the voltage comparator COMP1 17 18 I Note: * Only applicable for the HD404222 Series. 7 HD404202 Series/HD404222 Series Memory Map ROM Memory Map The areas in ROM are described below with its memory map shown in figure 1. Vector Address Area: Locations $0000 through $0009 can be used for JMPL instructions to branch to the starting address of an initialization program for interrupt programs. After MCU reset or an interrupt is performed, the program is executed from a vector address. Zero-Page Subroutine Area: Locations $0000 through $003F can be used for subroutines. The CAL instruction branches to subroutines within this area. Pattern Area ($0000 to $03FF: HD404201, HD40L4201; $0000 to $07FF: HD404202, HD40L4202, HD404222, HD40L4222; $0000 to $0FFF: HD4074224): The P instruction allows reference to ROM data in this area as a pattern. Program Area ($0000 to $03FF: HD404201, HD40L4201; $0000 to $07FF: HD404202, HD40L4202, HD404222, HD40L4222; $0000 to $0FFF: HD4074224) 8 HD404202 Series/HD404222 Series HD404201, HD40L4201, HD404202, HD40L4202 0 $0000 Vector address 9 10 $0009 $000A Zero-page subroutine (64 words) 63 64 1023 1024 2047 HD404201, HD40L4201 Program/pattern (1024 words) HD404202, HD40L4202 Program/pattern (2048 words) $003F $0040 0 1 2 3 4 5 6 7 8 9 $0000 $0001 $0002 $0003 $0004 Not used $0005 JMPL instruction $0006 (Jump to timer B routine) $0007 $0008 Not used $0009 0 1 2 3 4 5 6 7 8 9 JMPL instruction (Jump to RESET routine) JMPL instruction (Jump to INT routine) JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B routine) JMPL instruction (Jump to serial routine) JMPL instruction (Jump to reset routine) JMPL instruction (Jump to INT routine) $03FF $0400 $07FF HD404222, HD40L4222, HD4074224 0 $0000 Vector address 9 10 $0009 $000A Zero-page subroutine (64 words) 63 64 $003F $0040 HD404222, HD40L4222 Program/pattern (2048 words) 2047 2048 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $07FF $0800 HD4074224 Program/pattern (4096 words) 4095 $0FFF Figure 1 ROM Memory Map 9 HD404202 Series/HD404222 Series RAM Memory Map In addition to data and stack areas, interrupt control bits and special function registers are also mapped in RAM memory. The RAM memory map shown in figure 2 is described below. Interrupt Control Bits Area ($0000 to $0002): The interrupt control bits area (figure 3) is used for interrupt control. This area and CMR (location $03) register is accessible only by RAM bit manipulation instructions. However, the interrupt request flag cannot be set by software. The RSP bit is used only to reset the stack pointer. Note that if unusable bits are manipulated, the MCU may malfunction (HD404202 Series: bits 0, 1 of $001, and $002; HD404222 Series: bits 2, 3 of $002). Special Function Registers Area ($003 to $00C): The special function registers are the mode or data registers for external interrupt, the serial interface, the timer/counters, comparator and are also used as data control registers for I/O ports. These registers are classified into three types: write-only, read-only, and read/write, as shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions (except for CMR register). Note that if the unusable locations are set, the MCU may mulfunction (only applicable for HD404202 Series $003, $005 to $008 and $00C). Data Area ($020 to $03F: HD404202 Series; $020 to $07F: HD404222 Series): The 16 digits of $020 through $02F are called memory registers (MR) and are also accessible by the LAMR and XMRA instructions (figure 4). Stack Area ($0E0 to $0FF): Locations $0E0 through $0FF are reserved for LIFO stacks to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or CALL instruction) or interrupt is performed. This area can be used as an 8-level nesting stack in which one level requires 4 digits. Figure 4 shows the stack area levels. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. When this area is not used as a stack, it becomes available as a data area. 10 HD404202 Series/HD404222 Series HD404201, HD40L4201, HD404202, HD40L4202 $000 0 31 32 47 48 63 64 Memory registers (MR) (16 digits) Data (16 digits) 0 $000 Interrupt control bits RAM mapped registers (32 digits) $01F $020 $02F $030 $03F $040 Not used (160 digits) 2 Not used 3 4 Port mode register (PMR) 5 Not used 8 9 Timer mode register B (TMB) (TCBL)/(TLRL) 10 Timer B* (TCBU)/(TLRU) 11 12 $0DF $0E0 223 224 Stack (32 digits) 255 $0FF $002 $003 W $004 $005 $008 W $009 R/W $00A R/W $00B $00C Not used 31 $01F 0 $000 HD404222, HD40L4222, HD4074224 $000 0 RAM mapped registers (32 digits) 31 32 47 48 Memory registers (MR) (16 digits) Interrupt control bits $01F $020 $02F $030 Data (80 digits) $07F $080 127 128 Not used (96 digits) 2 3 4 5 6 7 8 9 10 11 12 Comparator mode register (CMR) Port mode register (PMR) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B (TMB) (TCBL)/(TLRL) Timer B* (TCBU)/(TLRU) Reference voltage select register (RSR) $0DF $0E0 223 224 Stack (32 digits) 255 $0FF R/W W W R/W R/W W W R/W R/W R/W $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C Not used $01F 31 Note: The status flag becomes invalid when CMR bits are tested by the TM or TMD instructions (only applicable for HD404222 Series). R: Read only W: Write only R/W: Read/Write Timer/event counter B lower R (TCBL) Timer/event counter B upper 11 R (TCBU) 10 Timer load register B lower (TLRL) Timer load register B upper (TLRU) W $00A W $00B * Two registers are mapped on the same address. Figure 2 RAM Memory Map 11 HD404202 Series/HD404222 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM of external INT (IMEX) IF of external INT (IFEX) Reset SP bit (RSP) 1 IM of timer B (IMTB) IF of timer B (IFTB) IM of timer A * (IMTA) IF of timer A * (IFTA) $001 2 Not used Not used IM of serial * (IMS) IF of serial * (IFS) $002 Interrupt enable flag $000 (IE) IF: Interrupt request flag IM: Interrupt mask IE: Interrupt enable flag SP: Stack pointer Note: Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, reset by the REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other instructions. Furthermore, the interrupt request flag is not affected by the SEM/SEMD instruction. The status flag becomes invalid when the unused bits and RSP bit are tested by the TM or TMD instruction. * Only applicable for the HD404222 Series. Figure 3 Configuration of Interrupt Control Bits Area Memory registers 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 MR (0) MR (1) MR (2) MR (3) MR (4) MR (5) MR (6) MR (7) MR (8) MR (9) MR (10) MR (11) MR (12) MR (13) MR (14) MR (15) Stack area Bit 3 Bit 2 Bit 1 Bit 0 $020 224 Level 8 $0E0 252 ST PC13 PC12 PC11 $0FC $021 Level 7 $022 Level 6 PC10 PC 9 PC 8 PC 7 253 $0FD $023 Level 5 $024 Level 4 CA PC 6 PC 5 PC 4 254 $0FE $025 Level 3 $026 Level 2 PC3 PC 2 PC 1 PC 0 255 $0FF $027 255 Level 1 $0FF $028 PC11 - PC 0 : Program counter $029 ST: Status flag $02A CA: Carry flag $02B Note: According to on-chip ROM capacity, following area are ignored. $02C HD404201, HD40L4201: PC13 - PC10 $02D HD404202, HD40L4202, HD404222, HD40L4222: PC13 - PC11 $02E HD4074224: PC13, PC12 $02F Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position 12 HD404202 Series/HD404222 Series Functional Description Registers and Flags The MCU has eight registers and two flags for CPU operations (figure 5). 3 0 A 3 Accumulator 0 B 3 B register 0 X 3 X register 0 Y 3 Y register 0 SPX 3 SPX register 0 SPY 11 SPY register CA Carry flag ST Status flag 0 PC Program counter 7 1 4 1 1 0 SP Stack pointer Figure 5 Registers and Flags Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results of the arithmetic logic unit (ALU), and transfer data to/from memory, I/O, and other registers. X Register (X), Y Register (Y): The X and Y registers are 4-bit registers used for indirect addressing of RAM. The Y register is also used for D port addressing. SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY are used to assist the X and Y registers, respectively. Carry Flag (CA): The carry flag stores the overflow from the ALU generated by an arithmetic operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions. 13 HD404202 Series/HD404222 Series During an interrupt, the carry flag is pushed onto the stack and is pulled from the stack only by the RTNI instruction. Status Flag (ST): The status flag holds the ALU overflow, ALU non-zero, and the results of a bit test instruction for arithmetic or compare instructions. The status flag is also used as a branch condition for the BR, BRL, CAL, and CALL instructions. The value of the status flag remains unchanged until the next arithmetic, compare, or bit test instruction is executed. The status flag becomes a 1 after the BR, BRL, CAL, or CALL instruction was either executed or not. During an interrupt, the status flag is pushed onto the stack and can be pulled from the stack only by the RTNI instruction. Program Counter (PC): The program counter is a 12-bit binary counter which controls the sequence in which the instructions stored in ROM are executed. Stack Pointer: The stack pointer (SP) is used to point to the address of the next stack area (up to 8 levels). The stack pointer is initialized to RAM address $FF. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is pulled from it. The stack can only be used up to 8 levels deep because the upper 3 bits of the stack pointer are fixed at 111. The stack pointer is initialized to $FF by either MCU reset or RSP bit reset by the REM/REMD instruction. Reset The MCU is reset by pulling the RESET pin low. At power-on or when cancelling the stop mode, the reset period must satisfy tRC for the oscillator to stabilize. In other cases, at least two instruction cycles are required for the MCU to be reset. Table 1 shows the components initialized by the MCU reset, and the status of each component. Table 2 shows how registers recover from the stop mode. Take note that the reset signal is not acknowledged immediately at power-on by the MCU but at the time the oscillator has stabilized, so during this period the statuses within the MCU and at the I/O pins are not defined. 14 HD404202 Series/HD404222 Series Table 1 Initial Values After MCU Reset Item Initial Value by MCU Reset (RESET = 0) Contents Program counter (PC) $0000 Execute program from the top of ROM address Status flag (ST) 1 Enable branching with conditional branch instructions Stack pointer (SP) $0FF Stack level is 0 Without pull-up MOS 1 Enable input With pull-up MOS 1 Enable input CMOS 1 -- Interrupt enable flag (IE) 0 Inhibit all interrupts Interrupt request flag (IF) 0 No interrupt request Interrupt mask (IM) 1 Mask interrupt request Port mode register (PMR) 000 See Port Mode Register section Serial mode register (SMR)* 0000 See Serial Mode Register section I/Opins, output registers Interrupt flags and mask Mode registers Timer mode register A (TMA)* 0000 See Timer Mode Register A section Timer mode register B (TMB) 0000 See Timer Mode Register B section Comparator mode register (CMR)* 00 See Comparator Mode Register section Comparator Reference voltage select register (RSR)* 0000 See Reference Voltage Select Register section Timer/counters, serial interface Prescaler $000 -- Timer counter A (TCA)* $00 -- Timer counter B (TCB) $00 -- Timer load register B (TLR) $00 -- Octal counter* 000 -- Note: * Only applicable for the HD404222 Series. 15 HD404202 Series/HD404222 Series Table 2 Initial Values After MCU Reset Item Carry flag (CA) Accumulator (A) B register (B) X/SPX registers (X/SPX) Y/SPY registers (Y/SPY) Serial data register (SR)* RAM After MCU Reset to Recover from Stop Mode After MCU Reset to Recover from Other Modes The contents of the items before MCU reset are not retained and must be initialized by software. The contents of the items before MCU reset are not retained and must be initialized by software. The contents of RAM before MCU reset The contents of RAM before MCU (just before the STOP instruction) are reset are not retained and must be retained. initialized by software. Note: * Only applicable for the HD404222 Series. 16 HD404202 Series/HD404222 Series Interrupts Two interrupt sources are available on the MCU of HD404202 Series. They are an external request (INT) and timer/counter (timer B). HD404222 Series has four interrupt sources: the two sources stated above, timer A and serial interface. For each source, an interrupt request flag (IF), interrupt mask (IM), and interrupt vector addresses are provided to control and maintain the interrupt request. An interrupt enable flag (IE) is also used to control interrupt operations. Interrupt Control Bits and Interrupt Operation: The interrupt control bits are mapped on $000 through $002 of the RAM. These bits are accessible by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. At MCU reset initialization, the IE and IF are cleared to 0, and IM is set to 1. Figure 6 is a block diagram of the interrupt control circuit. Table 3 shows the interrupt priority and vector addresses, and table 4 shows the interrupt conditions corresponding to each interrupt source. An interrupt request is generated when the IF is set to 1 and IM is 0. If the IE is 1 during this period, the interrupt will be activated and vector addresses will be generated from the priority PLA corresponding to the interrupt sources. Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the second cycle. Also in the second cycle and third cycle, the carry flag, status flag, and program counter are pushed onto the stack. Included in the third cycle is the generation of the vector address. At each vector address, program the JMPL instruction to branch to the starting address of the interrupt program. The IF which caused the interrupt must be reset by software in the interrupt program. 17 HD404202 Series/HD404222 Series $000,0 Sequence control: Push PC/CA/ST onto stack Reset IE Jump to vector address IE $000,2 INT interrupt IFEX $000,3 Vector address IMEX Priority control PLA $001,0 Timer A interrupt IFTA $001,1 IMTA $001,2 Timer B interrupt IFTB $001,3 IMTB $002,0 Serial interrupt IFS $002,1 IMS Note: indicates only applicable for the HD404222 Series. Figure 6 Interrupt Control Circuit Block Diagram Table 3 Vector Addresses and Interrupt Priority HD404202 Series Reset/Interrupts Priority Vector Addresses RESET -- $000 INT 1 $002 Timer B 2 $006 Reset/Interrupts Priority Vector Addresses RESET -- $000 INT 1 $002 Timer A 2 $004 Timer B 3 $006 Serial 4 $008 HD404222 Series 18 HD404202 Series/HD404222 Series Table 4 Interrupt Conditions HD404202 Series Interrupt Control Bits INT Timer B IE 1 1 IFEX * IMEX 1 0 IFTB * IMTB * 1 Note: * indicates don't care HD404222 Series Interrupt Control Bits INT Timer A Timer B Serial IE 1 1 1 1 IFEX * IMEX 1 0 0 0 IFTA * IMTA * 1 0 0 IFTB * IMTB * * 1 0 IFS * IMS * * * 1 Note: * indicates don't care Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 7 Interrupt Processing Sequence 19 HD404202 Series/HD404222 Series Power on RESET = 0? No Yes Interrupt request? Yes No No IE = 1? Yes Execute instruction Reset MCU Accept interrupt IE 0 PC (PC) + 1 Stack (PC) Stack (CA) Stack (ST) Yes PC $002 INT interrupt? No Yes PC $004 Timer-A interrupt? No Yes PC $006 Timer-B interrupt? No indicates only applicable for the HD404222 Series. (serial interrupt) PC $008 Figure 8 Interrupt Processing Flowchart 20 HD404202 Series/HD404222 Series Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag (table 5) enables or disables interrupt requests. It is reset by an interrupt and set by the RTNI instruction. Table 5 Interrupt Enable Flag IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupt (INT): The external interrupt request input (INT) can be selected by the port mode register (PMR: $004). Setting bit 2 of PMR causes the D5/INT pin to be used as INT . The external interrupt request flag IFEX (table 6) is set at the falling edge of INT input. The INT input can be used as a clock signal input to timer B, which counts up at each falling edge of the INT input. When using INT as the timer B external event input, the external interrupt mask IMEX (table 7) has to be set so that the INT interrupt request will not be accepted. Table 6 External Interrupt Request Flag IFEX Interrupt Request 0 No 1 Yes Table 7 External Interrupt Mask IMEX Interrupt Request 0 Enabled 1 Disabled (masked) External Interrupt Request Flag (IFEX: $000, Bit 2): The external interrupt request flag is set the falling edge of the INT input. External Interrupt Mask (IMEX: $000, Bit 3): The external interrupt mask (table 7) masks the external interrupt request. Timer A Interrupt Request Flag (IFTA: $001, Bit 0): The timer A interrupt request flag (table 8) is set by the timer A overflow output. It can be only used by the HD404222 Series. 21 HD404202 Series/HD404222 Series Table 8 Timer A Interrupt Request Flag IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 1): The timer A interrupt mask (table 9) prevents an interrupt request from being generated by the timer A interrupt request flag. It can be only used by the HD404222 Series. Table 9 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $001, Bit 2): The timer B interrupt request flag (table 10) is set by the overflow output of timer B. Table 10 Timer B Interrupt Request Flag IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $001, Bit 3): The timer B interrupt mask (table 11) prevents an interrupt request from being generated by the timer B interrupt request flag. Table 11 Timer B Interrupt Mask IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $002, Bit 0): The serial interrupt request flag (table 12) will be set when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal counter. It can be only used by the HD404222 Series. 22 HD404202 Series/HD404222 Series Table 12 Serial Interrupt Request Flag IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $002, Bit 1): The serial interrupt mask (table 13) masks the interrupt request. It can be only used by the HD404222 Series. Table 13 Serial Interrupt Mask IMS Interrupt Request 0 Enabled 1 Disabled (masked) Port Mode Register (PMR: $004): The 3-bit write-only port mode register controls the D5/INT, D 7/SI, and D8/SO pins as shown in table 14. The port mode register is initialized to $0 by MCU reset. Therefore these pins are initially used as ports. Note that if unusable bit 3 is set, the MCU may malfunction. Table 14 Port Mode Register PMR: $004 PMR2 PMR1* PMR0* D8 /SO pin mode selection D7 /SI pin mode selection D5 /INT pin mode selection PMR2 D5 /INT Pin 0 Used as D5 port input/output pin 1 Used as INT input pin PMR1* D7 /SI Pin 0 Used as D7 port input/output pin 1 Used as SI input pin PMR0* D8 /SO Pin 0 Used as D8 port input/output pin 1 Used as SO output pin Note: * PMR0 and PMR1 can be only used by the HD404222 Series. 23 HD404202 Series/HD404222 Series Operating Modes The MCU has two low-power dissipation modes, standby mode and stop mode (table 15). Figure 9 shows a mode transition diagram of these modes. Standby Mode: Executing the SBY instruction places the MCU into standby mode. In standby mode, the oscillator circuit, interrupts, timer/ counters, and serial interface remain active. On the other hand, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and I/O pins retain the states they were in just before the MCU went into standby mode. Table 15 Low-Power Dissipation Mode Function Low-Power Dissipation Mode Instruction Standby mode SBY instruction Active Stop mode Table 15 STOP instruction Oscillator Circuit Stop Instruction Execution Registers, Flags Interrupt Function Stop Retained Active Stop 1 Reset* Stop Low-Power Dissipation Mode Function (cont) Low-Power Dissipation Mode RAM Input/ Output Pins Timer/ Counters, Cancellation Serial Interface*3 Comparator*3 Method Standby mode Retained Retained*2 Active Stop mode Retained High impedance Stop Stop RESET input, interrupt request Stop RESET input Notes: *1. The MCU recovers from stop mode by RESET input. Refer to table 1 for the contents of the flags and registers. *2. If an I/O circuit is active, an I/O current may flow, depending on the state of the I/O pin in standby mode. This current is in addition to the current dissipation in standby mode. *3. Serial interface and comparator can be only used by the HD404222 Series. The Standby mode may be cancelled by enabling RESET or by asserting an interrupt request. In the former case, the MCU is reset. In the latter case, the MCU becomes active and executes the next instruction following the SBY instruction. After this instruction is completed and if the interrupt enable flag is 1 when an interrupt request asserted, the interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution continues. Figure 10 shows the flowchart of the standby mode. Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit and all functions of the MCU stop. The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 11, the RESET input must be applied for at least tRC for the oscillation to stabilize. (Refer to the AC Characteristics table.) After stop mode is cancelled, the RAM retains the state it was in just before the MCU went into stop mode, 24 HD404202 Series/HD404222 Series but the accumulator, B register, X/SPX and Y/SPY registers, carry flag, and serial data register will not retain their contents. (The serial data resister can be only used by the HD404222 Series.) Active mode SBY instruction STOP instruction Interrupt request Standby mode RESET = 0 RESET = 1 RESET = 0 Stop mode RESET = 0 Reset state Figure 9 MCU Operation Mode Transition 25 HD404202 Series/HD404222 Series Standby Oscillator: Active Peripheral clocks: Active All other clocks: Stop RESET = 0? Yes No IFEX = 1? No Yes IMEX = 0? IFTA = 1? No Yes IFTB = 1? No Yes IMTA = 0? No Yes No Yes IMTB = 0? IFS = 1? No Yes No Yes IMS = 0? No Yes Restart processor clocks Restart processor clocks Execute next instruction No Reset MCU Execute instruction IE = 1? Yes Accept interrupt indicates only applicable for the HD404222 Series. Figure 10 MCU Operating Flowchart in Standby Mode 26 HD404202 Series/HD404222 Series Stop mode Oscillator Internal clock RESET t res STOP instruction execution t res t RC (stabilization time) Figure 11 Timing of Stop Mode Cancellation 27 HD404202 Series/HD404222 Series Internal Oscillator Circuit Figure 12 shows a block diagram of the internal oscillator circuit. Through mask options, either a ceramic oscillator or resistor can be selected as the oscillator type and connected to OSC1 and OSC2. See figure 13 for the layout of the ceramic oscillator. For other cases, an external clock operation is available. OSC1 OSC2 Oscillator (selectable with mask options) 1/4 divider circuit Timing generator circuit System clock Figure 12 Internal Oscillator Circuit Table 16 Examples of Oscillator Circuits Circuit Configuration External clock operation Ceramic oscillator Circuit Constants Oscillator OSC1 Open OSC2 Ceramic oscillator: CSA4.00MG (MURATA) C1 OSC1 Rf C2 Rf C1=C2: 30pF20% Rf:1M20% OSC2 Ceramic oscillator: CSB1000J (MURATA) C1=C2:220pF20% Rf: 1 M 20% Rf: 20 k 1% Resistor OSC1 Rf OSC2 Notes: The circuit parameters listed above are dependent on the ceramic oscillator and the floating capacitance when designing the board. In employing the resonator, consult with the ceramic oscillator manufacturer to determine the circuit parameters. The wiring between OSC1, OSC2, and the elements should be as short as possible without crossing over other wires. Refer to the layout of the ceramic oscillator in figure 13. 28 /0()!"*# HD404202 Series/HD404222 Series TEST RESET OSC 2 OSC 1 V CC D11 Figure 13 Layout of the Ceramic Oscillator 29 HD404202 Series/HD404222 Series Input/Output The MCU has 22 standard I/O pins. As for the mask ROM version of HD404201, HD40L4201, HD404202, HD40L4202, HD404222 and HD40L4222, one of three circuit types can be selected by the mask option for each standard pin: with pull-up MOS or without pull-up MOS (NMOS open drain) or CMOS. The I/O pins for the HD4074224 are fixed as with pull-up MOS. When every input/output pin is used as an input pin, the mask option and output data must be selected as specified in table 17. Table 17 Data Input from Common Input/Output Pins I/O Pin Circuit Type Standard pins Input Possible Input Pin State CMOS No -- Without pull-up MOS (NMOS open drain) Yes 1 With pull-up MOS Yes 1 Output Circuit Operation of with Pull-Up MOS Standard Pins: In the standard pin option with pull-up MOS, the circuit shown in figure 14 is used to shorten the rise time of output. When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this instruction. This pulse will switch the PMOS (B) on (in figure 14) and shorten the rise time. The write pulse keeps PMOS on for two-eighths of the instruction cycle time. While the write pulse is 0, a high output level is maintained by the pull-up MOS (C). When the HLT signal becomes 0 in stop mode, MOSs (A), (B), and (C) turn off. When the HLT signal is 1, the pins' states are maintained. 30 HD404202 Series/HD404222 Series VCC Pull-up MOS (C) M3 VCC Write pulse (by output instruction) PMOS (B) M2 HLT NMOS (A) M1 Data 1 instruction cycle Output instruction execution Write pulse Figure 14 Output Circuit Operation of Standard Pins with Pull-Up MOS Option D Port: The D port has 14 discrete I/O pins, each of which can be addressed independently. The D port can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD instructions. For the HD404222 Series pins D5 to D11 are multiplexed with pins INT, SCK, SI, SO, Vref , COMP0, and COMP 1, respectively. Setting, resetting, or testing non-existing ports results in invalid data. As for the HD404202 Series only pin D 5/INT applies. R Ports: The R ports are I/O pins that are accessed in 4-bit units. Data is input through the LAR and LBR instructions and output through the LRA and LRB instructions. Writing into non-existing ports will not affect the MCU, however, the values read from the non-existing ports cannot be guaranteed. Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction due to noise. The I/O pins should be fixed as follows to prevent malfunction. * Select the option of without pull-up MOS for unused I/O pins and connect them to GND of the printed circuit board. * For the HD404222 Series sets D5/INT, D6/SCK, D7/SI, D8/SO, D9/Vref , D10/COMP0, and D11/COMP1 as D5 to D11, respectively, by software. As for the HD404202 Series only pin D5/INT applies. 31 HD404202 Series/HD404222 Series Table 18 I/O Pin Circuit Types Standard Pins I/O Pins Circuit Type I/O common pins (D0-D13 , R10-R13, R20-R23) Without pull-up MOS (NMOS open drain) (A) HLT Input data HLT Output data With pull-up MOS (B) HLT Input data VCC VCC Write pulse HLT Output data CMOS (C) HLT Input data VCC HLT Output data I/O common pins (SCK (output mode))* Without pull-up MOS (NMOS open drain) or CMOS (A or C) SCK HLT VCC (HLT + mode select) (internal SCK) With pull-up MOS (B) SCK VCC VCC HLT (HLT + mode select) (internal SCK) 32 HD404202 Series/HD404222 Series Table 18 I/O Pin Circuit Types (cont) Standard Pins I/O Pins Circuit Type Output pins (SO)* Without pull-up MOS (NMOS open drain) or CMOS (A or C) VCC HLT SO With pull-up MOS (B) VCC VCC HLT SO Input pins (INT, SI*, SCK* (input mode)) Without pull-up MOS (NMOS open drain) or CMOS (A or C) Input data HLT With pull-up MOS (B) Input data HLT Input pins (COMP0*, COMP1*) Without pull-up MOS (NMOS open drain) or CMOS (A or C) Reference voltage + CPU input - Analog comparator With pull-up MOS (B) Reference voltage + CPU input - Analog comparator Notes: 1. HD404202 Series: when selecting pin D 5 as INT by software, the pull-up MOS will be disabled even if selecting mask option B (with pull-up MOS). 2. HD404222 and HD40L4222: when selecting pins D5, D6, and D7 as INT, SCK, and SI input, respectively, by software, the pull-up MOS of each terminal will be disabled even if selecting mask option B (with pull-up MOS). HD4074224: pins D5, D6, and D7 are fixed as with pull-up MOS (B). But when selecting these pins as INT, SCK, and SI input, respectively, by software, the pull-up MOS of each terminal will be disabled * Only applicable for the HD404222 Series. 33 HD404202 Series/HD404222 Series Timers The MCU of HD404202 Series contains a prescaler and a timer/counter (timer B), where as one prescaler and two timer/counters (timers A and B) are available on the MCU of HD404222 Series. Figure 15 shows the block diagram of timer/counters. The prescaler is an 11-bit counter, timer A is an 8-bit freerunning/watchdog timer, and timer B is an 8-bit auto-reload timer/event counter. Prescaler: The system clock signal is input to the prescaler. At MCU reset, the prescaler is initialized to $000 and starts dividing the system clock frequency. The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals to timer A, timer B, and the serial interface (Timer A and the serial interface can be only used by the HD404222 Series). The prescaler divide ratio is selected by timer mode register A (TMA), timer mode register B (TMB), and serial mode register (SMR) (TMA and SMR can be only used by the HD404222 Series). Internal bus line (S1) Timer mode register B 4 TMB (4 bit) 4 TL (4 bit) Timer latch register 3 TBOF TCB (8 bit) Timer/event counter B Timer B MPX CPTB / 2048 /2 /4 /8 / 32 / 128 / 512 INT TLR (8 bit) Timer load register 4 System clock IFTB Interrupt request flag of timer B 4 Prescaler (11 bit) /4 /8 / 32 / 128 / 512 / 1024 / 2048 /2 Internal bus line (S2) TAOF CPTA Timer A MPX A TCA (8 bit) Timer/event counter A Mask B option 3 IFTA Interrupt request flag of timer A System reset Timer mode register A TMA (4 bit) indicates (timer A) only applicable for the HD404222 Series. 4 Mask option Type A B Internal bus line (S2) Figure 15 Timer/Counters Block Diagram 34 Function Free-running timer Watchdog timer HD404202 Series/HD404222 Series Timer A Operation (Only Applicable for the HD404222 Series): Timer A's function is selected via the mask option. When timer A is used as a free-running timer, it counts up every input clock signal after timer A has been initialized to $00 by MCU reset. When the next clock signal is input after timer A counts up to $FF, timer A is set to $00 again, and generates an overflow output. This sets the timer A interrupt request flag (IFTA: $001, bit 0) to 1. Therefore, this timer can function as an interval timer periodically generating overflow output at every 256th clock signal. The clock signals input to timer A are selected by timer mode register A (TMA: $008). Note that when timer A is used as a free-running timer, if setting bit 3 of timer mode resister A may cause the MCU to malfunction. When timer A is used as a watchdog timer, the input clock is specified as 1/2048 output divided by the prescaler. The watchdog timer is initialized to $00 at MCU reset, then counts up every input clock signal. If a clock signal is applied after the timer becomes $FF, an overflow is generated and the MCU is reset. After reset, the MCU re-executes the program from the beginning. The program must set bit 3 of timer mode register A to reset timer counter A. Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock source, and the prescaler divide ratio for timer B. When the external event input is used as an input clock signal to timer B, select D5/INT as INT and set the external interrupt mask (IMEX) to prevent an external interrupt request from occurring. Timer B is initialized by software according to the data written in timer load register B. Timer B counts up at every input clock signal. When the next clock signal is input after timer B is set to $FF, timer B will generate an overflow output. Then, if the auto-reload function is selected, timer B is initialized to the value of timer load register B. If it is not selected, timer B goes back to $00. The timer B interrupt request flag (IFTB: $001, bit 2) will hold the overflow output. Timer Mode Register A (TMA: $008): Four-bit write-only timer mode register A selects the timer function for timer A and the prescaler divide ratio of timer A's clock input as shown in table 19. Timer mode register A is initialized to $0 by MCU reset. Table 19 Timer Mode Register A TMA2 TMA1 TMA0 Prescaler Divide Ratio 0 0 0 / 2048 1 / 1024 0 / 512 1 / 128 0 / 32 1 /8 0 /4 1 /2 1 1 0 1 35 HD404202 Series/HD404222 Series Timer Mode Register B (TMB: $009): Four-bit write-only timer mode register B (TMB) selects the autoreload function, the prescaler divide ratio, and the source of the clock input signal as shown in table 20. Timer mode register B is initialized to $0 by MCU reset. The operation mode of timer B changes at the second instruction cycle after timer mode register B is written to. Timer B should be initialized by writing data into timer load register B after the contents of TMB are changed. The configuration and function of timer mode register B is shown in figure 16. Table 20 Timer Mode Register B TMB3 Auto-Reload Function 0 No 1 Yes TMB2 TMB1 TMB0 Prescaler Divide Ratio, Clock Input Source 0 0 0 / 2048 1 / 512 0 / 128 1 / 32 0 /8 1 /4 0 /2 1 INT (external event input) 1 1 0 1 TMA*: $008 TMB: $009 TMA3 TMA2 TMA1 TMA0 TMB3 TMB2 TMB1 TMB0 Timer-B input clock selection Auto-reload function selection Input clock selection for free-running timer TCA initialization for watchdog timer * TMA only applicable for the HD404222 Series. Figure 16 Mode Registers Configuration and Function 36 HD404202 Series/HD404222 Series Timer B Load Register (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit write-only timer load register and an 8-bit read-only timer/event counter. Each has a low-order digit (TCBL: $00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B) (figure 2). The timer/event counter can be initialized by writing data into timer load register B. In this case, write the low-order digit first, and then the high-order digit. The timer/event counter is initialized when the highorder digit is written. The timer load register is initialized to $00 by MCU reset. The counter value of timer B can be obtained by reading timer counter. In this case, read the high-order digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when the high-order digit is read. 37 HD404202 Series/HD404222 Series Serial Interface Only applicable for the HD404222 Series. The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register, serial mode register, octal counter, and multiplexer, as illustrated in figure 17. Pin D6/SCK and the transmit clock signal are controlled by the serial mode register. The contents of the serial data register can be written into or read out by software. The data in the serial data register can be shifted synchronously with the transmit clock signal. The STS instruction initiates serial interface operations and resets the octal counter to 000. The counter starts to count at the falling edge of the transmit clock (SCK) signal and increments by one at the rising edge of the SCK. When the octal counter is reset to 000 after eight transmit clock signals, or when a transmit/receive operation is discontinued by resetting the octal counter, the serial interrupt request flag will be set. OC (3 bits) Octal counter Prescaler (11 bits) SROF IFS Interrupt request flag of serial interface /2 /8 / 32 / 128 / 512 / 2048 System clock /2 Serial MPX Internal bus line (S1) MPX 4 SCK SR (8 bits) Serial data register 3 4 SMR (4 bits) Serial mode register Internal bus line (S2) 4 4 4 Internal bus line (S2) PMR (4 bits) Port mode register 2 SCK D6 /SCK port D 8 /SO port D7 /SI port SCK SI Figure 17 Serial Interface Block Diagram 38 4 SO HD404202 Series/HD404222 Series Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the D6/SCK, prescaler divide ratio, and transmit clock source as shown in table 21. A write signal sent to the serial mode register controls the operating state of the serial interface. The write signal to the serial mode register stops the serial data register and octal counter from using the transmit clock, and it also resets the octal counter to 000 simultaneously. Therefore, when serial interface is in the transfer state, the write signal causes the serial mode register to cease the data transfer and to set the serial interrupt request flag. The contents of the serial mode register will be changed on the second instruction cycle after writing into the serial mode register. Therefore, it is necessary to execute the STS instruction after the data in the serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU reset. Table 21 Serial Mode Register SMR3 D6 /SCK 0 Used as D6 port input/output pin 1 Used as SCK input/output pin SMR: $005 SMR3 SMR2 SMR1 SMR0 Transmit clock selection D6 /SCK pin mode selection Transmit Clock SMR2 SMR1 SMR0 D6 /SCK Port Clock Source Prescaler Divide System Clock Ratio Divide Ratio 0 0 0 SCK output Prescaler / 2048 / 4096 1 SCK output Prescaler / 512 / 1024 0 SCK output Prescaler / 128 / 256 1 SCK output Prescaler / 32 / 64 0 SCK output Prescaler /8 / 16 1 SCK output Prescaler /2 /4 0 SCK output System clock -- /1 1 SCK input External clock -- -- 1 1 0 1 39 HD404202 Series/HD404222 Series Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a loworder digit (SRL: $006) and a high-order digit (SRU: $007). The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the falling edge of the transmit clock signal. At the same time, external data will be input from the SI pin to the serial data register, to LSB first, synchronously with the rising edge of the transmit clock. Figure 18 shows the I/O timing chart for the transmit clock signal and the data. The read/write operations of the serial data register should be performed after the completion of data transmission/reception. Otherwise, the data may not be guaranteed. Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 18 Serial Interface I/O Timing Selecting and Changing the Operation Mode: Table 22 shows the serial interface operation modes which are determined by a combination of the values in the port mode register and in the serial mode register. Initialize the serial interface by the write signal to the serial mode register when the operation mode is changed. Table 22 Serial Interface Operation Mode SMR3 PMR1 PMR0 Serial Interface Operating Mode 1 0 0 Clock continuous output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 40 HD404202 Series/HD404222 Series Operating State of the Serial Interface: The serial interface has three operating states: the STS waiting state, transmit clock wait state, and transfer state, as shown in figure 19. The STS waiting state is the initialization of the serial interface. In this state, the serial interface does not operate even if the transmit clock is applied. If the STS instruction is executed, the serial interface shifts to the transmit clock wait state. In this state the falling edge of the first transmit clock causes the serial interface to shift to the transfer state, in which the octal counter counts up and the serial data register shifts simultaneously. If clock continuous output mode is selected, however, the serial interface stays in the transmit clock wait state while the transmit clock outputs continuously. The octal counter becomes 000 again after 8 transmit clocks or after the execution of the STS instruction, so that the serial interface is returned to the transmit clock wait state and the serial interrupt request flag is set simultaneously. When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the STS instruction, and stops after 8 clocks. STS waiting state octal counter = 000 transmit clock disable Change PMR * Write to SMR Change PMR* Write to SMR STS instruction (IFS 1) Transmit clock Transmit clock wait state (octal counter = 000) 8 transmit clocks, STS instruction Transfer state (octal counter 000) (IFS 1) * Change PMR means the change of operation mode as follows. Clock continuous output mode * Transmit mode * Receive mode * Transmit/receive mode Figure 19 Serial Interface Operation States 41 HD404202 Series/HD404222 Series Transmit Clock Error Detection: The serial interface functions abnormally when the transmit clock is disturbed by external noise. In this case, transmit clock errors can be detected by the procedure shown in figure 20. If more than 8 transmit clocks are applied in the transmit clock wait state, the state of the serial interface shifts in the following sequence: transfer state, transmit clock wait state, and transfer state again. The serial interrupt flag should be reset before entering into the STS state by writing data to SMR. This procedure causes the serial interface request flag to be set again. Transmit/receive (IFS 1) Interrupt disable IFS 0 Write to SMR IFS = 1? Yes Transmit clock error processing No Normal end Figure 20 Transmit Clock Error Detection 42 HD404202 Series/HD404222 Series Comparator Only applicable for the HD404222 Series. The MCU has two-channel comparators that compare input data with the reference voltage. Figure 21 shows the comparator block diagram. The comparator block consists of two analog comparators, the comparator mode register (CMR) which selects the comparator operation, the reference voltage select register (RSR) which selects the reference voltage, a ladder resistance which generates the internal reference voltage, and peripheral circuits. For the COMP0 input, either the external reference voltage or the internal reference voltage, which is generated by dividing VCC with the internal ladder resistance, can be selected as the reference voltage. For the COMP1 input, only the external reference voltage is used; the internal reference voltage cannot be selected. The power consumption increases after the comparator operation is selected by CMR, because direct current is constantly supplied to assure the analog comparator characteristics. To reduce the power consumption during comparator use, the comparator operation should not be selected by software except when analog comparison is required. In this case, a maximum of two instruction cycles are required after the comparator operation is selected in order for the analog comparator to stabilize and operate correctly. Therefore, the comparison result should be read at least two instruction cycles after the comparator operation is selected. The comparison result is obtained by executing the TD or TDD instruction. When the analog input voltage is higher than the reference voltage, a 1 is read as input data from the comparator. The comparator automatically stops operating in standby and stop modes. 43 HD404202 Series/HD404222 Series VCC D 9 /V ref + Analog comparator 0 - D10 /COMP 0 MPX + Analog comparator 1 - D11/COMP 1 MPX 3 RSR CMR 4 2 Internal bus Figure 21 Comparator Block Diagram Comparator Mode Register (CMR: $003): This 2-bit register selects the D10/COMP0 and D11/COMP1 functions. CMR is only affected by the bit manipulation instructions (set by the SEM or SEMD instruction and reset by the REM or REMD instruction). It is initialized to $0 by MCU reset. Therefore, it becomes input/output mode after MCU reset. Reference Voltage Select Register (RSR: $00C): This 4-bit read/write register selects the COMP0 reference voltage for the analog comparator from the eight-level internal voltage or the external voltage. It is initialized to $0 by MCU reset. Notes for Use: When using the analog comparator, carefully program the data output instruction and data input into the port next to COMP0 and COMP1 to assure precise and stabilized comparator operation. 44 HD404202 Series/HD404222 Series CMR: $003 CMR1 CMR0 D10 /COMP0 mode selection D11 /COMP1 mode selection CMR Mode Selection Bit 1 Bit 0 D10/COMP0 D11/COMP1 0 0 D10 D11 1 COMP0 D11 0 D10 COMP1 1 COMP0 COMP1 1 Figure 22 Comparator Mode Register RSR: $00C RSR3 RSR2 RSR1 RSR0 Internal reference voltage selection External/internal reference voltage selection RSR Bit 3 Bit 2 Bit 1 Bit 0 Reference Voltage 0 0 0 0 1/11 VCC 1 2/11 VCC 1 0 3/11 VCC 1 4/11 VCC 0 0 5/11 VCC 1 6/11 VCC 1 0 7/11 VCC 1 8/11 VCC -- -- External Vref (D9/Vref) 1 1 -- -- indicates 0 or 1 Figure 23 Reference Voltage Select Register 45 HD404202 Series/HD404222 Series Pins for PROM Mode VPP (Program Voltage): VPP is the input program voltage (12.5V 0.3V) for programming the PROM. CE (Chip Enable): CE input enables programming and verification of the internal PROM. OE (Output Enable): OE is the data output control signal for verification. A0-A12 (Address Bus): A0-A12 are address input pins for the internal PROM. O0-O4 (PROM Data Bus): O0-O4 are the data bus pins for the internal PROM. 46 HD404202 Series/HD404222 Series PROM Mode Pin Description Pin No. MCU Mode PROM Mode DP-28S, FP-28DA FP-30D Symbol 1 2 GND 2 3 R10 I/O A5 I 3 4 R11 I/O A6 I 4 5 R12 I/O A7 I 5 6 R13 I/O A8 I 6 7 D0 I/O A1 I 7 8 D1 I/O A2 I 8 9 D2 I/O A3 I 9 10 D3 I/O A4 I 10 11 D4 I/O A0 I 11 12 D5/INT I/O O0 I/O 12 13 D6/SCK I/O O1 I/O 13 14 D7/SI I/O O2 I/O 14 15 D8/SO I/O O3 I/O 15 16 D9/Vref I/O O4 I/O 16 17 D10/COMP0 I/O CE I 17 18 D11/COMP1 I/O OE I 18 19 VCC 19 20 OSC1 I 20 21 OSC2 O 21 22 RESET I GND 22 23 TEST I VPP 23 24 D12 I/O VCC 24 25 D13 I/O GND 25 26 R20 I/O A9 I 26 27 R21 I/O A10 I 27 28 R22 I/O A11 I 28 29 R23 I/O A12 I I/O Symbol I/O GND VCC VCC 47 HD404202 Series/HD404222 Series Programmable ROM Operation The HD4074224's on-chip PROM is programmed in PROM mode. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a 28-to-28-pin socket adapter as shown in figure 24. Table 23 lists the recommended PROM programmers and socket adapters. Since an instruction of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputer incorporates a conversion circuit to enable the use of a general purpose PROM programmer. By this circuit, an instruction is read or programmed using 2 addresses, lower 5 bits and upper 5 bits. For example, if 4 kwords of on-chip PROM are programmed by a general purpose PROM programmer, 8 kbytes of addresses ($0000-$1FFF) should be specified. CE, OE Control signals A14 A13 A12-A0 A12-A0 A14-A0 Address bus O7-O0 Data bus O7 O6 O4-O0 O5 O4-O0 VCC GND VPP VCC GND VPP HD4074224 28-to-28-pin socket adapter Figure 24 Socket Adapter for the HD4074224 48 PROM programmer HD404202 Series/HD404222 Series Table 23 PROM Programmer and Socket Adapter PROM Programmer Maker Type Name DATA I/O 29B UNISITE AVAL Corp. PKW-1100 PKW-3100 Socket Adapter Package Type Name Maker DP-28S HS422ESS01H Hitachi FP-28DA HS422ESP01H Hitachi FP-30D HS4224ESF01H Hitachi Programming and Verification The HD4074224 can be high-speed programmed without causing voltage stress or affecting data reliability. Table 24 shows how programming and verification modes are selected. Table 24 PROM Mode Selection Pin Mode CE OE VPP O0-O4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance Precautions 1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer. Note that the plastic package type devices cannot be erased and reprogrammed. 2. Be careful that the wrong PROM programmer or socket adapter may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and that the socket adapter is firmly fixed in the programmer. 3. The PROM should be programmed with VPP = 12.5V. Other PROMs use 21V. If 21V is applied to the HD4074224, the LSI may be permanently damaged. 12.5 V is Intel's 27256 V PP . 49 HD404202 Series/HD404222 Series Addressing Modes RAM Addressing Modes As shown in figure 25, the MCU has three RAM addressing modes: register indirect addressing, direct addressing, and memory register addressing. Register Indirect Addressing: The contents (8 bits) of the X and Y registers are used as the RAM address. Direct Addressing: A direct addressing instruction consists of two words, the first word contains the opcode, the second word (10 bits) is used as the RAM address. Memory Register Addressing: The memory registers (16 digits from $020 to $02F) are accessed by executing the LAMR and XMRA instructions. ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes as shown in figure 26. Direct Addressing Mode: The program can branch to any address in ROM memory by executing the JMPL, BRL, or CALL instruction. These instructions replace the 12 program counter bits (PC11 to PC0) with 12-bit immediate data. Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. The program can branch to an address on the current page by executing the BR instruction. This instruction replaces the lower eight bits of the program counter (PC7 to PC0) with 8-bit immediate data. When the BR instruction falls on a page boundry(256n + 255), executing the Br instruction transfers the PC contents to the next page (figure 27) according to the hardware architecture. Consequently, the program branches to the next page when the BR instruction is used on a page boundary. The HMCS400 series cross macroassembler has an automatic paging facility for ROM pages. Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page subroutine area, which is located at $0000-$003F. When the CAL instruction is executed, 6-bits of immediate data are placed in the low-order six bits of the program counter (PC 5 to PC0) and 0s are placed in the high-order six bits (PC11 to PC6). Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address determined by the contents of the 4-bit immediate data, accumulator, and B register. P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure 28). When bit 8 of the ROM data is 1 (RO8 = 1), 8 bits of ROM data are written into the accumulator and B register. When bit 9 is 1 (RO9 = 1), 8 bits of ROM data are written into the R1 and R2 port output registers. When both bits 8 and 9 are 1 (RO8 = 1, RO9 = 1), ROM data are written into the accumulator, B register, and R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 50 HD404202 Series/HD404222 Series X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 RAM address AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing First word instruction Second word instruction Opcode d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 RAM address AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 d 9 and d8 should be 0. Direct Addressing Instruction Opcode 0 0 m3 m2 m1 1 m0 0 RAM address AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing Figure 25 RAM Addressing Modes 51 HD404202 Series/HD404222 Series [JMPL] [BRL] [CALL] First word instruction Opcode p3 Second word instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Program counter PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 P3 and P2 should be 0. Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0 Program counter PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 Program counter PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 B2 B1 Accumulator B0 A 3 A 2 A1 A0 Program counter PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 26 ROM Addressing Modes 52 HD404202 Series/HD404222 Series BR AAA 256 (n - 1) + 255 256 n AAA NOP BR AAA BR BBB 256 n + 254 256 n + 255 256 (n + 1) BBB NOP Figure 27 BR Instruction Branch Destination on a Page Boundary Instruction [P] Opcode p3 p2 p1 p0 B register B3 B2 B1 Accumulator B0 A3 A2 A1 A0 Referred ROM address RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 B register and accumulator B 3 B 2 B1 B0 A3 A2 A1 A 0 If RO 8 = 1 ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R2 and R1 R23 R2 2 R21 R2 0 R13 R12 R11 R10 If RO 9 = 1 Pattern Figure 28 P Instruction 53 HD404202 Series/HD404222 Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14 V Pin voltage VT -0.3 to VCC + 0.3 V Total permissible input current Io 100 mA 2 Total permissible output current -Io 30 mA 3 Maximum input current Io 30 mA 4, 5 4 mA 4, 6 7 Maximum output current -Io 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes 1 Notes: 1. Applies to HD4074224. 2. The total permissible input current is the total of input currents simultaneously flowing in from all I/O pins to GND. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from any I/O pins to GND. 5. Applies to D12 , D13 , R10 to R13, and R20 to R23. 6. Applies to D0 to D11 . 7. The maximum output current is the maximum current flowing from VCC to any I/O pins. Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. All voltages are with respect to GND. 54 HD404202 Series/HD404222 Series HD404201, HD404202, HD404222 Electrical Characteristics DC Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Pin Min Typ Max Unit Test Condition Input high voltage VIH 0.9VCC -- VCC + 0.3 V SI* 0.9VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, -0.3 -- 0.2VCC V SI* -0.3 -- 0.2VCC V OSC1 -0.3 -- 0.5 V Output high voltage* VOH SCK, SO VCC - 1.0 -- -- V -IOH = 1.0 mA Output low voltage* SCK, SO -- -- 0.4 V IOL = 0.5 mA RESET, -- -- 1 A Vin = 0 V to VCC 1 -- -- 3.5 mA VCC = 5 V, 2, 5 RESET, Notes INT, SCK* Input low voltage VIL INT, SCK* VOL Input/output leakage |IIL| current INT, SCK*, SI*, SO*, OSC1 Current dissipation in ICC active mode ICMP* VCC fOSC = 4 MHz VCC -- -- 5.5 mA VCC = 5 V, 3, 5 fOSC = 4 MHz Comparator active Current dissipation in ISBY standby mode VCC Current dissipation in ISTOP stop mode VCC -- -- 1.7 mA VCC = 5 V, 4, 5 fOSC = 4 MHz -- -- 10 A Vin(RESET) = VCC - 0.3 V to VCC, Vin(TEST) = 0 V to 0.3 V Stop mode retaining VSTOP voltage VCC 2 -- -- V Notes on next page. * Applies to HD404222. 55 HD404202 Series/HD404222 Series Item Symbol Pin Input high voltage* VIHA COMP0, Min Typ Max Unit Test Condition VCref + 0.1 -- -- 0 -- VCref - 0.1 V Vref 0 -- VCC - 1.2 V -- -0.1 -- 0.1 V Notes V COMP1 Input low voltage* VILA COMP0, COMP1 Comparator input reference voltage scope* VCref Deviation of internal VOFS reference voltage* VCC = 4.5 V to 6.0 V 6 Notes: 1. Excluding output buffer current and pull-up MOS current. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET at GND, TEST at GND D0 to D13 , R1, R2 at VCC 3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in operation. Test conditions:MCU: Comparator active Pins: RESET at VCC, TEST at GND D0 to D8, D12 , D13 , R1, R2 at VCC D9 to D11 at GND 4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions:MCU: I/O same as at reset Standby mode Pins: RESET at VCC TEST at GND D0 to D13 , R1, R2 at VCC 5. Power dissipation is in proportion to f OSC while the MCU is operating or is in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 6. The reference voltage is the expected internal VCref voltage selected by the reference voltage select register (RSR). Example: when RSR = $1 reference voltage is 2/11 x VCC. * Applies to HD404222. 56 HD404202 Series/HD404222 Series Input/Output Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C ) Item Symbol Pin Input high voltage VIH D0-D13 , Min Typ Max Unit Test Condition 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V VCC - 1.0 -- -- V -IOH = 1.0 mA -- -- 0.4 V IOL = 0.5 mA -- -- 2 V Note R1, R2 Input low voltage VIL D0-D13 , R1, R2 Output high voltage VOH D0-D13 , 1 R1, R2 Output low voltage VOL D0-D13 , R1, R2 D12, D13 , Input/output leakage current |IIL| Pull-up MOS current -IPU D0-D13 , IOL = 15 mA, VCC = 4.5 V to 6.0 V R1, R2 -- -- 1 A Vin = 0 V to VCC 2 40 80 160 A VCC = 5 V, 3 R1, R2 D0-D13 , R1, R2 Vin = 0 V Notes: 1. For I/O pins selected as CMOS output by mask option. 2. Excluding output buffer current and pull-up MOS current. 3. Applies to I/O pins selected as with pull-up MOS by mask option. 57 HD404202 Series/HD404222 Series AC Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Oscillation frequency fOSC Pin Min Typ Max Unit Test Condition OSC1, 1 4 4.5 MHz Ceramic oscillator 1 -- 3 MHz Resistor oscillator Note OSC2 Rf = 20 k 1% Instruction cycle time tcyc Oscillator stabilization time tRC -- OSC1, 0.89 1 4 s Ceramic oscillator divided by 4 1.33 -- 4 s Resistor oscillator divided by 4 -- -- 20 ms Ceramic oscillator -- -- 0.5 ms Resistor oscillator -- -- 1 pF 1 OSC2 Capacitance between pins CRF OSC1, External clock high and low widths tCPH , tCPL OSC1 92 -- -- ns 2 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT high width tIH INT 2 -- -- tcyc 3 INT low width tIL INT 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 RESET rise time tRSTr RESET -- -- 20 ms 4 Input capacitance Cin All pins -- -- 15 pF OSC2 f = 1 MHz, V in = 0 V, Ta = 25C Comparator stabilization time* tCSTB COMP0 -- -- 2 tcyc Notes: 1. The oscillator stabilization time is the period from when V CC reaches its minimum allowable voltage (3.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At power-on or stop mode recovery, RESET must be kept low for at least tRC. Since tRC depends on the ceramic oscillator's circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer when designing the reset circuit. 2. Refer to figure 29. 3. Refer to figure 30. 4. Refer to figure 31. * Applies to HD404222. 58 HD404202 Series/HD404222 Series Serial Interface Timing Characteristics (HD404222: V CC = 3.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C ) During Transmit Clock Output Item Symbol Transmit clock cycle tScyc time Pin Min Typ Max Unit Test Condition Note SCK 1 -- -- tcyc Load shown in figure 33 1 Transmit clock high and low widths tSCKH, tSCKL SCK 0.4 -- -- tScyc Load shown in figure 33 1 Transmit clock rise and fall times tSCKr, tSCKf SCK -- -- 100 ns Load shown in figure 33 1 Serial output data delay time tDSO SO -- -- 250 ns Load shown in figure 33 1 Serial input data setup time tSSI SI 300 -- -- ns 1 Serial input data hold tHSI time SI 150 -- -- ns 1 Pin Min Typ Max Unit Transmit clock cycle tScy c time SCK 1 -- -- tcyc 1 Transmit clock high and low widths tSCKH, tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise and fall times tSCKr, tSCKf SCK -- -- 100 ns 1 Serial output data delay time tDSO SO -- -- 250 ns Serial input data setup time tSSI SI 300 -- -- ns 1 Serial input data hold tHSI time SI 150 -- -- ns 1 During Transmit Clock Input Item Note: Symbol Test Condition Load shown in figure 33 Note 1 1. Refer to figure 32. 59 HD404202 Series/HD404222 Series HD40L4201, HD40L4202, HD40L4222 Electrical Characteristics DC Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Pin Min Typ Max Unit Test Condition Input high voltage VIH 0.9VCC -- VCC + 0.3 V SI* 0.9VCC -- VCC + 0.3 V OSC1 VCC - 0.3 -- VCC + 0.3 V RESET, -0.3 -- 0.2VCC V SI* -0.3 -- 0.2VCC V OSC1 -0.3 -- 0.3 V Output high voltage* VOH SCK, SO VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage* VOL SCK, SO -- -- 0.4 V IOL = 0.5 mA Input/output leakage |IIL| current RESET, -- -- 1 A Vin = 0 V to VCC 1 -- -- 1 mA VCC = 3 V, 2, 5 RESET, Notes INT, SCK* Input low voltage VIL INT, SCK* INT, SCK*, SI*, SO*, OSC1 Current dissipation in active mode ICC VCC fOSC = 1 MHz ICMP* VCC -- -- 1.6 mA VCC = 3 V, 3, 5 fOSC = 1 MHz Comparator active Current dissipation in standby mode ISBY Current dissipation in stop mode ISTOP VCC -- -- 0.5 mA VCC = 3 V, 4, 5 fOSC = 1 MHz VCC -- -- 10 A Vin(RESET) = VCC - 0.3 V to VCC, Vin(TEST) = 0 V to 0.3 V Stop mode retaining VSTOP voltage VCC 2 -- -- V Input high voltage* COMP0, VCref + 0.1 -- -- V 0 -- VCref - 0.1 V Vref 0 -- VCC - 1.2 V -- -0.1 -- 0.1 V VIHA COMP1 Input low voltage* VILA COMP0, COMP1 Comparator input reference voltage scope* VCref Deviation of internal VOFS reference voltage* 60 VCC = 4.5 V to 5.5 V 6 HD404202 Series/HD404222 Series Notes: 1. Excluding output buffer current and pull-up MOS current. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET at GND, TEST at GND D0 to D13 , R1, R2 at VCC 3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in operation. Test conditions:MCU: Comparator active Pins: RESET at VCC, TEST at GND D0 to D8, D12 , D13 , R1, R2 at VCC D9 to D11 at GND 4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions:MCU: I/O same as at reset Standby mode Pins: RESET at VCC TEST at GND D0 to D13 , R1, R2 at VCC 5. Power dissipation is in proportion to f OSC while the MCU is operating or is in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 1 MHz) 6. The reference voltage is the expected internal VCref voltage selected by the reference voltage select register (RSR). Example: when RSR = $1 reference voltage is 2/11 x VCC. * Applies to HD40L4222. 61 HD404202 Series/HD404222 Series Input/Output Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C ) Item Symbol Input high voltage VIH Pin Min Typ Max Unit Test Condition Note D0-D13 , 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V VCC - 0.5 -- -- V -IOH = 0.5 mA 1 -- -- 0.4 V IOL = 0.4 mA -- -- 2 V IOL = 15 mA, R1, R2 Input low voltage VIL D0-D13 , R1, R2 Output high voltage VOH D0-D13 , R1, R2 Output low voltage VOL D0-D13 , R1, R2 D12, D13 , VCC = 4.5 V to 6.0 V R1, R2 Input/output leakage |IIL| current D0-D13 , R1, R2 Pull-up MOS current -IPU D0-D13 , -- -- 1 A Vin = 0 V to VCC 2 10 25 60 A VCC = 3 V, 3 R1, R2 Notes: 1. For I/O pins selected as CMOS output by mask option. 2. Excluding output buffer current and pull-up MOS current. 3. Applies to I/O pins selected as with pull-up MOS by mask option. 62 Vin = 0 V HD404202 Series/HD404222 Series AC Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Pin Min Typ Max Unit Test Condition Note Oscillation frequency fOSC OSC1, 0.4 1 1.125 MHz Ceramic oscillator -- 3.55 4 10 s Ceramic oscillator divided by 4 Oscillator stabilization tRC time OSC1, -- -- 20 ms Ceramic oscillator External clock high and low widths tCPH , tCPL OSC1 425 -- -- ns 2 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT high width tIH INT 2 -- -- tcyc 3 INT low width tIL INT 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 RESET rise time tRSTr RESET -- -- 20 ms 4 Input capacitance Cin All pins -- -- 15 pF OSC2 Instructioncycle time tcyc 1 OSC2 f = 1 MHz, Vin = 0 V, Ta = 25C Comparator stabilization time* tCSTB COMP0 -- -- 2 tcyc Notes: 1. The oscillator stabilization time is the period from when V CC reaches its minimum allowable voltage (2.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At power-on or stop mode recovery, RESET must be kept low for at least tRC. Since tRC depends on the ceramic oscillator's circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer when designing the reset circuit. 2. Refer to figure 29. 3. Refer to figure 30. 4. Refer to figure 31. * Applies to HD40L4222. 63 HD404202 Series/HD404222 Series Serial Interface Timing Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = -20C to +75C ) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 33 1 Transmit clock high and low widths tSCKH, tSCKL SCK 0.4 -- -- tScyc Load shown in figure 33 1 Transmit clock rise and fall times tSCKr , tSCKf SCK -- -- 300 ns Load shown in figure 33 1 Serial output data delay time tDSO SO -- -- 600 ns Load shown in figure 33 1 Serial input data setup tSSI time SI 1000 -- -- ns 1 Serial input data hold time SI 500 -- -- ns 1 tHSI Note During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high and low widths tSCKH, tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise and fall times tSCKr, tSCKf SCK -- -- 300 ns 1 Serial output data delay time tDSO SO -- -- 600 ns Load shown in figure 33 1 Serial input data setup tSSI time SI 1000 -- -- ns 1 Serial input data hold time SI 500 -- -- ns 1 Note: 64 tHSI 1. Refer to figure 32. Test Condition Note HD404202 Series/HD404222 Series HD4074224 Electrical Characteristics DC Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Pin Min Typ Max Unit Test Condition Input high voltage VIH RESET, 0.9VCC -- VCC + 0.3 V SI 0.7VCC -- VCC + 0.3 V OSC1 VCC - 0.3 -- VCC + 0.3 V 2.7 V VCC < 3.5 V VCC - 0.5 -- VCC + 0.3 V 3.5 V VCC 5.5 V -0.3 -- 0.2VCC V SI -0.3 -- 0.3VCC V OSC1 -0.3 -- 0.3 V 2.7 V VCC < 3.5 V -0.3 -- 0.5 V 3.5 V VCC 5.5 V -- V 2.7 V VCC < 3.5 V Notes SCK, INT Input low voltage VIL RESET, SCK, INT Output high voltage VOH SCK, SO VCC - 0.5 -- - IOH = 0.5 mA VCC - 1.0 -- -- V 3.5 V VCC 5.5 V - IOH = 1.0 mA Output low voltage VOL SCK, SO -- -- 0.4 V IOL = 0.5 mA Input/output leakage current RESET, -- -- 1 A Vin = 0 V to VCC -- -- 4.2 mA VCC = 5 V, f OSC = 4 MHz 2, 5 -- -- 1 mA VCC = 3 V, fOSC = 1 MHz 2, 5 -- -- 6.5 mA VCC = 5 V, |IIL| 1 SCK, INT, SI, SO, OSC1 Current dissipation ICC in active mode ICMP VCC VCC 3, 5 fOSC = 4 MHz, comparator active -- -- 1.6 mA VCC = 3 V, fOSC = 1 MHz 3, 5 comparator active Current dissipation ISBY in standby mode Current dissipation ISTOP in stop mode VCC VCC -- -- 2 mA VCC = 5 V, fOSC = 4 MHz 4, 5 -- -- 0.5 mA VCC = 3 V, fOSC = 1 MHz 4, 5 -- -- 10 A Vin(RESET) = VCC - 0.3 V to VCC Vin(TEST) = 0 V to 0.3 V Stop mode retaining voltage VSTOP VCC 2 -- -- V Notes on next page. 65 HD404202 Series/HD404222 Series Item Symbol Pin Input high voltage VIHA COMP0, Min Typ Max Unit VCref + 0.1 -- -- V 0 -- VCref - 0.1 V Test Condition Notes VCC = 4.5 V to 5.5 V 6 COMP1 Input low voltage VILA COMP0, COMP1 Comparator input reference voltage scope VCref Vref 0 -- VCC - 1.2 V Deviation of internal reference voltage VOFS -- -0.1 -- 0.1 V Notes: 1. Excluding output buffer current and pull-up MOS current. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET at GND, TEST at GND D0 to D13 , R1, R2 at VCC 3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in operation. Test conditions:MCU: Comparator active Pins: RESET at VCC, TEST at GND D0 to D8, D12 , D13 , R1, R2 at VCC D9 to D11 at GND 4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions:MCU: I/O same as at reset Standby mode Pins: RESET at VCC, TEST at GND D0 to D13 , R1, R2 at VCC 5. Power dissipation is in proportion to f OSC while the MCU is operating or is in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 6. The reference voltage is the expected internal VCref voltage selected by the reference voltage select register (RSR). Example: When RSR = $1, the reference voltage is 2/11 x VCC. 66 HD404202 Series/HD404222 Series Input/Output Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Input high voltage VIH Pin Min Typ Max Unit Test Condition D0-D13 , 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V -- -- 0.4 V IOL = 0.5 mA -- -- 2 V IOL = 15 mA, Note R1, R2 Input low voltage VIL D0-D13 , R1, R2 Output low voltage VOL D0-D13 , R1, R2 D12, D13 , VCC = 4.5 V to 5.5 V R1, R2 Input/output leakage current |IIL| Pull-up MOS current -IPU D0-D13 , -- -- 1 A Vin = 0 V to VCC 40 80 160 A VCC = 5 V, 1 R1, R2 D0-D13 , Vin = 0 V R1, R2 10 25 60 A VCC = 3 V, Vin = 0 V Note: 1. Excluding output buffer current and pull-up MOS current. 67 HD404202 Series/HD404222 Series AC Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C) Item Symbol Pin Oscillation frequency (ceramic oscillator) fOSC Instruction cycle time (ceramic oscillator) OSC1, Min Typ Max Unit Test Condition 1 4 4.5 MHz VCC = 3.5 V to 5.5 V 0.4 1 1.125 MHz VCC = 2.7 V to 3.5 V 0.89 1 4 Note OSC2 tcyc -- s VCC = 3.5 V to 5.5 V divided by 4 3.55 4 10 s VCC = 2.7 V to 3.5 V divided by 4 Oscillator stabilization tRC time(ceramic oscillator) OSC1, Oscillation frequency (resistor oscillator) fOSC OSC1, Instruction cycle time (resistor oscillator) tcyc -- -- 20 ms 1 -- 3 MHz 1 OSC2 -- VCC = 3.5 V to 5.5 V Rf = 20 k 1% OSC2 1.33 -- 4 s VCC = 3.5 V to 5.5 V divided by 4 Oscillator stabilization tRC time(resistor oscillator) OSC1, Capacitance between pins OSC1, CRF -- -- 0.5 ms VCC = 3.5 V to 5.5 V -- -- 1 pF VCC = 3.5 V to 5.5 V 92 -- -- ns VCC = 3.5 V to 5.5 V 2 425 -- -- ns VCC = 2.7 V to 3.5 V 2 OSC2 OSC2 External clockhigh and tCPH , tCPL low widths OSC1 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT high width tIH INT 2 -- -- tcyc 3 INT low width tIL INT 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 RESET rise time tRSTr RESET -- -- 20 ms 4 Input capacitance Cin TEST -- -- 180 pF Others -- -- 15 pF COMP0 -- -- 2 tcyc Comparator tCSTB f = 1 MHz, V in = 0 V, Ta = 25C stabilization time Notes: 1. The oscillator stabilization time is the period from when V CC reaches its minimum allowable voltage (3.5 V) at power-on to when the oscillator stabilizes, or after RESET goes low. At poweron or stop mode release, RESET must be kept low for at least tRC. Since tRC depends on the ceramic oscillator's circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer when designing the reset circuit. 2. Refer to figure 29. 3. Refer to figure 30. 4. Refer to figure 31. 68 HD404202 Series/HD404222 Series Serial Interface Timing Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = -20C to +75C) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 33 1 0.4 -- -- tScyc Load shown in figure 33 1 -- -- 100 ns VCC = 3.5 V to 5.5 V, 1 Transmit clock high and low tSCKH, tSCKL SCK widths Transmit clock rise and fall tSCKr, tSCKf times SCK load shown in figure 33 -- -- 300 ns VCC = 2.7 V to 3.5 V, 1 load shown in figure 33 Serial output data delay time tDSO SO -- -- 250 ns VCC = 3.5 V to 5.5 V, 1 load shown in figure 33 -- -- 600 ns VCC = 2.7 V to 3.5 V, 1 load shown in figure 33 Serial input data setup time tSSI Serial input data hold time SI tHSI 300 SI -- -- ns VCC = 3.5 V to 5.5 V 1 1000 -- -- ns VCC = 2.7 V to 3.5 V 1 150 -- -- ns VCC = 3.5 V to 5.5 V 1 500 -- -- ns VCC = 2.7 V to 3.5 V 1 Typ Max Unit Test Condition During Transmit Clock Input Item Symbol Pin Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high and low widths tSCKH, tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise and fall times tSCKr, tSCKf SCK -- -- 100 ns VCC = 3.5 V to 5.5 V 1 -- -- 300 ns VCC = 2.7 V to 3.5 V 1 -- -- 250 ns VCC = 3.5 V to 5.5 V, 1 Serial output data delay time tDSO SO Min Note load shown in figure 33 -- -- 600 ns VCC = 2.7 V to 3.5 V, 1 load shown in figure 33 Serial input data setup time Serial input data hold time Note: tSSI tHSI SI SI 300 -- -- ns VCC = 3.5 V to 5.5 V 1 1000 -- -- ns VCC = 2.7 V to 3.5 V 1 150 -- -- ns VCC = 3.5 V to 5.5 V 1 500 -- -- ns VCC = 2.7 V to 3.5 V 1 1. Refer to figure 32. 69 HD404202 Series/HD404222 Series HD404201, HD404202, HD404222, HD4074224 (3.5 V VCC 5.5 V) 1/fCP OSC1 VCC - 0.5 V 0.5 V t CPr t CPL t CPH t CPf HD40L4201, HD40L4202, HD40L4222, HD4074224 (2.7 V VCC 3.5 V) 1/fCP OSC1 VCC - 0.3 V 0.3 V t CPr t CPL t CPH t CPf Figure 29 External Clock Timing INT 0.9VCC t IH t IL 0.2VCC Figure 30 Interrupt Timing t RSTL 0.9V CC RESET 0.2V CC t RSTr Figure 31 RESET Timing t Scyc SCK SO VCC - 0.5 V (0.9VCC ) * 0.4 V (0.2VCC ) * t SCKf t SCKL t SCKH t SCKr t DSO V CC - 0.5 V 0.4 V t SSI SI t HSI 0.7VCC 0.3VCC Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output. 0.9VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 32 Serial Interface Timing 70 HD404202 Series/HD404222 Series V CC D Test point RL D C R1 D D D: RL: R1 : C: 1S2074 H 2.6 k 12 k 30 pF Figure 33 Timing Load Circuit 71 HD404202 Series/HD404222 Series Electrical Characteristics (Reference data) 4 Oscillation frequency (MHz) 4.0 Oscillation frequency (MHz) VCC = 5.0 V Ta = -20 to 75 Rf = 20 k Ta = -20 to 75 3.0 max. 2.0 min. 3 2 max. 1 1.0 min. 0 0.0 3.0 5.0 4.0 6.0 7.0 0 10 20 30 R f (k ) VCC (V) Resistor oscillator characteristics (1) Oscillator frequency v.s. VCC (Rf = 20 k) Resistor oscillator characteristics (2) Oscillator frequency v.s. Rf (VCC = 5.0 V) 4 4 VCC = 6.0 V Ta = -20 to 75 3 Oscillation frequency (MHz) Oscillation frequency (MHz) VCC = 3.5 V Ta = -20 to 75 2 max. 1 3 2 max. 1 min. min. 0 0 0 10 20 30 40 R f (k ) Resistor oscillator characteristics (3) Oscillator frequency v.s. Rf (VCC = 3.5 V) 72 50 40 50 0 10 20 30 40 R f (k ) Resistor oscillator characteristics (4) Oscillator frequency v.s. Rf (VCC = 6.0 V) 50 HD404202 Series/HD404222 Series Notes On ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 2-kword versions (HD404202, HD40L4202). A 2-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 2-kword version. This limitation apply to the case of using EPROM and the case of using data base. ROM 2 kwords version: HD404201, HD40L4201 Address $0800 to $0FFF $0000 Vector address $0009 $000A Zero-page subroutine (64 words) $003F $0040 Pattern and program (2048 words) $03FF $0400 Not used $07FF Fill this area with all 1s 73 HD404202 Series/HD404222 Series HD404201/HD40L4201/HD404202/HD40L4202 Option List Please check off the appropriate applications and enter the necessary information. Order date Customer name Department Name ROM code name 1. ROM Size 5-V operation: HD404201 1-kword LSI type name Low-voltage operation: HD40L4201 2-kword 5-V operation: HD404202 Low-voltage operation: HD40L4202 2. I/O Options A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input) Pin name I/O D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option B A C Pin name I/O D11 D12 D13 R10 R11 R1 R12 R13 R20 R21 R2 R22 R23 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A I/O option B C 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4. System Oscillator (OSC1 and OSC2) HD404201/HD404202 HD40L4201/HD40L4202 External clock f= MHz Resistor f= MHz Ceramic oscillator f= MHz 5. Stop Mode f= MHz Ceramic oscillator f= MHz 6. Package Used DP-28S Not used FP-28DA FP-30D 74 External clock HD404202 Series/HD404222 Series HD404222/HD40L4222 Option List Please check off the appropriate applications and enter the necessary information. Order date Customer name Department Name ROM code name 1. ROM Size LSI type name 5-V operation: HD404222 Low-voltage operation: HD40L4222 2. I/O Options A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input) Pin name I/O D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option B A C Pin name I/O D11 D12 D13 R10 R11 R1 R12 R13 R20 R21 R2 R22 R23 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A I/O option B C 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4. System Oscillator (OSC1 and OSC2) HD404222 HD40L4222 External clock f= MHz Resistor f= MHz Ceramic oscillator f= MHz 5. Timer A External clock f= MHz Ceramic oscillator f= MHz 6. Stop Mode 7. Package Free-running timer operation Used DP-28S Watchdog timer operation Not used FP-28DA FP-30D 75 H43xx Family HD404304 Series Rev. 5.0 March 1997 Description The HD404304 Series is a CMOS 4-bit single-chip microcomputer basically equivalent to the HMCS400 series, providing high programming productivity, high speed operation, and low power dissipation. It incorporates ROM, RAM, I/O, A/D converter, two timer/counters, including high voltage I/O pins to drive fluorescent display tubes directly. The HD404304 Series includes three chips: the HD404302R with 2 k-word ROM, the HD404304 with 4 kword ROM and the HD4074308 with 8 k-word PROM. The HD4074308, which includes PROM, is ZTAT microcomputer that can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd. Features * 2048-word x 10-bit ROM (mask ROM version, HD404302R) 4096-word x 10-bit ROM (HD404304) 8192-word x 10-bit PROM (ZTAT version) * 160-digit x 4-bit RAM * 33 I/O pins, including 25 high-voltage I/O pins (40 V max.) * Two timer/counters 11-bit prescaler 8-bit timer (free-running timer/watchdog timer) 8-bit timer (auto-reload timer/event counter) * Five interrupt sources Two by external sources Two by timer/counters One by A/D converter * 4-channel x 8-bit A/D converter * Two tone generator outputs * Subroutine stack, up to 16 levels including interrupts HD404304 Series * Two low-power dissipation modes Standby mode Stop mode * On-chip oscillator Crystal or ceramic oscillator External clock * Package 42-pin plastic DIP (DP-42) 42-pin ceramic DIP with window (DC-42)* 42-pin plastic shrink DIP (DP-42S) 54-pin flat plastic package (FP-54) * Instruction cycle time: 2 s (fOSC = 4 MHz) Note: * Available as a sample Ordering Information Type Product Name Model Name ROM (Words) Package Mask ROM HD404302R HD404302RP 2,048 DP-42 HD404304 ZTAT HD4074308 Note: * Available as a sample 2 HD404302RS DP-42S HD404302RF FP-54 HD404304P 4,096 DP-42 HD404304S DP-42S HD404304F FP-54 HD4074308P 8,192 DP-42 HD4074308S DP-42S HD4074308C* DC-42* HD4074308F FP-54 HD404304 Series Pin Arrangement D10 TG0/D11 TG1/D12 Vdisp/RA1 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 INT0/R32 INT1/R33 GND 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 11 12 DP-42 DP-42S DC-42 33 32 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCC OSC2 OSC1 TEST RESET AVSS R43/AN3 R42/AN2 R41/AN1 R40/AN0 AVCC R00 Vdisp/RA1 TG1/D12 TG0/D11 D10 D9 D8 D7 D6 D5 5 4 3 2 1 54 53 52 51 50 Top view NC 6 49 NC NC 7 48 NC NC 8 47 NC R01 9 46 D4 R02 10 45 D3 R03 11 44 D2 R10 12 43 D1 R11 13 42 D0 R12 14 41 VCC R13 15 40 OSC2 R20 16 39 OSC1 R21 17 38 TEST R22 18 37 RESET R23 19 36 AVSS NC 20 35 NC NC 21 34 NC NC 22 33 NC 29 30 31 32 R40/AN0 R41/AN1 R42/AN2 R43/AN3 R33/INT1 28 26 R32/INT0 AVCC 25 27 24 R31 GND 23 R30 FP-54 Top view 3 HD404304 Series Pin Description Pin Number DP-42, DP-42S,DC-42 FP-54 Pin Name I/O 1 1 D10 I/O 2 2 D11/TG0 I/O 3 3 D12/TG1 I 4 4 RA1/Vdisp I 5 5 R00 I/O 6 9 R01 I/O 7 10 R02 I/O 8 11 R03 I/O 9 12 R10 I/O 10 13 R11 I/O 11 14 R12 I/O 12 15 R13 I/O 13 16 R20 I/O 14 17 R21 I/O 15 18 R22 I/O 16 19 R23 I/O 17 23 R30 I/O 18 24 R31 I/O 19 25 R32/INT0 I/O 20 26 R33/INT1 I/O 21 27 GND 22 28 AVCC 23 29 R40/AN0 I/O 24 30 R41/AN1 I/O 25 31 R42/AN2 I/O 26 32 R43/AN3 I/O 27 36 AVSS 28 37 RESET I 29 38 TEST I 30 39 OSC1 I 31 40 OSC2 O 32 41 VCC 33 42 D0 4 I/O HD404304 Series Pin Number DP-42, DP-42S, DC-42 FP-54 Pin Name I/O 34 43 D1 I/O 35 44 D2 I/O 36 45 D3 I/O 37 46 D4 I/O 38 50 D5 I/O 39 51 D6 I/O 40 52 D7 I/O 41 53 D8 I/O 42 54 D9 I/O -- 6 NC -- 7 NC -- 8 NC -- 20 NC -- 21 NC -- 22 NC -- 33 NC -- 34 NC -- 35 NC -- 47 NC -- 48 NC -- 49 NC NC: No connection 5 HD404304 Series Pin Functions Power Supply VCC: Apply power supply voltage to this pin. GND: Connect to ground. Vdisp: This pin, multiplexed with RA1, is for the power supply of the high-voltage output pins with a maximum voltage of VCC - 40 V. For details, see the Input/Output section. AVCC, AVSS: Power supply pins for the A/D converter. TEST: Non-user pin. Connect this pin to VCC. RESET: MCU reset pin. For details, see the Reset section. Oscillators OSC 1, OSC 2: Input/output pins for the internal oscillator circuit. They can be connected to a crystal, ceramic, or external oscillator circuit. For details, see the Internal Oscillator Circuit section. Ports D0 to D 12 (D Port): Input/output port addressed by its bits. These 13 pins are all high-voltage input/output pins. The circuit type for each pin can be selected using a mask option. For details, see the Input/Output section. R00 to R0 3, R10 to R13, R20 to R23, R30 to R3 3, R40 to R43, RA1 (R Ports): R0 to R4 are 4-bit I/O ports. RA is a 1-bit input-only port. The pins of R0 to R2 and RA1 are high-voltage pins, and the pins of R3 to R4 are standard pins. R32 and R33 are multiplexed with INT0 and INT1, respectively. For details, see the Input/Output section. Interrupts INT0, INT1: External interrupt pins. INT1 can be used as an external event input pin for timer B. INT0 and INT 1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section. Tone Generator TG 0, TG1: Tone generator output pins. These pins are high-voltage pins multiplexed with D11 and D 12, respectively. 6 R30 R31 indicates high voltage pins. R3 A B PC D port CA R0 ST R1 SPY SPX ALU R00 R01 R02 R03 R10 R11 R12 R13 R2 Y X Instruction decoder 2048 x 10-bit (HD404302R) 4096 x 10-bit (HD404304) 8192 x 10-bit (HD4074308) ROM D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11/TG0 D12/TG1 R20 R21 R22 R23 RA W SP GND INT0/R32 INT1/R33 AVSS AVCC 160 x 4-bit RAM (ZTATTM and mask ROM versions) OSC2 AN0/R40 D11/TG0 D12/TG1 R4 VCC AN1/R41 R33/INT1 AN2/R42 R32/INT0 Interrupt control RESET AN3/R43 TEST System control OSC1 Pulse Timer Timer A/ External A/D genB watchdog interrupt erator HD404304 Series A/D Converter AN 0 to AN3 (AN Port): A/D converter input port. AN0 to AN3 are multiplexed with R40 to R43 , respectively. For details, see the A/D Converter section. Block Diagram RA1/Vdisp 7 HD404304 Series Memory Map ROM Memory Map The ROM is described in the following paragraphs with the ROM memory map in figure 1. Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL instructions to branch to the starting address of the initialization program and the interrupt programs. After a reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for subroutines. The CAL instruction branches to these subroutines. Pattern Area ($0000 to $07FF: HD404302R; $0000 to $0FFF: HD404304, HD4074308): Locations $0000 through $07FF or $0FFF are reserved for ROM data. The P instruction allows reference to ROM data as a pattern. Program Area ($0000 to $07FF: HD404302R; $0000 to $0FFF: HD404304; $0000 to $1FFF: HD4074308): Locations from $0000 to $1FFF can be used for program code. 0 $0000 Vector address 15 16 Zero-page subroutine (64 words) $000F $0010 $003F $0040 63 64 Program pattern (2048 words) 2047 2048 For HD404302R $07FF $0800 Program pattern (4096 words) 4095 4096 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (jump to reset routine) JMPL instruction (jump to INT0 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to A/D routine) For HD404304 $0FFF $1000 Program (8192 words) 8191 8192 For HD4074308 $1FFF $2000 Not used 16383 $3FFF Figure 1 ROM Memory Map 8 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F HD404304 Series RAM Memory Map The MCU contains a 160-digit x 4-bit RAM as the data and stack area. In addition to these areas, interrupt control bits and special function registers are also mapped on the RAM memory space. The RAM memory map (figure 2) is described in the following paragraphs. 0 $000 RAM-mapped registers Memory registers (MR) (16 digits) $03F $040 $04F $050 Data (80 digits) $09F $0A0 Not used $3BF $3C0 Stack (64 digits) 1023 $3FF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Interrupt control bits area Port mode register A (PMRA) Port mode register B (PMRB) Not used Not used Timer mode register A (TMA) Timer mode register B (TMB) (TCBL/TLRL) * Timer B (TCBU/TLRU) A/D mode register (AMR) A/D data register lower (ADRL) A/D data register upper (ADRU) A/D port select register (ADPR) W W W W R/W R/W W R R W $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 Not used $01F $020 $021 $022 $023 $024 31 32 Special flag bits area 35 36 Not used 50 51 Port R3 DCR 52 Port R4 DCR 53 Notes: * Two registers are mapped on the same address. TCBL: Timer counter B lower TCBU: Timer counter B upper TLRL: Timer load register B lower TLRU: Timer load registr B upper W: Write only R: Read only R/W: Read/Write (DCR3) (DCR4) W W $032 $033 $034 $035 Not used 63 $03F Figure 2 RAM Memory Map 9 HD404304 Series Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag cannot be set by software. The RSP bit is used only to reset the stack pointer. Bit 3 Bit 2 Bit 1 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMAD (IM of A/D) IFAD (IF of A/D) IMTB (IM of timer B) IFTB (IF of timer B) $002 3 Not used Not used Not used Not used $003 IF: IM: IE: SP: Bit 0 IE $000 (Interrupt enable flag) Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Note: Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, reset by the REM/REMD instruction, and tested by the TM/TMD instruction. Other instructions have no effect. Furthermore, the interrupt request flag is not affected by the SEM/SEMD instruction. The contents of the status flag become invalid when unusable bits and the RSP bit are tested by the TM or TMD instruction. 32 Bit 3 Bit 2 Bit 1 Bit 0 Not used Not used WDON (Watchdog on flag) ADSF (A/D start flag) $020 $021 Reserved $022 $023 Note: The WDON flag can be used by the SEM/SEMD instruction, and reset by MCU reset. ADSF stays high during A/D conversion and becomes low after A/D conversion. Figure 3 Configuration of Interrupt Control Bits Area 10 HD404304 Series Special Function Registers Area ($004 to $034): The special function registers are the mode or data registers for external interrupt, A/D conversion, and the timer/counters, and are the I/O port data control registers. These registers are classified into three types: write-only, read-only, and read/write as shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions. However, WDON ($020) can be accessed only by those bit instructions. Data Area ($040 to $09F): The 16 digits of $040 through $04F are called memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). Memory registers Stack area 64 MR (0) $040 960 Level 16 $3C0 65 MR (1) $041 Level 15 66 MR (2) $042 Level 14 67 MR (3) $043 Level 13 68 MR (4) $044 Level 12 69 MR (5) $045 Level 11 70 MR (6) $046 Level 10 71 MR (7) $047 Level 9 72 MR (8) $048 Level 8 73 MR (9) $049 Level 7 74 MR (10) $04A Level 6 75 MR (11) $04B Level 5 76 MR (12) $04C Level 4 77 MR (13) $04D Level 3 78 MR (14) $04E Level 2 79 MR (15) $04F 1023 Level 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC12 PC11 $3FC 1021 PC10 PC9 PC8 PC7 $3FD 1022 CA PC6 PC5 PC4 $3FE 1023 PC3 PC2 PC1 PC0 $3FF PC13 to PC0: Program counter ST: Status flag CA: Carry flag Notes: 1. Since the HD404302R has a 2-kword ROM, PC11, PC12, and PC13 are not used. 2. Since the HD404304 has a 4-kword ROM, PC12 and PC13 are not used. 3. Since the HD4074308 has a 8-kword ROM, PC13 is not used. Figure 4 Configuration of Memory Registers, Stack Area, amd Stack Position Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for the stack area to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL and CALL instructions) and interrupts are processed. This area can be used as a 16-level nesting stack in which one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is available as a data area. 11 HD404304 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. The following paragraphs describe the registers and flags shown in figure 5 in detail. 3 0 A Accumulator 3 0 B B register 1 0 W 3 W register 0 X 3 X register 0 Y 3 Y register 0 SPX 3 SPX register 0 SPY 13 SPY register CA Carry flag ST Status flag 0 PC Program counter 9 1 5 1 1 1 0 SP Stack pointer Figure 5 Registers and Flags Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the arithmetic logic unit (ALU) as well as the transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): The 2-bit W register and the 4-bit X and Y registers indirectly address the RAM. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): The 4-bit SPX and SPY registers are used to assist the X and Y registers, respectively. 12 HD404304 Series Carry Flag (CA): The carry flag (CA) indicates an overflow generated from the ALU during arithmetic operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt, and popped off the stack by the RTNI instruction. This flag is not affected by the RTN instruction. Status Flag (ST): The status flag (ST) indicates an ALU overflow and ALU non-zero during arithmetic or compare instructions, and the result of a bit test instruction. Moreover, the status flag controls branching caused by the BR, BRL, CAL, or CALL instruction. Whether these instructions are executed or skipped, the status flag is always set to 1. The state of this flag remains unchanged until the next arithmetic, compare, bit test, or branch instruction is executed. During an interrupt, ST is pushed onto the stack, and popped off the stack by the RTNI instruction. This flag is not affected by the RTN instruction. Program Counter (PC): The program counter is a 14-bit binary counter which holds the address of the next program instruction to be executed. Stack Pointer (SP): The stack pointer (SP) is a 10-bit register which indicates the next stack address. This pointer, which is initialized to $3FF, is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped off the stack. The highest four bits are fixed to 1111, which allows the pointer to indicate up to 16 levels of subroutines. The stack pointer is initialized when the MCU is reset or the RSP bit ($000, bit 1) is reset by the REM or REMD instruction. Interrupts Five interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timer A, timer B), and A/D. For each source, the interrupt request flag (IF), interrupt mask (IM), and interrupt vector addresses are provided to control and maintain the interrupt request. The interrupt enable flag (IE) is also used to control interrupt operations. Interrupt Control Bits and Interrupt Service: The interrupt control bits are mapped on $000 through $003 of the RAM space. They are accessible by RAM bit manipulation instructions. However, the interrupt request flag (IF) cannot be set by software. The interrupt enable flag (IE) and IF are cleared to 0, and the interrupt mask (IM) is set to 1 after MCU reset. Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source. The interrupt request is generated when the IF is set to 1 and IM is 0. If the IE is 1 at this time, the interrupt will be activated and vector addresses will be generated from the priority PLA corresponding to the interrupt sources. Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed onto the stack. In the third cycle, the instruction is re-executed, after jumping to the vector address. At each vector address, program the JMPL instruction to branch to the starting address of the interrupt program. The IF which caused the interrupt must be reset by software in the interrupt program. 13 HD404304 Series Table 1 Vector Addresses and Interrupt Priority Reset/Interrupt Priority Vector Addresses RESET -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 A/D 5 $000A Table 2 Interrupt Conditions Interrupt Control Bit INT0 INT1 Timer A Timer B A/D IE 1 1 1 1 1 IF0 IM0 1 0 0 0 0 IF1 IM1 * 1 0 0 0 IFTA IMTA * * 1 0 0 IFTB IMTB * * * 1 0 IFAD IMAD * * * * 1 Note: * Don't care 14 HD404304 Series $000,0 IE Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $000,2 IF0 $000,3 IM0 Priority control logic Vector address $001,0 IF1 $001,1 IM1 $001,2 IFTA $001,3 IMTA $002,0 IFTB $002,1 IMTB $002,2 IFAD $002,3 IMAD Note: $m, n is RAM address $m, bit number n. Figure 6 Interrupt Control Circuit Block Diagram 15 HD404304 Series Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 7 Interrupt Processing Sequence 16 Execution of instruction at start address of interrupt routine HD404304 Series Power on RESET = 1? No Yes Interrupt request? Yes No No IE = 1? Yes Reset MCU Execute instruction Accept interrupt IE 0 PC (PC) + 1 Stack (PC) Stack (CA) Stack (ST) PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer A interrupt? No PC $0008 Yes Timer B interrupt? No PC $000A (A/D interrupt) Figure 8 Interrupt Processing Flowchart 17 HD404304 Series Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests. It is reset by an interrupt and set by the RTNI instruction. External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by port mode register A (PMRA: $004) (figure 10). The external interrupt request flags (IF0, IF1) are set at the falling edge of INT0 and INT1 inputs, respectively. The INT1 input can be used as a clock signal input to time B. Timer B is incremented at each falling edge of the INT1. When using INT1 as the timer B external event input, the external interrupt mask (IM1) must be set so that the interrupt request by INT 1 will not be accepted. Figure 9 shows the interrupt mode register. External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request flags (IF0, IF1) (figure 9) are set at the falling edge of the INT 0 and INT1 inputs, respectively. External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt mask bits (figure 9) mask an interrupt request caused by the external interrupt request flags. Port Mode Register A (PMRA: $004): Port mode register A is a 4-bit write-only register which controls the R32/INT0 pin and R33/INT1 pin as shown in figure 10. Port mode register A will be initialized to $0 by MCU reset. Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag (figure 9) is set when an overflow occurs in timer A. Timer A Interrupt Mask (IMTA: 001, Bit 3): The timer A interrupt mask bit (figure 9) masks an interrupt request caused by the timer A interrupt request flag. Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag (figure 9) is set when an overflow occurs in timer B. Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask bit (figure 9) masks an interrupt request caused by the timer B interrupt request flag. A/D Interrupt Request Flag (IFAD: $002, Bit 2): The A/D interrupt request flag (figure 9) is set when an A/D conversion is completed. A/D Interrupt Mask (IMAD: $002, Bit 3): The A/D interrupt mask bit (figure 9) masks an interrupt request caused by the A/D interrupt request flag. 18 HD404304 Series Bit 3 Bit 2 Bit 1 RSP Bit 0 : $000 Interrupt enable flag IE INT0 interrupt request flag IF0 INT0 interrupt mask Bit 3 Bit 2 Bit 1 Bit 0 IM0 0 1 0 1 0 1 : $001 INT1 interrupt request flag 0 IF1 1 INT1 interrupt mask 0 IM1 1 Timer A interrupt request flag 0 IFTA 1 Timer A interrupt mask 0 IMTA 1 Bit 3 Bit 2 Bit 1 Bit 0 : $002 Timer B interrupt request flag Timer B interrupt mask IFTB IMTB A/D interrupt request flag IFAD A/D interrupt mask IMAD 0 1 0 1 0 1 0 1 Disabled Enabled No interrupt request Interrupt requested Interrupt request enabled Interrupt request masked Interrupt request No Yes Enabled Disabled (masked) No Yes Enabled Disabled (masked) Interrupt request No Yes Enabled Disabled (masked) No Yes Enabled Disabled (masked) Figure 9 Interrupt Control Bits Bit 3 Bit 2 Bit 1 Bit 0 Port mode register A (PMRA: $004) Not used 0 1 0 Bit 3 1 Bit 2 R32 I/O pin INT0 input pin R33 I/O pin INT1 input pin Figure 10 Port Mode Register A 19 HD404304 Series Timers The MCU contains a prescaler and two timer/counters (timers A and B) as shown by the block diagram in figure 11. Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $000 by MCU reset or by setting bit 3 of timer mode register A (TMA: $008) when the watchdog timer on flag (WDON: $020, bit 1) is 0, after which the prescaler starts to divide the system clock. It continues operation until MCU reset or stop mode occurs. The pulse frequency of timer A input clock, timer B input clock, and the tone generator outputs (TG 0, TG1) are selected among prescaler outputs by timer mode register A (TMA: $008), timer mode register B (TMB: $009), and port mode register B (PMRB: $005), respectively. After MCU reset, WDON is 0. Thus, when timer A is reset by setting bit 3 of timer mode register A (TMA) when the watchdog timer is off, the prescaler is also reset, which affects the operation of timer B and the tone generator outputs (TG 0, TG1). Consequently, the program should control these conditions. Timer A Operation: Timer A is an 8-bit interval timer which can be used also as a watchdog timer. The prescaler divide ratio of timer A is selected by timer mode register A (TMA: $008). After timer A is initialized to $00 by MCU reset or setting bit 3 of timer mode register A (TMA: $008), it is incremented at every clock input signal. Eight different clock signals, divided by the prescaler, can be used as an input clock. The clock input signals to timer A are selected by timer mode register A. When the next clock signal is applied after timer A becomes $FF, an overflow is generated and timer A is reset to $00. This overflow causes the timer A interrupt request flag (IFTA $001, bit 2) to go to 1. This timer can function as a watchdog timer to detect a runaway program. The MCU is reset when an overflow output is generated from a timer counter that cannot be controlled due to a runaway program while the watchdog timer on flag (WDON) is 1. Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function input clock source, and the prescaler divide ratio for timer B. When an external event input is used as an input clock signal to timer B, select R3 3/INT1 as INT1 by setting port mode register A (PMRA: $004), and set the external interrupt mask (IM1) to prevent an external interrupt request from occurring. Timer B is initialized according to data written into timer load register B by software. Timer B is incremented at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will generate an overflow output. In this case, if the auto-reload function is selected, timer B is initialized according to the value of timer load register B. If it is not selected, timer B is reset to $00. The timer B interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output. 20 HD404304 Series System reset Watchdog timer on flag WDON Timer mode register A 3 Timer coutner A (8 bits) Timer A MPX IFTA Interrupt request flag of timer A /2 /4 /8 /32 /128 /512 /1024 /2048 System reset System clock PMRB 2 Prescaler (11 bits) /1024 /512 /256 /128 2 TG0 MPX TG1 Timer B MPX /2048 INT1 /2 /4 /8 /32 /128 /512 Internal bus line (S1) 4 TL (4 bits) Timer latch register 4 TCB (8 bits) Timer counter B 8 3 Timer mode register B 4 TLR (8 bits) Timer load register B 4 TBOF IFTB Interrupt request flag of timer B 4 Internal bus line (S2) Figure 11 Timers A and B Block Diagram 21 HD404304 Series Timer Mode Register A (TMA: $008): Timer mode register A is a 4-bit write-only register. Bits 0 to 2 of TMA control the prescaler divide ratio of the timer counter A clock input, as shown in figure 12. Bit 3 resets timer A when set to 1; if WDON = 0, the prescaler is also reset. Bit 3 retains a 1 for only one instruction cycle. Timer mode register A can be modified from the second instruction cycle of the write instruction. Timer mode register A (TMA: $008) Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 0 Bit 1 0 Bit 0 0 1 0 1 0 1 0 1 1 1 0 1 Prescaler divide ratio /2048 /1024 /512 /128 /32 /8 /4 /2 WDON Bit 3 Function 0 0 Not changed 0 1 1 0 Timer counter A and prescaler are reset 1 1 Timer counter A is reset WDON ADSF Special flag bit ($020) : Not used WDON : Watchdog on flag ADSF : A/D start flag Figure 12 Timer Mode Register A Configuration Timer Mode Register B (TMB: $009): Timer mode register B is a 4-bit write-only register which selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in figure 13. Timer mode register B is initialized to $0 by MCU reset. The operation mode of timer B can be modified from the second instruction cycle after timer mode register B is written to. The initialization of timer B by a write to the timer load register should be performed after the contents of timer mode register B have been appropriately changed. 22 HD404304 Series Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit writeonly timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL: $00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B). Timer counter B can be initialized by writing data into timer load register B. In this case, write the loworder digit first, and then the high-order digit. The timer counter is initialized when the high-order digit is written. The timer load register is initialized to $00 by MCU reset. The counter value of timer B can be obtained by reading time counter B. In this case, read the high-order digit first, and then the low-order digit. The count value of the low-order digit is latched when the highorder digit is read. Timer mode register B (TMB: $009) Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 Bit 3 0 1 Prescaler divide ratio input clock source /2048 /512 /128 /32 /8 /4 /2 INT1 (external event input) No auto-reload function Auto-reload function provided Figure 13 Timer Mode Register B Configuration Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag (figure 14) is set by the overflow output of timer A. When the watchdog timer function is selected, the timer interrupt request flag is not set since the MCU is reset by an overflow output. Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask (figure 14) prevents an interrupt request from being generated by the timer A interrupt request flag. Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag (figure 14) is set by the overflow output of timer B. Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask (figure 14) prevents an interrupt request from being generated by the timer B interrupt request flag. 23 HD404304 Series IMTA IFTA -- -- : $001 IFTA IMTA -- -- IMTB IFTB 0 1 0 1 Timer A interrupt request disabled Timer A interrupt request enabled Timer A interrupt request accepted Timer A interrupt request masked 0 1 0 1 Timer B interrupt request disabled Timer B interrupt request enabled Timer B interrupt request accepted Timer B interrupt request masked : $002 IFTB IMTB --: Other interrupt control bit Figure 14 Timer Interrupt Control Bits 24 HD404304 Series A/D Converter The HD404302R, HD404304, and HD4074308 incorporate a sequential comparison system A/D converter consisting of a resistor ladder. It can measure four analog inputs with 8-bit resolution. Figure 15 shows the A/D converter block diagram. The A/D converter consists of the following registers: * * * * A/D mode register (4 bits) A/D start flag (1 bit) A/D port select register (4 bits) A/D data register (4 bits + 4 bits) Internal bus ADPR: $00F A/D port select register (ADPR) 4 R40/AN0 R41/AN1 R42/AN2 R43/AN3 AMR: $00C A/D mode register (AMR) 2 ADSF: $020 A/D start flag (ADSF) ADRL: $00D ADRU: $00E A/D data register (ADR) 2 IFAD A/D interrupt request flag MPX + COMP - Control logic Counter AVCC AVSS D/A Figure 15 A/D Converter Block Diagram A/D Mode Register (AMR: $00C): The A/D mode register (figure 16) is a 4-bit write-only register which selects the A/D conversion speed (bit 0, bit 1) and analog input channel (bit 2, bit 3). A/D Start Flag (ADSF: $020, Bit 0): A/D conversion is started when a 1 is written to the A/D start flag (figure 16). After a conversion is completed, the conversion data is set in the A/D data register and the A/D start flag is cleared simultaneously. Note that the bit manipulation instruction SEM or SEMD should be used to write data to ADSF. During A/D conversion, ADSF must not be written to. 25 HD404304 Series A/D Port Select Register (ADPR: $00F): The A/D port select register (figure 16) is a write-only register which selects the digital port and analog port. A/D mode register (AMR: $00C) Bit 3 Bit 3 0 1 Bit 2 Bit 1 Bit 0 Bit 1 0 Bit 0 0 1 Bit 2 0 1 0 1 Conversion cycle 34 67 Analog input AN0 AN1 AN2 AN3 Special flag bit ($020) Bit 3 Bit 2 Bit 1 Bit 0 A/D start flag (ADSF) ADSF Start bit Status information (write) (test) 0 Not affect A/D idle A/D converting 1 Start WDON (see Timer section) Not used A/D port select register (ADPR: $00F) Bit 3 Bit 2 Bit 1 Bit 0 1 0 Port select AN3 AN2 AN1 R43 R42 R41 Figure 16 A/D Register Configuration 26 AN0 R40 HD404304 Series A/D Data Register (ADRL: $00D, ADRU: $00E): The A/D data register (figure 17) is a 4-bit/4-bit readonly register in which the 8-bit conversion result is set after completing A/D conversion. The data is preserved until the next conversion begins. Data read is not guaranteed during A/D conversion. The A/D data register is initialized to $80 by the MCU reset. Precautions on Using the A/D Converter: * If a digital signal is input to the R40 to R43 or adjacent pins during A/D conversion, conversion accuracy may be affected. * Data in the A/D data register is not guaranteed during A/D conversion. * Port output instructions should not be executed during A/D conversion to allow for a stable A/D converter operation. ADRU ($00E) 3 2 1 ADRL ($00D) 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Conversion result Figure 17 A/D Data Register Configuration 27 HD404304 Series Input/Output The MCU has 33 I/O pins, 25 being high-voltage pins. The on/off status of the output buffers of the standard pins (figure 19) is controlled by the combinations of the value of the port register (PDR) and data control register (DCR). D Port: The D port is an I/O port which has 13 discrete I/O pins, each of which can be addressed independently. It can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD instructions. Furthermore, the contents of the status flag become invalid when the unused ports are tested. D 11 and D12 ports are multiplexed with tone generator pins TG0 and TG 1, respectively. The circuit type of the D port is shown in table 3. R Ports: The R ports are composed of 20 I/O pins and one input-only pin. Data is input through the LAR and LBR instructions and output through the LRA and LRB instructions. The MCU will not be affected by writing into the input-only and non-existing ports. The on/off status of the output buffers of the R3 and R4 ports are controlled by the R port data control register (DCR3, DCR4). R32 and R33 are multiplexed with INT0 and INT1, respectively. R40, R41, R4 2, and R43 pins are multiplexed with AN0, AN1, AN2, and AN3, respectively. The circuit type of the R port is shown in table 3. Port Mode Register B (PMRB: $005): Port mode register B is a 4-bit write-only register which controls the D11/TG0 pin and D12/TG1 pin as shown in figure 18. The port mode register is initialized to $0 by MCU reset. These pins are therefore initially used a ports. Unused I/O Pins: If any unused I/O pins are left floating, the LSI may malfunction due to noise. The I/O pins should be fixed as follows to prevent malfunction. * If without pull-down MOS (PMOS open drain) is selected for high-voltage pins connect to VCC on the printed circuit board. * If without pull-up MOS is selected for standard pins, connect to GND on the printed circuit board. The contents of PDR and DCR of the corresponding pin should be programmed to remain the same as in the reset state. The corresponding pin should not be used as a peripheral function I/O pin. 28 HD404304 Series Port mode register B (PMRB: $005) Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 0 0 1 0 1 Prescaler Pulse frequency divide ratio (o = 1.9 s) /1024 0.5 kHz /512 1.0 kHz /256 2.0 kHz /128 4.0 kHz 0 1 0 1 D11 I/O pin TG0 output pin D12 I/O pin TG1 output pin 1 Bit 2 Bit 3 Figure 18 Port Mode Register B Functions 29 HD404304 Series VCC VCC Pull-up MOS HLT PMOS (A) DCR PDR NMOS (B) CPU input indicates an option Input control Mask Option With Pull-Up MOS (B) With Pull-Up MOS (C) DCR (data control register) 0 0 PDR (port data register) 0 1 0 1 0 1 0 1 CMOS PMOS (A) -- -- -- On -- -- -- On buffer NMOS (B) -- -- On -- -- -- On -- On On On On -- -- -- -- Pull-up MOS (C) Notes: 1: On 0: Off 1 1 --: Off Figure 19 I/O Buffer Configuration (Standard Pins) 30 HD404304 Series Table 3 (1) I/O Pin Circuit Types: Standard Pins Pin Type With Pull-Up MOS (B) I/O common pins Input control VCC CPU input VCC Input control VCC Without Pull-Up MOS (C) HLT Pin Name CPU input VCC DCR PDR PDR HLT Input control CPU input VCC R30 to R33 HLT DCR CPU input VCC Input control R40 to R43 HLT DCR DCR PDR PDR Note: Cannot be used as an analog input pin (AN0 to AN3). Input pins VCC HLT Input control Input control CPU input INT0, INT1 CPU input 31 HD404304 Series Table 3 (2) I/O Pin Circuit Types : High-Voltage Pins Pin Type Without Pull-Down MOS (D) With Pull-Down MOS (E) VCC I/O common pins Pin Name VCC HLT PDR D0 to D12 , HLT R00 to R03, PDR R10 to R13, VCC R20 to R23 Vdisp CPU input Input control Input pins Input control CPU input Input control CPU input RA1 Note: In the stop mode, the MCU is reset, peripheral functions cannot be selected, HLT becomes 1, and I/O pins are in high impedance. Circuit type B C D Product type Mask ROM (HD404302R, HD404304) Option ZTATTM (HD4074308) Fixed 32 E HD404304 Series Reset Setting the RESET pin high resets the MCU. At power-on or when cancelling stop mode, the reset must satisfy tRC for the oscillator to stabilize. In all other cases, at least two instruction cycles are required for the MCU to be reset. Table 4 shows the components initialized by MCU reset and the status of each after the reset has been carried out. Note: After reset, the standard pin port data register (PDR) is not stable. Therefore, write the data to the standard pin port data register (PDR) and set data control register (DCR) to output the data. Table 4 Initial Values after MCU Reset Item Initial Value Contents Program counter (PC) $0000 Execute program from the top of ROM address Status flag (ST) 1 Enable branching with conditional instructions Stack pointer (SP) $3FF Stack level is 0 I/O All bits are 0 Enable to output 0 High-voltage pin port data register (PDR) Standard pin port data register (PDR) -- Enable to output 1 (with pull-up MOS) Data control register (DCR) All bits are 0 Output buffer is off (high impedance) Port mode register A (PMRA) 0000 See Port Mode Register A section Port mode register B (PMRB) 0000 See Port Mode Register B section Interrupt enable flag (IE) 0 Inhibit all interrupts Interrupt request flag (IF) 0 No interrupt request Interrupt mask (IM) 1 Mask interrupt request Mode registers Timer mode register A (TMA) 0000 See Timer Mode Register A section Timer mode register B (TMB) 0000 See Timer Mode Register B section $00 -- Timer counter B (TCB) $00 -- Timer load register (TLR) $00 -- Prescaler $000 See Prescaler section A/D port select register (ADPR) 0000 See A/D Port Select Register section A/D mode register (AMR) 0000 See A/D Mode Register section A/D data register (ADR) $80 See A/D Data Register section A/D start flag (ADSF) 0 See A/D Start Flag section Watchdog timer on flag (WDON) 0 See Timer A section Interrupt flags/mask Timer/ counter Timer counter A/D Bit register Note: Registers and flags except above become as follows after MCU reset. 33 HD404304 Series Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM 34 After MCU Reset to Recover from Stop Mode After MCU Reset to Recover from Other Modes The contents of these items following The contents of these items following MCU reset are not retained; they MCU reset are not retained; they must be reinitialized by software must be reinitialized by software The contents of RAM just before MCU reset (just before a STOP instruction) are retained HD404304 Series Internal Oscillator Circuit Figure 20 is a block diagram of the internal oscillator circuit. Refer to table 5 for the selection type. In addition, see figure 21 for the layout of the crystal or ceramic oscillator. In all cases, an external clock operation is available. OSC1 (4.5 MHz) Oscillator Divider circuit (divide-by-8) Timing generator circuit 562.5-kHz system clock OSC2 Figure 20 Internal Oscillator Circuit D0 VCC OSC2 OSC1 TEST RESET ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, GND Figure 21 Layout of Crystal and Ceramic Oscillator 35 HD404304 Series Table 5 Example of Oscillator Circuits Circuit Configuration External clock operation Circuit Constant External oscillator OSC1 Open OSC2 C1 Ceramic oscillator Ceramic oscillator: CSA 4.00 MG OSC1 Ceramic (Murata) Rf = 1 M 20% Rf C1 = C2 = 30 pF 20% OSC2 C2 GND Rf = 1 M 20% C1 Crystal oscillator OSC1 Crystal C1 = 10 pF to 22 pF 20% C2 = 10 pF to 22 pF 20% Rf OSC2 C2 GND Crystal:Equivalent to the circuit shown at bottom left AT-cut parallel resonance crystal OSC1 L C1 RS C0 OSC2 C0= 7 pF max. RS = 100 max. f = 1.0 MHz to 4.5 MHz Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal, ceramic oscillator, and the floating capacitance when designing the board. When using the resonator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and other elements should be as short as possible, and avoid crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator (figure 21). 36 HD404304 Series Low-Power Dissipation Modes The MCU has two low-power dissipation modes, standby mode and stop mode (table 6). Figure 22 is a mode transition diagram of these modes. Table 6 Low-Power Dissipation Modes Condition Standby Mode Stop Mode Instruction SBY instruction STOP instruction Oscillator circuit Active Stopped Instruction execution Stopped Stopped Registers, flags Retained Reset*1 Interrupt function Active Stopped RAM Retained Retained 2 Input/output pins Retained* High impedance Timer/counters Active Stopped A/D Active Stopped Cancellation method RESET input, interrupt request RESET input Notes: 1. The MCU recovers from stop mode by RESET input. Refer to table 4 for the contents of flags and registers. 2. When I/O circuits are active, an I/O current may flow in standby mode, depending on the state of the I/O pins. This is an additional current added to the standby mode current dissipation. Active mode SBY instruction STOP instruction Interrupt request Standby mode RESET = 1 RESET = 0 RESET = 1 Stop mode RESET = 1 Reset Figure 22 MCU Operation Mode Transition 37 HD404304 Series Standby Mode: Executing the SBY instruction places the MCU into standby mode. In standby mode, the oscillator circuit continues working, and the timer/counter, A/D, and interrupts remain active. On the other hard, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and I/O pins retain the state they were in just before the MCU went into standby mode. Standby mode may be cancelled by inputting RESET or by asserting an interrupt request. In the former case the MCU is reset. In the later case, the MCU becomes active and executes the next instruction following the SBY instruction. If the interrupt enable flag is 1 when an interrupt request asserted, the interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution continues. Figure 23 shows the flowchart of the standby mode. Standby Oscillator: Active Peripheral clocks: Active All other clocks: Stop RESET = 1? Yes No IF0 = 1? No Yes IM0 = 0? IF1 = 1? No Yes IFTA = 1? No Yes IM1 = 0? No Yes No Yes IMTA = 0? IFTB = 1? No No Yes IFAD = 1? No Yes IMTB = 0? No Yes Yes IMAD = 0? Yes Restart processor clocks Restart processor clocks Execute next instruction (active mode) No Reset MCU Execute next instruction IE = 1? Yes Interrupt accept Figure 23 MCU Operating Flowchart in Standby Mode 38 No HD404304 Series Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit and every function of the MCU stop. The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 24, reset input must be applied for at least tRC for oscillation to stabilize. (Refer to AC Characteristics table.) After the stop mode is cancelled, RAM retains the state it was in just before the MCU went into stop mode, but the accumulator, B register, W register, X/SPX registers, Y/SPY registers, carry flag, and A/D data register will not retain their contents. Stop mode Oscillator Internal clock RESET tres STOP instruction execution tres tRC (stabilization time) Figure 24 Timing of Stop Mode Cancellation 39 HD404304 Series PROM Mode Pin Description (DP-42, DP-42S, DC-42) MCU Mode PROM Mode Pin No. Pin Name I/O Pin Name I/O 1 D10 I/O M2 I 2 D11/TG0 I/O VCC 3 D12/TG1 I/O VCC 4 RA1/Vdisp I 5 R00 I/O A1 I 6 R01 I/O A2 I 7 R02 I/O A3 I 8 R03 I/O A4 I 9 R10 I/O A5 I 10 R11 I/O A6 I 11 R12 I/O A7 I 12 R13 I/O A8 I 13 R20 I/O A0 I 14 R21 I/O A10 I 15 R22 I/O A11 I 16 R23 I/O A12 I 17 R30 I/O O0 I/O 18 R31 I/O O1 I/O 19 R32/INT0 I/O O2 I/O 20 R33/INT1 I/O O3 I/O 21 GND GND 22 AVCC VCC 23 R40/AN0 I/O O4 I/O 24 R41/AN1 I/O O5 I/O 25 R42/AN2 I/O O6 I/O 26 R43/AN3 I/O O7 I/O 27 AVSS 28 RESET I VPP /RESET 29 TEST I TEST 30 OSC1 I 31 OSC2 O 32 VCC 33 D0 40 GND I VCC I/O M0 I HD404304 Series MCU Mode PROM Mode Pin No. Pin Name I/O Pin Name I/O 34 D1 I/O M1 I 35 D2 I/O A9 I 36 D3 I/O 37 D4 I/O A13 I 38 D5 I/O A14 I 39 D6 I/O CE I 40 D7 I/O OE I 41 D8 I/O 42 D9 I/O Notes: I/O: I: O: Input/output pin Input pin Output pin 41 HD404304 Series PROM Mode Pin Description (FP-54) MCU Mode PROM Mode Pin No. Pin Name I/O Pin Name I/O 1 D10 I/O M2 I 2 D11/TG0 I/O VCC 3 D12/TG1 I/O VCC 4 RA1/Vdisp I 5 R00 I/O A1 I 6 NC 7 NC 8 NC 9 R01 I/O A2 I 10 R02 I/O A3 I 11 R03 I/O A4 I 12 R10 I/O A5 I 13 R11 I/O A6 I 14 R12 I/O A7 I 15 R13 I/O A8 I 16 R20 I/O A0 I 17 R21 I/O A10 I 18 R22 I/O A11 I 19 R23 I/O A12 I 20 NC 21 NC 22 NC 23 R30 I/O O0 I/O 24 R31 I/O O1 I/O 25 R32/INT0 I/O O2 I/O 26 R33/INT1 I/O O3 I/O 27 GND GND 28 AVCC VCC 29 R40/AN0 I/O O4 I/O 30 R41/AN1 I/O O5 I/O 31 R42/AN2 I/O O6 I/O 32 R43/AN3 I/O O7 I/O 33 NC 42 HD404304 Series MCU Mode PROM Mode Pin No. Pin Name 34 NC 35 NC 36 AVSS 37 RESET I VPP /RESET 38 TEST I TEST 39 OSC1 I 40 OSC2 O 41 VCC 42 D0 I/O M0 I 43 D1 I/O M1 I 44 D2 I/O A9 I 45 D3 I/O 46 D4 I/O A13 I 47 NC 48 NC 49 NC 50 D5 I/O A14 I 51 D6 I/O CE I 52 D7 I/O OE I 53 D8 I/O 54 D9 I/O Notes: I/O: I: O: NC: I/O Pin Name I/O GND I VCC Input/output pin Input pin Output pin No connection 43 HD404304 Series Programmable ROM (HD4074308) The MCU on-chip PROM is programmed in PROM mode. PROM mode is set by pulling TEST low, and RESET, M0, M1, and M2 high, as shown in figure 25. In PROM mode, the MCU does not operate. Table 7 shows the PROM mode selection. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a 42-to-28-pin socket adapter. Table 8 lists recommended PROM programmers and socket adapters. Since an instruction of the HMCS400 series consists of 10 bits, the HMCS400 series MCU incorporates a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit, an instruction is read or programmed using 2 addresses, generated as the lower 5 bits and upper 5 bits. For example, if 8 kwords of on-chip PROM are programmed by a general-purpose PROM programmer, 16 kbytes of addresses ($0000-$3FFF) should be specified. Programming and Verification The MCU can be high-speed programmed without causing voltage stress or affecting data reliability. Table 7 shows how programming and verification modes are selected. Erasing PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits are set to 1. Erasing conditions are: ultraviolet (UV) light with a wavelength of 2537 A with a minimum irradiation of 15 W*sec/cm2. These conditions are satisfied by exposing the LSI to a 12,000-W/cm2 UV source for 15 to 20 minutes at a distance of 1 inch. Precautions 1. Addresses $0000 to $3FFF must be specified if the PROM is programmed by a PROM programmer. If addresses of $4000 or higher are accessed, the PROM may not be programmed or verified. Note that the plastic type packages cannot be erased and reprogrammed. (Ceramic window packages can be erased and re-programmed by ultraviolet light.) Data in unused addresses must be set to $FF. 2. Be sure that the PROM programmer, socket adapter, and LSI are inserted correctly (pin 1 positions match). Using the wrong programmer or socket adapter may cause an overvoltage and damage the LSI (table 8). Make sure that the LSI is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed onto the programmer. 3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the MCU, the LSI may be permanently damaged. 12.5 V is Intel's 27256 VPP . 44 HD404304 Series Table 7 PROM Modes Selection Pin Mode CE OE VPP O0 to O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance Table 8 PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Type Name Manufacturer Package Type Name DATA I/O 22B Hitachi DP-42 HS430ESD01H DP-42S HS430ESS01H FP-54 HS430ESF01H DP-42 HS430ESD01H DP-42S HS430ESS01H FP-54 HS430ESF01H 29B AVAL Corp. PKW-1100 PKW-1000 Hitachi Note: An automatic programming mode of the PROM programmer is not available, therefore if a silicon signature check is performed, the A9 port will be permanently damaged. The A9 port is a highvoltage I/O port of the MCU. It will be damaged if an overvoltage (12.5 V) exceeding the voltage resistance of the MCU buffer is applied. When a connection check is made using a protection diode between the MCU and its socket, an open error occurs on an address port. Since the direction of the protection diode of the MCU highvoltage pin is reversed, the address port is regarded as open. 45 HD404304 Series VCC VCC M2 OE OE CE CE O0 to O7 Data O0 to O7 A0 to A14 Address A0 to A14 VCC M1 M0 TEST VPP/RESET AVCC AVSS GND VPP VCC Figure 25 Coonections for PROM Module 46 HD404304 Series Addressing Modes RAM Addressing Modes As shown in figure 26, the MCU has three RAM addressing modes: register indirect addressing, direct addressing, and memory register addressing. Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits) are used as the RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits) following the opcode used as the RAM address. Memory Register Addressing Mode: The memory registers (16 digits from $040 to $04F) are accessed by executing the LAMR and XMRA instructions. ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes as shown in figure 27. Direct Addressing Mode: The program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC 13 to PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. By executing the BR instruction, the program can branch to an address in the current page. This instruction replaces the low-order 8 bits of the program counter (PC7 to PC0) with 8-bit immediate data. When the BR instruction is on a page boundary (256n + 255) (figure 28), executing it transfers the PC contents to the next page according to the hardware architecture. Consequently, the program branches to the next page when the BR instruction is used on a page boundary. The HMCS400-series cross macroassembler has an automatic paging facility for ROM pages. Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page subroutine area, which is located at $0000-$003F. When the CAL instruction is executed, 6 bits of immediate data are placed in the low-order six bits of the program counter (PC 5 to PC0) and 0s are placed in the high-order eight bits (PC13 to PC6). Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address determined by the contents of the 4-bit immediate data, accumulator, and B register. P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure 29). When bit 8 in the referred ROM data is 1, 8 bits of ROM data are written into the accumulator and B register. When bit 9 is 1, 8 bits of ROM data are written into the R1 and R2 port output registers. When both bits 8 and 9 are 1, ROM data are written into the accumulator and B register, and also to the R1 and R2 port output registers at the same time. 47 HD404304 Series The P instruction has no effect on the program counter. W register W1 W0 X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing Instruction 1st word Instruction 2nd word Opcode d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Direct Addressing Instruction Opcode 0 0 0 1 m3 m2 m1 0 m0 0 RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing Figure 26 RAM Addressing Modes 48 HD404304 Series [JMPL] [BRL] [CALL] Instruction 1st word Opcode p3 Instruction 2nd word p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 Program counter PC13 PC12 PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A 3 A 2 A1 A0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 27 ROM Addressing Modes 49 HD404304 Series BR AAA 256(n - 1) + 255 256n AAA NOP BR AAA BR BBB 256n + 254 256n + 255 256(n + 1) BBB NOP Figure 28 BR Instruction Branch Destination on a Page Boundary 50 HD404304 Series Instruction [P] Opcode p3 0 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R2 2 R21 R2 0 R13 R12 R11 R10 If RO 9 = 1 Pattern Figure 29 P Instruction 51 HD404304 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V 1, 12 Program voltage VPP -0.3 to +14.0 V 2 Pin voltage VT -0.3 to VCC + 0.3 V 3 VCC - 45 to VCC + 0.3 V 4 Total permissible input current Io 50 mA 5 Maximum input current Io 15 mA 7, 8 Maximum output current -Io 4 mA 8, 9 6 mA 9, 10 30 mA 9, 11 6 Total permissible output current -Io 150 mA Operation temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: 1. Normal operation should be performed under the conditions specified by the electrical characteristics. Exceeding these conditions can result in malfunction, degraded performance, and permanent damage to the LSI. 2. Applies to the RESET pin (VPP ). (HD4074308) 3. Applies to pins other than high-voltage pins. 4. Applies to high-voltage pins. 5. Total permissible input current is the sum of input currents which flow in from all I/O pins to GND simultaneously. 6. Total permissible output current is the sum of output currents which flow from VCC to all I/O pins simultaneously. 7. Maximum input current is the amount of input current allowed from each I/O pin to GND. 8. Applies to R3 and R4. 9. Maximum output current is the amount of output current allowed from VCC to each I/O pin. 10. Applies to R0 to R2. 11. Applies to D0 to D12 . 12. Voltage is based on GND. 52 HD404304 Series Electrical Characteristics DC Characteristics (V CC = 5 V 10%, GND = 0 V, V disp = VCC - 40 V to V CC , T a = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Condition Notes Input high voltage VIH 0.8VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, -0.3 -- 0.2VCC V OSC1 -0.3 -- 0.5 V RESET, -- -- 1 A Vin = 0 V to VCC 1 -- -- 3.0 mA VCC = 5 V; 2, 5 RESET, INT0, INT1 Input low voltage VIL INT0, INT1 Input/output leakage current | IIL | INT0, INT1, OSC1 Current dissipation ICC in active mode VCC Current dissipation ISBY in standby mode VCC Current dissipation ISTOP in stop mode VCC Stop mode retaining voltage VCC VSTOP fOSC = 4 MHz -- -- 1.5 mA VCC = 5 V; 3, 5 fOSC = 4 MHz -- -- 10 A Vin(TEST) = VCC 4 Vin(RESET) = GND 2 -- -- V Notes: 1. Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. * MCU in reset state, operation mode * RESET, TEST: VCC * R3, R4: VCC * D0 to D12 , R0 to R2, RA1: Vdisp 3. The timer/counter operates with the fastest clock. Input/output current does not flow. * MCU in standby mode * Input/output in reset state * RESET: GND * TEST: VCC * R3, R4: VCC * D0 to D12 , R0 to R2, RA1: Vdisp 4. Excluding pull-down MOS current. 5. When fOSC = x MHz estimate the current dissipation as follows: Max. value fOSC = x MHz = x/4 x (max. value fOSC = 4 MHz) 53 HD404304 Series Input/Output Characteristics for Standard Pins (VCC = 5 V 10%, GND = 0 V, Vdisp = VCC - 40 V to VCC, T a = -20C to +75C unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Condition Note Input high voltage VIH R3, R4 0.7VCC -- VCC + 0.3 V Input low voltage VIL R3, R4 -0.3 -- 0.2VCC V Output high voltage VOH R3, R4 VCC - 1.0 -- -- V -IOH = 1.0 mA 1 VCC - 0.5 -- -- V -IOH = 0.5 mA 1 Output low voltage VOL R3, R4 -- -- 0.4 V IOL = 1.6 mA Input/output leakage current | IIL | R3, R4 -- -- 1 A Vin = 0 V to VCC 2 Pull-up MOS current -IPU R3, R4 30 70 150 A VCC = 5 V, 3 Notes: 1. Applied to I/O pins selected as CMOS output by mask option. 2. Pull-up MOS current and output buffer current are excluded. 3. Applied to I/O pins selected as with pull-up MOS by mask option. 54 Vin = 0 V HD404304 Series Input/Output Characteristics for High Voltage Pins (VCC = 5 V 10%, GND = 0 V, V disp = V CC - 40 V to VCC, T a = -20C to +75C unless otherwise specified) Item Symbol Pin Input high voltage VIH Min Typ Max Unit Test Condition -- VCC + 0.3 V -- 0.2VCC V D0 to D12 , VCC - 3.0 -- -- V -IOH = 15 mA TG0, TG1 VCC - 2.0 -- -- V -IOH = 10 mA VCC - 1.0 -- -- V -IOH = 4 mA R0 to R2 VCC - 3.0 -- -- V -IOH = 3 mA VCC - 2.0 -- -- V -IOH = 2 mA VCC - 1.0 -- -- V -IOH = 0.8 mA -- VCC - 37 V Vdisp = VCC - 40 V 1 -- VCC - 37 V 150 k atVCC - 40 V 2 -- 20 A Vin = VCC - 40 V to VCC 3 400 800 A HD404302R, 1 D0 to D12 , 0.7VCC Note R1, R2, RA1, R0 Input low voltage VIL D0 to D12 , VCC - 40 R1, R2, RA1, R0 Output high voltage VOH Output low voltage VOL D0 to D12 , -- R0 to R2 D0 to D12 , -- R0 to R2 Input/output leakage current | IIL | D0 to D12 , -- R0 to R2, RA1 Pull-down MOS current IPD D0 to D12 , 200 R0 to R2 HD404304: Vdisp = VCC - 35 V, Vin = VCC Notes: 1. Applied to I/O pins selected as with pull-up MOS by mask option. 2. Applied to I/O pins selected as without pull-up MOS (PMOS open drain) by mask option. 3. Pull-up MOS current and output buffer current are excluded. 55 HD404304 Series AC Characteristics (V CC = 5 V 10%, GND = 0 V, V disp = VCC - 40 V to V CC , T a = -20C to +75C unless otherwise specified) Test Condition Note Item Symbol Pin Min Typ Max Unit Oscillation frequency (divide-by-8) fOSC OSC1, OSC2 0.4 4 4.5 MHz Instruction cycle time tcyc 1.78 2 20 s Oscillation stabilization time tRC -- -- 20 ms (Ceramic oscillator) 40 ms (Crystal) OSC1, OSC2 1 External clock frequency tCP OSC1 0.4 -- 4.5 MHz External clock high and low widths tCPH , tCPL OSC1 92 -- -- ns Divide-by-8 2 External clock rising and falling times tCPr , tCPf OSC1 -- -- 20 ns 2 INT0 high and low widths tIH, tIL INT0 2 -- -- tcyc 3 INT1 high and low widths tIH, tIL INT1 2 -- -- tcyc 3 RESET high width tRSTH RESET 2 -- -- tcyc 4 Input capacitance HD404302R/ HD404304 Cin All pins -- (except RESET) -- 30 pF -- RESET -- -- 30 pF -- All pins -- (except RESET) -- 20 pF f = 1 MHz, Vin = 0 V RESET -- -- 250 pF f = 1 MHz, Vin = 0 V RESET -- -- 20 ms HD4074308 Cin RESET falling time tRSTf 4 Notes: 1. The oscillation stabilization time is the period from when V CC reaches 4.5 V at power-on until when the oscillator stabilizes, or after RESET goes to high to quit the stop mode. At power-on or when cancelling the stop mode, RESET must remain high for at least tRC. Since tRC depends on the crystal or ceramic oscillator's circuit constant and stray capacitance, it is recommended that the user follow the crystal or ceramic oscillator manufacturer's recommendations when designing the reset circuit. Applies to the HD404302R, HD4074308, and HD404304. C1 C1 OSC1 Crystal Rf OSC2 Crystal: HC-491U (4.19304 MHz: Kinseki) Rf = 1 M 20% C1 = C2 = 20 pF 20% OSC1 Ceramic OSC2 C2 GND 2. See figure 30. 3. See figure 31. 4. See figure 32. 56 Rf C2 GND Ceramic oscillator: CSA 4.00 MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% HD404304 Series A/D Converter Characteristics (VCC = 5.0 V 10%, VSS = AVSS = GND, T a = 0C to +70C) Item Symbol Pin Min Typ Analog power supply voltage AVCC AVCC Analog input voltage AVin AN0 to AN3 AVSS VCC - 0.3 VCC Current between AVCC IAD and AVSS -- Max Unit Test Condition Notes VCC + 0.3 V -- AVCC V 0.08 -- mA Analog input capacity CAin AN0 to AN3 -- 15 -- pF Resolution -- -- -- 8 -- Bit Conversion time -- -- 61 -- 536 s Number of inputs -- -- 0 -- 4 Channel Absolute accuracy -- -- -- -- 2 LSB 1 Ta = 25C, 1, 2 VCC = 5.0 V, fOSC = 1 MHz to 4.5 MHz Input impedance -- AN0 to AN3 1 M -- -- Notes: 1. The operating frequency fOSC of the A/D conversion is from 1 MHz to 4.5 MHz. 2. When using the R4/AN port as an analog input, the I/O option of the R4 port must be set as without pull-up MOS. 1/fCP VCC - 0.5V OSC1 tCPL tCPH 0.5V tCPr tCPf Figure 30 Oscillator Timing INT0, INT1 0.8VCC tIL tIH 0.2VCC Figure 31 Interrupt Timing 0.8VCC RESET tRSTH 0.2VCC tRSTf Figure 32 Reset Timing 57 HD404304 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404302R as an 4 k-word version (HD404304). The 4 k-word data size is required to change ROM data to mask manufacturing data since the program used is for a 4 k-word version. This limitation applies when using an EPROM or a data base. ROM 2 k-word version: HD404302R $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (2,048 words) $07FF $0800 Not used $0FFF Fill this area with 1s 58 HD404304 Series HD404302R and HD404304 Option List Order date Please check off the appropriate applications and enter the necessary information. Company name 1. ROM size Name Department HD404302R 2-kword ROM code HD404304 4-kword LSI type: 2. I/O option Note: I/O options masked by I/O option Pin name I/O A B C D E Pin name I/O A I/O I/O R11 I/O I/O R12 D3 I/O R13 D4 I/O D5 I/O R21 I/O R22 I/O I/O R23 I/O R30 I/O I/O R31 I/O I/O R32 D11 I/O R33 D12 I/O R4* R40 D2 D6 D7 D8 D9 D10 R1 R2 R3 I/O R20 R41 Standard pins D1 High-voltage pins I/O High-voltage pins R10 D0 B C D E I/O I/O I/O I/O I/O I/O I/O RA RA1 I R0 R00 I/O R42 I/O R01 I/O R43 I/O R02 I/O R03 I/O Selected in option 3 are not available I/O option I/O B: CMOS output with pull-up MOS C: CMOS D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS Note: *If pin R4/AN is used for analog input, select it with CMOS output (I/O option C). 3. RA1/Vdisp RA1: Without pull-down MOS (D) Vdisp Note: If even one high-voltage pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 4. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System oscillator for OSC1 and OSC2 Ceramic oscillator f= 6. Stop Mode 7. Package MHz Used DP-42 Not used DP-42S Crystal oscillator f= MHz External clock f= MHz FP-54 59 HD404318 Series Rev. 5.0 March 1997 Description The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter and input capture timer built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM. The HD4074318 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features * 34 I/O pins One input-only pin 33 input/output pins: 21 pins are high-voltage pins (40 V, max.) * On-chip A/D converter (8-bit x 8-channel) * Three timers One event counter input One timer output One input capture timer * 8-bit clock-synchronous serial interface (1 channel) * Alarm output * Built-in oscillators Ceramic or crystal oscillator External clock drive is also possible HD404318 Series * Seven interrupt sources Two by external sources Three by timers One each by the A/D converter and serial interface * Two low-power dissipation modes Standby mode Stop mode * Instruction cycle time 1 s (fosc = 4 MHz) Ordering Information Type Model Name ROM (words) RAM (digit) Package Mask ROM HD404314S 4,096 384 DP-42S HD404314H HD404316S FP-44A 6,144 DP-42S HD404316H HD404318S FP-44A 8,192 DP-42S HD404318H ZTAT HD4074318S FP-44A 8,192 DP-42S HD4074318H FP-44A Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacturer Model Name DATA I/O Corp. 121B DP-42S Hitachi HS4318ESS01H FP-44A AVAL Corp. PKW-1000 DP-42S FP-44A 2 HS4318ESH01H Hitachi HS4318ESS01H HS4318ESH01H HD404318 Series Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DP-42S 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R23 R22 R21 R20 R13 R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 44 43 42 41 40 39 38 37 36 35 34 NC R03 /TOC R02 /SO R01 /SI R00 /SCK RA1/Vdisp R23 R22 R21 R20 R13 RA1/Vdisp R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 AV CC V CC FP-44A 33 32 31 30 29 28 27 26 25 24 23 R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 R41/AN5 R42/AN6 R43/AN7 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC NC TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 3 HD404318 Series Pin Description Pin Number Item Symbol Power supply VCC DP-42S FP-44A I/O Function 21 16 Applies power voltage 10 5 Connected to ground Vdisp (shared 1 with RA1) 39 Used as a high-voltage output power supply pin when selected by the mask option Test TEST 6 1 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 7 2 I Resets the MCU Oscillator OSC1 8 3 I Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC1 to an external oscillator circuit. OSC2 9 4 O D0-D8 22-30 17-21, I/O Input/output pins addressed individually by bits; D 0-D8 are all high-voltage I/O pins. Each pin can be 23-26 individually configured as selected by the mask option. RA1 1 39 GND Port I One-bit high-voltage input port pin R00-R03, 2-5, R30-R43 12-19 40-43, I/O Four-bit input/output pins consisting of standard voltage pins 7-14 R10-R23, 31-42 27-38 I/O Four-bit input/output pins consisting of high voltage pins R80-R83 Interrupt INT0, INT1 22, 23 17, 18 I Input pins for external interrupts Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode Serial interface SCK 2 40 I/O Serial interface clock input/output pin SI 3 41 I Serial interface receive data input pin SO 4 42 O Serial interface transmit data output pin TOC 5 43 O Timer output pin EVNB 24 19 I Event count input pin BUZZ 25 20 O Square waveform output pin A/D converter AVCC 20 15 Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AVSS 11 6 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN0-AN7 12-19 7-14 Timer Alarm 4 I Analog input pins for the A/D converter HD404318 Series Pin Description in PROM Mode The HD4074318 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 1 39 RA1/Vdisp I 2 40 R00/SCK I/O VCC 3 41 R01/SI I/O VCC 4 42 R02/SO I/O 5 43 R03/TOC I/O 6 1 TEST I VPP 7 2 RESET I RESET 8 3 OSC1 I VCC 9 4 OSC2 O 10 5 GND GND 11 6 AVSS GND 12 7 R30/AN0 I/O O0 I/O 13 8 R31/AN1 I/O O1 I/O 14 9 R32/AN2 I/O O2 I/O 15 10 R33/AN3 I/O O3 I/O 16 11 R40/AN4 I/O O4 I/O 17 12 R41/AN5 I/O O5 I/O 18 13 R42/AN6 I/O O6 I/O 19 14 R43/AN7 I/O O7 I/O 20 15 AVCC VCC 21 16 VCC VCC 22 17 D0/INT0 I/O M0 I 23 18 D1/INT1 I/O M1 I 24 19 D2/EVNB I/O A1 I 25 20 D3/BUZZ I/O A2 I 26 21 D4/STOPC I/O 27 23 D5 I/O A3 I 28 24 D6 I/O A4 I 29 25 D7 I/O A9 I 30 26 D8 I/O VCC I 5 HD404318 Series Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 31 27 R80 I/O CE I 32 28 R81 I/O OE I 33 29 R82 I/O A13 I 34 30 R83 I/O A14 I 35 31 R10 I/O A5 I 36 32 R11 I/O A6 I 37 33 R12 I/O A7 I 38 34 R13 I/O A8 I 39 35 R20 I/O A0 I 40 36 R21 I/O A10 I 41 37 R22 I/O A11 I 42 38 R23 I/O A12 I I/O: Input/output pin; I: Input pin; O: Output pin 6 HD404318 Series INT0 GND VCC OSC2 OSC1 STOPC TEST RESET Block Diagram System control Interrupt control D0 INT1 RAM (384 x 4 bits) D1 D port D2 W (2 bits) Timer A D5 D7 D8 R0 port Timer B D4 D6 X (4 bits) EVNB D3 SPX (4 bits) R00 R01 R02 R03 SCK R1 port SPY (4 bits) R11 R12 R20 R21 R22 R23 ALU AVSS * * * A/D converter ST (1 bit) CA (1 bit) R3 port R30 AN0 * * * R10 R13 R2 port Serial interface Internal data bus SI SO Internal data bus Timer C TOC Internal address bus Y (4 bits) R33 AN7 A (4 bits) R40 R4 port AVCC B (4 bits) BUZZ R31 R32 R41 R42 R43 Buzzer SP (10 bits) R80 Instruction decoder PC (14 bits) R8 port Data bus R81 R82 Directional signal line ROM (4,096 x 10 bits) (6,144 x 10 bits) (8,192 x 10 bits) RA port R83 High voltage pin RA1 7 HD404318 Series Memory Map ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404314), $0000-$17FF (HD404316), $0000-$1FFF (HD404318, HD4074318)): The entire ROM area can be used for program coding. $0000 $000F Vector address (16 words) $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) HD404314 Program (4,096 words) $0FFF $1000 $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F HD404316 Program (6,144 words) $17FF $1800 HD404318, HD4074318 Program (8,192 words) $1FFF Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map 8 HD404318 Series RAM MemoryMap Initial values after reset $000 RAM-mapped registers $040 Memory registers (MR) $050 Data (304 digits) $180 Not used $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000 Undefined Undefined -000 0000 *2/0000 *1 Undefined 00-0000 *2/0000 Undefined Not used $3C0 Stack (64 digits) $3FF (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W -000 0000 1000 0000 --00 $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) (TMB2) $026 Timer mode register B2 W W W 0000 00-0 -000 (DCR0) W 0000 (DCR3) (DCR4) W W 0000 0000 $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 Not used Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $030 Port R0 DCR 2. Undefined. Not used R: Read only W: Write only R/W: Read/write $033 $034 Port R3 DCR Port R4 DCR Not used $03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map and Initial Values 9 HD404318 Series Table 1 Initial Values of Flags after MCU Reset Item Initial Value Interrupt flags/mask Bit registers RAM Address Interrupt enable flag (IE) 0 Interrupt request flag (IF) 0 Interrupt mask (IM) 1 Watchdog timer on flag (WDON) 0 A/D start flag (ADSF) 0 Input capture status flag (ICSF) 0 Input capture error flag (ICEF) 0 IAD off flag (IAOF) 0 RAM enable flag (RAME) 0 Bit 3 Bit 2 Bit 1 Bit 0 $0000 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $0001 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $0002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $0003 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 Not used ICSF (Input capture status flag) $020 Not used ADSF (A/D start flag) WDON (Watchdog on flag) $021 RAME (RAM enable flag) IAOF (IAD off flag) ICEF (Input capture error flag) IF: Interrupt request flag $022 IM: Interrupt mask IE: Interrupt $023 enable flag SP: Stack pointer Not used Register flag area Figure 3 Interrupt Control Bits and Register Flag Areas Configuration 10 HD404318 Series SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed RSP Not executed Allowed Inhibited WDON Allowed Not executed Inhibited ADSF Allowed Inhibited Allowed Not used Not executed Not executed Inhibited IE IM IAOF IF ICSF ICEF RAME Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1 $3C0 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC 13 PC 12 PC 11 $3FD PC 10 PC 9 PC 8 PC 7 $3FE CA PC 6 PC 5 PC 4 $3FF PC 3 PC2 PC 1 PC0 PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position 11 HD404318 Series Registers and Flags 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 Figure 6 Registers and Flags 12 0 (SP) HD404318 Series Addressing Modes RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. 1 0 3 W 9 0 3 3 Y X 7 0 3 Instruction 0 9 0 RAM address RAM address 0 0 0 1 0 0 Register Indirect Addressing Memory Register Addressing 9 Instruction 1st instruction word 0 9 0 Opcode 2nd instruction word 0 Opcode 9 0 RAM address Direct Addressing Figure 7 RAM Addressing Modes 13 HD404318 Series ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000-$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction. 2nd instruction word 1st instruction word 9 3 Opcode 09 0 Opcode 9 5 Operand 13 0 Operand 0 13 Program counter 0 Program counter 0 0 0 0 0 0 0 0 Direct Addressing Zero-Page Addressing Operand Opcode 9 7 0 Operand 13 9 3 Opcode 0 Program counter * * * * * * B 13 Program counter 0 0 Current Page Addressing Table Data Addressing Figure 8 ROM Addressing Modes 14 3 0 7 0 A 0 HD404318 Series Table 2 Instruction Set Classification Instruction Type Function Number of Instructions Immediate Transferring constants to the accumulator, B register, and RAM. 4 Register-to-register Transferring contents of the B, Y, SPX, SPY, or memory registers to the accumulator 8 RAM addressing Available when accessing RAM in register indirect addressing mode 13 RAM register Transferring data between the accumulator and memory. 10 Arithmetic Performing arithmetic operations with the contents of the accumulator, 25 B register, or memory. Compare Comparing contents of the accumulator or memory with a constant 12 RAM bit manipulation Bit set, bit reset, and bit test. 6 ROM addressing Branching and jump instructions based on the status condition. 8 Input/output Controlling the input/output of the R and D ports; ROM data reference 11 with the P instruction Control Controlling the serial communication interface and low-power dissipation modes. 4 Total: 101 instructions 15 HD404318 Series Interrupts $000,0 IE Interrupt request (RESET, STOPC) $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0004 3 $0006 4 $0008 5 $000A 6 $000C 7 $000E $001,2 Timer A interrupt IFTA $001,3 IMTA $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Figure 9 Interrupt Control Circuit 16 HD404318 Series Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 10 Interrupt Processing Sequence 17 HD404318 Series Operating Modes The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3 Operations in Each Operating Mode Function Active Mode Standby Mode Stop Mode System oscillator OP OP Stopped CPU OP Retained Reset RAM OP Retained Retained Timer A OP OP Reset Timers B, C OP OP Reset Serial interface OP OP Reset A/D OP OP Reset I/O OP Retained Reset Note: OP implies in operation 18 , , HD404318 Series Reset by RESET input or by watchdog timer RAME = 0 RESET 1 RAME = 1 RESET 2 STOPC Active mode Standby mode fOSC: Oscillate oCPU: Stop SBY instruction Interrupt oPER: fcyc Stop mode fOSC: Oscillate oCPU: fcyc STOP instruction oPER: fcyc fOSC: Stop oCPU: Stop oPER: Stop fOSC: Main oscillation frequency fcyc: fOSC/4 oCPU: System clock oPER: Clock for other peripheral functions Figure 11 MCU Status Transitions In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least tRC when clearing stop mode, execute the cancellation according to the timing chart in figure12. Stop mode Oscillator Internal clock RESET or STOPC tres STOP instruction execution tres tRC (stabilization period) Figure 12 Timing of Stop Mode Cancellation 19 HD404318 Series MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14. The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power ON RESET = 0? No Yes MCU operation cycle RAME = 0 Yes IF = 1? Reset MCU No No IM = 0 IE = 1 Yes Instruction RAME = 1 execution Reset input SBY/STOP instruction IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle (figure 15) PC (PC)+1 Figure 13 MCU Operating Sequence (Power ON) 20 PC vector address HD404318 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Stop mode Standby mode No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle Figure 14 MCU Operating Sequence (Low-Power Mode Operation) 21 HD404318 Series Oscillator Circuit Figure 15 shows a block diagram of the clock generation circuit. OSC2 1/4 System fOSC division oscillator circuit fcyc tcyc Timing generator circuit oCPU CPU with ROM, RAM, registers, flags, and I/O oPER Peripheral function interrupt OSC1 Figure 15 Clock Generation Circuit TEST RESET OSC1 OSC2 GND AVSS Figure 16 Typical Layout of Crystal and Ceramic Oscillator 22 HD404318 Series Table 4 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator (OSC1, OSC2) Ceramic oscillator: CSA4.00MG (Murata) C1 Rf = 1 M 20% OSC1 Ceramic C1 = C2 = 30 pF 20% Rf OSC2 C2 GND Crystal oscillator (OSC1, OSC2) Rf = 1 M 20% C1 C1 = C2 = 10 to 22 pF 20% OSC1 Crystal Crystal: Equivalent to circuit shown below Rf C0 = 7 pF max. OSC2 RS = 100 max. C2 GND L CS OSC1 RS OSC2 CO Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 16). 23 HD404318 Series I/O Ports The MCU has 33 input/output pins (D0-D 8, R0-R4, R8) and one input-only pin (RA1). The following describes the features of the I/O ports. * The 21 pins consisting of D0-D8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. * All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for NMOS open-drain output. * In stop mode, input/output pins go to the high-impedance state * All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by software Table 5 Control of Standard I/O Pins by Program MIS3 (bit 3 of MIS) 0 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS 1 1 0 1 Note: -- indicates off. Data control register (DCR0: $030, DCR3: $033, DCR4: $034) DCR0, DCR3, DCR4 Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name DCR03, DCR33, DCR43, Bits 0 to 3 CMOS Buffer Control DCR02, DCR01, DCR00, DCR32, DCR31, DCR30, DCR42, DCR41, DCR40 0 CMOS buffer off (high impedance) 1 CMOS buffer on Correspondence between ports and DCR bits Register Bit 3 Bit 2 Bit 1 Bit 0 DCR0 R03 R02 R01 R00 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 Figure 17 Data Control Register (DCR) 24 HD404318 Series Table 6 Circuit Configurations of Standard I/O Pins I/O Pin Type Circuit Input/output pins Pins VCC VCC Pull-up control signal Buffer control signal HLT R00, R01, R03 MIS3 R30-R33, DCR Output data R40-R43 PDR Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R02 MIS3 DCR MIS2 PDR Input data Input control signal Peripheral function pins Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC SCK HLT VCC Pull-up control signal Output data SO MIS3 MIS2 SO HLT VCC SCK MIS3 TOC MIS3 TOC Notes on next page. 25 HD404318 Series I/O Pin Type Peripheral function pins Circuit Input/ pins Pins VCC SI Input data HLT MIS3 PDR SI VCC AN0-AN7 HLT MIS3 PDR A/D input Input control Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. 26 HD404318 Series Table 7 Circuit Configurations for High-Voltage Input/Output Pins I/O Pin Type With Pull-Down Resistance Input/output pins VCC HLT Without Pull-Down Resistance VCC Output data Pull-down resistance HLT Output data D0-D8, R10-R13, R20-R23, Input data R80-R83 Input data RA1 Input control signal Vdisp Pins Input data Input control signal Input pins Input control signal Peripheral function pins Output pins VCC HLT Pull-down resistance Output data VCC BUZZ HLT Output data Vdisp Input data Input pins Pull-down resistance Vdisp Input data INT0, INT1, EVNB, STOPC Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. 3. The circuits of HD4074318 are without pull-down resistance. 27 HD404318 Series Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 18 Port Mode Register A (PMRA) Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W Bit name W W W * PMRB3 PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 19 Port Mode Register B (PMRB) 28 HD404318 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 -- -- -- -- Read/Write Bit name W W MIS3 MIS2 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 5) Not used Not used MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 CMOS on 1 CMOS off Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Figure 20 Miscellaneous Register (MIS) 29 HD404318 Series Prescaler The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then outputs divided clock signals to the peripheral function modules, as shown in figure21. Timer A System clock Clock selector Timer B Prescaler S Timer C Serial Figure 21 Prescaler Output Supply 30 HD404318 Series Timers The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that has the following features: * One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008) * An interrupt request can be generated when timer counter A (TCA) overflows * Input clock frequency must not be modified during timer A operation Table 7 Timer Functions Functions Clock source Timer functions Timer output Timer A Timer B Timer C Prescaler S Available Available Available External event -- Available -- Free-running Available Available Available Event counter -- Available -- Reload -- Available Available Watchdog -- -- Available Input capture -- Available -- PWM -- -- Available 31 HD404318 Series Timer counter A (TCA) Overflow System clock /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector oPER 3 Prescaler S (PSS) Timer mode register A (TMA) Figure 22 Timer A Block Diagram Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- W W W Not used TMA2 TMA1 TMA0 Bit name Source Input clock TMA2 TMA1 TMA0 Prescaler frequency 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc Figure 23 Timer Mode Register A (TMA) 32 Internal data bus Timer A interrupt request flag (IFTA) HD404318 Series Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows. * By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter * By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected * By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation * By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can be read out * Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event * An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation 33 HD404318 Series Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Free-running timer control signal Timer write register B lower (TWBL) /2 /4 /8 / 32 / 128 / 512 / 2048 Edge detector oPER 2 Overflow Timer write register B upper (TWBU) Selector EVNB System clock Timer counter B (TCB) 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control signal Timer mode register B2 (TMB2) Figure 24 Timer B Free-Running and Reload Operation Block Diagram 34 Internal data bus Clock HD404318 Series Input capture status flag (ICSF) Interrupt request flag of timer B (IFTB) Input capture error flag (ICEF) Error controller Timer read register BU (TRBU) Timer read register B lower (TRBL) Read signal Edge detector Clock Timer counter B (TCB) Overflow Input capture timer control signal Selector 3 /2 /4 /8 / 32 / 128 / 512 / 2048 System clock oPER 2 Internal data bus EVNB Timer mode register B1 (TMB1) Prescaler S (PSS) Edge detection control signal Timer mode register B2 (TMB2) Figure 25 Timer B Input Capture Operation Block Diagram 35 HD404318 Series Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D2/EVNB (external event input) 1 1 0 1 Figure 26 Timer Mode Register B1 (TMB1) Timer mode register B2 (TMB2: $026) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling edge detection 0 Rising edge detection 1 Rising and falling edge detection Bit name 2 Not used TMB22 1 1 TMB22 0 EVNB Edge Detection Selection Free-Running/Reload and Input Capture Selection 0 Free-Running/Reload 1 Input capture Figure 27 Timer Mode Register B2 (TMB2) 36 HD404318 Series Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. * By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected * By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled * By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be written to * By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be read out * An interrupt can be requested when timer counter C overflows * Timer counter C can be used as a watchdog timer for detecting runaway program 37 HD404318 Series System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL) Clock Timer output control signal /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector System oPER clock Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running timer control signal Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 28 Timer C Block Diagram 38 HD404318 Series Timer mode register C (TMC: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 29 Timer Mode Register C (TMC) T x (N + 1) TMC3 = 0 (Free-running timer) T T x 256 TMC3 = 1 (Reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 30 PWM Output Waveform 39 HD404318 Series $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Normal operation Reset Figure 31 Watchdog Timer Operation Flowchart Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Timer write register updated to value N Reload T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 40 T x (N + 1) T HD404318 Series Alarm Output Function The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected. Table 9 Port Mode Register C Bit 3 Bit 2 System Clock Divisor 0 0 / 2048 1 / 1024 0 / 512 1 / 256 1 BUZZ Alarm output control signal Alarm output controller System oPER clock 2 / 2048 / 1024 / 512 / 256 Selector Port mode register A (PMRA) Port mode register C (PMRC) Internal data bus PMRC Prescaler S (PSS) Figure 32 Alarm Output Function Block Diagram 41 HD404318 Series Serial Interface The MCU has a one-channel serial interface built in with the following features. * One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. * During idle states, the serial output pin can be controlled to be high or low output * Transmit clock errors can be detected * An interrupt request can be generated after transfer has completed when an error occurs Table 10 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 42 HD404318 Series Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Internal data bus Serial data register (SR) Selector /2 /8 / 32 / 128 / 512 / 2048 3 System clock oPER Prescaler S (PSS) Serial mode register (SMR) Port mode register C (PMRC) Figure 33 Serial Interface Block Diagram 43 HD404318 Series STS wait state (Octal counter = 000, transmit clock disabled) MCU reset SMR write (IFS 1) SMR write STS instruction Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 8 transmit clocks or STS instruction (IFS 1) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write Continuous clock output state (PMRA 0, 1 = 0, 0) SMR write MCU reset 8 transmit clocks or SMR write (IFS 1) STS instruction Transmit clock Transmit clock Transmit clock wait state (Octal counter = 000) STS instruction (IFS 1) Transfer state (Octal counter = 000) Internal clock mode Figure 34 Serial Interface State Transitions Transmit clock 1 Serial output data 2 3 4 5 LSB Serial input data latch timing Figure 35 Serial Interface Timing 44 6 7 8 MSB , !" HD404318 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Dummy write for state transition Output level control in idle states Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 36 Example of Serial Interface Operation Sequence 45 HD404318 Series Transmit clock erors are detected as illustrated in figure 37. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write Yes IFS = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000. Transmit clock error detection procedure Figure 37 Transmit Clock Error Detection 46 Flag reset at transfer completion. HD404318 Series Table 11 Transmit Clock Selection PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 System Clock Divisor Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 0 Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK Clock Source Output Prescaler Refer to table 11 0 Output System clock -- 1 Input External clock -- SMR1 SMR0 0 0 0 1 1 Prescaler Division Ratio SCK SMR2 0 1 1 0 0 1 1 Figure 38 Serial Mode Register (SMR) 47 HD404318 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write W W W W PMRC2 PMRC1 PMRC0 Bit name PMRC3 PMRC0 Alarm output function. Refer to table 9. Serial Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 39 Port Mode Register C (PMRC) 48 HD404318 Series A/D Converter The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The following describes the A/D converter. * A/D mode register 1 (AMR1: $019) is used to select digital or analog ports * A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports * The A/D channel register (ACR: $016) is used to select an analog input channel * A/D conversion is started by setting the A/D start flag (ADSF: $02C, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is cleared to 0 * By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode 4 A/D mode register 1 (AMR1) 3 Selector AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Encoder + Comp - AVCC A/D controller Control signal for conversion time A/D start flag (ADSF) AVSS A/D mode register 2 (AMR2) A/D data register (ADRU, L) Internal data bus A/D interrupt request flag (IFAD) A/D channel register (ACR) IAD off flag (IAOF) D/A Operating mode signal (1 in stop mode) Figure 40 A/D Converter Block Diagram 49 HD404318 Series Notes on Usage * * * * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) Do not write to the A/D start flag during A/D conversion Data in the A/D data register during A/D conversion is undefined Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power while in stop mode, all current flowing through the converter's resistance ladder is cut off. * If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up. A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 41 A/D Mode Register 1 (AMR1) 50 R30/AN0 Mode Selection HD404318 Series A/D mode register 2 (AMR2: $01A) Bit 3 2 Initial value -- -- 0 0 Read/Write -- -- W W Bit name 0 1 Not used Not used AMR21 AMR20 AMR20 Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4-AN7 Pin Selection 0 R4 1 AN4-AN7 Figure 42 A/D Mode Register (AMR2) A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write Bit name -- W W W Not used ACR2 ACR1 ACR0 ACR2 ACR1 ACR0 0 0 1 1 0 1 Analog Input Selection 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 Figure 43 A/D Channel Register (ACR) 51 HD404318 Series A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value -- 0 0 -- Read/Write -- R/W W -- Not used ADSF Bit name WDON Not used WDON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of timers Figure 44 A/D Start Flag (ADSF) IAD off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name ICSF IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off Refer to the description of timers ICEF RAME Refer to the description of timers Refer to the description of operating modes Figure 45 IAD Off Flag (IAOF) 52 HD404318 Series ADRU: $018 3 2 1 ADRL: $017 0 3 2 1 0 MSB LSB bit 7 bit 0 RESULT Figure 46 A/D Data Registers A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R R R R ADRL3 ADRL2 ADRL1 ADRL0 Figure 47 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write Bit name R R R R ADRU3 ADRU2 ADRU1 ADRU0 Figure 48 A/D Data Register Upper Digit (ADRU) 53 HD404318 Series Notes on Mounting Assemble all parts including the HD404318 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS . 1. When not using an A/D converter. VCC AVCC AN 0 0.1 F AN 1 to AN 7 AVSS GND 2. When using pins AN 0 and AN 1 but not using AN 2 to AN 7 . AVCC VCC AN 0 AN 1 AN 2 to AN 7 AVSS GND 0.1 F x 3 3. When using all analog pins. VCC AVCC AN 0 AN 1 AN 2 to AN 7 GND AVSS 0.1 F x 9 Figure 49 Example of Connections (1) 54 HD404318 Series Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 50. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. VCC VCC C1 GND C2 GND Figure 50 Example of Connections (2) 55 HD404318 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V 1 Pin voltage VT -0.3 to VCC + 0.3 V 2 VCC - 45 to VCC + 0.3 V 3 Total permissible input current IO 70 mA 4 Total permissible output current -IO 150 mA 5 Maximum input current IO 4 mA 6, 7 20 mA 6, 8 4 mA 9, 10 30 mA 10, 11 Maximum output current -IO Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074318. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3 and R4. 8. Applies to port R0. 9. Applies to ports R0, R3, and R4. 10. The maximum output current is the maximum current flowing from VCC to each I/O pin. 11. Applies to ports D0-D8, R1, R2, and R8. 56 HD404318 Series Electrical Characteristics DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VC C, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Input high voltage VIH 0.8VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, SCK, -0.3 -- 0.2VCC V VCC - 40 -- 0.2VCC V -0.3 -- 0.5 V RESET, SCK, Notes SI, INT0, INT1, STOPC, EVNB Input low voltage VIL SI INT0, INT1, STOPC, EVNB OSC1 Output high voltage VOH SCK, SO, TOC VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK, SO, TOC -- -- 0.4 V IOL = 0.4 mA I/O leakage current |IIL| RESET, SCK, -- -- 1 A Vin = 0 V to VCC -- -- 20 A Vin = VCC - 40 to VCC 1 -- -- 5.0 mA VCC = 5 V, 1 SI, SO, TOC, OSC1 INT0, INT1, STOPC, EVNB Current dissipation in active mode ICC VCC 2, 5, 6 fOSC = 4 MHz Current dissipation in standby mode ISBY Current dissipation in stop mode ISTOP VCC -- -- 8.0 mA -- -- 2.0 mA 2, 5, 7 VCC = 5 V, 3, 5 fOSC = 4 MHz Stop mode VSTOP retaining voltage VCC VCC -- -- 10 A -- -- 20 A 2 -- -- V VCC = 5 V 4, 6 4, 7 Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET, TEST at GND R0, R3, R4 at VCC D0-D8, R1, R2, R8, RA1 at Vdisp 57 HD404318 Series 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions:MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND R0, R3, R4 at VCC D0-D8, R1, R2, R8, RA1 at Vdisp 4. This is the source current when no I/O current is flowing. Test conditions:Pins: R0, R3, R4 at VCC D0-D8, R1, R2, R8, RA1 at GND 5. Current dissipation is in proportion to fOSC while the MCU is operating or in standby mode. The value of the dissipation current when fOSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 6. Applies to the HD404314, HD404316 and HD404318. 7. Applies to the HD4074318. I/O Characteristics for Standard Pins (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = V CC - 40 V to VCC, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Input high voltage VIH Unit Test Condition R0, R3, R4 0.7VCC -- VCC + 0.3 V Input low voltage VIL R0, R3, R4 -0.3 -- 0.3VCC V Output high voltage VOH R0, R3, R4 VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage VOL R3, R4 -- -- 0.4 V IOL = 1.6 mA R0 -- -- 2.0 V IOL = 10 mA Note Input leakage current |IIL| R0, R3, R4 -- -- 1 A Vin = 0 V to VCC 1 Pull-up MOS -IPU R0, R3, R4 30 150 300 A VCC = 5 V, Vin = 0 V 2 30 80 180 A Notes: 1. Output buffer current is excluded. 2. Applies to the HD404314, HD404316, and HD404318. 3. Applies to the HD4074318. 58 3 HD404318 Series I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Input high voltage VIH D0-D8, R1, 0.7VCC -- VCC + 0.3 V Input low voltage VIL Output high voltage VOH Output low voltage I/O leakage current Unit Test Condition Note R2, R8, RA1 D0-D8, R1, VCC - 40 -- 0.3VCC V VCC - 3.0 -- -- V -IOH = 15 mA VCC - 2.0 -- -- V -IOH = 10 mA VCC - 1.0 -- -- V -IOH = 4 mA -- -- VCC - 37 V Vdisp = VCC - 40 V -- -- VCC - 37 V 150 k at VCC - 40 V 2 -- -- 20 A 200 600 1000 A R2, R8, RA1 D0-D8, R1, R2, R8, BUZZ VOL D0-D8, R1, 1 R2, R8, BUZZ |IIL| Pull-down IPD MOS current D0-D8, R1, R2, Vin = VCC - 40 V to VCC 3 R8, RA1, BUZZ D0-D8, R1, Vdisp = VCC - 35 V, 1 Vin = VCC R2, R8, BUZZ Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current. A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Analog supply voltage AVCC AVCC Analog input voltage AVin AN0-AN7 AVSS Current flowing between IAD AVCC and AVSS Analog input capacitance CAin Min Typ VCC - 0.3 VCC Max Unit VCC + 0.3 V -- AVCC V -- -- 200 A AN0-AN7 -- -- 30 pF Resolution 8 8 8 Bit Number of input channels 0 -- 8 Chan nel Absolute accuracy -- -- 2.0 LSB Conversion time 34 -- 67 tcyc -- -- M Input impedance Note: AN0-AN7 1 Test Condition Note 1 VCC = AVCC = 5.0 V 1. Connect this to VCC if the A/D converter is not used. 59 HD404318 Series AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C) Item Symbol Pins Min Typ Max Unit Test Condition Clock oscillation frequency fOSC 0.4 4 4.5 MHz System clock divided by 4 Instruction cycle time tcyc 0.89 1 10 s Oscillation stabilization time (ceramic oscillator) tRC OSC1, OSC2 -- -- 7.5 ms 1 Oscillation stabilization time (crystal oscillator) tRC OSC1, OSC2 -- -- 40 ms 1 External clock high width tCPH OSC1 92 -- -- ns 2 External clock low width tCPL OSC1 92 -- -- ns 2 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT0, INT1, EVNB high widths tIH INT0, INT1, 2 -- -- tcyc 3 INT0, INT1, EVNB low widths tIL 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 STOPC low width tSTPL STOPC 1 -- -- tRC 5 RESET rise time tRSTr RESET -- -- 20 ms 4 STOPC rise time tSTPr STOPC -- -- 20 ms 5 Input capacitance Cin All input pins -- except TEST -- 30 pF TEST -- -- 30 pF 6 -- -- 180 pF 7 OSC1, OSC2 Note EVNB INT0, INT1, EVNB f = 1 MHz, V in = 0 V Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 47. 3. Refer to figure 48. 4. Refer to figure 49. 5. Refer to figure 50. 6. Applies to the HD404314, HD404316, and HD404318. 7. Applies to the HD4074318. 60 HD404318 Series Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 56 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc Load shown in figure 56 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc Load shown in figure 56 1 Transmit clock rise time tSCKr SCK -- -- 80 ns Load shown in figure 56 1 Transmit clock fall time tSCKf SCK -- -- 80 ns Load shown in figure 56 1 Serial output data delay time tDSO SO -- -- 300 ns Load shown in figure 56 1 Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 Pins Min Typ Max Unit Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK -- -- 80 ns 1 Transmit clock fall time tSCKf SCK -- -- 80 ns 1 Serial output data delay time tDSO SO -- -- 300 ns Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 During Transmit Clock Input Item Note: Symbol Test Condition Load shown in figure 56 Note 1 1. Refer to figure 51. OSC1 1/fCP VCC - 0.5 V 0.5 V tCPr tCPH tCPL tCPf Figure 51 External Clock Timing 61 HD404318 Series INT0, INT1, EVNB 0.8VCC tIL tIH 0.2VCC Figure 52 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 53 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 54 STOPC Timing 62 HD404318 Series t Scyc t SCKf SCK VCC - 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t SCKr t SCKL t SCKH t DSO VCC - 2.0 V 0.8 V SO t SSI 0.8V CC 0.2VCC SI Note: t HSI *VCC-2.0V and 0.8V are the threshold voltages for transmit clock output. 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 55 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent Figure 56 Timing Load Circuit 63 HD404318 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and HD404316 as an 8-kword version (HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the program used is for an 8-kword version. This limitation applies when using an EPROM or a data base. ROM 4-kword version: HD404314 Address $1000-$1FFF ROM 6-kword version: HD404316 Address $1800-$1FFF $0000 $0000 Vector address Vector address $000F $0010 $000F $0010 Zero-page subroutine (64 words) Zero-page subroutine (64 words) $003F $0040 $003F $0040 Pattern & program (4,096 words) Pattern & program (6,144 words) $17FF $1800 $0FFF $1000 Not used $1FFF $1FFF Fill this area with 1s 64 Not used HD404318 Series HD404314/HD404316/HD404318 Option List Please check off the appropriate applications and enter the necessary information. Date of order Customer 1. ROM Size Department HD404314 4-kword Name HD404316 6-kword ROM code name HD404318 8-kword LSI number 2. I/O Options D: Without pull-down resistance Pin name D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 E: With pull-down resistance I/O option I/O D E I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin name R1 R2 R8 RA 3. RA1/Vdisp R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 RA1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O option D E Selected in option (3) RA1 without pull-down resistance Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 4. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 6. Stop mode 5. System Oscillator for OSC1 and OSC2 7. Package Ceramic oscillator f= MHz Used DP-42S Crystal oscillator f= MHz Not used FP-44A External clock f= MHz 65 HD404328 Series Rev. 5.0 March 1997 Description The HD404328 Series is an HMCS400-Series microcomputer designed to increase program productivity and also to incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D converter, and zero-crossing detection circuit. Each also has a 32.768-kHz oscillator and low-power dissipation modes. The HD404328 Series includes eight chips: the HD404324 and HD404324U with 4-kword ROM; the HD404326 and HD404326U with 6-kword ROM; the HD404328 and HD404328U with 8-kword ROM; the HD4074329 and HD4074329U with 16-kword PROM. The HD404324U, HD404326U, HD404328U and HD4074329U are designed to reduce current dissipation in subactive mode and watch mode. The HD4074329 and HD4074329U, which include PROM, are ZTAT microcomputers that can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) Features * 4,096-word x 10-bit ROM (HD404324, HD404324U) 6,144-word x 10-bit ROM (HD404326, HD404326U) * 8,192-word x 10-bit ROM (HD404328, HD404328U) 16,384-word x 10-bit PROM (HD4074329, HD4074329U) * 280-digit x 4-bit RAM (HD404328, HD404328U) 536-digit x 4-bit RAM (HD4074329, HD4074329U) * 35 I/O pins 2 input pins 33 input/output pins, including 8 high-current pins (15 mA, max.) and 16 pins multiplexed with LCD segment pins * Three timer/counters * 8-bit clock-synchronous serial interface * 8-bit x 4-channel A/D converter * 12-digit LCD controller/driver (24 S EG x 4 C OM) (HD404328U, HD4074329U: External LCD voltage division resistors are required) * Zero-crossing detection circuit HD404328 Series * Eight interrupt sources Two external sources, including one double-edge function Six internal sources * Subroutine stack Up to 16 levels, including interrupts * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * Built-in oscillator Crystal or ceramic oscillator (external clock also enabled) 32.768 kHz crystal subclock * Instruction cycle time: 2 s (fOSC = 4 MHz) * Two operating modes MCU mode PROM mode (HD4074329, HD4074329U) ZTAT is a trademark of Hitachi Ltd. 2 HD404328 Series Ordering Information Type Product Name Model Name ROM (Words) RAM (Digits) Package Mask ROM HD404324 4,096 280 HD404326 HD404328 HD404324U* HD404326U* HD404328U* ZTAT HD4074329 HD4074329U* Note: * HD404324S DP-64S HD404324FS FP-64B HD404324H FP-64A HD404326S 6,144 DP-64S HD404326FS FP-64B HD404326H FP-64A HD404328S 8,192 DP-64S HD404328FS FP-64B HD404328H FP-64A HD404324US 4,096 DP-64S HD404324UFS FP-64B HD404324UH FP-64A HD404326US 6,144 DP-64S HD404326UFS FP-64B HD404326UH FP-64A HD404328US 8,192 DP-64S HD404328UFS FP-64B HD404328UH FP-64A HD4074329S 16,384 536 DP-64S HD4074329FS FP-64B HD4074329US DP-64S HD4074329UFS FP-64B Type with external LCD voltage-dividing resistor. 3 HD404328 Series Pin Arrangement AVCC AN 0 AN 1 AN 2 AN 3 AVSS TEST OSC 1 OSC 2 DP-64S DC-64S VCC COM4 COM3 COM2 COM1 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 SEG24 AN 2 AN 3 2 50 SEG23 AVSS SEG22 3 49 4 48 SEG21 TEST SEG20 OSC 1 5 47 OSC 2 6 46 SEG19 7 45 SEG18 RESET SEG17 8 44 X1 9 43 R5 3 /SEG16 X2 FP-64B R5 2 /SEG15 GND 10 42 11 41 R5 1 /SEG14 D0 12 40 R5 0 /SEG13 D1 13 39 R4 3 /SEG12 D2 14 38 R4 2 /SEG11 D3 15 37 R4 1 /SEG10 D4 16 36 R4 0 /SEG9 D5 17 35 R3 3 /SEG8 D6 18 34 R3 2 /SEG7 D7 19 33 R3 1 /SEG6 * 20 21 22 23 24 25 26 27 28 29 30 31 32 R3 0 /SEG5 R2 3 /SEG4 R2 2 /SEG3 R2 1 /SEG2 R2 0 /SEG1 R13 /BUZZ R12 /SO Note: * D8 /ZCD/EVENT R11 /SI AN 1 AN 0 AVCC V3 V2 V1 VCC COM4 COM3 COM2 COM1 SEG24 SEG23 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AN 3 AN 2 AN 1 AN 0 AVCC V3 V2 V1 VCC COM4 COM3 COM2 COM1 SEG24 SEG23 SEG22 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 * D9 /INT0 D10 /INT1 R00 R01 R02 R03 R10 /SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D9 /INT0 D 10 /INT1 R00 R01 R02 R03 R10 /SCK R11 /SI R12 /SO R13 /BUZZ R2 0 /SEG1 R2 1 /SEG2 R2 2 /SEG3 V1 V2 V3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 FP-64A 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 * D9 /INT 0 D10 /INT 1 R0 0 R0 1 R0 2 R0 3 R10 /SCK R11 /SI R12 /SO R13 /BUZZ SEG1/R2 0 SEG2/R2 1 SEG3/R2 2 SEG4/R2 3 SEG5/R3 0 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 (top view) 4 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16/R5 3 SEG15/R5 2 SEG14/R5 1 SEG13/R5 0 SEG12/R4 3 SEG11/R4 2 SEG10/R4 1 SEG9/R4 0 SEG8/R3 3 SEG7/R3 2 SEG6/R3 1 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R5 3 /SEG16 R5 2 /SEG15 R5 1 /SEG14 R5 0 /SEG13 R4 3 /SEG12 R4 2 /SEG11 R4 1 /SEG10 R4 0 /SEG9 R3 3 /SEG8 R3 2 /SEG7 R3 1 /SEG6 R3 0 /SEG5 R2 3 /SEG4 HD404328 Series Pin Description Pin Number Item Symbol DP-64S DC-64S FP-64B FP-64A Power supply VCC 64 58 56 Applies power voltage GND 16 10 8 Connected to ground Test TEST 10 4 2 I Used for factory testing only; connect this pin to VCC Reset RESET 13 7 5 I Resets the MCU Oscillator OSC1 11 5 3 I Input/output pins for the internal oscillator circuit; connect them to a crystal, ceramic, or external oscillator circuit OSC2 12 6 4 O X1 14 8 6 I X2 15 9 7 O D0-D8 17-25 11-19 9-17 I/O Input/output ports addressed by individual bits; pins D0-D7 are highcurrent pins that can each supply up to 15 mA D9, D10 26, 27 20, 21 18, 19 I Input ports addressable by individual bits R00-R53 28-51 22-45 20-43 I/O Input/output ports addressable in 4-bit units Interrupt INT0, INT1 26, 27 20, 21 18, 19 I Input pins for external interrupts Serial interface SCK 32 26 24 I/O Serial interface clock input/output pin SI 33 27 25 I Serial interface receive data input pin SO 34 28 26 O Serial interface transmit data output pin Buzzer BUZZ 35 29 27 O Buzzer signal output pin LCD V1, V2, V3 1-3 59-61 57-59 COM1-COM4 60-63 54-57 52-55 O Common signal pins for LCD SEG1-SEG24 36-59 30-53 28-51 O Segment signal pins for LCD Port I/O Function Used for a 32.768-kHz crystal for clock purposes; if not used, fix X1 to VCC and leave X2 open Power pins for LCD driver; can be left open in operation because they are connected by internal voltage division resistors (except for HD404328U and HD4074329U) Voltage conditions are: VCC V1 V2 V3 GND 5 HD404328 Series Pin Number Item Symbol DP-64S DC-64S FP-64B FP-64A A/D converter AVCC 4 62 60 Power pin for A/D converter; connect it to the same potential as VCC, as physically close as possible to the power source AVSS 9 3 1 Ground for AVCC; connect it to the same potential as GND, as physically close as possible to the power source AN0-AN3 5-8 63, 64, 1, 2 61-64 I Analog input pins for 4-channel A/D converter Zerocrossing detection ZCD 25 19 17 I Zero-crossing detection input pin Counter EVENT 25 19 17 I Event count input pin 6 I/O Function HD404328 Series GND VCC X2 X1 OSC2 OSC1 TEST RESET Block Diagram D0 INT1 D1 System control Interrupt control D2 D3 RAM (280 x 4 bits) (536 x 4 bits) D4 D port INT0 Timer A D5 D6 D7 W (2 bits) D8 D9 R0 port SPX (4 bits) BUZZ Buzzer ZCD Zerocrossing detection SPY (4 bits) CPU ALU ST (1 bit) CA (1 bit) R3 port A/D converter Internal data bus SCK AVSS AN 0 AN 1 AN 2 AN 3 AVCC Internal data bus Serial interface R2 port R1 port Y (4 bits) SI R4 port Timer C SO D10 R5 port Timer B Internal data bus EVENT X (4 bits) R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 A (4 bits) Data bus B (4 bits) V1 V2 V3 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 . . . . . SEG23 SEG24 SP (10 bits) LCD driver/ controller Instruction decoder Large-current pins PC (14 bits) Directional signal line ROM (8,192 x 10 bits) (16,384 x 10 bits) 7 HD404328 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. 0 $0000 Vector address $000F $0010 15 16 4095 4096 Pattern (4,096 words) HD404324, HD404324U program (4,096 words) 2 4 $003F $0040 5 6 7 8 $0FFF $1000 9 10 11 HD404326, HD404326U program (6,144 words) 6143 6144 1 3 Zero-page subroutine (64 words) 63 64 0 12 13 $17FF $1800 JMPL instruction (jump to reset routine) $0000 JMPL instruction (jump to INT0 routine) $0002 JMPL instruction (jump to INT1 routine) $0004 JMPL instruction (jump to timer A routine) $0006 JMPL instruction (jump to timer B routine) $0008 JMPL instruction (jump to timer C routine) $000A JMPL instruction (jump to ZCD routine) $000C 14 JMPL instruction 15 (jump to A/D, serial routines) $0001 $0003 $0005 $0007 $0009 $000B $000D $000E $000F HD404328, HD404328U program (8,192 words) 8191 8192 $1FFF $2000 HD4074329, HD4074329U program (16,384 words) 16383 $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area (HD404324, HD404324U: $0000-$0FFF; HD404326, HD404326U: $0000-$17FF; HD404328, HD404328U: $0000-$1FFF; HD4074329, HD4074329U: $0000-$3FFF): Used for program coding. 8 HD404328 Series RAM Memory Map The MPU contains a 280-digit x 4-bit (HD404328, HD404328U) or 536-digit x 4-bit (HD4074329, HD4074329U) RAM area consisting of a data area and a stack area. In addition, interrupt control bits and special registers are mapped onto the same RAM memory space outside this area. The RAM memory map is shown in figure 2 and described below. 0 63 64 79 80 103 104 RAM-mapped registers (64 digits) Memory registers (MR) (16 digits) LCD display area (24 digits) $000 $03F $040 $04F $050 $067 $068 Not used 111 112 287 288 Data (176 digits) $06F $070 $11F $120 Data (256 digits) 543 544 $21F $220 Not used $3BF $3C0 959 960 Stack (64 digits) 1023 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Interrupt control bits area (PMRA) Port mode register A (SMR) Serial mode register Serial data register, lower (SRL) Serial data register, upper (SRU) (TMA) Timer mode register A (TMB) Timer mode register B (TCBL/TLRL) * Timer B (TCBU/TLRU) (MIS) Miscellaneous register (TMC) Timer mode register C (TCCL/TCRL) * Timer C (TCCU/TCRU) Interrupt mode register (IMR) Port mode register B (PMRB) Port mode register C (PMRC) LCD control register (LCR) LCD mode register (LMR) LCD output register (LOR) A/D mode register (AMR) A/D data register, lower (ADRL) A/D data register, upper (ADRU) Not used $3FF Shaded area can only be used by the HD4074329, and HD4074329U 32 35 $020 $023 Register flag area Not used 48 49 50 51 52 53 R: Read only W: Write only R/W: Read/write W W R/W R/W W W R/W R/W W W R/W R/W W W W W W W W R R $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) W W W W W W $030 $031 $032 $033 $034 $035 59 Port D0-D3 DCR (DCRB) 60 Port D4 -D7 DCR (DCRC) 61 Port D8 DCR (DCRD) 62 Not used 63 W W W $03B $03C $03D $03E $03F Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Not used Note: * Two registers mapped on the same area Timer/event counter B, lower (TCBL) Timer/event counter B, upper (TCBU) Timer counter C, lower (TCCL) Timer counter C, upper (TCCU) R R R R Timer load register B, lower (TLRL) Timer load register B, upper (TLRU) W $00A Timer load register C, lower (TCRL) Timer load register C, upper (TCRU) W $00E W $00B W $00F Figure 2 RAM Memory Map 9 HD404328 Series Interrupt Control Bits Area and Register Flag Area ($000-$003, $020-$023): Used for interrupt control bits and the bit register (figure 3). This area can be accessed only by RAM bit manipulation instructions. In addition, note that the interrupt request flag cannot be set by software, the RSP bit is used only to reset the stack ppointer, and the WDON flag can be set only by the SEM and SEMD instructions. Special Function Registers Area ($004-$01F, $024-$03F): Used as mode registers for external interrupts, serial interface, and timer/counters, and as data registers and as data control registers for I/O ports. As shown in figure 2, these registers can be classified into three types: write-only, read-only, and read/write. The SEM, SEMD, REM, and REMD instructions can be used for the LCD control register (LCR), but RAM bit manipulation instructions cannot be used for other registers. LCD Data Area ($050-$067): Used for storing LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Data Area (HD404328, HD404328U: $040-$04F and $070-$11F, HD4074329, HD4074329U: $040- $04F and $070-$21F): The memory registers (MR), which consist of 16 digits ($040-$04F), can be accessed by the LAMR and XMRA instructions. Its structure is shown in figure 4. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine calls (CAL, CALL) and interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 4. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 10 HD404328 Series 0 1 2 3 Bit 3 IM0 (IM of INT0) IMTA (IM of timer A) IMTC (IM of timer C) IMAD (IM of A/D) DTON 32 (Direct transfer on flag) Bit 2 IF0 (IF of INT0) IFTA (IF of timer A) IFTC (IF of timer C) IFAD (IF of A/D) Bit 1 RSP (Reset SP bit) IM1 (IM of INT1) IMTB (IM of timer B) IMZC (IM of ZCD) Bit 0 IE (Interrupt enable flag) IF1 (IF of INT1) IFTB (IF of timer B) IFZC (IF of ZCD) ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $000 $001 $002 $003 $020 $021 33 Not used 34 $022 IMS IFS 35 (IM of serial interface) (IF of serial interface) $023 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other instructions have no effect. However, note the following usage limitations of RAM bit manipulation instructions. SEM/SEMD REM/REMD TM/TMD IF Not executed Allowed Allowed RSP Not executed Allowed Inhibited WDON Allowed Not executed Inhibited DTON Not executed in active mode Allowed Allowed Used in subactive mode Note: WDON is reset by MCU reset. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 11 HD404328 Series Memory registers 64 MR (0) $040 65 MR (1) $041 66 MR (2) $042 67 MR (3) $043 68 MR (4) $044 69 MR (5) $045 70 MR (6) $046 71 MR (7) $047 72 MR (8) $048 73 MR (9) $049 74 MR (10) $04A 75 MR (11) $04B 76 MR (12) $04C 77 MR (13) $04D 78 MR (14) $04E 79 MR (15) $04F Stack area 960 Level 16 $3C0 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC 13 PC 12 PC 11 $3FC 1021 PC10 PC 9 PC 8 PC 7 $3FD 1022 CA PC 6 PC 5 PC 4 $3FE 1023 PC3 PC 2 PC 1 PC 0 $3FF PC13-PC 0 : Program counter ST: Status flag CA: Carry flag Figure 4 Configuration of Memory Registers and Stack Area, and Stack Position 12 HD404328 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 5 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W 0 (B) 1 W register Initial value: Undefined, R/W 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register Initial value: Undefined, R/W SPX register Initial value: Undefined, R/W 0 (Y) 3 0 (SPX) 3 SPY register Initial value: Undefined, R/W 0 (SPY) 0 Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W (CA) 0 Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 5 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. 13 HD404328 Series W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): A 14-bit counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset, is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped from the stack. Since the top four bits of the SP are fixed at 1111, a stack of up to 16 levels can be used. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. 14 HD404328 Series Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are shown in table 1. Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCR) All bits 0 Turns output buffer off (to high impedance) Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of port mode register B Port mode register C (PMRC) 0000 Refer to description of port mode register C Interrupt mode register (IMR) 0000 Refer to description of interrupt mode register Timer/ Timer mode counters, serial register A interface (TMA) 0000 Refer to description of timer mode register A Timer mode register B (TMB) 0000 Refer to description of timer mode register B Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S $000 -- Prescaler W $00 -- Interrupt flags/mask I/O Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- 15 HD404328 Series Item Abbr. Initial Value Contents Timer counter C Timer/ counters, serial interface (TCC) $00 -- Timer load register B (TLR) $00 -- Timer load register C (TCR) $00 -- Octal counter 000 -- A/D A/D mode register (AMR) 0000 Refer to description of A/D mode register LCD LCD control register (LCR) 000 Refer to description of LCD control register LCD mode register (LMR) 0000 Refer to description of LCD duty cycle/clock control register LCD output register (LOR) 0000 Refer to description of LCD output register Low speed on flag (LSON) 0 Refer to description of low-power dissipation modes Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter Direct transfer on flag (DTON) 0 Refer to description of low-power dissipation modes 0000 Refer to description of miscellaneous register Bit register Miscellaneous register (MIS) Note: The statuses of other registers and flags after MCU reset are as follows: Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SR) A/D data register (ADRL, ADRU) RAM 16 Status After Cancellation of Stop Mode by MCU Reset Status After Cancellation of all Other Types of Modes by MCU Reset Pre-MCU-reset values are not guaranteed: values must be initialized by program Pre-MCU-reset values are not guaranteed: values must be initialized by program Pre-MCU-reset (pre-STOPinstruction) values are retained HD404328 Series Interrupts The MCU has eight interrupt sources: two external signals (INT0 and INT1), three timer/counters (timer A, timer B, and timer C), serial interface, zero-crossing detection, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Vector addresses are shared by serial interface and A/D converter interrupt causes, so software must first check which type of request has occurred. Interrupt Control Bits and Interrupt Servicing: Locations $000-$003 and $020-$023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 6, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the eight interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. Priority control logic generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 7 and an interrupt processing flowchart is shown in figure 8. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. 17 HD404328 Series $000, 0 IE INT0 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $000, 2 IF0 $000, 3 IM0 Vector address Priority control logic $001, 0 INT1 interrupt IF1 $001, 1 IM1 $001, 2 Timer A interrupt IFTA $001, 3 IMTA $002, 0 Timer B interrupt IFTB $002, 1 IMTB $002, 2 Timer C interrupt IFTC $002, 3 IMTC $003, 0 ZCD interrupt IFZC $003, 1 IMZC Note: $m, n is RAM address $m, bit number n. $003, 2 A/D interrupt IFAD $003, 3 IMAD $023, 2 IFS Serial interrupt $023, 3 IMS Figure 6 Block Diagram of Interrupt Control Circuit 18 HD404328 Series Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A ZCD 6 $000C A/D, Serial 7 $000E Table 3 Interrupt Processing and Activation Conditions Interrupt Cause Interrupt Control Bit INT0 INT1 Timer A Timer B Timer C ZCD A/D, Serial IE 1 1 1 1 1 1 1 IF0 IM0 1 0 0 0 0 0 0 . . IF1 IM1 * 1 0 0 0 0 0 . IFTA IMTA * * 1 0 0 0 0 . IFTB IMTB * * * 1 0 0 0 . IFTC IMTC * * * * 1 0 0 . IFZC IMZC * * * * * 1 0 . * * * * * * 1 IFAD IMAD + IFS .IMS Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. 19 HD404328 Series Instruction cycles 1 2 3 Stacking; IE reset Stacking; vector address generation 4 5 6 Instruction execution Interrupt acceptance Execution of JMPL instruction at vector address The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 7 Interrupt Processing Sequence 20 Execution of instruction at start address of interrupt routine HD404328 Series Power on RESET? Yes No Interrupt request? No Yes No Reset MCU IE = 1? Yes Execute instruction Accept interrupt PC (PC) + 1 IE 0 Stack (PC) Stack (CA) Stack (ST) PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer A interrupt? No PC $0008 Yes Timer B interrupt? No PC $000A Yes Timer C interrupt? No PC $000C Yes ZCD interrupt? No PC $000E (A/D, serial interrupt) Figure 8 Interrupt Processing Flowchart 21 HD404328 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as shown in table 4. Table 4 Interrupt Enable Flag IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): Specified by port mode register A (PMRA: $004). External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the rising or falling edges of the INT 0 and INT1 inputs, as shown in table 5. Table 5 External Interrupt Request Flags IF0, IF1 Interrupt Request 0 No 1 Yes IF0 is set at the falling edge of signals input to INT0, and IF1 is set at the rising and falling edges of signals input to INT1. The INT1 interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in figure 9. Interrupt mode register (IMR): $010 3 2 1 0 Initial value: 0000, R/W: W INT1 detection edge selection ZCD detection edge selection IMR Bit 3 0 1 IMR Bit 2 ZCD Detection Edge 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection Bit 1 0 1 Bit 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection Figure 9 Interrupt Mode Register 22 INT1 Detection Edge HD404328 Series External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as shown in table 6. Table 6 External Interrupt Masks IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (Masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as shown in table 7. Table 7 Timer A Interrupt Request Flag IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as shown in table 8. Table 8 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (Masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as shown in table 9. Table 9 Timer B Interrupt Request Flag IFTB Interrupt Request 0 No 1 Yes 23 HD404328 Series Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as shown in table 10. Table 10 Timer B Interrupt Mask IMTB Interrupt Request 0 Enabled 1 Disabled (Masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as shown in table 11. Table 11 Timer C Interrupt Request Flag IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as shown in table 12. Table 12 Timer C Interrupt Mask IMTC Interrupt Request 0 Enabled 1 Disabled (Masked) Zero-Crossing Interrupt Request Flag (IFZC: $003, Bit 0): Set by a zero crossing of an AC input signal, as shown in table 13. The interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in figure 9. Table 13 Zero-Crossing Interrupt Request Flag IFZC Interrupt Request 0 No 1 Yes Zero-Crossing Interrupt Mask (IMZC: $003, Bit 1): Prevents (masks) an interrupt request caused by the zero-crossing interrupt request flag, as shown in table 14. 24 HD404328 Series Table 14 Zero-Crossing Interrupt Mask IMZC Interrupt Request 0 Enabled 1 Disabled (Masked) A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as shown in table 15. Table 15 A/D Interrupt Request Flag IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as shown in table 16. Table 16 A/D Interrupt Mask IMAD Interrupt Request 0 Enabled 1 Disabled (Masked) Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when the octal counter counts the eighth transmit clock signal or when data transfer is discontinued by resetting the octal counter (table 17). Table 17 Serial Interrupt Request Flag IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as shown in table 18. Table 18 Serial Interrupt Mask IMS Interrupt Request 0 Enabled 1 Disabled (Masked) 25 HD404328 Series Operating Modes The MCU has five operating modes that are specified by how the clock is used. The functions available in each mode are listed in table 19, and operations are shown in table 20. Transitions between operating modes are shown in figure 10. Table 19 Functions Available in Each Operating Mode Mode Name Active Standby Stop Watch Subactive*4 Activation method RESET cancellation, interrupt request SBY instruction TMA3 = 0 STOP instruction TMA3 = 1 STOP instruction INT0 or timer A interrupt request from watch mode Status System oscillator OP OP Stopped Stopped Stopped Subsystem oscillator OP OP *1 OP OP OP Instruction execution (oCPU) OP Stopped Stopped Stopped OP Interrupt OP function interrupt (oPER) OP Stopped Stopped *5OP Clock function OP interrupt (oCLK) OP Stopped *2 OP *2OP RAM Retained Retained OP Retained OP 6 Registers/flags OP Retained Reset* Retained Retained/ operating I/O Retained Reset*3 Retained OP Cancellation method OP RESET input, RESET input RESET input STOP/SBY interrupt instruction request RESET input, RESET input, INT0 or timer STOP/SBY instruction A interrupt request Notes: OP: indicates in operation 1. To reduce current dissipation, stop all oscillation in external circuits. 2. Refer to the Interrupt Frame section for details. 3. Output pins are at high impedance. 4. Subactive mode is an optional function; specify it on the function option list. 5. The A/D converter does not operate. 6. Port mode register B retains the contents it had in active mode. 26 HD404328 Series System Clock (oCPU) Non-Time-Base Peripheral Function Clock (oPER) Operating Operating Stopped Active mode Standby mode Subactive mode Stopped -- Watch mode (TMA3 = 1) Stop mode (TMA3 = 0) Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*3 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Stopped* OP OP OP OP OP Retained Retained OP OP Stopped OP OP Serial interface Reset LCD Reset 3 1 I/O Reset* A/D Reset Zero-crossing Stopped 4 Stopped* 4 Stopped* detection Notes: OP: indicates in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. (However interrupts stop.) 4. The bias circuits still operate when the D8/ZCD/EVENT pin is set to ZCD. 27 HD404328 Series Reset Standby mode Active mode Stop mode (TMA3 = 0) oOSC: fX: oCPU: oCLK: oPER: Operating Operating Stopped = fcyc = fcyc SBY (standby) Interrupt oOSC: fX: oCPU: oCLK: oPER: Operating Operating = fcyc = fcyc = fcyc oOSC: fX: oCPU: oCLK: oPER: STOP (TMA3 = 0) Watch mode (TMA3 = 1, LSON = 0) (TMA3 = 1) oOSC: fX: oCPU: oCLK: oPER: Operating Operating Stopped = fSUB = fcyc SBY (standby) Interrupt oOSC: fX: oCPU: oCLK: oPER: Operating Operating = fcyc = fSUB = fcyc STOP INT0, time-base*1 *2 oOSC: fX: oCPU: oCLK: oPER: oOSC: fX: oCPU: oCLK: oPER: Stopped Operating Stopped = fSUB Stopped *3 Subactive mode oOSC: Main oscillation frequency fX: Suboscillation frequency, for time-base fcyc: fOSC/8 fSUB: fX/8 oCPU: System clock oCLK: Clock for time-base oPER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag Stopped Operating Stopped Stopped Stopped Stopped Operating fSUB fSUB fSUB STOP INT0, time-base *1 STOP/SBY (LSON = 1) *4 Notes: 1. 2. 3. 4. (TMA3 = 1, LSON = 1) oOSC: fX: oCPU: oCLK: oPER: Stopped Operating Stopped = fSUB Stopped Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) DTON can be 0 or 1. Figure 10 MCU Status Transitions Active Mode: The MCU operates according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode. In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM and register contents and maintaining the current I/O pin status. The standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 11. 28 HD404328 Series Standby Watch Oscillator: Stopped Sub-oscillator: Active Peripheral clocks: Stopped All other clocks: Stopped Oscillator: Active Peripheral clocks: Active All other clocks: Stopped RESET = 1? Yes No IF0 = 1? No Yes IM0 = 0? Yes IF1 = 1? No IFTA = 1? Yes No IM1 = 0? Yes No Yes IMTA = 0? No IFTB = 1? No Yes IFTC = 1? No Yes No Yes IMTB = 0? IFZC = 1? No Yes IMTC = 0? No Yes IFAD = 1? No Yes IMZC = 0? Yes No Yes IFS = 1? No IMAD = 0? Yes No Yes (SBY only) (SBY only) (SBY only) (SBY only) Execute next instruction Restart processor clocks No No (SBY only) IMS = 0? No (SBY Yes only) Restart processor clocks IF = 1, IM = 0, IE = 1? Yes Reset MCU Execute next instruction Accept interrupt Figure 11 MCU Operation Flowchart 29 HD404328 Series Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 = 0. In this mode, the system oscillator stops, which stops all MCU functions as well. The stop mode is terminated by a RESET input as shown in figure 12. RESET must be high for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET t res STOP instruction execution t res t RC (stabilization time) Figure 12 Timing of Stop Mode Cancellation Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. The watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + t RC) for an INT 0 interrupt, as shown in figures 13 and 14. 30 HD404328 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) tRC T TX T: Interrupt frame length t RC : Oscillation stabilization period Figure 13 Interrupt Frame Miscellaneous register (MIS): $00C 3 2 1 0 MIS Initial value: 0000, R/W: W T *1 Bit 1 Bit 0 Setting for switching the system oscillator's frequency 0.12207 ms 0 0 0.24414 ms 0 1 15.625 ms 7.8125 ms 1 0 125 ms 62.5 ms 1 1 tRC selection R12 /SO PMOS off t RC* 1 0.24414 * 2 ms Not used T: Interrupt frame length tRC: Oscillation stabilization period Notes: 1. The value of tRC applies only when using a 32.768-kHz crystal oscillator. 2. Only direct transfer. Figure 14 Miscellaneous Register 31 HD404328 Series Operation during mode transition is the same as that at standby mode cancellation (figure 11). Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits. Functions that can operate in subactive mode are listed in table 20. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a transition to active mode. The subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, timer A and INT0 interrupts are generated in synchronism with the interrupt frame. Three interrupt frame lengths (T) can be selected by the settings of the miscellaneous register, as shown in figure 14. The time from an interrupt strobe to interrupt request generation is the oscillation stabilization period (tRC), as shown in figure 13. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Operation during the transition from watch mode to active mode is the same as that at standby mode cancellation (figure 11). Direct Transfer: By controlling the DTON flag, the MCU will be placed directly from subactive to active mode. The detailed procedure is as follows: * Set the DTON flag in subactive mode while LSON = 0 and DTON = 1. * Execute the STOP or SBY instruction. * After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive to active mode (see figure 15). Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag is always at reset. The transition time (tD) from subactive to active mode is tRC < tD < T + tRC. 32 HD404328 Series STOP/SBY execution Internal execution Subactive mode time Oscillation stabilization time Active mode (LSON = 0, DTON = 1) Interrupt strobe Direct transfer timing t RC T T: Interrupt frame length tRC: Oscillation stabilization period Figure 15 Direct Transfer Timing MCU Operation Sequence: The MCU operates in the sequence shown in figures 16 to 18. It is reset by an asynchronous RESET input, regardless of its state. The low-power mode operation sequence is shown in figure 18. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on No RESET = 1? Yes MCU operation cycle Reset MCU Figure 16 MCU Operating Sequence (Power On) 33 HD404328 Series MCU operation cycle IF = 1? No Yes No IM = 0, IE = 1? Yes Instruction execution Yes SBY, STOP instruction? IE 0; stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC next location PC vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 17 MCU Operating Sequence (MCU Operation Cycle) 34 HD404328 Series Low-power mode operation cycle IF = 1, IM = 0? No Yes Standby/watch mode Stop mode For IF and IM operation, refer to figure 11. No IF = 1, IM = 0? Yes Hardware NOP execution Hardware NOP execution PC next location PC next location Instruction execution MCU operation cycle Figure 18 MCU Operating Sequence (Low-Power Mode Operation) Limitation on Use * In subactive mode, the timer A interrupt request or the external interrupt request (INT 0) occurs in synchronism with the interrupt strobe. If the STOP or SBY instruction is executed at the same time with the interrupt strobe, these interrupt requests will be cancelled and its corresponding interrupt request flags (IFTA, IF0) will be not set. In subactive mode, do not use the STOP or SBY instruction at the time of the interrupt strobe. 35 HD404328 Series * When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Edge detection is shown in figure 19. The level of the INT 0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 20, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 19 Edge Detection INT 0 INT 0 Interrupt frame Interrupt frame A: Low B: Low a. High level period Figure 20 Sampling Example 36 A: High B: High b. Low level period HD404328 Series Internal Oscillator Circuit A block diagram of the internal oscillator circuit is shown in figure 22. As shown in table 21, crystal and ceramic oscillators can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 3 of the miscellaneous register (MIS: $00C) must be set according to the frequency of the oscillator connected to OSC1 and OSC2. Note: If the MIS register setting does not match the oscillator frequency, subsystems using 32-kHz oscillation will malfunction. Set the system oscillator frequency to anything outside the range of 1.0 MHz to 1.6 MHz when using 32-kHz oscillation. Miscellaneous register (MIS): $00C 3 2 1 0 MIS Initial value: 0000, R/W: W tRC selection Bit 3 System Oscillator's Frequency 0 1.6 MHz to 4.5 MHz 1 0.4 MHz to 1.0 MHz R12 /SO PMOS off Setting for switching the system oscillator's frequency Figure 21 Miscellaneous Register OSC2 System oscillator Divide-by-8 circuit OSC1 X1 Sub-system oscillator X2 Divide-by-8 circuit Timing generator circuit Timing generator circuit Synch. (tcyc) Synch. (tsubcyc ) System clock (o CPU) Mode control circuit System clock (o PER) Time-base clock (o CLK ) Figure 22 Internal Oscillator Circuit 37 HD404328 Series Table 21 Oscillator Circuit Examples Circuit Configuration External Clock Operation (OSC1, OSC2) Circuit Constants External oscillator OSC1 Open OSC2 C1 Ceramic Oscillator (OSC1, OSC2) Ceramic: CSA4.00MG (Murata) R f = 1 M 20% C 1 = C2 = 30 pF 20% OSC1 Ceramic Rf OSC2 C2 GND Crystal Oscillator (OSC1, OSC2) R f: 1 M 20% C1 = C2 = 10 pF 10% Crystal: Equivalent to circuit shown at bottom left C0 = 7 pF, max. RS = 100 , max. f = 1.0 MHz to 4.5 MHz C1 OSC1 Crystal Rf OSC2 C2 GND AT-cut parallel resonance crystal L OSC1 CS RS OSC2 C0 Crystal Oscillator (X1, X2) C1 =C2 = 15 pF 5% Crystal: 32.768 kHz, MX38T (Nippon Denpa) C0 = 1.5 pF, typ. RS = 14 k , typ. C1 X1 Crystal X2 C2 GND X1 L CS RS X2 C0 Notes: 38 1. Circuit constants differ with different types of crystal and ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1 and OSC 2 pins (X1 and X2 pins) and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 23. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. HD404328 Series D0 GND X2 X1 RESET OSC 2 OSC 1 TEST AV SS Figure 23 Typical Layout of Crystal and Ceramic Oscillators 39 HD404328 Series Input/Output The MCU has 2 input pins and 33 input/output pins, 8 of the input/output pins being large-current pins (15 mA, max.). A program-controlled pull-up MOS transistor is provided for each input/output pin. The output buffer is turned on and off by the data control register (DCR) during input through an input/output pin. I/O pin circuit types are shown in table 22. Table 22 Circuit Configurations of I/O Pins I/O Pin Type Common I/O Pin (with pull-up MOS transistor) Circuit Applicable Pins Pull-up control signal VCC VCC DCR Output data Input control PDR Input data Pull-up control signal VCC D 0-D 8 R 0 0-R 0 3 R 10-R 13 R 2 0-R 2 3 R 3 0-R 3 3 R 4 0-R 4 3 R 5 0-R 5 3 SCK VCC DCR Output data SCK (internal) SCK Output Pin (with pull-up MOS transistor) Pull-up control signal VCC VCC DCR Output data SO or BUZZ Input Pin INT0 INT1 Pull-up control signal PDR VCC Input data Input control AC input signal External capacitor Zero-crossing detection circuit Note: For details of the R12 /SO pin, refer to note 2 of table 23. 40 SO BUZZ SI EVENT D9 D 10 ZCD HD404328 Series D Port (D0-D10): Consist of 9 input/output pins and 2 input pins. Pins D0-D7 are high-current I/O pins, D8 is an ordinary input/output pin, and D 9 and D10 are input-only pins. These pins are set by the SED and SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD instructions. The operating modes of D8-D10 are set by bits 2 and 3 of port mode register A (PMRA) and bits 0 and 1 of port mode register B (PMRB), as shown in figure 24. The on/off status of the output buffer is controlled by D port data control registers (DCRB, DCRC, and DCRD) that are mapped to memory addresses. R Ports: Accessed in 4-bit units. Data is input to these ports by the LAR and LBR instructions and output from them by the LRA and LRB instructions. The on/off status of the output buffers of the R ports are controlled by R port data control registers (DCR0-DCR5) that are mapped to memory addresses. Pins R10-R13 are multiplexed with pins SCK, SI, SO, and BUZZ, respectively. The operating modes of these pins are controlled by bit 3 of the serial mode register (SMR), bits 1 and 0 of port mode register A (PMRA), and bit 2 of port mode register C (PMRC), as shown in figure 24. Ports R2-R5 are multiplexed with SEG1-SEG16. The functions of these pins must be specified by the LCD output register (LOR: $015). 41 HD404328 Series Serial mode register (SMR): $005 3 2 1 0 Initial value: 0000, R/W: W R10 /SCK pin mode selection SMR Bit 3 Port Selection 0 R10 1 SCK Port mode register A (PMRA): $004 3 2 1 0 Initial value: 0000, R/W: W R12 /SO pin mode selection R11 /SI pin mode selection D9 /INT0 pin mode selection D10/INT 1 pin mode selection PMRA PMRA Bit 3 Port Selection PMRA Bit 2 Port Selection 0 1 PMRA Bit 1 Port Selection Bit 0 Port Selection D10 0 D9 0 R11 0 INT1 1 R12 INT0 1 SI 1 SO Port mode register B (PMRB): $011 3 2 1 0 Initial value: 0000, R/W: W D8 /ZCD/EVENT pin mode selection Not used PMRB Bit 1 0 1 Port Selection Bit 0 0 ZCD (low sensitivity) 1 ZCD (high sensitivity) * 0 D8 1 EVENT Note: * Becomes low sensitivity in subactive mode. Figure 24 I/O Switching Mode Registers 42 HD404328 Series Port mode register C (PMRC): $012 3 2 1 0 Initial value: 0000, R/W: W BUZZ output frequency selection R13/BUZZ pin mode selection Pull-up MOS transistor on/off selection PMRC Bit 3 Pull-Up MOS On/Off Selection PMRC Bit 3 Port Selection 0 Off 0 R13 1 On 1 BUZZ LCD output register (LOR): $015 3 2 1 0 Initial value: 0000, R/W: W R2/SEG1-SEG4 pin mode selection R3/SEG5-SEG8 pin mode selection R4/SEG9-SEG12 pin mode selection R5/SEG13-SEG16 pin mode selection LOR LOR Bit 3 Port Selection LOR Bit 2 Port Selection 0 1 LOR Bit 1 Port Selection Bit 0 Port Selection R5 0 R4 0 R3 0 R2 SEG13-SEG16 1 SEG9-SEG12 1 SEG5-SEG8 1 SEG1-SEG4 Figure 24 I/O Switching Mode Registers (cont) Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin. The on/off status of all these transistors is controlled by bit 3 of port mode register C (PMRC), and the on/off status of an individual transistor can also be controlled by the port data register of the corresponding pin--enabling on/off control of that pin alone. The on/off status of each transistor and the peripheral function mode of each pin can be set independently. The configuration of the I/O buffer is shown in figure 25, and the configurations of various programcontrolled I/O circuits are given in table 23. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. 43 HD404328 Series VCC PMRC3 VCC Pull-up MOS transistor PMOS (A) DCR NMOS (B) PDR Input data Input control Figure 25 I/O Buffer Configuration Table 23 Programmable I/O Circuits PMRC, Bit 3 0 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS (A) Off Off Off On Off Off Off On NMOS (B) Off Off On Off Off Off On Off Off Off Off Off Off On Off On CMOS Buffer Pull-Up MOS Transistor Notes: 1 1 1 1. Various I/O methods can be selected by different combinations of settings of the above mode registers (PMRC3, DCR, PDR). 2. The PMOS (A) transistor of the R12 /SO pin can be turned off by setting bit 2 of the miscellaneous register (MIS) to 1. MIS DCR Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 R12 /SO Pin PMOS (A) DCR0 R0 3 R0 2 R0 1 R0 0 0 On DCR1 R1 3 R1 2 R1 1 R1 0 1 Off DCR2 R2 3 R2 2 R2 1 R2 0 DCR3 R3 3 R3 2 R3 1 R3 0 DCR4 R4 3 R4 2 R4 1 R4 0 DCR5 R5 3 R5 2 R5 1 R5 0 DCRB D3 D2 D1 D0 DCRC D7 D6 D5 D4 DCRD -- -- -- D8 3. The relationships between DCRs and pins are as shown on the right. 44 0 HD404328 Series Timers The MCU has two prescalers (S and W) and three timer/counters (A, B, and C). Prescaler S: Eleven-bit counter that inputs a system clock signal. After being initialized to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes, and at MCU reset. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode register B (TMB), timer mode register C (TMC), and the serial mode register (SMR). Prescaler W: Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output can be selected as a timer A input clock by timer mode register A (TMA). Timer A: Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts from $00. Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software. 1/4 fW 1/2 twcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) /2 /8 / 16 / 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow System clock o PER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 26 Timer A Block Diagram 45 HD404328 Series Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register (TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The eight-bit configuration consists of lower and upper digits located at sequential addresses. A block diagram of timer B is shown in figure 27. Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower nibble must be written to first. The contents of TLR are loaded into the timer counter at the same time the upper nibble is written to, initializing the timer counter. TLR is initialized to $00 by MCU reset. The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first; the count is latched when the upper nibble is read. An auto-reload function, input clock source, and prescaler division ratio of timer B depend on the state of timer mode register B (TMB). When an external event input is used as the input clock source of TMB, the D 8/ZCD/EVENT pin must be set to function as the ZCD or EVENT pin by setting port mode register B (PMRB: $011). Timer B is initialized to the value set in TMB by software, and is then incremented by one by each clock input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). Interrupt request flag of timer B (IFTB) Clock Free-running/ reload timer control signal /2 /4 /8 / 32 / 128 / 512 / 2048 o PER Prescaler S (PSS) Overflow Timer load register B upper (TLRU) Timer load register B lower (TLRL) Selector EVENT System clock Timer/counter B (TCB) 3 Timer mode register B (TMB) Figure 27 Timer B Free-Running and Reload Operation Block Diagram 46 Internal data bus Timer latch register B (TLB) HD404328 Series Timer C (TCCL and TCRL: $00A, TCCU and TCRU: $00B): Eight-bit write-only timer load register (TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The eight-bit configuration consists of lower and upper digits located at sequential addresses. The operation of timer C is basically the same as that of timer B. A block diagram of timer C is shown in figure 28. The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register C (TMC). Timer C is initialized to the value set in TMC by software, then is incremented by one at each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by having the program control timer C reset before timer C reaches $FF. The WDON can only have 1 written to it; it is cleared to 0 only by MCU reset. System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Clock Timer/counter C (TCC) Overflow Timer load register C upper (TCRU) /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector System clock o PER Free-running/ reload timer control signal Internal data bus Timer latch register C (TLC) Timer load register C lower (TCRL) 3 Prescaler S (PSS) Timer mode register C (TMC) Figure 28 Timer C Block Diagram 47 HD404328 Series Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in table 24. Table 24 Timer Mode Register A TMA Bit 3 Bit 2 Bit 1 Bit 0 Source Prescaler, Input Clock Period, Operating Mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS, 2048 tcyc 1 PSS, 1024 tcyc 0 PSS, 512 tcyc 1 PSS, 128 tcyc 0 PSS, 32 tcyc 1 PSS, 8 tcyc 0 PSS, 4 tcyc 1 PSS, 2 tcyc 0 PSW, 32 tsubcyc 1 PSW, 16 tsubcyc 0 PSW, 8 tsubcyc 1 PSW, 2 tsubcyc 0 PSW, 1/2 tsubcyc 1 Do not use 0 PSW, TCA reset Timer A mode Time-base mode 1 tsubcyc = 244.14 s (when 32.768-kHz crystal oscillator is used) tcyc = 1.9074 s (when 4.1943-MHz crystal oscillator is used) Timer counter overflow output period (seconds) = input clock period (seconds) x 256. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the program to the minimum. 5. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Notes: 1. 2. 3. 4. Timer Mode Register B (TMB: $009): Four-bit write-only register that selects the auto-reload function, input clock source, and the prescaler division ratio as shown in table 25. It is initialized to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle. Timer B initialization set by writing to TMB must be done after a mode change becomes valid. 48 HD404328 Series Table 25 Timer Mode Register B TMB Bit 3 Auto Reload Function 0 Disabled 1 Enabled TMB Bit 2 Bit 1 Bit 0 Input Clock Period/ Input Clock Source 0 0 0 2048 tcyc 1 512 tcyc 0 128 tcyc 1 32 tcyc 0 8 tcyc 1 4 tcyc 0 2 tcyc 1 ZCD/EVENT (external event input) 1 1 0 1 Timer Mode Register C (TMC: $00D): Four-bit write-only register that selects the auto-reload function and prescaler division ratio as shown in table 26. It is initialized to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle. Timer C initialization set by writing to TMC must be done after a mode change becomes valid. Table 26 Timer Mode Register C TMC Bit 3 Auto Reload Function 0 Disabled 1 Enabled 49 HD404328 Series TMC Bit 2 Bit 1 Bit 0 Input Clock Period 0 0 0 2048 tcyc 1 1024 tcyc 0 512 tcyc 1 128 tcyc 0 32 tcyc 1 8 tcyc 0 4 tcyc 1 2 tcyc 1 1 0 1 Pulse Output The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the prescaler S' s outputs, and the output frequency depends on the state of port mode register C (PMRC: $012), as shown in table 27. The duty cycle of the pulse output is fixed at 50%. When the pulse output function is used, the R13/BUZZ pin must be specified as BUZZ by PMRC. Table 27 Port Mode Register C PMRC Bit 1 Bit 0 Prescaler Division Ratio 0 0 / 1024 1 / 512 0 / 256 1 / 128 1 50 HD404328 Series Serial Interface The MCU has a clock-synchronous serial interface which transmits and receives 8-bit data. The serial interface consists of a serial data register (SR), serial mode register (SMR), port mode register A (PMRA), octal counter, and selector, as shown in figure 29. The R10/SCK pin and the transmit clock are controlled by writing data to the SMR. The transmit clock shifts the contents of the SR, which can be read and written to by software, before transmission starts between two MCUs. The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, it starts counting at the falling edge of the transmit clock (SCK), and it increments at the rising edge of the clock. A serial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial transmission is discontinued (the octal counter is reset). Serial interrupt request flag (IFS) Octal counter (OC) SO SCK I/O controller SI Selector Clock 1/2 Transfer control signal Internal data bus Serial data register (SR) Selector /2 /8 / 32 / 128 / 512 / 2048 3 System clock oPER Serial mode register (SMR) Prescaler S (PSS) Figure 29 Serial Interface Block Diagram Serial Mode Register (SMR: $005): Four-bit write-only register that controls the R10/SCK pin, transmit clock, and prescaler division ratio as shown in figure 30. Writing to this register initializes the serial interface. A write signal input to the serial mode register discontinues the input of the transmit clock to the serial data register and octal counter. Therefore, if a write is performed during data transmission, the octal counter is reset to 000 to stop transmission, and, at the same time, the serial interrupt request flag is set. 51 HD404328 Series Write operations are valid from the second instruction execution cycle, so the STS instruction must be executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU reset. Serial mode register (SMR): $005 3 2 1 0 Initial value: 0000, R/W: W SMR R10 /SCK Pin Bit 3 Transmit clock selection R10 /SCK pin mode selection SMR Transmit Clock Period 0 SCK output Prescaler / 2048 4096 tcyc 1 SCK output Prescaler / 512 1024 t cyc 0 SCK output Prescaler / 128 256 t cyc 1 SCK output Prescaler / 32 64 tcyc 0 SCK output Prescaler /8 16 tcyc 1 SCK output Prescaler /2 4 t cyc 0 SCK output System clock -- 1 tcyc 1 SCK input External clock -- -- 0 0 1 SCK input or output pin Prescaler Division Ratio Bit 0 0 1 Clock Source Bit 1 1 R10 port input or output pin R1 0 /SCK Pin Bit 2 1 0 Note: t cyc = 1.9074 s (with 4.1943-MHz crystal oscillator used at 1/8 division ratio) Figure 30 Serial Mode Register Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and lower digits located at sequential addresses. Data in this register is output from the SO pin, LSB first, in synchronism with the falling edge of the transmit clock; and data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 31. Data cannot be read or written during serial data transmission. If a read/write occurs during transmission, the accuracy of the resultant data cannot be guaranteed. 52 HD404328 Series Transmit clock 1 Serial output data 2 3 4 5 6 7 8 MSB LSB Serial input data latch timing Figure 31 Timing of Serial Interface Output Selecting and Changing Operating Mode: Table 28 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of PMR and SMR settings; to change the operating mode, always initialize the serial interface internally by writing data to the SMR. Table 28 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Serial Interface Operation: Three operating modes are provided for the serial interface; transitions between them are shown in figure 32. In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed, the serial interface enters transmit clock wait state. In transmit clock wait state, input of the transmit clock increments the octal clock, shifts the serial clock register, and activates serial transmission. However, note that if clock output mode is selected, the transmit clock is continuously output but data is not transmitted. During transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters transmit clock wait state. If the state changes from transmit to another state, the serial interrupt request flag is set by the octal counter reaching 000. In this state, if the internal clock has been selected, the transmit clock is output in answer to the execution of the STS instruction, but serial transmission is inhibited after the eighth clock is output. 53 HD404328 Series If port mode register A (PMRA) is written to in transmit clock wait state or transfer state, the serial mode register (SMR) must be written to, to initialize the serial interface. The serial interface then enters STS wait state. If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the serial interrupt request flag. STS instruction wait state (octal counter = 000, transmit clock disabled) SMR write STS instruction 8 transmit clocks (internal clock) (IFS 1) SMR write (IFS 1) Transmit clock Transmit clock wait state (octal counter = 000) 8 transmit clocks (external clock) STS instruction (IFS 1) Transfer state (octal counter 000) Figure 32 Serial Interface Mode Transitions Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this type can be detected as shown in figure 33. If more than eight transmit clocks are input in transmit clock wait state, the serial interface's state changes to transfer, transmit clock wait, then back to transfer. If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request flag has been reset, the flag is reset again. 54 HD404328 Series Transmission completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1? Yes Transmit clock error processing No Normal termination Figure 33 Transmit Clock Error Detection Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the execution of an SMR write or STS instruction during the first period that the transmit clock is low. To prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port) before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is set. 55 HD404328 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure four analog inputs with an eight-bit resolution. As shown in the block diagram of figure 34, the A/D converter has a four-bit A/D mode register, a one-bit A/D start flag, and a four-bit plus four-bit A/D data register. Internal bus line (S2) 4 1 A/D mode register (AMR: $016) 2 Internal bus line (S1) 1 A/D start flag (ADSF: $020) 4 A/D data register (ADRL: $017, ADRU: $018) 1 AN 2 Selector AN 0 AN 1 AN 3 4 IFAD Comparator + Control logic AVCC AVSS Counter - D/A Figure 34 A/D Converter Block Diagram A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the AMR selects the A/D conversion period, and bits 2 and 3 select a channel, as shown in figure 35. A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when 1 is written to it. At the completion of A/D conversion, the converted data is stored in the A/D data register and the ADSF is cleared. Refer to figure 35. Note: Use the SEM and SEMD instructions to write data to the ADSF, but make sure that the ADSF is not written to during A/D conversion. 56 HD404328 Series A/D mode register (AMR): $016 3 2 1 0 Initial value: 0000, R/W: W Switching time Not used Analog input selection AMR Switching Time Bit 0 0 34 tcyc 1 67 tcyc AMR Analog Input Selection Bit 3 Bit 2 0 0 AN 0 1 AN 1 0 AN 2 1 AN 3 1 Special flag bits: $020 3 2 1 0 LSON (refer to description of low-power dissipation modes) WDON (refer to description of timers) A/D start flag (ADSF) DTON (refer to description of low-power dissipation modes) Bit 2 A/D Start Flag (ADSF) 1 A/D conversion started 0 A/D conversion completed Figure 35 A/D Registers A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register that is not cleared by a reset. Note that data read from this register during A/D conversion cannot be guaranteed. After the completion of A/D conversion, the resultant eight-bit data is held in this register, as shown in figure 36, until the start of the next conversion. 57 HD404328 Series ADRL: $017 ADRU: $018 3 2 1 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Result Figure 36 A/D Data Registers Note on Use: The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D converter operates stably, do not execute port output instructions during A/D conversion. 58 HD404328 Series LCD Controller/Driver The MCU has an LCD controller and driver which drive four common signal pins and 24 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR), and a duty cycle/clock control register (LMR), as shown in figures 37 and 38. Four duty cycles and the LCD clock are program-controllable, and a built-in dual-port RAM ensures that display data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz oscillation clock is selected as the LCD clock source, the LCD can be used even in watch mode, in which the system clock stops. VCC Power switch V1 LCD power control circuit V2 * V3 COM1 COM2 COM3 COM4 LCD common driver * LCD clock * GND LCD output register (LOR: $015) Display on/off 4 1 2 Display control register (LCR: $013) R2 0 /SEG1 R2 1 /SEG2 $050 Display area (dual-port RAM) LCD segment driver Segment/ R2-R5 port multiplexer R5 3 /SEG16 SEG17 $067 LCD duty cycle/ clock control register (LMR: $014) 2 2 SEG24 RAM area Duty cycle selection LCD clock 3 Divided system clock output 1 Divided 32-kHz clock output Clock selection Note: * HD404328U and HD4074329U require external LCD voltage division resistors. LCD: Liquid crystal display Figure 37 Block Diagram of LCD Controller/Driver 59 HD404328 Series LCD control register (LCR): $013 2 1 0 Initial value: 000, R/W: W Blank/display Power switch on/off Display on/off in watch mode or subactive mode (not used) LCD mode register (LMR): $014 3 2 1 0 Initial value: 0000, R/W: W Duty cycle selection Input clock selection LCD output register (LOR): $015 3 2 1 0 Initial value: 0000, R/W: W R2/SEG1-SEG4 pin mode selection R3/SEG5-SEG8 pin mode selection R4/SEG9-SEG12 pin mode selection R5/SEG13-SEG16 pin mode selection Figure 38 LCD Registers LCD Data Area and Segment Data ($050-$067): As shown in figure 39, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. 60 HD404328 Series Bit 3 Bit 2 Bit 1 Bit 0 80 SEG1 SEG1 SEG1 SEG1 $050 92 SEG13 SEG13 SEG13 SEG13 $05C 81 SEG2 SEG2 SEG2 SEG2 $051 93 SEG14 SEG14 SEG14 SEG14 $05D 82 SEG3 SEG3 SEG3 SEG3 $052 94 SEG15 SEG15 SEG15 SEG15 $05E 83 SEG4 SEG4 SEG4 SEG4 $053 95 SEG16 SEG16 SEG16 SEG16 $05F 84 SEG5 SEG5 SEG5 SEG5 $054 96 SEG17 SEG17 SEG17 SEG17 $060 85 SEG6 SEG6 SEG6 SEG6 $055 97 SEG18 SEG18 SEG18 SEG18 $061 86 SEG7 SEG7 SEG7 SEG7 $056 98 SEG19 SEG19 SEG19 SEG19 $062 87 SEG8 SEG8 SEG8 SEG8 $057 99 SEG20 SEG20 SEG20 SEG20 $063 88 SEG9 SEG9 SEG9 SEG9 $058 100 SEG21 SEG21 SEG21 SEG21 $064 89 SEG10 SEG10 SEG10 SEG10 $059 101 SEG22 SEG22 SEG22 SEG22 $065 90 SEG11 SEG11 SEG11 SEG11 $05A 102 SEG23 SEG23 SEG23 SEG23 $066 91 SEG12 SEG12 SEG12 SEG12 $05B 103 SEG24 SEG24 SEG24 SEG24 $067 COM4 COM3 COM2 Bit 3 COM1 COM4 Bit 2 COM3 Bit 1 COM2 Bit 0 COM1 Figure 39 Configuration of LCD RAM Area (for Dual-Port RAM) LCD Control Register (LCR: $013): Three-bit write-only register which controls LCD blanking, the turning on and off of the liquid-crystal display's power supply division resistor, and display in watch and subactive modes, as shown in table 29. * Blank/display Blank: Segment signals are turned off, regardless of LCD RAM data setting. Display: LCD RAM data is output as segment signals. * Power switch on/off Off: The power switch is off. On: The power switch is on and V1 is VCC. * Watch/subactive mode display Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. On: In watch and subactive modes, LCD RAM data is output as segment signals. 61 HD404328 Series Table 29 LCD Control Register LCR LCR LCR Bit 2 Display in Watch Mode or Subactive Mode Bit 1 Power Switch On/Off Bit 0 Blank/Display 0 Off 0 Off 0 Blank 1 On 1 On 1 Display Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the LCD clock, always set bit 2 of the LCR to 0. LCD Duty Cycle/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in table 30. The dependence of frame frequency on duty cycle is shown in table 31. Table 30 LCD Duty Cycle/Clock Control Register LMR Bit 3 Bit 2 Bit 1 Bit 0 Duty Selection/Input Clock Selection -- -- 0 0 1/4 duty cycle 1 1/3 duty cycle 0 1/2 duty cycle 1 Static -- CL0 (32.768/64 kHz when using a 32.768-kHz oscillator) 1 0 1 0 -- 1 CL1 (fcyc/256) 0 CL2 (fcyc/2048) 1 CL3 (refer to table 31) Note: fcyc is the divided system clock output. 62 HD404328 Series Table 31 LCD Frame Periods for Different Duty Cycles Static Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 s 512 Hz 1953 Hz 244 Hz 122 Hz/64 Hz 1/2 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 s 256 Hz 976.5 Hz 122 Hz 61 Hz/32 Hz 1/3 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 s 170.6 Hz 651 Hz 81.3 Hz 40.6 Hz/21.3 Hz 1/4 Duty Cycle LMR Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 Bit 3 Bit 2 0 0 0 1 1 0 1 1 Instruction Cycle Time CL0 CL1 CL2 CL3* 2 s 128 Hz 488.2 Hz 61 Hz 30.5 Hz/16 Hz Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA); the first value is for TMA3 = 0 and the second is for TMA3 = 1. When TMA3 = 0, CL3 = fcyc /4096 When TMA3 = 1, CL3 = 32.768 kHz/512. 63 HD404328 Series LCD Output Register (LOR: $015): Write-only register used to specify that ports R2-R5 act as pins SEG1-SEG16, as shown in table 32. Table 32 LCD Output Register LOR LOR LOR LOR Bit 3 Port Selection Bit2 Port Selection Bit 1 Port Selection Bit 0 Port Selection 0 R5 0 R4 0 R3 0 R2 1 SEG16-SEG13 1 SEG12-SEG9 1 SEG8-SEG5 1 SEG4-SEG1 Large Liquid-Crystal Panel Drive and VLCD : To drive a large-capacity LCD, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 40. Since HD404328U and HD4074329U do not have built-in division resistors, they require external LCD voltage division resistors for voltage adjustment. The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix configuration of the LCD complicates the paths of charge/discharge currents flowing through the capacitors--and the resistance will also vary with lighting conditions. This size must be determined by trial-and-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 k to 10 k would usually be suitable. (Another effective method is to attach capacitors of 0.1 F to 0.3 F.) Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (VLCD). 64 HD404328 Series R VCC (V1) R V2 V2 C R VCC (V1) R C V3 V3 R R C GND GND C = 0.1 F to 0.3 F 1 V CC COM1 3-digit LCD V1 VCC VLCD V2 V3 GND 24 SEG1- SEG24 Static drive V CC V1 VCC VLCD COM1 COM2 2 6-digit LCD V2 V3 GND 24 SEG1- SEG24 1/2 duty cycle, 1/2 bias drive V CC V1 VCC VLCD COM1- COM3 3 8-digit LCD V2 V3 GND 24 SEG1- SEG24 1/3 duty cycle, 1/3 bias drive V CC V1 VCC VLCD COM1- COM4 4 12-digit LCD V2 V3 SEG1- SEG24 1/4 duty cycle, 1/3 bias drive 24 GND VCC VLCD GND Figure 40 LCD Connection Examples 65 HD404328 Series Zero-Crossing Detection Circuit The MCU has a zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input to the ZCD pin through an external capacitor. A block diagram of the zero-crossing detection circuit is shown in figure 41. The zero-crossing detection circuit has two modes (low sensitivity mode and high sensitivity mode) which are set by port mode register B (PMRB: $011) as shown in table 33. A digital signal generated by the zero-crossing detection circuit sets the zero-crossing interrupt request flag (IFZC). The interrupt edge is selected by the interrupt mode register (IMR: $010). This signal can be made as the input clock of timer B by setting the input clock source of timer mode register B (TMB: $009) for external event input. Note: After MCU reset, the D8/ZCD/EVENT pin is set to ZCD. With this setting, a supply current (bias current) always flows because a bias circuit within the zero-crossing circuit is still operating. This current flows in all MCU operation modes, but it is particularly critical in stop mode because the MCU is more affected by bias current since the other circuits of the LSI are not dissipating much current. If the zero-crossing detection function is not being used, use port mode register B to set this pin to D8 or EVENT. This prevents the bias current from flowing. D8 port input AC input signal EVENT (Refer to figure 27.) MPX D 8/ZCD/ EVENT pin MPX Zero-crossing detection circuit MPX MPX 2 2 IFZC External capacitor Port mode register B Interrupt mode register Figure 41 Block Diagram of Zero-Crossing Detection Circuit Table 33 Port Mode Register B PMRB 1 0 Port Selection 0 0 ZCD (low sensitivity mode) 1 ZCD (high sensitivity mode)* 0 D8 1 EVENT 1 Note: * Becomes low sensitivity in subactive mode. 66 HD404328 Series Table 34 Registers in Special Register Area Name Address R/W Bit Description PMRA $004 0 R12/S0 pin mode selection 1 R11/SI pin mode selection 2 D9/INT0 pin mode selection 3 D10/INT1 pin mode selection 2-0 Serial transmit clock speed selection 3 R10/SCK pin mode selection SMR $005 W W SRL $006 R/W 3-0 Serial interface data register, lower 4 bits SRU $007 R/W 3-0 Serial interface data register, upper 4 bits TMA $008 W 2-0 Input clock selection (timer A) 3 Timer-A/time-base mode selection 2-0 Input clock selection (timer B) 3 Auto-reload function selection TMB $009 W TCBL/TLRL $00A R/W 3-0 Timer counter/timer load register (timer B), lower 4 bits TCBU/TLRU $00B R/W 3-0 Timer counter/timer load register (timer B), upper 4 bits MIS $00C W 1, 0 Interrupt frame period selection 2 R12/SO PMOS off 3 Changeover to setting by system oscillator frequency 2-0 Input clock selection (timer C) 3 Auto-reload function selection TMC $00D W TCCL/TCRL $00E R/W 3-0 Timer counter/timer load register (timer C), lower 4 bits TCCU/TCRU $00F R/W 3-0 Timer counter/timer load register (timer C), upper 4 bits IMR $010 W 1, 0 INT1 detection edge selection 3, 2 Zero-crossing detection edge selection 1, 0 D8/ZCD/EVENT pin mode selection 3, 2 Do not use 1, 0 Buzzer frequency selection 2 R13/ BUZZ pin mode selection 3 Pull-up MOS transistor on/off selection 0 LCD display selection 1 LCD power switch on/off selection 2 LCD display selection during watch mode 3 Do not use 1, 0 LCD duty cycle selection 3, 2 LCD input clock selection PMRB PMRC LCR LMR $011 $012 $013 $014 W W W W 67 HD404328 Series Name Address R/W Bit Description LOR $015 0 R2/SEG1-SEG4 pin mode selection 1 R3/SEG5-SEG8 pin mode selection 2 R4/SEG9-SEG12 pin mode selection 3 R5/SEG13-SEG16 pin mode selection 0 Conversion timing selection (A/D) 1 Do not use 3, 2 Analog input selection (A/D) AMR $016 W W ADRL $017 R 3-0 A/D data register, lower 4 bits ADRU $018 R 3-0 A/D data register, upper 4 bits DCR0 $030 W 3-0 Data control register for port R0 DCR1 $031 W 3-0 Data control register for port R1 DCR2 $032 W 3-0 Data control register for port R2 DCR3 $033 W 3-0 Data control register for port R3 DCR4 $034 W 3-0 Data control register for port R4 DCR5 $035 W 3-0 Data control register for port R5 DCRB $03B W 3-0 Data control register for port D 0-D3 DCRC $03C W 3-0 Data control register for port D 4-D7 DCRD $03D W 0 Data control register for port D 8 3-1 Do not use 68 HD404328 Series PROM Mode Description Programming the Built-In ROM The MCU's built-in ROM is programmed in PROM mode in which the pins are arranged as shown in figure 42. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 43. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 64-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 35. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable use of a general-purpose PROM programmer. This circuit splits each instruction into a lower five bits and an upper five bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. VCC M0 M1 VCC VCC GND TEST VCC RESET GND GND A7 A8 A0 A 10 A 11 A 12 A 13 A 14 A9 VPP A5 A6 O4 O3 O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 HD4074329S HD4074329US HD4074329C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC M 0 M 1VCC VCC VCC GND TEST VCC RESET GND OE CE A4 A3 A2 A1 O7 O6 O5 O4 O3 O2 O1 O0 VCC O0 O1 GND A7 A8 A0 A 10 A 11 A 12 A 13 A 14 VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 2 50 3 49 4 48 5 47 6 46 7 45 8 44 9 43 HD4074329FS 10 42 HD4074329UFS 11 41 12 40 13 39 14 38 15 37 16 36 17 35 18 34 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 OE CE A4 A3 A2 A1 O7 O6 O5 O4 O3 A 9VPP A 5 A 6 O 4 O 3 O 2 O 1 O 0VCCO 0 O 1 O 2 Note: Externally connect pins of the same name. This is not necessary if one of the sockets listed in table 35 is used. Figure 42 Pin Arrangement in PROM Mode 69 HD404328 Series VCC VCC VCC RESET TEST M0 M1 O0 -O7 Data O0 -O7 A 0-A14 Address A 0-A14 VPP VPP OE OE CE CE GND Figure 43 PROM Mode Connections Table 35 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Model Name Manufacturer DATA I/O Corp. 29B DP-64S DC-64S HS432ESS01H Hitachi FP-64B HS432ESF01H Hitachi DP-64S DC-64S HS432ESS01H Hitachi FP-64B HS432ESF01H Hitachi AVAL Data Corp. 70 PKW-1000 HD404328 Series Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed, but the ceramic windowpackage version can be reprogrammed after being exposed to ultraviolet light. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed in the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification: The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as shown in table 36. For details of PROM programming, refer to the Notes on PROM Programming section. Table 36 PROM Mode Selection Pin Mode CE OE VPP O0-O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedence Erasure (Window Package) Data in the PROM is erased by exposing the LSI to ultraviolet light of a wavelength of 2537 A for an integrated dose of at least 15 W.s/cm2. These conditions can be satisfied by placing the LSI about 2 cm to 3 cm away from an ultraviolet lamp with a rating of 12,000 W/cm2 for about 20 minutes. After erasure, all PROM bits are set to 1. For details of packages with windows, refer to the Notes on Window Packages section. 71 HD404328 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 44 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which consist of 16 digits from $040- $04F, are accessed with the LAMR and XMRA instructions. W register W1 RAM address X register W0 X 3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP 9 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing 1st word of instruction 2nd word of instruction Opcode d9 RAM address d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 0 m2 m1 m0 0 AP 9 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing Figure 44 RAM Addressing Modes 72 m3 HD404328 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 45 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 47. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-Series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 46. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R0 and R1 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R0 and R1 port output registers at the same time. The P instruction has no effect on the program counter. 73 HD404328 Series 1st word of instruction [JMPL] [BRL] [CALL] p3 Opcode 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b 7 b6 b5 b4 b3 b2 b1 b0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 Opcode 0 0 a5 0 a4 a3 a2 a1 a0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] p3 Opcode p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 45 ROM Addressing Modes 74 HD404328 Series Instruction [P] p3 Opcode p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Specification ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register B3 B2 B1 B0 A3 A2 A1 A0 If RO8 = 1 ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R0, R1 R13 R12 R11 R1 0 R0 3 R0 2 R0 1 R0 0 If RO9 = 1 Pattern Output Figure 46 P Instruction BR AAA NOP BR BR BBB 256(n - 1) + 255 AAA 256n AAA 256n + 254 BBB 256n + 255 256(n + 1) NOP Figure 47 Branching when Branch Destination is on a Page Boundary 75 HD404328 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Power voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V Pin voltage VT -0.3 to (VCC + 0.3) V Total permissible input current Io 100 mA 2 Total permissible output current -Io 50 mA 3 Maximum input current Io 4 mA 4, 5 30 mA 4, 6 7, 8 Maximum output current -Io 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the Electrical Characteristics table. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. D10 (VPP ) of the HD4074329 and HD4074329U. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from any I/O pin to ground. 5. Applies to D8, R0-R5. 6. Applies to D0-D7. 7. The maximum output current is the maximum current flowing from VCC to any I/O pin. 8. Applies to D0-D8, R0-R5. 76 HD404328 Series Electrical Characteristics DC Characteristics (HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20Cto+75C;unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH RESET, SCK, INT0, INT1, SI,EVENT 0.8VCC -- V VCC + 0.3 Notes HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V OSC1 0.9VCC -- VCC + 0.3 V VCC - 0.5 -- VCC + 0.3 V HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V Input low voltage VIL RESET, SCK, INT0, INT1,EVENT, SI VCC - 0.3 -- VCC + 0.3 V -0.3 -- 0.2VCC V HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V OSC1 -0.3 -- 0.1VCC V -0.3 -- 0.5 V HD404328, HD404328U: VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V -0.3 -- 0.3 V VOH SCK, SO, BUZZ VCC - 1.0 -- -- V -I OH = 0.5 mA Output low voltage VOL SCK, SO, BUZZ -- -- 0.4 V IOL = 0.4 mA I/O leakage current |IIL| RESET, SCK, INT0, INT1, SI, SO, OSC1, -- -- 1.0 A Vin = 0 to VCC Output high voltage 1 BUZZ 77 HD404328 Series DC Characteristics (HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) (cont) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Notes Current dissipation ICC in active mode VCC -- 3 6 mA 2, 4 Current dissipation ISBY in standby mode VCC -- 0.6 1.5 mA Current dissipation ISUB in subactive mode VCC VCC = 5.0 V, fOSC = 4 MHz VCC = 3.0 V, 3, 4 LCD on -- 50 70 A HD404328: VCC = 3.0 V, LCD on -- 40 60 A HD404328U: VCC = 3.0 V, LCD on -- 70 150 A HD4074329: VCC = 3.0 V, LCD on -- 60 140 A HD4074329U: VCC = 3.0 V, LCD on Current dissipation IWTC1 in watch mode(1) VCC Current dissipation IWTC2 in watch mode(2) VCC -- 4 15 A VCC = 3.0 V, 5 LCD off -- 15 35 A HD404328, HD4074329: 5 VCC = 3.0 V, LCD on -- 5 25 A HD404328U, HD4074329U: 5 VCC = 3.0 V, LCD on Current dissipation ISTOP in stop mode VCC Stop mode retain voltage VCC VSTOP -- 1 10 A VCC = 3.0 V, X1 = VCC 2 -- -- V No 32-kHz oscillator Notes: 1. Output buffer current is excluded. 2. ICC1 is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST, D0-D7, D9, D10 , R0-R5 at VCC D8 open 78 5 6 HD404328 Series 3. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND TEST, D0-D7, D9, D10 , R0-R5 at VCC D8 open 4. The power dissipation is in proportion to f OSC only when the MCU is operating or is in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 5. D10 is connected to VCC in the HD4074329 and HD4074329U. 6. RAM data retention. I/O Characteristics for Standard Pins (HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V D8-D10 , Note R0-R5 Input low voltage VIL D8-D10 , Output high voltage VOH D8, R0-R5 VCC - 1.0 -- -- V -I OH = 0.5 mA Output low voltage VOL D8, R0-R5 -- -- 0.4 V IOL = 0.4 mA I/O leakage current |IIL| D8, D9, -- -- 1.0 A Vin = 0 to VCC * -- -- 1.0 A HD404328, HD404328U: * -- -- 20.0 A R0-R5 R0-R5 D10 Vin = 0 to VCC HD4074329, HD4074329U: Vin = 0 to VCC Pull-up MOS current -I pu D8, R0-R5 5 25 90 A VCC = 3.0 V, Vin = 0.0 V Note: * Output buffer current is excluded. 79 HD404328 Series I/O Characteristics for High-Current Pins (HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = - 20C to +75C; HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high voltage VIH D0-D7 0.7VCC -- VCC + 0.3 V Input low voltage VIL D0-D7 -0.3 -- 0.3VCC V Output high voltage VOH D0-D7 VCC - 1.0 -- -- V -I OH = 0.5 mA Output low voltage VOL D0-D7 -- -- 0.4 V IOL = 0.4 mA -- -- 2.0 V HD404328, HD404328U: Note IOL = 15 mA, VCC = 4.5 V to 6.0 V HD4074329, HD4074329U: IOL = 15 mA, VCC = 4.5 V to 5.5 V I/O leakage current |IIL| D0-D7 -- -- 1.0 A Vin = 0 to VCC Pull-up MOS current D0-D7 5 25 90 A VCC = 3.0, Vin = 0 -I pu Note: * Output buffer current is excluded. 80 * HD404328 Series LCD Circuit Characteristics (HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Segment driver voltage drop VDS SEG1-SEG24 -- -- 0.6 V Id = 3.0 A 1 Common driver voltage drop VDC COM1-COM4 -- -- 0.3 V Id = 3.0 A 1 100 300 900 k HD404328, HD4074329: LCD power supply RW division resistor Note Between V 1 and GND, V1 = VCC LCD voltage VLCD V1 2.7 -- VCC V HD404328, HD404328U 2 2.9 -- VCC V HD4074329, HD4074329U 2 Notes: 1. VDS and VDC are the voltage drops from power supply pins V 1, V2, and V3, and GND to each segment pin and each common pin. 2. When VLCD is supplied from an external source, the following relations must be retained: V CC V1 V2 V3 GND A/D Converter Characteristics (HD404328: VCC = 2.7 V to 6.0 V, AVSS = 0.0 V, T a = -20C to +75C; HD404328U: VCC = 2.7 V to 6.0 V, AV SS = 0.0 V, T a = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, AVSS = 0.0 V, T a = -20C to +75C; unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Analog power voltage AV CC AV CC VCC - 0.3 VCC VCC + 0.3 V Analog input voltage AV in AN0-AN 3 AV SS -- AV CC V Current between AV CC and AVSS IAD -- -- 50 -- A Analog input capacitance CAin AN0-AN 3 -- 30 -- pF Resolution 8 8 8 Bit Number of inputs 0 -- 4 Cha nnel Absolute accuracy -- -- 2.0 LSB Conversion period 34 -- 67 tcyc 1 -- -- M f = 1 MHz, Analog input impedance AN0-AN 3 Note VCC = AVCC = 5.0 V * Vin = 0.0 V Note: * Operating frequency of A/D conversion fOSC is from 1 (MHz) to 4.5 (MHz). 81 HD404328 Series Zero-Crossing Detection Circuit Characteristics Low Sensitivity Mode (HD404328, HD404328U: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = 0C to +70C; HD4074329, HD4074329U: VCC = 3.0 V to 5.5 V, GND = 0.0 V, Ta = 0C to +70C; unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Note Zero-crossing detection input voltage VZC ZCD 2.0 -- VP-P AC connection, Zero-crossing detection accuracy VAZC Zero-crossing detection input frequency fZC 3.0 C = 0.1 F -- -- 750 mV fZC = 50/60 Hz (sine wave), fOSC = 4 MHz 45 -- 250 Refer to figure 48 Hz High Sensitivity Mode (VCC = 5.0 V, GND = 0.0 V, Ta = 0C to 70C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Conditions Zero-crossing detection input voltage VZC ZCD 2.0 -- VP-P AC connection, 3.0 C = 0.1 F Zero-crossing VAZC detection accuracy -- -- 100 mV fZC = 50/60 Hz (sine wave), fOSC = 4 MHz, VCC = 5.0 V Zero-crossing detection input frequency 82 Note fZC 45 -- 1000 Hz Refer to figure 48 HD404328 Series 1/f ZC VAZC AC input VAZC VZC(P-P) Internal CPU signal Note: The internal CPU signal is shown lagging behind the original waveform in the figure, but this is not fixed--it could actually lead. Figure 48 Zero-Crossing Detection 83 HD404328 Series AC Characteristics (HD404328: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: VCC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) Item Symbol Clock oscillation frequency fOSC Pin(s) Min Typ Max Unit Test Conditions Note OSC1, OSC2 0.4 4.0 4.5 MHz 1/8 division, 1 0.4 4.0 4.5 MHz 1/8 division used, 32 kHz used 32 kHz not used X1, X2 Instruction cycle time tcyc Oscillation stabilization time(crystal) tRC OSC1, OSC2 -- 32.768 -- kHz -- 2 -- s fOSC = 4 MHz -- -- 40 ms HD404328, HD404328U: 2 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V Oscillation stabilization time(ceramic) tRC OSC1, OSC2 -- -- 60 ms -- -- 20 ms 2 HD404328, HD404328U: 2 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: VCC = 3.5 V to 5.5 V -- -- 60 ms 2 Oscillation stabilization time tRC X1, X2 -- -- 3 s 3 External clock high width tCPH OSC1 90 -- -- ns 4 External clock low width tCPL OSC1 90 -- -- ns 4 External clock rise time tCPr OSC1 -- -- 20 ns 4 External clock fall time tCPf OSC1 -- -- 20 ns 4 INT0, INT1, EVENT high width tIH INT0, INT1, 2 -- -- tcyc / tsubcyc 5 INT0, INT1, EVENT width tIL 2 -- -- tcyc / tsubcyc 5 EVENT INT0, INT1, EVENT 84 HD404328 Series Item Symbol Pin(s) Min Typ Max Unit Test Conditions Note RESET high width tRSTH RESET 2 -- -- fcyc 6 RESET fall time tRSTf RESET -- -- 20 ms 6 Input capacitance Cin All pins except D10 , AN 0-AN 3 -- -- 30 pF f = 1 MHz, Vin = 0.0 V D10 -- -- 30 pF HD404328, HD404328U: f = 1 MHz, Vin = 0.0 V -- -- 180 pF HD4074329, HD4074329U: f = 1 MHz, Vin = 0.0 V Notes: 1. If fOSC = 0.4 MHz to 1.0 MHz, bit 3 of the miscellaneous register (MIS: $00C) must be set to 1; if fOSC = 1.6 MHz to 4.5 MHz, bit 3 must be set to 0. Do not use fOSC = 1.0 MHz to1.6 MHz with 32kHz oscillation. 2. The oscillation stabilization time is the time required for the oscillator to stabilize after VCC reaches 2.7 V (2.9 V for the HD4074329 and HD4074329U, or 3.5 V if V CC = 3.5 V to 5.5 V) at power-on or after RESET input goes high after stop mode is canceled. At power-on and when stop mode is cancelled, RESET must be input for at least tRC to ensure the oscillation stabilization time. If using a crystal oscillator or a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 3. The oscillation stabilization time is the time required for the oscillator to stabilize after VCC reaches 2.7 V (2.9 V for the HD4074329 and HD4074329U) at power-on--at least t RC must be ensured. If using a 32.768-kHz crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. Refer to figure 49. 5. Refer to figure 50. The tcyc unit applies when the MCU is in standby or active mode. The tsubcyc unit applies when the MCU is in watch or subactive mode. t subcyc = 244.14 s (32.768kHz crystal) 6. Refer to figure 51. 85 HD404328 Series Serial Interface Timing Characteristics (HD404328: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -20C to +75C; HD404328U: V CC = 2.7 V to 6.0 V, GND = 0.0 V, Ta = -40C to +85C; HD4074329, HD4074329U: VCC = 2.9 V to 5.5 V, GND = 0.0 V, Ta = -20C to +75C; unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Conditions Notes Transmit clock cycle time tScyc SCK 1.0 -- -- tcyc , tsubcyc Load shown in figure 53 1, 2 Transmit clock high width tSCKH SCK 0.3 -- -- tScyc Load shown in figure 53 1 Transmit clock low width tSCKL SCK 0.3 -- -- tScyc Load shown in figure 53 1 Transmit clock rise time tSCKr SCK -- -- 100 ns HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Transmit clock fall time tSCKf SCK -- -- 200 ns Load shown in figure 53 -- -- 100 ns HD404328, HD404328U: 1 1 VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Serial output data delay time tDSO SO -- -- 200 ns Load shown in figure 53 1 -- -- 300 ns HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 -- -- 500 Notes: 1. Refer to figure 52. 2. The tsubcyc unit applies when subactive mode is operating. 86 ns Load shown in figure 53 1 HD404328 Series Item Symbol Pin Min Typ Max Unit Test Conditions Serial input data setup time tSSI SI 200 -- -- ns HD404328, HD404328U: * Note VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: * VCC = 3.5 V to 5.5 V Serial input data hold time tHSI SI 300 -- -- ns * 150 -- -- ns HD404328, HD404328U * VCC = 3.5 V to 6.0 V HD4074329, HD4074329U * VCC = 3.5 V to 5.5 V 300 -- -- ns * Note: * Refer to figure 52. 87 HD404328 Series During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Transmit clock cycle time tScyc Transmit clock high width Test Conditions Notes SCK 1.0 -- -- tcyc , t subcyc 1, 2 tSCKH SCK 0.3 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.3 -- -- tScyc Transmit clock rise time tSCKr SCK -- -- 100 ns 1 HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Transmit clock fall time tSCKf SCK -- -- 200 ns -- -- 100 ns 1 HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Serial output data delay time tDSO SO -- -- 200 ns -- -- 300 ns 1 HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V, load shown in figure 53 HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V, load shown in figure 53 Serial input data setup time tSSI SI -- -- 500 ns Load shown in figure 53 1 200 -- -- ns HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V Serial input data hold time tHSI SI 300 -- -- ns 150 -- -- ns 1 HD404328, HD404328U: 1 VCC = 3.5 V to 6.0 V HD4074329, HD4074329U: 1 VCC = 3.5 V to 5.5 V 300 -- -- ns Notes: 1. Refer to figure 52. 2. The tsubcyc unit applies when subactive mode is operating. 88 1 HD404328 Series VCC = 3.5 V to 6.0 V (HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) 1/fcp VCC - 0.5 V OSC 1 t CPL t CPH 0.5 V t CPr t CPf VCC = 2.7 V to 3.5 V (HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) 1/fcp VCC - 0.3 V OSC 1 t CPL t CPH 0.3 V t CPr t CPf Figure 49 Oscillator Timing VCC = 3.5 V to 6.0 V (HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) INT0 , INT1 , EVENT 0.8VCC t IH 0.2VCC t IL VCC = 2.7 V to 3.5 V (HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) INT0 , INT1 , EVENT 0.9VCC 0.1VCC t IH t IL Figure 50 Interrupt Timing 89 HD404328 Series VCC = 3.5 V to 6.0 V (HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) RESET 0.8VCC t RSTH 0.2VCC t RSTf VCC = 2.7 V to 3.5 V (HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) RESET 0.9VCC 0.1VCC t RSTH t RSTf Figure 51 Reset Timing 90 HD404328 Series VCC = 3.5 V to 6.0 V (HD404328, HD404328U) VCC = 3.5 V to 5.5 V (HD4074329, HD4074329U) t Scyc t SCKf SCK VCC - 2.0 V (0.8VCC ) * 0.8 V (0.2VCC ) * t SCKr t SCKHD t SCKL t SCKH t DSO VCC - 2.0 V 0.8 V SO t SSI t HSI 0.8VCC 0.2VCC SI Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output, 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input, and t DSO , tSSI , and t HSI are the timings used with transmit clock input voltages. VCC = 2.7 V to 3.5 V (HD404328, HD404328U) VCC = 2.9 V to 3.5 V (HD4074329, HD4074329U) t Scyc t SCKf SCK VCC - 0.5 V (0.9VCC ) * 0.4 V (0.1VCC ) * t SCKr t SCKHD t SCKL t SCKH t DSO SO VCC - 0.5 V 0.4 V t SSI t HSI 0.9VCC 0.1VCC SI Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input, and t DSO , tSSI , and t HSI are the timings used with transmit clock input voltages. Figure 52 Serial Interface Timing VCC Test point C 30 pF RL = 2.6 k R 12 k 1S2074 H or equivalent Figure 53 Timing Load Circuit 91 HD404328 Series HD404328/HD404328U Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer 1. ROM size Department HD404324 4-kword With internal ROM code name HD404326 6-kword LCD voltage HD404328 8-kword division registers LSI number (to be filled in by Hitachi) HD404324U 4-kword Without internal HD404326U 6-kword LCD voltage HD404328U 8-kword division registers 2. Optional Function (1) * With 32-kHz CPU operation * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. Optional Function (2) With zero-crossing detection function Without zero-crossing detection function 4. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 6. Stop Mode 7. Packages Used DP-64S Not used FP-64A FP-64B 92 HD404339 Series Rev. 5.0 March 1997 Description The HD404339 Series is 4-bit HMCS400-Series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter, input capture timer, and a 32kHz oscillator circuit for clock use all built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404339 Series includes six chips: the HD404339 with 16-kword ROM; the HD4043312 with 12kword ROM; the HD404338 with 8-kword ROM; the HD404336 with 6-kword ROM; the HD404334 with 4-kword ROM; the HD4074339 with 16-kword PROM. The HD4074339 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features * 54 I/O pins One input-only pin 53 input/output pins: 30 pins are high-voltage pins (40 V, max.) * On-chip A/D converter (8-bit x 12-channel) * Three timers One event counter input One timer output One input capture timer * 8-bit clock-synchronous serial interface (1 channel) * Alarm output * Built-in oscillators Ceramic or crystal oscillator External clock drive is also possible Subclock: 32.768-kHz crystal oscillator HD404339 Series * Seven interrupt sources Two by external sources Three by timers One each by the A/D converter and serial interface * Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode * Instruction cycle time: 1 s (fOSC = 4 MHz, 1/4 division ratio) 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selected Ordering Information Type Product Name Model Name ROM (words) RAM (digit) Package Mask ROM HD404334 HD404334S 4,096 512 DP-64S HD404334FS HD404336 HD404336S FP-64B 6,144 HD404336FS HD404338 HD404338S FP-64B 8,912 HD404338FS HD4043312 HD4043312S HD404339S 12,288 HD4074339 HD4074339S DP-64S FP-64B 16,384 HD404339FS ZTAT DP-64S FP-64B HD4043312FS HD404339 DP-64S DP-64S FP-64B 16,384 HD4074339FS DP64S FP-64B Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacture Model Name DATA I/O corp 121 B DP-64S Hitachi HS4339ESS01H FP-64B AVAL corp PKW-1000 DP-64S FP-64B 2 HS4339ESF01H Hitachi HS4339ESS01H HS4339ESF01H HD404339 Series 64 63 62 61 60 59 58 57 56 55 54 53 52 R71 R70 R63 R62 R61 R60 RA1/Vdisp R23 R22 R21 R20 R13 R12 Pin Arrangement FP-64B 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 R60 R61 R62 R63 R70 R71 R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AV CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DP-64S 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA1/Vdisp R23 R22 R21 R20 R13 R12 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 VCC 3 HD404339 Series Pin Description Pin Number Item Symbol DP-64S FP-64B I/O Power supply VCC 33 27 Applies power voltage GND 16 10 Connected to ground Vdisp 64 58 Used as a high-voltage output power supply pin when selected by the mask option (shared with RA1) Function Test TEST 12 6 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 13 7 I Resets the MCU Oscillator OSC1 14 8 I Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC1 to an external oscillator circuit. OSC2 15 9 O X1 17 11 I X2 18 12 O D0-D13 34-47 28-41 I/O Input/output pins addressed individually by bits; D0-D13 are all high-voltage I/O pins. Each pin can be individually configured as selected by the mask option. RA1 64 58 I One-bit high-voltage input port pin 1-5, I/O Four-bit input/output pins consisting of standard voltage pins 42-57 I/O Four-bit input/output pins consisting of high voltage pins Port R00-R03, 1-11, R3 -R7 20-31 0 2 14-25, Used with a 32.768-kHz crystal oscillator for clock purposes 59-64 R10-R23, 48-63 R80-R93 Interrupt INT0, INT1 34, 35 28, 29 I Input pins for external interrupts Stop clear STOPC 38 32 I Input pin for transition from stop mode to active mode 8 2 I/O Serial interface clock input/output pin SI 9 3 I Serial interface receive data input pin SO 10 4 O Serial interface transmit data output pin TOC 11 5 O Timer output pin EVNB 36 30 I Event count input pin BUZZ 37 31 O Square waveform output pin Serial interface SCK Timer Alarm 4 HD404339 Series Pin Number Item Symbol DP-64S FP-64B A/D converter AVCC 32 26 Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AVSS 19 13 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN0-AN11 20-31 14-25 I/O I Function Analog input pins for the A/D converter 5 HD404339 Series Pin Description in PROM Mode The HD4074339 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-64S FP-64B Pin I/O Pin I/O 1 59 R60 I/O O4 I/O 2 60 R61 I/O O3 I/O 3 61 R62 I/O O2 I/O 4 62 R63 I/O O1 I/O 5 63 R70 I/O O0 I/O 6 64 R71 I/O 7 1 R72 I/O 8 2 R00/SCK I/O VCC 9 3 R01/SI I/O VCC 10 4 R02/SO I/O 11 5 R03/TOC I/O 12 6 TEST I VPP 13 7 RESET I RESET 14 8 OSC1 I VCC 15 9 OSC2 O 16 10 GND -- GND 17 11 X1 I GND 18 12 X2 O 19 13 AVSS -- GND 20 14 R30/AN0 I/O O0 I/O 21 15 R31/AN1 I/O O1 I/O 22 16 R32/AN2 I/O O2 I/O 23 17 R33/AN3 I/O O3 I/O 24 18 R40/AN4 I/O O4 I/O 25 19 R41/AN5 I/O O5 I/O 26 20 R42/AN6 I/O O6 I/O 27 21 R43/AN7 I/O O7 I/O 28 22 R50/AN8 I/O 29 23 R51/AN9 I/O 30 24 R52/AN10 I/O 6 I HD404339 Series Pin Number MCU Mode PROM Mode DP-64S FP-64B Pin I/O Pin I/O 31 25 R53/AN11 I/O 32 26 AVCC -- VCC 33 27 VCC -- VCC 34 28 D0 /INT0 I/O M0 I 35 29 D1 /INT1 I/O M1 I 36 30 D2 /EVNB I/O A1 I 37 31 D3 /BUZZ I/O A2 I 38 32 D4 /STOPC I/O 39 33 D5 I/O A3 I 40 34 D6 I/O A4 I 41 35 D7 I/O A9 I 42 36 D8 I/O VCC 43 37 D9 I/O 44 38 D10 I/O 45 39 D11 I/O 46 40 D12 I/O 47 41 D13 I/O 48 42 R80 I/O CE 49 43 R81 I/O OE 50 44 R82 I/O A13 I 51 45 R83 I/O A14 I 52 46 R90 I/O 53 47 R91 I/O 54 48 R92 I/O 55 49 R93 I/O 56 50 R10 I/O A5 I 57 51 R11 I/O A6 I 58 52 R12 I/O A7 I 59 53 R13 I/O A8 I 60 54 R20 I/O A0 I 61 55 R21 I/O A10 I 62 56 R22 I/O A11 I 63 57 R23 I/O A12 I 64 58 RA1/Vdisp I Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O4 consist of two pins each. Tie each pair together before using them. 7 HD404339 Series GND VCC X2 X1 OSC2 OSC1 STOPC TEST RESET Block Diagram D0 INT0 D1 System control Interrupt control D2 INT1 D3 RAM (512 x 4 bits) D4 D port D5 W (4 bits) Timer A D6 D7 D8 D9 X (4 bits) D10 D11 D12 D13 R0 port SPX (4 bits) R1 port SCK ALU AV SS R2 port SPY (4 bits) R3 port Serial interface Internal data bus SI SO Internal data bus Timer C TOC Internal address bus Y (4 bits) R4 port Timer B EVNB CA (1 bit) R6 port A (4 bits) AVCC B (4 bits) BUZZ Buzzer SP (10 bits) Data bus High voltage pin Directional signal line 8 Instruction decoder PC (14 bits) ROM (16,384 x 10 bits) (6,144 x 10 bits) (12,288 x 10 bits) (4,096 x 10 bits) (8,192 x 10 bits) R7 port ST (1 bit) R8 port A/D converter R9 port * * * RA port * * * AN11 R5 port AN 0 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R80 R81 R82 R83 R90 R91 R92 R93 RA1 HD404339 Series Memory Map ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404334), $0000-$17FF (HD404336), $0000-$1FFF (HD404338), $0000-$2FFF (HD4043312), $0000-$3FFF (HD404339, HD4074339)): The entire ROM area can be used for program coding. $0000 $000F Vector address (16 words) $0010 Zero-page subroutine (64 words) $003F $0040 $0FFF $1000 $17FF $1800 $1FFF Pattern (4,096 words) HD404334 Program (4,096 words) HD404336 Program (6,144 words) HD404338 Program (8,192 words) $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F $2000 HD4043312 Program (12,288 words) $2FFF $3000 HD404339, HD4074339 Program (16,384 words) $3FFF Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map 9 HD404339 Series RAM Memory Map Initial values after reset $000 RAM-mapped registers $040 Memory registers (MR) $050 Data (432 digits) $200 Not used $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000 Undefined Undefined 0000 0000 *2/0000 Undefined 0000 0000 *2/0000 Undefined Not used $3C0 Stack (64 digits) $3FF (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W 0000 0000 1000 0000 -000 $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) $027 System clock selection register 1 (SSR1) System clock selection register 2 (SSR2) $028 W W W W W 0000 00-0 -000 000--00 (DCR0) W 0000 (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) W W W W W 0000 0000 0000 0000 -000 $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 Not used Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $030 Port R0 DCR 2. Undefined. Not used R: Read only W: Write only R/W: Read/write $033 $034 $035 $036 $037 Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Not used $03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map and Initial Values 10 *1 HD404339 Series Table 1 Initial Values of Flags after MCU Reset Item Initial Value Interrupt flags/mask Bit registers Interrupt enable flag (IE) 0 Interrupt request flag (IF) 0 Interrupt mask (IM) 1 Watchdog timer on flag (WDON) 0 A/D start flag (ADSF) 0 Input capture status flag (ICSF) 0 Input capture error flag (ICEF) 0 IAD off flag (IAOF) 0 RAM enable flag (RAME) 0 Low speed on flag (LSON) 0 Direct transfer on flag (DTON) 0 RAM Address Bit 3 Bit 2 Bit 1 Bit 0 $0000 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $0001 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $0002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $0003 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) Interrupt control bits area Bit 2 Bit 1 Bit 0 $020 DTON (Direct transfer on flag) Bit 3 ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) IAOF (IAD off flag) ICEF (Input capture error flag) ICSF (Input capture status flag) IF: Interrupt request flag $022 IM: Interrupt mask IE: Interrupt $023 enable flag SP: Stack pointer Not used Register flag area Figure 3 Interrupt Control Bits and Register Flag Areas Configuration 11 HD404339 Series SEM/SEMD IE REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed RSP Not executed Allowed Inhibited WDON Allowed Not executed Inhibited ADSF Allowed Inhibited Allowed DTON Not executed in active mode Allowed Allowed IM LSON IAOF IF ICSF ICEF RAME Used in subactive mode Not used Not executed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instruction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1 $3C0 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC 13 PC 12 PC 11 $3FD PC 10 PC 9 PC 8 PC 7 $3FE CA PC 6 PC 5 PC 4 $3FF PC 3 PC2 PC 1 PC0 PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position 12 HD404339 Series Registers and Flags 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W 0 (B) 1 W register Initial value: Undefined, R/W 0 (W) 3 X register Initial value: Undefined, R/W Y register Initial value: Undefined, R/W 0 (X) 3 0 (Y) 3 SPX register Initial value: Undefined, R/W 0 (SPX) 3 SPY register Initial value: Undefined, R/W 0 (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Initial value: 1, no R/W Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 6 Registers and Flags 13 HD404339 Series Addressing Modes RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. 0 3 1 0 3 W 9 3 Y X 7 0 3 Instruction 0 9 0 RAM address 0 0 0 1 0 0 Register Indirect Addressing Memory Register Addressing Instruction 1st instruction word 0 9 2nd instruction word 0 Opcode 9 RAM address Direct Addressing Figure 7 RAM Addressing Modes 14 Opcode RAM address 9 0 0 HD404339 Series ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000-$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction. 2nd instruction word 1st instruction word 9 3 Opcode 09 0 Opcode 9 5 Operand 13 0 Operand 0 13 Program counter 0 Program counter 0 0 0 0 0 0 0 0 Direct Addressing Zero-Page Addressing Operand Opcode 9 7 0 Operand 13 9 3 Opcode 0 Program counter * * * * * * 0 7 0 B 13 A 0 Program counter 0 0 Current Page Addressing Table Data Addressing Figure 8 ROM Addressing Modes 15 HD404339 Series Instruction Set Table 2 Instruction Set Classification Instruction Type Function Number of Instructions Immediate Transferring constants to the accumulator, B register, and RAM. 4 Register-to-register Transferring contents of the B, Y, SPX, SPY, or memory registers to 8 the accumulator. RAM addressing Available when accessing RAM in register indirect addressing mode. 13 RAM register Transferring data between the accumulator and memory. 10 Arithmetic Performing arithmetic operations with the contents of the accumulator, B register, or memory. 25 Compare Comparing contents of the accumulator or memory with a constant. 12 RAM bit manipulation Bit set, bit reset, and bit test. 6 ROM addressing Branching and jump instructions based on the status condition. 8 Input/output Controlling the input/output of the R and D ports; ROM data reference with the P instruction. 11 Control Controlling the serial communication interface and low-power dissipation modes. 4 Total: 101 instructions 16 HD404339 Series Interrupts $000,0 IE Interrupt request (RESET, STOPC) $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0004 3 $0006 4 $0008 5 $000A 6 $000C 7 $000E $001,2 Timer A interrupt IFTA $001,3 IMTA $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Figure 9 Interrupt Control Circuit 17 HD404339 Series Instruction cycles 1 2 3 4 5 6 Instruction execution* Stacking Interrupt acceptance IE reset Vector address generation Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction. Figure 10 Interrupt Processing Sequence 18 HD404339 Series Operating Modes The MCU has five operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3 Operations in Each Operating Mode Function Active Mode Subactive Mode Standby Mode Watch Mode Stop Mode System oscillator OP Stopped OP Stopped Stopped Subsystem oscillator OP OP OP OP * OP CPU OP OP Retained Retained Reset RAM OP OP Retained Retained Retained Timer A OP OP OP OP Reset Timers B, C OP OP OP Stopped Reset Serial OP OP OP Stopped Reset A/D OP Stopped OP Stopped Reset I/O OP OP Retained Retained Reset Notes: OP implies in operation. * Oscillation can be switched on or off with bit 3 of system clock selection register 1 (SSR1: $027). 19 HD404339 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RESET 1 RAME = 1 RESET 2 STOPC STOPC Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: o CPU: o CLK: o PER: fOSC: fX: o CPU: o CLK: o PER: SBY instruction Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc STOP instruction STOP instruction (TMA3 = 0, SSR13 = 1) fOSC: fX: o CPU: o CLK: o PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fW fcyc SBY instruction Interrupt (TMA3 = 1) fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fW fcyc STOP instruction INT0, timer A (TMA3 = 1, LSON = 0) fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop *2 fOSC: fX: Main oscillation frequency Subsystem oscillation frequency for time base fcyc: fOSC/4, fOSC/8, fOSC/16, or fOSC/32 (software selectable) fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU: System clock o CLK: Clock for timer A o PER: Clock for other peripheral functions (except timer A) LSON: Low speed on flag DTON: Direct transfer on flag *1 STOP instruction Subactive mode fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate fSUB fW fSUB *3 INT0, timer A fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop Notes: 1. STOP/SBY (DTON = 1, LSON = 0) 2. STOP/SBY (DTON = 0, LSON = 0) 3. STOP/SBY (DTON = Don't care, LSON = 1) Figure 11 MCU Status Transitions 20 (TMA3 = 1, LSON = 1) , , HD404339 Series In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least tRC when clearing stop mode, execute the cancellation according to the timing chart in figure 12. In watch and subactive modes, a timer A or INT0 interrupt can be accepted during the interrupt frame period T (see figure 13). Note: In watch and subactive modes, an interrupt will not be properly detected if the INT0 high or low level period is shorter than the interrupt frame period T. Thus, when operating in watch and subactive modes, maintain the INT0 high or low level period longer than period T to ensure interrupt detection. Stop mode Oscillator Internal clock RESET or STOPC tres tres tRC (stabilization period) STOP instruction execution Figure 12 Timing of Stop Mode Cancellation Active mode Oscillation stabilization period Watch mode Active mode Interrupt strobe INT0 Interrupt request generation (During the transition from watch mode to active mode only) T t RC T Tx T + tRC TX 2T + tRC T: Interrupt frame length t RC : Oscillation stabilization period Figure 13 Interrupt Frame 21 HD404339 Series The MCU automatically provides an oscillation stabilization period tRC when operation switches from watch mode to active mode. The interrupt frame period T and one of three values for t RC can be selected with the miscellaneous register (MIS: $00C), as listed in figure 14. Operation can switch directly from subactive mode to active mode, as illustrated in figure 15. In this case, the transition time TD obeys the following relationship. tRC < TD < T + tRC Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 24. MIS1 MIS0 0 0 T*1 tRC*1 0.24414 ms 0.12207 ms 0.24414 0 1 15.625 ms 1 0 125 ms 1 1 Not used Oscillation Circuit Conditions External clock input ms*2 7.8125 ms 62.5 ms Ceramic oscillator Crystal oscillator -- Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 14 Miscellaneous Register 22 HD404339 Series STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T t RC Interrupt frame period T: t RC : Oscillation stabilization time Figure 15 Direct Transition Timing MCU Operation Sequence: The MCU operation flow is shown in figures 16 and 17. RESET input is asynchronous, and causes an immediate transition to the reset state from any MPU operation state. The low-power mode operation sequence is shown in figure 17. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. 23 HD404339 Series Power on RESET = 0? No Yes MCU operation cycle RAME = 0 Yes IF = 1? MCU reset No No IM = 0 IE = 1 Yes Instruction RAME = 1 execution Reset input Yes SBY/STOP instruction IE 0 Stack (PC), (CA), (ST) No Power-down mode operation cycle (see figure 17) PC (PC)+1 Figure 16 MCU Operation Sequence (Power On) 24 PC vector address HD404339 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Stop mode Standby mode No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle Figure 17 MCU Operating Sequence (Low-Power Mode Operation) 25 HD404339 Series Oscillator Circuit Figure 18 shows a block diagram of the clock generation circuit. The system clock frequency of the oscillator connected to OSC1 and OSC2 can be selected by system clock selection registers 1 and 2 (SSR1, 2: $027, $028) as shown in figures 20 and 21. The system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. The subsystem clock division ratio can be set by software to be 1/4 or 1/8. LSON OSC2 OSC1 System fOSC 1/4, 1/8, fcyc 1/16, or oscillator tcyc 1/32 division circuit *1 fX X1 Subsystem oscillator Timing generator circuit o CPU CPU with ROM, RAM, registers, flags, and I/O o PER Peripheral function interrupt System clock selection fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit *2 circuit TMA3 X2 1/8 division circuit fW tWcyc Timing generator circuit Time-base clock oCLK selection Time-base interrupt Notes: 1. The system clock division ratio can be selected by setting bit 1 or 0 of the system clock select register 2 (SSR2: $028). 2. The system clock division ratio can be selected by setting bit 2 of the system clock select register 1 (SSR1: $027). Figure 18 Clock Generation Circuit 26 HD404339 Series GND RESET OSC1 OSC2 GND X1 X2 AVSS Figure 19 Typical Layout of Crystal and Ceramic Oscillators 27 HD404339 Series Table 4 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator (OSC1, OSC2) Ceramic oscillator: CSA4.00MG C1 (Murata) OSC1 Ceramic Rf = 1 M 20% Rf C1 = C2 = 30 pF 20% OSC2 C2 GND Crystal oscillator (OSC1, OSC2) Rf = 1 M 20% C1 C1 = C2 = 10 to 22 pF 20% OSC1 Crystal Crystal: Equivalent to circuit shown below C0 = 7 pF max. Rf OSC2 RS = 100 max. C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Crystal: 32.768 kHz: MX38T (Nippon Denpa) X1 C1 = C2 = 20 pF 20% Crystal RS = 14 k X2 C0 = 1.5 pF C2 GND L CS RS X1 X2 C0 Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, X1, X2 and elements should be as short as possible, and must not cross other wiring (see figure 19). 3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open. 28 HD404339 Series System clock selection register 1 (SSR1: $027) Bit 3 2 1 0 Initial value 0 0 0 -- W W W -- Read/Write SSR13*1 SSR12 Bit name SSR11 Not used SSR11 System Clock Selection*2 0 0.4 to 1.0 MHz 1 1.6 to 4.5 MHz SSR12 32-kHz Oscillation Division Ratio Selection 0 fSUB = fX/8 1 fSUB = fX/4 SSR13 32-kHz Oscillation Stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode Notes: *1 SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode. *2 When the subsystem oscillator (32.768 kHz crystal oscillator) is used, set 0.4 MHz fOSC 1.0MHz or 1.6 MHz fOSC 4.5 MHz. Figure 20 System Clock Selection Register 1 (SSR1) System clock selection register 2 (SSR2: $028) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used SSR21 SSR20 SSR21 SSR20 0 0 1/4 division 0 1 1/8 division 1 0 1/16 division 1 1 1/32 division Figure 21 System Clock Division Ratio System Clock Selection Register 2 (SSR2) 29 HD404339 Series I/O Ports The MCU has 53 input/output pins (D0-D13, R00-R9 3) and one input-only pin (RA1). * The 30 pins consisting of ports D0-D13, R1, R2, R8, and R9 are all high-voltage I/O pins. RA1 is a highvoltage input-only pin. The high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. * All standard voltage output pins are CMOS output pins. However, the R0 2/SO pin can be programmed for NMOS open-drain output. * In stop mode, input/output pins go to the high-impedance state. * All standard voltage input/output pins have pull-up MOS built in, which can be individually turned on or off by software (Table 5). Pull-up MOS on/off settings can be made independently of settings as on-chip supporting module pins. Table 5 Control of Standard I/O Pins by Program MIS3 (bit 3 of MIS) 0 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS Note: -- indicates off. 30 1 1 0 1 HD404339 Series Data control register (DCR0: $030, DCR3 to DCR7: $033 to $037) DCR0, DCR3 to DCR7 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name Bits 0 to 3 CMOS Buffer Control DCR03, DCR02, DCR01, DCR00, DCR33 DCR32 DCR31 DCR30 to to to to DCR63 DCR72 DCR71 DCR70 0 CMOS buffer off (high impedance) 1 CMOS buffer on Correspondence between ports and DCR bits Register Bit 3 Bit 2 Bit 1 Bit 0 DCR0 R03 R02 R01 R00 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR5 R53 R52 R51 R50 DCR6 R63 R62 R61 R60 DCR7 Not used R72 R71 R70 Figure 22 Data Control Register (DCR) 31 HD404339 Series Table 6 Circuit Configurations of Standard I/O Pins I/O Pin Type Circuit Input/output pins Pins VCC VCC Pull-up control signal Buffer control signal HLT R00, R01, R03, MIS3 R30-R33, DCR Output data R40-R43, R50-R53, PDR R60-R63, R70-R72 Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R02 MIS3 DCR MIS2 PDR Input data Input control signal Peripheral function pins Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC VCC SO MIS3 MIS2 SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 TOC TOC HD404339 Series I/O Pin Type Circuit Pins VCC Peripheral function Input/ pins pins SI HLT MIS3 PDR SI Input data VCC AN0-AN11 HLT MIS3 PDR A/D input Input control Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active, standby, watch, and subactive modes. Table 7 Circuit Configurations for High-Voltage Input/Output Pins I/O Pin Type Input/output pins With Pull-Down Resistance VCC Without Pull-Down Resistance VCC HLT Output data Pull-down resistance HLT Output data Input data Input control signal Vdisp Pins D0-D13 , R10-R13, R20-R23, R80-R83, R90-R93 Input data Input control signal Input data Input pins Input control signal Peripheral function pins Output pins VCC HLT Pull-down resistance Output data VCC RA1 BUZZ HLT Output data Vdisp Input data Input pins Pull-down resistance Vdisp Input data INT0, INT1, EVNB, STOPC Note: HLT goes high in active, standby, watch, and subactive modes. 33 HD404339 Series Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 23 Port Mode Register A (PMRA) Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 24 Port Mode Register B (PMRB) 34 HD404339 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W MIS3 MIS2 MIS1 MIS0 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 5) MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 CMOS on 1 CMOS off MIS1 MIS0 tRC selection. Refer to figure 14 in the operation modes section. Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Figure 25 Miscellaneous Register 35 HD404339 Series Prescaler The MCU has two built-in prescalers, S and W (PSS, PSW). They divide the system clock and subsystem clock, and output these divided clocks to the peripheral function modules, as shown in figure 26. Subsystem clock fX/8 Prescaler W Timer A Timer B fX/4 or fX/8 Timer C System clock Clock selector Prescaler S Figure 26 Prescaler Output Supply 36 Serial HD404339 Series Timers The MCU has three built-in timers A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that can also be used as a clock time-base with a 32.768-kHz subsystem oscillator. Timer A has the following features: * One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008) * In time-base mode, one of five internal clocks can be selected from prescaler W according to the setting of timer mode register A * An interrupt request can be generated when timer counter A (TCA) overflows * Input clock frequency must not be modified during timer A operation Table 7 Timer Functions Functions Clock source Timer functions Timer output Timer A Timer B Timer C Prescaler S Available Available Available Prescaler W Available -- -- External event -- Available -- Free-running Available Available Available Time base Available -- -- Event counter -- Available -- Reload -- Available Available Watchdog -- -- Available Input capture -- Available -- PWM -- -- Available 37 HD404339 Series 1/4 fW 1/2 t Wcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) /2 /8 / 16 / 32 32.768-kHz oscillator 1/2 t Wcyc Clock Timer counter A (TCA) Overflow System clock oPER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 27 Timer A Block Diagram 38 Internal data bus Selector Selector HD404339 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMA3 TMA2 TMA1 TMA0 Bit name Source Input Clock TMA3 TMA2 TMA1 TMA0 Prescaler Frequency Operating Mode 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 PSS 2048 tcyc 1 PSS 1024 tcyc 0 PSS 512 tcyc 1 PSS 128 tcyc 0 PSS 32 tcyc 1 PSS 8 tcyc 0 PSS 4 tcyc 1 PSS 2 tcyc 0 PSW 32t Wcyc 1 PSW 16t Wcyc 0 PSW 8t Wcyc 1 PSW 2t Wcyc 0 PSW 1/2t Wcyc 1 Not used X PSW and TCA reset Timer A mode Time-base mode X = Don't care. Notes: 1. t Wcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 28 Timer Mode Register A (TMA) 39 HD404339 Series Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows. * By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter * By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected. * By setting timer write register BL, U (TWBL, U: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation * By setting timer read register BL, U (TRBL, U: $00A, $00B), the contents of timer counter B can be read out * Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event * An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation 40 HD404339 Series Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Free-running timer control signal Timer write register B lower (TWBL) /2 /4 /8 / 32 / 128 / 512 / 2048 Edge detector oPER 2 Overflow Timer write register B upper (TWBU) Selector EVNB System clock Timer counter B (TCB) Internal data bus Clock 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control signal Timer mode register B2 (TMB2) Figure 29 Timer B Free-Running and Reload Operation Block Diagram 41 HD404339 Series Input capture status flag (ICSF) Interrupt request flag of timer B (IFTB) Input capture error flag (ICEF) Error controller Timer read register BU (TRBU) Timer read register B lower (TRBL) Read signal Edge detector Clock Timer counter B (TCB) Overflow Input capture timer control signal Selector /2 /4 /8 / 32 / 128 / 512 / 2048 3 System clock oPER 2 Timer mode register B1 (TMB1) Prescaler S (PSS) Edge detection control signal Timer mode register B2 (TMB2) Figure 30 Timer B Input Capture Operation Block Diagram 42 Internal data bus EVNB HD404339 Series Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D2/EVNB (External event input) 1 1 0 1 Figure 31 Timer Mode Register B1 (TMB1) Timer mode register B2 (TMB2: $026) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling edge detection 0 Rising edge detection 1 Rising and falling edge detection Bit name 2 Not used TMB22 1 1 TMB22 0 EVNB Edge Detection Selection Free-Running/Reload and Input Capture Selection 0 Free-Running/Reload 1 Input Capture Figure 32 Timer Mode Register B2 (TMB2) 43 HD404339 Series Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. * By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected * By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled * By setting timer write register CL, U (TWCL, U: $00E, $00F), timer counter C (TCC) can be written to * By setting timer read register CL, U (TRCL, U: $00E, $00F), the contents of timer counter C can be read out * An interrupt can be requested when timer counter C overflows * Timer counter C can be used as a watchdog timer for detecting runaway programs 44 HD404339 Series System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL) Clock Timer output control signal /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector System oPER clock Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running timer control signal Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 33 Timer C Block Diagram 45 HD404339 Series Timer mode register C (TMC: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 34 Timer Mode Register C (TMC) $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Reset Figure 35 Watchdog Timer Operation Flowchart 46 Normal operation HD404339 Series T x (N + 1) TMC3 = 0 (Free-running timer) T T x 256 TMC3 = 1 (Reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 36 PWM Output Waveform 47 HD404339 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Reload Timer write register updated to value N T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 48 T x (N + 1) T HD404339 Series Alarm Output Function BUZZ Alarm output control signal Alarm output controller System oPER clock 2 /2048 /1024 /512 /256 Selector Port mode register A (PMRA) Port mode register C (PMRC) Internal data bus The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected. Prescaler S (PSS) Figure 37 Alarm Output Function Block Diagram Table 9 Port Mode Register C PMRC Bit 3 Bit 2 System Clock Divisor 0 0 / 2048 1 / 1024 0 / 512 1 / 256 1 49 HD404339 Series Serial Interface The MCU has a one-channel serial interface built in with the following features. * One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. * During idle status, the serial output pin can be controlled to be high or low output * Transmit clock errors can be detected * An interrupt request can be generated after transfer has completed when an error occurs Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Selector /2 /8 / 32 / 128 / 512 / 2048 3 System clock oPER Prescaler S (PSS) Figure 38 Serial Interface Block Diagram 50 Serial mode register (SMR) Port mode register C (PMRC) Internal data bus Serial data register (SR) HD404339 Series Table 10 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 STS wait state (Octal counter = 000, transmit clock disabled) MCU reset SMR write (IFS 1) SMR write STS instruction Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 8 transmit clocks or STS instruction (IFS 1) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write Continuous clock output state (PMRA 0, 1 = 00) SMR write STS instruction MCU reset 8 transmit clocks or SMR write (IFS 1) Transmit clock Transmit clock Transmit clock wait state (Octal counter = 000) STS instruction (IFS 1) Transfer state (Octal counter = 000) Internal clock mode Figure 39 Serial Interface State Transitions 51 HD404339 Series Transmit clock 1 Serial output data 2 3 4 5 LSB Serial input data latch timing Figure 40 Serial Interface Timing 52 6 7 8 MSB , HD404339 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states Dummy write for state transition Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 41 Example of Serial Interface Operation Sequence 53 HD404339 Series Transmit clock errors are detected as illustrated in figure 42. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write Yes IFS = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000. Transmit clock error detection procedure Figure 42 Transmit Clock Error Detection 54 Flag reset at transfer completion. HD404339 Series Table 11 Transmit Clock Selection PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 System Clock Divisor Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 0 Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK Clock Source Output Prescaler Refer to table 11 0 Output System clock -- 1 Input External clock -- SMR1 SMR0 0 0 0 1 1 Prescaler Division Ratio SCK SMR2 0 1 1 0 0 1 1 Figure 43 Serial Mode Register (SMR) 55 HD404339 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write W W W W PMRC2 PMRC1 PMRC0 Bit name PMRC3 PMRC0 Alarm output function. Refer to table 9. Serial Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 44 Port Mode Register C (PMRC) 56 HD404339 Series A/D Converter The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The following describes the A/D converter. * A/D mode register 1 (AMR1: $019) is used to select digital or analog ports * A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports * The A/D channel register (ACR: $016) is used to select an analog input channel * A/D conversion is started by setting the A/D start flag (ADSF: $02C, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time the A/D start flag is cleared to 0. * By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode * The A/D data register is a read-only register consisting of a lower 4 bits and upper 4 bits (ADRL: $017, ADRU: $018). This register is not cleared by a reset. Data reads during A/D conversion are not guaranteed. After A/D conversion ends, the resultant 8-bit data is set in this register and held until the start of the next conversion (figures 51 to 53). 57 HD404339 Series 4 A/D mode register 1 (AMR1) A/D interrupt request flag (IFAD) 2 Selector Encoder + Comp - AVCC AVSS A/D controller Control signal for conversion time A/D start flag (ADSF) A/D mode register 2 (AMR2) A/D data register (ADRU, L) A/D channel register (ACR) IAD off flag (IAOF) D/A Operating mode signal (1 in stop, watch, and subactive modes) Figure 45 A/D Converter Block Diagram 58 Internal data bus 4 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 HD404339 Series Notes on Usage * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) * Do not write to the A/D start flag during A/D conversion * Data in the A/D data register during A/D conversion is undefined * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these modes, all current flowing through the converter's resistance ladder is cut off. * If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain pulled up. A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 46 A/D Mode Register 1 (AMR1) 59 HD404339 Series A/D mode register 2 (AMR2: $01A) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W AMR21 AMR20 Bit name 2 Not used AMR22 1 0 AMR20 AMR22 R5/AN8-AN11 Pin Selection Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4-AN7 Pin Selection 0 R5 0 R4 1 AN8-AN11 1 AN4-AN7 Figure 47 A/D Mode Register 2 (AMR2) 60 HD404339 Series A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W ACR3 ACR2 ACR1 ACR0 ACR3 ACR2 ACR1 ACR0 0 0 0 1 1 0 1 1 0 0 1 1 Analog Input Selection 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 AN8 1 AN9 0 AN10 1 AN11 Don't Don't care care Not used Figure 48 A/D Channel Register (ACR) 61 HD404339 Series A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W W R/W DTON ADSF WDON LSON Bit name LSON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of operating modes DTON WDON Refer to the description of operating modes Refer to the description of timers Figure 49 A/D Start Flag (ADSF) IAD off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name ICSF IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off Refer to the description of timers ICEF RAME Refer to the description of timers Refer to the description of operating modes Figure 50 IAD Off Flag (IAOF) 62 HD404339 Series ADRU: $018 3 2 ADRL: $017 1 0 3 2 1 0 MSB LSB bit 7 bit 0 RESULT Figure 51 A/D Data Register A/D data register (lower) (ADRL: $017) Bit 3 2 1 0 Read/write R R R R Initial value after reset 0 0 0 0 ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 52 A/D Data Register (Lower) (ADRL) A/D data register (upper) (ADRU: $018) Bit 3 2 1 0 Read/write R R R R Initial value after reset 1 0 0 0 ADRU3 ADRU2 ADRU1 ADRU0 Bit name Figure 53 A/D Data Register (Upper) (ADRU) 63 HD404339 Series Notes on Mounting Assemble all parts including the HD404339 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS . 64 HD404339 Series 1. When not using an A/D converter. VCC AVCC AN 0 0.1 F AN 1 to AN 11 AVSS GND 2. When using pins AN 0 and AN 1 but not using AN 2 to AN 11. AVCC VCC AN 0 AN 1 AN 2 to AN 11 AVSS GND 0.1 F x 3 3. When using all analog pins. VCC AVCC AN 0 AN 1 AN 2 to AN 11 GND AVSS 0.1 F x 13 Figure 54 Example of Connections (AVCC to AVSS ) Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 54. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. 65 HD404339 Series VCC VCC C1 GND C2 GND Figure 55 Example of Connections (VCC to GND) 66 HD404339 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V 1 Pin voltage VT -0.3 to VCC + 0.3 V 2 VCC - 45 to VCC + 0.3 V 3 Total permissible input current IO 70 mA 4 Total permissible output current -IO 150 mA 5 Maximum input current IO 4 mA 6, 7 20 mA 6, 8 4 mA 9, 10 30 mA 10, 11 Maximum output current -IO Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074339. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3, R4, and R5. 8. Applies to ports R0, R6, and R7. 9. Applies to ports R0 and R3 to R7. 10. The maximum output current is the maximum current flowing from VCC to each I/O pin. 11. Applies to ports D0-D13 , R1, R2, R8, and R9. 67 HD404339 Series Electrical Characteristics DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VC C, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Input high voltage VIH 0.8VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, SCK, SI -0.3 -- 0.2VCC V INT0, INT1, VCC - 40 -- STOPC, EVNB 0.2VCC V OSC1 0.5 V SCK, SO, TOC VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK, SO, TOC -- -- 0.4 V IOL = 0.4 mA I/O leakage current RESET, SCK, SI, SO,TOC, OSC1 -- -- 1 A Vin = 0 V to VCC 1 INT0, INT1, -- STOPC, EVNB -- 20 A Vin = VCC - 40 to VCC 1 VCC -- 5.0 mA VCC = 5 V, 2, 5, 6 RESET, SCK, SI, INT0, INT1, Notes STOPC, EVNB Input low voltage Output high voltage VIL VOH |IIL| Current dissipation ICC in active mode VCC Current dissipation ISUB in subactive mode VCC -- 8.0 mA -- -- 2.0 mA 2, 5, 7 VCC = 5 V, 3, 5 -- -- 100 A VCC = 5 V, 4, 6 32 kHz oscillator VCC Current dissipation ISTOP in stop mode VCC 68 -- fOSC = 4 MHz Current dissipation IWTC in watch mode VSTOP -- -- fOSC = 4 MHz Current dissipation ISBY in standby mode Stop mode retaining voltage -0.3 -- -- 320 A -- -- 20 A 4, 7 VCC = 5 V, 4 32 kHz oscillator -- -- 10 A X1 = GND, 4, 6 X2 = Open VCC -- -- 20 A 2 -- -- V 4, 7 HD404339 Series Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND R0, R30 to R72 at VCC D0-D13 , R1, R2, R8, R9, RA1 at Vdisp 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND R0, R30 to R72 at VCC D0-D13 , R1, R2, R8, R9, RA1 at Vdisp 4. This is the source current when no I/O current is flowing. Test conditions: Pins: R0, R30 to R72 at VCC D0-D13 , R1, R2, R8, R9, RA1 at GND 5. Current dissipation is in proportion to fOSC while the MCU is operating or in standby mode. The value of the dissipation current when fOSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 6. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. 7. Applies to the HD4074339. 69 HD404339 Series I/O Characteristics for Standard Pins (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = V CC - 40 V to VCC, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V VCC - 0.5 -- -- V -IOH = 0.5 mA R3-R5 -- -- 0.4 V IOL = 1.6 mA R0, -- -- 2.0 V IOL = 10 mA -- -- 1 A Vin = 0 V to VCC 1 30 150 300 A VCC = 5 V, 2 R0, R30-R72 Input low voltage VIL R0 , R30-R72 Output high voltage VOH R0, R30-R72 Output low voltage VOL R60-R72 Input leakage current |IIL| R0, R30-R72 Pull-up MOS current -IPU R0, R30-R72 Vin = 0 V 30 80 180 A Notes: 1. Output buffer current is excluded. 2. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. 3. Applies to the HD4074339. 70 3 HD404339 Series I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Input high voltage VIH D0-D13 , R1, 0.7VCC -- Unit Test Condition Note VCC + 0.3 V R2, R8, R9, RA1 Input low voltage VIL D0-D13 , R1, VCC - 40 -- 0.3VCC V VCC - 3.0 -- -- V -IOH = 15 mA VCC - 2.0 -- -- V -IOH = 10 mA VCC - 1.0 -- -- V -IOH = 4 mA -- -- VCC - 37 V Vdisp = VCC - 40 V 1 -- -- VCC - 37 V 150 k at VCC - 40 V 2 -- -- 20 A Vin = VCC - 40 V to VCC 3 200 600 1000 A Vdisp = VCC - 35 V, 1 R2, R8, R9, RA1 Output high voltage VOH D0-D13 , R1, R2, R8, R9, BUZZ Output low voltage VOL D0-D13 , R1, R2, R8, R9, BUZZ I/O leakage current |IIL| D0-D13 , R1, R2, R8, R9, RA1, BUZZ Pull-down MOS current IPD D0-D13 , R1, R2, R8, R9 Vin = VCC Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current. 71 HD404339 Series A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC - 40 V to VCC, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Analog supply voltage AVCC AVCC Analog input voltage AVin AN0-AN11 Max Unit VCC - 0.3 VCC VCC + 0.3 V AVSS -- AVCC V -- -- 200 A -- -- 30 pF Resolution 8 8 8 Bit Number of input channels 0 -- 12 Channel Absolute accuracy -- -- 2.0 LSB Conversion time 34 -- 67 tcyc 1 -- -- M Current flowing IAD between AVCC and AVSS Analog input capacitance Input impedance CAin AN0-AN11 AN0-AN11 Typ Note: 1. Connect this to VCC if the A/D converter is not used. 72 Test Condition Note 1 VCC = AVCC = 5.0 V HD404339 Series AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C) Item Symbol Pins Clock oscillation frequency fOSC Instruction cycle time Min Typ Max Unit Test Condition Note OSC1, OSC2 0.4 4 4.5 MHz System clock 1 X1, X2 -- 32.768 -- kHz tcyc 0.89 1 10 s tsubcyc -- 244.14 -- s divided by 4 1 32-kHz oscillator, 1/8 system clock division ratio -- 122.07 -- s 32-kHz oscillator, 1/4 system clock division ratio Oscillation stabilization time tRC (ceramic oscillator) OSC1, OSC2 -- -- 7.5 ms 2 Oscillation stabilization time tRC (crystal oscillator) OSC1, OSC2 -- -- 40 ms 2 X1, X2 -- -- 2 s 2 External clock high width tCPH OSC1 92 -- -- ns 3 External clock low width tCPL OSC1 92 -- -- ns 3 External clock rise time tCPr OSC1 -- -- 20 ns 3 External clock fall time tCPf OSC1 -- -- 20 ns 3 INT0, INT1, EVNB high widths tIH INT0, INT1, 2 -- -- tcyc / 4 EVNB INT0, INT1, EVNB low widths tIL INT0, INT1, tsubcyc 2 -- -- EVNB tcyc / 4 tsubcyc RESET low width tRSTL RESET 2 -- -- tcyc 5 STOPC low width tSTPL STOPC 1 -- -- tRC 6 RESET rise time tRSTr RESET -- -- 20 ms 5 STOPC rise time tSTPr STOPC -- -- 20 ms 6 Input capacitance Cin All input -- pins except TEST -- 30 pF TEST -- -- f = 1 MHz, Vin = 0 V 30 pF f = 1 MHz, 7 Vin = 0 V -- -- 180 pF 8 Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for fOSC must be applied. 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 4.5 MHz The operating range for fOSC can be set with bit 1 of system selection register 1 (SSR1: $027). 2. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: 73 HD404339 Series 3. 4. 5. 6. 7. 8. a. After VCC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. Refer to figure 56. Refer to figure 57. Refer to figure 58. Refer to figure 59. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. Applies to the HD4074339. Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC - 40 V to VCC, T a = -20 to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 61 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc Load shown in figure 61 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc Load shown in figure 61 1 Transmit clock rise time tSCKr SCK -- -- 80 ns Load shown in figure 61 1 Transmit clock fall time tSCKf SCK -- -- 80 ns Load shown in figure 61 1 Serial output data delay time tDSO SO -- -- 300 ns Load shown in figure 61 1 Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK -- -- 80 ns 1 Transmit clock fall time tSCKf SCK -- -- 80 ns 1 Serial output data delay time tDSO SO -- -- 300 ns Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 Note: 74 1. Refer to figure 60. Load shown in figure 61 1 HD404339 Series OSC1 1/fCP VCC - 0.5 V tCPL tCPH 0.5 V tCPr tCPf Figure 56 External Clock Timing INT0, INT1, EVNB 0.8VCC tIL tIH 0.2VCC Figure 57 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 58 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 59 STOPC Timing 75 HD404339 Series t Scyc t SCKf SCK VCC - 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t SCKr t SCKL t SCKH t DSO VCC - 2.0 V 0.8 V SO t SSI t HSI 0.8V CC 0.2VCC SI Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 60 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent Figure 61 Timing Load Circuit 76 HD404339 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404334 and HD404336 as an 8-kword version (HD404338), and to create the same data size for the HD4043312 as a 16-kword version (HD404339). The 8-kword and 16-kword data sizes are required to change ROM data to mask manufacturing data since the program used is for an 8-k or 16-kword version. This limitation applies when using an EPROM or a data base. ROM 4-kword version: HD404334 Address $1000-$1FFF $0000 $0000 Vector address $0000 Vector address $000F $0010 $000F $0010 Zero-page subroutine (64 words) Zero-page subroutine (64 words) Pattern & program (4,096 words) Pattern & program (6,144 words) Not used Pattern & program (12,288 words) $2FFF $3000 Not used $1FFF $1FFF Zero-page subroutine (64 words) $003F $0040 $17FF $1800 $0FFF $1000 Vector address $000F $0010 $003F $0040 $003F $0040 ROM 12-kword version: HD4043312 Address $3000-$3FFF ROM 6-kword version: HD404336 Address $1800-$1FFF Not used $3FFF Fill this area with 1s 77 HD404339 Series HD404334/HD404336/HD404338/HD4043312/HD404339 Option List Please check off the appropriate applications and enter the necessary information. 1. ROM Size Date of order HD404334 4-kword Customer HD404336 6-kword Department HD404338 8-kword Name HD4043312 12-kword ROM code name HD404339 16-kword LSI number 2. Optional Functions * With 32-kHz CPU operation, with time base for clock * Without 32-kHz CPU operation, with time base for clock Without 32-kHz CPU operation, without time base Note: *Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. I/O Options D: Without pull-down resistance Pin name D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 D9 D10 D11 D12 D13 E: With pull-down resistance I/O option I/O D E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin name R1 R2 R8 R9 4. RA1/Vdisp R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 R90 R91 R92 R93 I/O I/O option D E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RA1 without pull-down resistance Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 5. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 7. Stop Mode 6. System Oscillator (OSC1, OSC2) 78 8. Package Ceramic oscillator f= MHz Used FP-64B Crystal oscillator f= MHz Not used DP-64S External clock f= MHz HD404358 Series Rev. 5.0 March 1997 Description The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input capture timer, and two low-power dissipation modes. The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the HD407A4359 with 16-kword PROM. The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum instruction cycle time: 0.47 s) The HD407A4359 is a PROM version (ZTATmicrocomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTAT version is 27256-compatible.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features * 34 I/O pins One input-only pin 33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15 mA, max.) * On-chip A/D converter (8-bit x 8-channel) Low power voltage 2.7 V to 6.0 V * Three timers One event counter input One timer output One input capture timer * Eight-bit clock-synchronous serial interface (1 channel) * Alarm output HD404358 Series * Built-in oscillators Ceramic oscillator or crystal External clock drive is also possible * Seven interrupt sources Two by external sources Three by timers One by A/D converter One by serial interface * Two low-power dissipation modes Standby mode Stop mode * Instruction cycle time 0.47 s (fOSC = 8.5 MHz, 1/4 division ratio): HD40A4354, HD40A4356, HD40A4358, HD407A4359 0.8 s (fOSC = 5 MHz, 1/4 division ratio): HD404354, HD404356, HD404358 Ordering Information Type Instruction Cycle Time Mask ROM Standard versions Product Name Model Name ROM (Words) RAM (Digit) Package HD404354 HD404354S 4,096 384 DP-42S (fOSC= 5 MHz) HD404354H HD404356 HD404356S FP-44A 6,144 DP-42S HD404356H HD404358 HD404358S FP-44A 8,192 DP-42S HD404358H High speed versions HD40A4354 HD40A4354S (fOSC= 8.5 MHz) HD40A4354H HD40A4356 HD40A4356S FP-44A 4,096 384 FP-44A 6,144 DP-42S HD40A4356H HD40A4358 HD40A4358S FP-44A 8,192 DP-42S HD40A4358H ZTAT HD407A4359 HD407A4359S HD407A4359H 2 DP-42S FP-44A 16,384 512 DP-42S FP-44A HD404358 Series Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DP-42S 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R23 R22 R21 R20 R13 R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 44 43 42 41 40 39 38 37 36 35 34 NC R03 /TOC R02 /SO R01 /SI R00 /SCK RA1 R23 R22 R21 R20 R13 RA 1 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 AV CC V CC FP-44A 33 32 31 30 29 28 27 26 25 24 23 R12 R11 R10 R83 R82 R81 R80 D8 D7 D6 D5 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 R41/AN5 R42/AN6 R43/AN7 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC NC TEST RESET OSC1 OSC2 GND AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 3 HD404358 Series Pin Description Pin Number Item Symbol DP-42S FP-44A I/O Function Power supply VCC 21 16 Applies power voltage GND 10 5 Connected to ground Test TEST 6 1 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 7 2 I Resets the MCU Oscillator OSC1 8 3 I Input/output pin for the internal oscillator. Connect these pins to the ceramic oscillator or crystal oscillator, or OSC1 to an external oscillator circuit. OSC2 9 4 O D0-D8 22-30 17-21, I/O Input/output pins addressed individually by bits; D 0-D8 are all standard-voltage I/O pins. Port 23-26 RA1 1 39 I One-bit standard-voltage input port pin R00-R13, 2-5, 40-43, I/O R30-R43, 12-19, 7-14 Four-bit input/output pins consisting of standard-voltage pins R80-R83 31-38 27-34 R20-R23 39-42 35-38 I/O Four-bit input/output pins consisting of intermediate voltage pins Interrupt INT0, INT1 22, 23 17, 18 I Input pins for external interrupts Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode Serial Interface SCK 2 40 I/O Serial interface clock input/output pin SI 3 41 I Serial interface receive data input pin SO 4 42 O Serial interface transmit data output pin TOC 5 43 O Timer output pin EVNB 24 19 I Event count input pin Buzzer BUZZ 25 20 O Square waveform output pin A/D converter AVCC 20 15 Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to VCC, connect a 0.1F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AVSS 11 6 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN0-AN7 12-19 7-14 Timer 4 I Analog input pins for the A/D converter HD404358 Series INT0 GND VCC OSC2 OSC1 STOPC TEST RESET Block Diagram System control Interrupt control D0 RAM (384 x 4 bits) (512 x 4 bits) D1 D2 D port INT1 W (2 bits) Timer A D5 D7 D8 R0 port Timer B D4 D6 X (4 bits) EVNB D3 SPX (4 bits) R00 R01 R02 R03 SO SCK R1 port SPY (4 bits) R11 R12 R20 R21 R22 R23 ALU AVSS * * * A/D converter ST (1 bit) CA (1 bit) R3 port R30 AN0 * * * R10 R13 R2 port Serial interface Internal data bus SI Internal data bus Timer C TOC Internal address bus Y (4 bits) R33 AN7 A (4 bits) R40 R4 port AVCC B (4 bits) BUZZ R31 R32 R41 R42 R43 Buzzer SP (10 bits) R80 Instruction decoder PC (14 bits) R8 port Data bus R81 R82 Directional signal line ROM (4,096 x 10 bits) (6,144 x 10 bits) (16,384 x 10 bits)(8,192 x 10 bits) RA port R83 Intermediate voltage pin RA1 5 HD404358 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000-$17FF (HD404356, HD40A4356), $0000-$1FFF (HD404358, HD40A4358), $0000-$3FFF (HD407A4359)): The entire ROM area can be used for program coding. $0000 $000F Vector address (16 words) $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) Program (4,096 words) $0FFF For HD404354, HD40A4354 $1000 Program (6,144 words) For HD404356, HD40A4356 $17FF $1800 $1FFF $2000 Program (8,192 words) For HD404358, HD40A4358 $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F Program (16,384 words) HD407A4359 $3FFF Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map RAM Memory Map The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384-digit x 4-bit RAM areas. The HD407A4359 MCU contain 512-digit x 4-bit RAM areas. Both of 6 HD404358 Series these RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. D a t a A r e a ( $ 0 5 0 - $ 1 7 F f o r HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358, $050-$1FF for HD407A4359) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 7 HD404358 Series RAM Memory Map Initial values after reset $000 RAM-mapped registers $040 $050 Memory registers (MR) HD404354, HD40A4354, HD404356, HD40A4356, HD404358, HD40A4358 Data (304 digits) $180 HD407A4359 Data (432 digits) $200 $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000 Undefined Undefined -000 0000 *2/0000 Undefined 00-0000 *2/0000 Undefined Not used Not used $3C0 Stack (64 digits) $016 $017 $018 $019 $01A $3FF A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W -000 0000 1000 0000 --00 W W W 0000 00-0 -000 W (DCD2) W W 0000 0000 ---0 (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) W W W W W 0000 0000 0000 0000 0000 (DCR8) W 0000 Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). 2. Undefined. R: Read only W: Write only R/W: Read/write $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) Not used $02C Port D0-D3 DCR (DCD0) $02D Port D4-D7 DCR (DCD1) $02E $02F Port D8 DCR $030 $031 $032 $033 $034 Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Not used Not used $038 $03F Port R8 DCR Not used $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map 8 *1 HD404358 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $002 3 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) $003 Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 32 Not used ADSF (A/D start flag) WDON (Watchdog on flag) Not used $020 33 RAME (RAM enable flag) IAOF (IAD off flag) ICEF (Input capture error flag) ICSF (Input capture status flag) $021 $022 34 Not used $023 35 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM IAOF IF ICSF ICEF RAME RSP WDON ADSF Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Not executed Inhibited Not executed Inhibited Inhibited Allowed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 9 HD404358 Series Bit 3 Bit 2 Bit 0 Bit 1 $000 Interrupt control bits area $003 PMRA $004 D3 /BUZZ SMR $005 R00 /SCK R03/TOC R01/SI SRL $006 Serial data register (lower digit) SRU $007 Serial data register (upper digit) TMA $008 Not used TMB1 $009 *1 R02 /SO Serial transmit clock speed selection Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) TRBL/TWBL $00A Timer B register (upper digit) TRBU/TWBU $00B MIS $00C *2 TMC $00D *1 Not used SO PMOS control Clock source selection (timer C) TRCL/TWCL $00E Timer C register (lower digit) TRCU/TWCU $00F Timer C register (upper digit) Not used ACR $016 Not used A/D data register (upper digit) ADRU $018 AMR1$019 AMR2 $01A Analog channel selection A/D data register (lower digit) ADRL $017 R33/AN3 R32/AN2 Not used R31/AN1 R30/AN0 R4/AN4-AN7 *3 Not used $020 Register flag area $023 PMRB $024 PMRC $025 TMB2 $026 D4/STOPC D2/EVNB D1/INT1 D0/INT0 *4 *5 Buzzer output Not used EVNB detection edge selection *6 Not used DCD0 $02C Port D3 DCD Port D2 DCD Port D1 DCD Port D0 DCD DCD1 $02D Port D7 DCD Port D6 DCD Port D5 DCD Port D4 DCD DCD2 $02E Not used Port D8 DCD Not used DCR0 $030 DCR3 $033 Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR DCR4 $034 Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR DCR1 $031 DCR2 $032 Not used DCR8 $038 Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR Not used $03F Notes: 1. 2. 3. 4. 5. 6. Auto-reload on/off Pull-up MOS control A/D conversion time SO output level control in idle states Serial clock source selection Input capture selection Figure 5 Special Function Register Area 10 HD404358 Series Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC 12 PC11 $3FC 1021 PC 10 PC9 PC 8 PC7 $3FD 1022 CA PC6 PC 5 PC4 $3FE 1023 PC 3 PC2 PC 1 PC0 $3FF PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 11 HD404358 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 (ST) 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. 12 HD404358 Series Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction-- but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one t RC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1. Interrupts The MCU has 7 interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A, B, and C), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. 13 HD404358 Series The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. 14 HD404358 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0 - DCD1) All bits 0 Turns output buffer off (to high impedance) (DCD2) ---0 (DCR0 - DCR4, DCR8) All bits 0 Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B bits 2-0 (PMRB2 - PMRB0) 000 Refer to description of port mode register B Port mode register C (PMRC) 00 - 0 Refer to description of port mode register C Timer mode register A (TMA) - 000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - 000 Refer to description of timer mode register B2 Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S (PSS) $000 -- Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer write register B (TWBU, TWBL) $X0 -- Timer write register C (TWCU, TWCL) $X0 -- 000 -- Interrupt flags/mask I/O Timer/ counters, serial interface Octal counter 15 HD404358 Series Abbr. Initial Value Contents A/D mode register 1 (AMR1) 0000 A/D mode register 2 (AMR2) - - 00 A/D channel register (ACR) - 000 Refer to description of A/D channel register A/D data register (ADRL) 0000 Refer to description of A/D data register (ADRU) 1000 Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter IAD off flag (IAOF) 0 Refer to the description of A/D converter Input capture status flag (ICSF) 0 Refer to description of timer B Input capture error flag (ICEF) 0 Refer to description of timer B Miscellaneous register (MIS) 00 - - Refer to description of operating modes, I/O, and serial interface Item A/D Bit registers Others Refer to description of A/D mode register Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Status After Cancellation of Stop Mode by STOPC Input Status After all Other Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register B bit 3 (PMRB3) Pre-stop-mode values are retained 0 16 HD404358 Series Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A A/D 6 $000C Serial 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 17 HD404358 Series $ 000,0 IE INT0 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $ 000,2 IFO $ 000,3 IMO Vector address Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt $ 002,0 IFTB $ 002,1 IMTB Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC A/D interrupt $ 003,0 IFAD $ 003,1 IMAD Serial interrupt $ 003,2 IFS $ 003,3 IMS Note: $m,n is RAM address $m, bit number n. Figure 8 Interrupt Control Circuit 18 HD404358 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source INT0 INT1 Timer A Timer B Timer C A/D Serial IE 1 1 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 0 0 IF1 * IM1 * 1 0 0 0 0 0 IFTA * IMTA * * 1 0 0 0 0 IFTB * IMTB * * * 1 0 0 0 IFTC * IMTC * * * * 1 0 0 IFAD * IMAD * * * * * 1 0 IFS * IMS * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 9 Interrupt Processing Sequence 19 HD404358 Series Power on RESET = 0? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC) + 1 PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer-A interrupt? No PC $0008 Yes Timer-B interrupt? No PC $000A Yes Timer-C interrupt? No PC $000C Yes A/D interrupt? No PC $000E (serial interrupt) Figure 10 Interrupt Processing Flowchart Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. 20 HD404358 Series Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising edge of signals input to INT0 and INT1, as listed in table 5. Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0) IF0, IF1 Interrupt Request 0 No 1 Yes External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1) IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. 21 HD404358 Series Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2) IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. 22 HD404358 Series Table 14 Serial Interrupt Mask (IMS: $003, Bit 3) Mask IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in table 15. Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 16. Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1) IMAD Interrupt Request 0 Enabled 1 Disabled (masked) 23 HD404358 Series Operating Modes The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables 18 and 19. Transitions between operating modes are shown in figure 11. Table 17 Operating Modes and Clock Status Mode Name Active Standby Stop Activation method RESET cancellation, SBY instruction interrupt request, STOPC cancellation in stop mode STOP instruction Status OP Stopped System oscillator OP RESET input, STOP/ SBY RESET input, interrupt instruction request Cancellation method RESET input, STOPC input in stop mode Note: OP implies in operation Table 18 Operations in Low-Power Dissipation Modes Function Stop Mode Standby Mode CPU Reset Retained RAM Retained Retained Timer A Reset OP Timer B Reset OP Timer C Reset OP Serial Reset OP A/D Reset OP I/O Reset Retained Note: OP implies in operation Table 19 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode Stop Mode Active Mode RA1 -- -- Input enabled R0-D8, R0-R4, Retained or output of peripheral functions High impedance Input enabled R8, 24 HD404358 Series Reset by RESET input or by watchdog timer RAME = 0 RESET 1 oCPU: Stop RESET 2 Active mode Standby mode fOSC: Oscillate RAME = 1 SBY instruction Interrupt oPER: fcyc fOSC: Oscillate oCPU: fcyc STOPC Stop mode STOP instruction oPER: fcyc fOSC: Stop oCPU: Stop oPER: Stop fOSC: Main oscillation frequency fcyc: fOSC/4 oCPU: System clock oPER: Clock for other peripheral functions Figure 11 MCU Status Transitions Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12. 25 HD404358 Series Stop Standby Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop No RESET = 0? Yes RESET = 0? Yes No No IF0 * IMO = 1? No STOPC = 0? Yes IF1 * IM1 = 1? No Yes Yes IFTA * IMTA = 1? Yes RAME = 1 RAME = 0 No IFTB * IMTB = 1? Yes No IFTC * IMTC = 1? Yes No IFAD * IMAD = 1? Yes No IFS * IMS = 1? Yes Restart processor clocks Restart processor clocks Execute next instruction No Reset MCU IF = 1, IM = 0, and IE = 1? Execute next instruction Yes Accept interrupt Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. 26 No , HD404358 Series Stop mode Oscillator Internal clock RESET or STOPC tres tres tRC (stabilization period) STOP instruction execution Figure 13 Timing of Stop Mode Cancellation Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by R ESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by R ESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 0 ? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 14 MCU Operating Sequence (Power On) 27 HD404358 Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 15 MCU Operating Sequence (MCU Operation Cycle) 28 HD404358 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Stop mode Standby mode No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle For IF and IM operation, refer to figure 12. Figure 16 MCU Operating Sequence (Low-Power Mode Operation) 29 HD404358 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 17. As shown in table 20, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2. The system oscillator can also be operated by an external clock. See figure 18 for the layout of crystal and ceramic oscillator. OSC2 1/4 System fOSC division oscillator circuit fcyc tcyc Timing generator circuit oCPU CPU with ROM, RAM, registers, flags, and I/O oPER Peripheral function interrupt OSC1 Figure 17 Clock Generation Circuit TEST RESET OSC1 OSC2 GND AVSS Figure 18 Typical Layout of Crystal and Ceramic Oscillator 30 HD404358 Series Table 20 Oscillator Circuit Examples Circuit Configuration External clock operation Ceramic oscillator (OSC1, OSC2) Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator: C1 CSA4.00MG OSC1 Ceramic (Murata) Rf Rf = 1 M 20% C1 = C2 = 30 pF 20% OSC2 C2 GND Crystal oscillator (OSC1, OSC2) Rf = 1 M 20% C1 C1 = C2 = 10 to 22 pF 20% OSC1 Crystal Crystal: Equivalent to circuit shown below Rf C0 = 7 pF max. OSC2 RS = 100 max. C2 GND L CS OSC1 RS OSC2 CO Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 18). 31 HD404358 Series Input/Output The MCU has 33 input/output pins (D0-D 8, R0-R4, R8) and an input pin (RA1). The features are described below. * Four pins (R2 0-R2 3) are high-current (15 mA max) input/output with intermediate voltage NMOS open drain pins. * The D0-D4, R0, R3-R4 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R02/SO pin can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Each input/output pin except for R2 has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 19, programmable I/O circuits are listed in table 21, and I/O pin circuit types are shown in table 22. Table 21 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS Note: -- indicates off status. 32 1 1 0 1 HD404358 Series HLT Pull-up control signal VCC MIS3 VCC Pull-up MOS Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 19 I/O Buffer Configuration 33 HD404358 Series Table 22 Circuit Configurations of I/O Pins I/O Pin Type Input/output pins Circuit Pins VCC Pull-up control signal Buffer control signal VCC HLT D0-D8, MIS3 R00, R01, R03 R10-R13, DCR, DCD Output data PDR R30-R33, R40-R43, R80-R83 Input data Input control signal HLT VCC VCC Pull-up control signal Buffer control signal Output data R02 MIS3 DCR MIS2 PDR Input data Input control signal HLT R20-R23 DCR Output data PDR Input data Input control signal Input pins RA1 Input data Input control signal Peripheral Input/output function pins pins VCC HLT VCC Pull-up control signal Output data Input data Notes on next page. 34 SCK MIS3 SCK SCK HD404358 Series I/O Pin Type Peripheral function pins Circuit Pins Output pins VCC HLT VCC Pull-up control signal MIS3 PMOS control signal Output data VCC VCC Output data Input pins MIS2 SO HLT Pull-up control signal SO TOC, BUZZ MIS3 TOC, BUZZ SI, VCC HLT INT0, INT1, MIS3 PDR EVNB, STOPC Input data AN0-AN7 VCC HLT MIS3 PDR A/D input Input control Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active and standby modes. 35 HD404358 Series Evaluation Chip Set and ZTAT/Mask ROM Product Differences As shown in figure 20, the NMOS intermediate breakdown voltage open drain pin circuit in the evaluation chip set differs from that used in the ZTAT microcomputer and built-in mask ROM microcomputer products. Please note that although these outputs in the ZTAT microcomputer and built-in mask ROM microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs cannot be set to high impedance in the evaluation chip set. Table 23 Program Control of High Impedance States Register Set Value DCR 0 1 PDR * 1 Notes: * An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation. This applies to the ZTAT and built-in mask ROM microcomputer NMOS open drain pins. HLT VCC MIS3 VCC DCR PDR CPU input Input control signal Evaluation Chip Set Circuit Structure HLT DCR PDR CPU input Input control signal ZTAT and Built-in Mask ROM Microcomputer Circuit Structure Figure 20 NMOS Intermediate Breakdown Voltage Open Drain Pin Circuits 36 HD404358 Series D Port (D 0-D8): Consist of 9 input/output pins addressed by one bit. Pins D0-D8 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D8 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DC D0-DC D2: $02C-$02E) that are mapped to memory addresses (figure 21). Pins D0-D2, D4 are multiplexed with peripheral function pins INT0, INT1, EVNB, and STOPC, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0-PMRB3) of port mode register B (PMRB: $024) (figure 22). Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 23). R Ports (R0 0-R43, R8): 24 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR4: $030-$034, DCR8: $038) that are mapped to memory addresses (figure 21). Pin R0 0 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 24). Pins R01-R03 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function modes of these pins are selected by bits 0-2 (PMRA0-PMRA2) of port mode register A (PMRA: $004), as shown in figures 23. Port R3 is multiplexed with peripheral function pins AN 0-AN3, respectively. The peripheral function modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019) (figure 25). Ports R4 is multiplexed with peripheral function pins AN4-AN7, respectively. The peripheral function modes of these pins can be selected in 4-pin units by setting bit 1 (AMR21) of A/D mode register 2 (AMR2: $01A) (figure 26). Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 21 and figure 27). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. 37 HD404358 Series Data control register (DCD0 to 2: $02C to $02E) (DCR0 to 4: $030 to $034, DCR8: $038) DCD0, DCD2, DCR0 to DCR4, DCR8 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W DCD03, DCD13, DCR03- DCR43, DCR83 DCD02, DCD12, DCR02- DCR42, DCR82 DCD01, DCD11, DCR01- DCR41, DCR81 DCD00- DCD20, DCR00- DCR40, DCR80 Bit name Bits 0 to 3 CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 Not used Not used Not used D8 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR8 R83 R82 R81 R80 Figure 21 Data Control Registers (DCD, DCR) 38 HD404358 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 22 Port Mode Register B (PMRB) Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 23 Port Mode Register A (PMRA) 39 HD404358 Series Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name R00/SCK Mode Selection SMR3 0 R00 1 SCK SMR2 SMR1 SMR0 Transmit clock selection. Refer to figure 55 in the serial interface section. Figure 24 Serial Mode Register (SMR) A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 25 A/D Mode Register 1 (AMR1) 40 R30/AN0 Mode Selection HD404358 Series A/D mode register 2 (AMR2: $01A) Bit 3 2 Initial value -- -- 0 0 Read/Write -- -- W W Bit name 0 1 Not used Not used AMR21 AMR20 AMR20 Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4-AN7 Pin Selection 0 R4 1 AN4-AN7 Figure 26 A/D Mode Register 2 (AMR2) Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 -- -- -- -- Read/Write Bit name W W MIS3 MIS2 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 21) Not used Not used MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 PMOS active 1 PMOS off Figure 27 Miscellaneous Register (MIS) 41 HD404358 Series Prescalers The MCU has a built-in prescaler labeled as prescaler S (PSS). The prescalers operating conditions are listed in table 24, and the prescalers output supply is shown in figure 28. The timers A-C input clocks except external events, the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Table 24 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock MCU reset MCU reset, stop mode Timer A System clock Clock selector Timer B Prescaler S Timer C Serial Figure 28 Prescaler Output Supply 42 HD404358 Series Timers The MCU has four timer/counters (A to C). * Timer A: Free-running timer * Timer B: Multifunction timer * Timer C: Multifunction timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are listed in table 25. The operating modes are selected by software. Table 25 Timer Functions Functions Clock source Timer functions Timer output Timer A Timer B Timer C Prescaler S Available Available Available External event -- Available -- Free-running Available Available Available Event counter -- Available -- Reload -- Available Available Watchdog -- -- Available Input capture -- Available -- PWM -- -- Available Note: -- implies not available. 43 HD404358 Series Timer A Timer A Functions: Timer A has the following functions. * Free-running timer The block diagram of timer A is shown in figure 29. Timer counter A (TCA) Overflow System clock oPER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Prescaler S (PSS) Internal data bus Timer A interrupt request flag (IFTA) 3 Timer mode register A (TMA) Figure 29 Timer A Block Diagram Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 30. 44 HD404358 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write Bit name -- W W W Not used TMA2 TMA1 TMA0 Source Input Clock TMA2 TMA1 TMA0 Prescaler Frequency 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc Figure 30 Timer Mode Register A (TMA) 45 HD404358 Series Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Input capture timer The block diagram for each operation mode of timer B is shown in figures 31 and 32. Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Free-running timer control signal Timer write register B lower (TWBL) /2 /4 /8 / 32 / 128 / 512 / 2048 Edge detector o PER 2 Overflow Timer write register B upper (TWBU) Selector EVNB System clock Timer counter B (TCB) 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control signal Timer mode register B2 (TMB2) Figure 31 Timer B Free-Running and Reload Operation Block Diagram 46 Internal data bus Clock HD404358 Series Input capture status flag (ICSF) Interrupt request flag of timer B (IFTB) Input capture error flag (ICEF) Error controller Timer read register BU (TRBU) Timer read register B lower (TRBL) Read signal Edge detector Clock Timer counter B (TCB) Overflow Input capture timer control signal Selector 3 /2 /4 /8 / 32 / 128 / 512 / 2048 System clock o PER 2 Internal data bus EVNB Timer mode register B1 (TMB1) Prescaler S (PSS) Edge detection control signal Timer mode register B2 (TMB2) Figure 32 Timer B Input Capture Operation Block Diagram 47 HD404358 Series Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting the external event input as an input clock source. In this case, pin D2/EVNB must be set to EVNB by port mode register B (PMRB: $024). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2tcyc or longer. Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026). The other operation is basically the same as the free-running/reload timer operation. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVNB. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by timer mode register 2 (TMB2: $026). When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL: $00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $026) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register B (PMRB: $024) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 33. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. 48 HD404358 Series Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D2/EVNB (external event input) 1 1 0 1 Figure 33 Timer Mode Register B1 (TMB1) 49 HD404358 Series * Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of signals input to pin EVNB and input capture operation as shown in figure 34. It is reset to $0 by MCU reset. Timer mode register B2 (TMB2: $026) Bit 3 2 1 0 Initial value -- 0 0 0 -- W Read/Write Bit name Not used TMB22 W W TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling edge detection 0 Rising edge detection 1 Rising and falling edge detection 1 EVNB Edge Detection Selection Free-Running/Reload and Input Capture Selection TMB22 0 Free-running/reload 1 Input capture Figure 34 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid (figures 35 and 36). Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 35 Timer Write Register B Lower Digit (TWBL) 50 HD404358 Series Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 36 Timer Write Register B Upper Digit (TWBU) * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 37 and 38). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained. When the input capture timer operation is selected and if the count of timer B is read after a trigger is input, either the lower or upper digit can be read first. Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 37 Timer Read Register B Lower Digit (TRBL) Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 38 Timer Read Register B Upper Digit (TRBU) 51 HD404358 Series * Port mode register B (PMRB: $024): Write-only register that selects D2/EVNB pin function as shown in figure 39. It is reset to $0 by MCU reset. Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 39 Port Mode Register B (PMRB) 52 HD404358 Series Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (PWM output) The block diagram of timer C is shown in figure 40. System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL) Clock Timer output control signal /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector System o PER clock Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running timer control signal Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 40 Timer C Block Diagram 53 HD404358 Series Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C (TMC: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is shown in figure 41. Program run can be controlled by initializing timer C by software before it reaches $FF. $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Reset Normal operation Figure 41 Watchdog Timer Operation Flowchart * Timer output operation: The PWM output modes can be selected for timer C by setting port mode register A (PMRA: $004). By selecting the timer output mode, pin R03/TOC is set to TOC. The output from TOC is reset low by MCU reset. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C (TMC: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 42. 54 HD404358 Series T x (N + 1) TMC3 = 0 (free-running timer) T T x 256 TMC3 = 1 (reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 42 PWM Output Waveform Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 26. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not change the timer C value. Timer C is changed to the value in timer write register B at the same time the upper digit (TWCU) is written to. Table 26 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Reload Timer write register updated to value N T Timer Write Register is Updated during Low PWM Output Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) T Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. 55 HD404358 Series Timer mode register C (TMC: $00D) Port mode register A (PMRA: $004) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C (TMC: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C (TMC: $00D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 43 Timer Mode Register C (TMC) 56 HD404358 Series * Port mode register A (PMRA: $004): Write-only register that selects R03/TOC pin function as shown in figure 44. It is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection 0 R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 44 Port Mode Register A (PMRA) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit (TWCL) and the upper digit (TWCU) as shown in figures 45 and 46. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 45 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 46 Timer Write Register C Upper Digit (TWCU) 57 HD404358 Series * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit (TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 47 and 48). The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 47 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 48 Timer Read Register C Upper Digit (TRCU) 58 HD404358 Series Alarm Output Function BUZZ Alarm output control signal Alarm output controller System o PER clock 2 Port mode register C (PMRC) / 2048 / 1024 / 512 / 256 Selector Port mode register A (PMRA) Internal data bus The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the prescaler S's outputs, and the output frequency depends on the state of port mode register C (PMRC: $025). The duty cycle of the pulse output is fixed at 50%. Prescaler S (PSS) Figure 49 Alarm Output Function Block Diagram Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as shown in figure 50. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) Bit 3 0 0 0 Undefined 0 Read/Write W W W W PMRC3 PMRC2 PMRC1 PMRC0 PMRC3 1 1 Initial value Bit name 0 2 PMRC2 System Clock Divisor PMRC0 Serial Clock Division Ratio 0 /2048 0 Prescaler output divided by 2 1 /1024 1 Prescaler output divided by 4 0 /512 1 /256 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 50 Port Mode Register C (PMRC) Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as shown in figure 44. It is reset to $0 by MCU reset. 59 HD404358 Series Serial Interface The serial interface serially transfers and receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a selector are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register (SMR: $005) Port mode register A (PMRA: $004) Port mode register C (PMRC: $025) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 51. Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Selector /2 /8 / 32 / 128 / 512 / 2048 3 System clock o PER Prescaler S (PSS) Figure 51 Serial Interface Block Diagram 60 Serial mode register (SMR) Port mode register C (PMRC) Internal data bus Serial data register (SR) HD404358 Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 27 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to the serial mode register. Note that the serial interface is initialized by writing data to the serial mode register. Refer to the following Serial Mode Register section for details. Table 27 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The R01/SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SMR0- SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0) of port mode register C (PMRC: $025) as listed in table 28. 61 HD404358 Series Table 28 Serial Transmit Clock (Prescaler Output) PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 62 0 HD404358 Series Operating States: The serial interface has the following operating states; transitions between them are shown in figure 52. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. * Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait state is entered. 63 HD404358 Series External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write 04 00 06 01 MCU reset SMR write (IFS 1) STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Transfer state (Octal counter = 000) 05 STS instruction (IFS 1) Internal clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write 18 Continuous clock output state (PMRA 0, 1 = 0, 0) 10 13 SMR write 14 11 STS instruction MCU reset 8 transmit clocks 16 SMR write (IFS 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 15 STS instruction (IFS 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 52 Serial Interface State Transitions Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC: $025) to 0 or 1. The output level control example is shown in figure 53. Note that the output level cannot be controlled in transfer state. 64 , HD404358 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states Dummy write for state transition Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 53 Example of Serial Interface Operation Sequence Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 54. 65 HD404358 Series Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Yes Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000 Flag reset at transfer completion Transmit clock error detection procedure Figure 54 Transmit Clock Error Detection If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. Notes on Use: 66 HD404358 Series * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode register (SMR: $005) again. * Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register (SMR: $005) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Port Mode Register C (PMRC: $025) Miscellaneous Register (MIS: $00C) Serial Mode Register (SMR: $005): This register has the following functions (figure 55). * * * * R0 0/SCK pin function selection Transmit clock selection Prescaler division ratio selection Serial interface initialization Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 67 HD404358 Series Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK Clock Source Output Prescaler Refer to table 28 0 Output System clock -- 1 Input External clock -- SMR1 SMR0 0 0 0 1 1 Prescaler Division Ratio SCK SMR2 0 1 1 0 0 1 1 Figure 55 Serial Mode Register (SMR) Port Mode Register C (PMRC: $025): This register has the following functions (figure 56). * Prescaler division ratio selection * Output level control in idle states Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer. By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle states. The output level changes at the same time that PMRC1 is written to. 68 HD404358 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write W W W W PMRC2 PMRC1 PMRC0 Bit name PMRC3 PMRC0 Alarm output function. Refer to figure 50. Serial Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 56 Port Mode Register C (PMRC) Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 57 and 58). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 59. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register (lower digit) (SRL: $006) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 57 Serial Data Register (SRL) Serial data register (upper digit) (SRU: $007) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 58 Serial Data Register (SRU) 69 HD404358 Series Transmit clock 1 Serial output data 2 3 4 5 6 7 LSB 8 MSB Serial input data latch timing Figure 59 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 60). * R0 1/SI pin function selection * R0 2/SO pin function selection Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 60 Port Mode Register A (PMRA) Miscellaneous Register (MIS: $00C): This register has the following functions (figure 61). * R0 2/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. 70 HD404358 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 -- -- -- -- Read/Write Bit name W W MIS3 MIS2 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 21) Not used Not used MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 PMOS active 1 PMOS off Figure 61 Miscellaneous Register (MIS) 71 HD404358 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure eight analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown in figure 62. 4 A/D mode register 1 (AMR1) 3 Selector AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Encoder + Comp - AVCC A/D controller Control signal for conversion time A/D start flag (ADSF) AVSS D/A Operating mode signal (1 in stop mode) Figure 62 A/D Converter Block Diagram 72 A/D mode register 2 (AMR2) A/D data register (ADRU, L) A/D channel register (ACR) IAD off flag (IAOF) Internal data bus A/D interrupt request flag (IFAD) HD404358 Series Registers for A/D Converter Operation A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as shown in figure 63. A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 63 A/D Mode Register 1 (AMR1) A/D Mode register 2 (AMR2: $01A): Two-bit write-only register which is used to set the A/D conversion period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion period, and bit 1 selects port R4 as pins AN4-AN7 in 4-pin units (figure 64). A/D mode register 2 (AMR2: $01A) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name AMR21 Not used Not used AMR21 R4/AN4-AN7 Pin Selection AMR20 AMR20 Conversion Time 0 R4 0 34tcyc 1 AN4-AN7 1 67tcyc Figure 64 A/D Mode Register 2 (AMR2) 73 HD404358 Series A/D Channel Register (ACR: $016): Three-bit write-only register which indicates analog input pin information, as shown in figure 65. A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- W W W Not used ACR2 ACR1 ACR0 Bit name ACR2 ACR1 ACR0 0 0 1 1 0 1 Analog Input Selection 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 Figure 65 A/D Channel Register (ACR) A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 66. A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value -- 0 0 -- Read/Write -- R/W W -- Not used ADSF Bit name WDON Not used WDON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of timers Figure 66 A/D Start Flag (ADSF) 74 HD404358 Series IAD Off Flag (IAOF: $021, Bit 2): By setting the IAD off flag to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 67. IAD off flag (IAOF: $021, bit 2) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name ICSF IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off Refer to the description of timers ICEF RAME Refer to the description of timers Refer to the description of operating modes Figure 67 IAD Off Flag (IAOF) A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 68, 69, and 70). ADRU: $018 3 2 1 ADRL: $017 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Figure 68 A/D Data Registers (ADRU, ADRL) 75 HD404358 Series A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R R R R ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 69 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 Bit name ADRU1 ADRU0 Figure 70 A/D Data Register Upper Digit (ADRU) Notes on Usage * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) * Do not write to the A/D start flag during A/D conversion * Data in the A/D data register during A/D conversion is undefined * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power while in these modes, all current flowing through the converter's resistance ladder is cut off. * If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) * The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D converter oparates stably, do not execute port output instructions during A/D convention. * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog pin will remain pulled up (figure 71). 76 HD404358 Series HLT VCC MIS3 VCC AMR A/D mode register value DCR PDR CPU input Input control signal A/D input ACR A/D channel register value Figure 71 R Port/Analog Multiplexed Pin Circuit 77 HD404358 Series Pin Description in PROM Mode The HD4074359 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 1 39 RA1 I O0 I/O 2 40 R00/SCK I/O VCC 3 41 R01/SI I/O VCC 4 42 R02/SO I/O O1 I/O 5 43 R03/TOC I/O O2 I/O 6 1 TEST I VPP 7 2 RESET I RESET 8 3 OSC1 I VCC 9 4 OSC2 O 10 5 GND GND 11 6 AVSS GND 12 7 R30/AN0 I/O O0 I/O 13 8 R31/AN1 I/O O1 I/O 14 9 R32/AN2 I/O O2 I/O 15 10 R33/AN3 I/O O3 I/O 16 11 R40/AN4 I/O O4 I/O 17 12 R41/AN5 I/O M0 I 18 13 R42/AN6 I/O M1 I 19 14 R43/AN7 I/O 20 15 AVCC VCC 21 16 VCC VCC 22 17 D0/INT0 I/O O3 I/O 23 18 D1/INT1 I/O O4 I/O 24 19 D2/EVNB I/O A1 I 25 20 D3/BUZZ I/O A2 I 26 21 D4/STOPC I/O 27 23 D5 I/O A3 I 28 24 D6 I/O A4 I 29 25 D7 I/O A9 I 30 26 D8 I/O VCC 78 I HD404358 Series Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 31 27 R80 I/O CE I 32 28 R81 I/O OE I 33 29 R82 I/O A13 I 34 30 R83 I/O A14 I 35 31 R10 I/O A5 I 36 32 R11 I/O A6 I 37 33 R12 I/O A7 I 38 34 R13 I/O A8 I 39 35 R20 I/O A0 I 40 36 R21 I/O A10 I 41 37 R22 I/O A11 I 42 38 R23 I/O A12 I Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O4 consist of two pins each. The each pair together before using them. 79 HD404358 Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0 , and M1 low, as shown in figure 72. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 29. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Table 29 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacture Model Name DATA I/O corp 121 B DP-42S Hitachi HS4359ESS01H FP-44A AVAL corp PKW-1000 HS4359ESH01H DP-42S Hitachi HS4359ESS01H FP-44A HS4359ESH01H CE, OE Control signals A14-A0 Address bus O7 O6 O4-O0 O5 O4-O0 O7-O0 Data bus M0 M1 RESET VCC GND VPP HD407A4359 PROM mode pins VCC GND VPP Socket adapter Figure 72 PROM Mode Connections 80 PROM programmer HD404358 Series Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 30. For details of PROM programming, refer to the following Notes on PROM Programming section. Table 30 PROM Mode Selection Pin Mode CE OE VPP O0-O4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 81 HD404358 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 73 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Direct Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 73 RAM Addressing Modes ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 74 and described below. 82 m1 HD404358 Series Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 76. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000-$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight high-order bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 75. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter 83 HD404358 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 74 ROM Addressing Modes 84 B2 B1 Accumulator HD404358 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 75 P Instruction 256 (n - 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 76 Branching when the Branch Destination is on a Page Boundary 85 HD404358 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V 1 Pin voltage VT -0.3 to VCC + 0.3 V 2 -0.3 to +15.0 V 3 Total permissible input current IO 105 mA 4 Total permissible output current -IO 50 mA 5 Maximum input current IO 4 mA 6, 7 30 mA 6, 8 7, 9 Maximum output current -IO 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD407A4359. 2. Applies to all standard voltage pins. 3. Applies to intermediate-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports D0 to D8, R0, R1, R3, R4, and R8. 8. Applies to port R2. 9. The maximum output current is the maximum current flowing from VCC to each I/O pin. 86 HD404358 Series Electrical Characteristics DC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404354/ HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Input high voltage VIH 0.8VCC -- VCC + 0.3 V SI 0.7 VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, SCK, -0.3 -- 0.2VCC V SI -0.3 -- 0.3VCC V OSC1 -0.3 -- 0.5 V RESET, SCK, Unit Test Condition Notes INT0, INT1, STOPC, EVNB Input low voltage VIL INT0, INT1, STOPC, EVNB Output high voltage VOH SCK, SO, TOC VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK, SO, TOC -- -- 0.4 V IOL = 0.4 mA I/O leakage current |IIL| RESET, SCK, SI, -- -- 1 A Vin = 0 V to VCC 1 -- 5.0 mA VCC = 5 V, SO,TOC,OSC1, INT0, INT1, STOPC, EVNB Current dissipation in active mode ICC VCC -- Current dissipation in standby mode ISBY Current dissipation in stop mode ISTOP VCC -- -- 10 A Stop mode retaining voltage VSTOP VCC 2 -- -- V 2, 5 fOSC = 4 MHz VCC -- -- 2.0 mA VCC = 5 V, 3, 5 fOSC = 4 MHz VCC = 5 V 4 Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET, TEST at GND 87 HD404358 Series 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions:MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND D0-D8, R0-R4, R8, RA1 at VCC 4. This is the source current when no I/O current is flowing. Test conditions: Pins: RESET at VCC TEST at GND D0-D8, R0-R4, R8, RA1 at VCC 5. Current dissipation is in proportion to fOSC while the MCU is operating or in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) I/O Characteristics for Standard Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Input high voltage VIH D0-D8, Min Typ Max Unit Test Condition 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V VCC - 0.5 -- -- V -IOH = 0.5 mA -- -- 0.4 V IOL = 1.6 mA -- -- 1 A Vin = 0 V to VCC 30 150 300 A Note R0, R1, R3, R4, R8, RA1 Input low voltage VIL D0-D8, R0, R1, R3, R4, R8, RA1 Output high voltage VOH D0-D8, R0, R1, R3, R4, R8 Output low voltage VOL D0-D8, R0, R1, R3, R4, R8 Input leakage current |IIL| D0-D8, R0, R1, R3, R4, R8, RA1 Pull-up MOS current -IPU D0-D8, R0, R1, R3, R4, R8 Note: 88 1. Output buffer current is excluded. VCC = 5 V, Vin = 0 V 1 HD404358 Series I/O Characteristics for Intermediate-Voltage Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C;HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD 40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Input high voltage VIH R2 0.7VCC -- 12 V Input low voltage VIL R2 -0.3 -- 0.3VCC V Output high voltage VOH R2 11.5 -- -- V 500 k at 12 V Output low voltage VOL R2 -- -- 0.4 V IOL = 0.4 mA -- -- 2.0 V IOL = 15 mA, Note VCC = 4.5 to 5.5 V I/O leakage current Note: |IIL| R2 -- -- 20 A Vin = 0 V to VCC 1 1. Excludes output buffer current. A/D Converter Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Analog supply voltage AVCC AVCC VCC - 0.3 VCC VCC + 0.3 V Analog input voltage AVin AN0-AN7 AVSS -- AVCC V -- -- 200 A -- -- 30 pF Resolution 8 8 8 Bit Number of input channels 0 -- 8 Channe l Absolute accuracy -- -- 2.0 LSB Conversion time 34 -- 67 tcyc 1 -- -- M Current flowing IAD between AVCC and AVSS Analog input capacitance Input impedance Note: CAin AN0-AN7 AN0-AN7 Typ Max Unit Test Condition Note 1 VCC = AVCC = 5.0 V 1. Connect this to VCC if the A/D converter is not used. 89 HD404358 Series Standard f OSC = 5.0 MHz Version AC Characteristics (HD404354/HD404356/HD404358: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C) Item Symbol Pins Clock oscillation frequency fOSC Instruction cycle time tcyc OSC1, OSC2 Min Typ Max Unit Test Condition 0.4 4 5.0 MHz 1/4 system clock division ratio 0.8 1 10 s Note Oscillation stabilization tRC time (ceramic oscillator) OSC1, OSC2 -- -- 7.5 ms 1 Oscillation stabilization time (crystal oscillator) tRC OSC1, OSC2 -- -- 40 ms 1 External clock high width tCPH OSC1 80 -- -- ns 2 External clock low width tCPL OSC1 80 -- -- ns 2 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB 2 -- -- tcyc 3 INT0, INT1, EVNB low widths tIL INT0, INT1, EVNB 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 STOPC low width tSTPL STOPC 1 -- -- tRC 5 RESET rise time tRSTr RESET -- -- 20 ms 4 STOPC rise time tSTPr STOPC -- -- 20 ms 5 Input capacitance Cin All input pins except and R2 -- -- 15 pF f = 1 MHz, V in = 0 V R2 -- -- 30 pF f = 1 MHz, V in = 0 V Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 77. 3. Refer to figure 78. 4. Refer to figure 79. 5. Refer to figure 80. 90 HD404358 Series High-Speed fOSC = 8.5 MHz Version AC Characteristics (HD407A4359: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C) Item Symbol Pins Clock oscillation frequency fOSC Instruction cycle time OSC1, OSC2 tcyc Min Typ Max Unit Test Condition 0.4 4 5.0 MHz 1/4 system clock division ratio 0.4 4 8.5 MHz 1/4 system clock division ratio, VCC = 4.5 to 5.5 V 0.8 1 10 s 0.47 1 10 s Note VCC = 4.5 to 5.5 V Oscillation stabilization time (ceramic oscillator) tRC OSC1, OSC2 -- -- 7.5 ms 1 Oscillation stabilization time (crystal oscillator) tRC OSC1, OSC2 -- -- 40 ms 1 External clock high width tCPH OSC1 80 -- -- ns 2 47 -- -- ns 80 -- -- ns 47 -- -- ns -- -- 20 ns -- -- 15 ns -- -- 20 ns -- -- 15 ns External clock low width External clock rise time tCPL tCPr External clock fall time tCPf OSC1 OSC1 OSC1 VCC = 4.5 to 5.5 V 2 2 VCC = 4.5 to 5.5 V 2 2 VCC = 4.5 to 5.5 V 2 2 VCC = 4.5 to 5.5 V 2 INT0, INT1, EVNB high tIH widths INT0, INT1, EVNB 2 -- -- tcyc 3 INT0, INT1, EVNB low widths tIL INT0, INT1, EVNB 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 STOPC low width tSTPL STOPC 1 -- -- tRC 5 RESET rise time tRSTr RESET -- -- 20 ms 4 STOPC rise time tSTPr STOPC -- -- 20 ms 5 Input capacitance Cin All input pins except TEST and R2 -- -- 15 pF f = 1 MHz, V in = 0 V TEST -- -- 15 pF f = 1 MHz, V in = 0 V 6 -- -- 180 pF R2 -- -- 30 pF 7 f = 1 MHz, V in = 0 V 91 HD404358 Series Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 77. 3. Refer to figure 78. 4. Refer to figure 79. 5. Refer to figure 80. 6. Applies to the HD40A4354, HD40A4356, HD40A4358. 7. Applies to the HD407A4359. 92 HD404358 Series Serial Interface Timing Characteristics (HD407A4359: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V CC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 82 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc Load shown in figure 82 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc Load shown in figure 82 1 Transmit clock rise time tSCKr SCK -- -- 80 ns Load shown in figure 82 1 Transmit clock fall time SCK -- -- 80 ns Load shown in figure 82 1 Serial output data delay tDSO time SO -- -- 300 ns Load shown in figure 82 1 Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 tSCKf During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK -- -- 80 ns 1 Transmit clock fall time SCK -- -- 80 ns 1 Serial output data delay tDSO time SO -- -- 300 ns Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 Note: tSCKf Test Condition Load shown in figure 82 Note 1 1. Refer to figure 81. 93 HD404358 Series OSC1 1/fCP VCC - 0.5 V tCPL tCPH 0.5 V tCPr tCPf Figure 77 External Clock Timing INT0, INT1, EVNB 0.8VCC tIL tIH 0.2VCC Figure 78 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 79 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 80 STOPC Timing 94 HD404358 Series t Scyc t SCKf SCK VCC - 0.5 V (0.8VCC )* 0.4 V (0.2VCC)* t SCKr t SCKL t SCKH t DSO VCC - 0.5 V 0.4 V SO t SSI t HSI 0.7V CC 0.3VCC SI Note: *VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 81 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent Figure 82 Timing Load Circuit 95 HD404358 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404354, HD40A4354, HD404356 and HD40A4356 as an 8-kword version (HD404358, HD40A4358). The 8-kword and 16-kword data sizes are required to change ROM data to mask manu facturing data since the program used is for an 8-k or 16-kword version. This limitation applies when using an EPROM or a data base. ROM 4-kword version: HD404354, HD40A4354 $0000 ROM 6-kword version: HD404356, HD40A4356 $0000 Vector address $000F $0010 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Zero-page subroutine (64 words) $003F $0040 Pattern & program (4,096 words) $0FFF $1000 Pattern & program (6,144 words) $17FF $1800 Not used $1FFF $1FFF Fill this area with 1s 96 Not used HD404358 Series HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358 Please check off the appropriate applications and enter the necessary information. 1. ROM size 5 MHz operation HD404354 4-kword 8.5 MHz operation HD40A4354 5 MHz operation HD404356 Customer 6-kword 8.5 MHz operation HD40A4356 5 MHz operation HD404358 Date of order Department Name 8-kword 8.5 MHz operation HD40A4358 ROM code name LSI number 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. System Oscillator (OSC1, OSC2) Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 4. Stop mode Used Not used 5. Package DP-42S FP-44A 97 HD404369 Series Rev. 5.0 March 1997 Description The HD404369 Series is a 4-bit HMCS400-Series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input capture timer, 32-kHz oscillator for clock, and four low-power dissipation modes. The HD404369 Series includes nine chips: the HD404364, HD40A4364 with 4-kword ROM; the HD404368, HD40A4368 with 8-kword ROM; the HD4043612, HD40A43612 with 12-kword ROM; the HD404369, HD40A4369 with 16-kword ROM; the HD407A4369 with 16-kword PROM. The HD40A4364, HD40A4368, HD40A43612, HD40A4369, and HD407A4369 are high speed versions (minimum instruction cycle time: 0.47 s). The HD407A4369 is a PROM version (ZTAT microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTAT version is 27256-compatible.) Features * 512-digit x 4-bit RAM * 54 I/O pins One input-only pin 53 input/output pins: 8 pins are intermediate-voltage NMOS open drain with high-current pins (15 mA, max.) * On-chip A/D converter (8-bit x 12-channel) Low power voltage 2.7 V to 6.0 V * Three timers One event counter input One timer output One input capture timer * Eight-bit clock-synchronous serial interface (1 channel) * Alarm output HD404369 Series * Built-in oscillators Ceramic oscillator or crystal External clock drive is also possible Subclock: 32.768-kHz crystal oscillator * Seven interrupt sources Two by external sources Three by timers One by A/D converter One by serial interface * Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode * Instruction cycle time 0.47 s (fOSC = 8.5 MHz, 1/4 division ratio): D40A4364, HD40A4368, HD40A43612, HD40A4369, HD407A4369 0.8 s (fOSC = 5 MHz, 1/4 division ratio): HD404364, HD404368, HD4043612, HD404369 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selecte 2 HD404369 Series Ordering Information Type Instruction Cycle Time Mask ROM Standard version (fOSC= 5 MHz) Product Name Model Name ROM (Words) Package HD404364 HD404364S 4,096 HD404368 HD4043612 HD404369 High speed versions HD40A4364 (fOSC = 8.5 MHz) HD40A4368 HD40A43612 HD40A4369 ZTAT HD407A4369 DP-64S HD404364F FP-64B HD404364H FP-64A HD404368S 8,192 DP-64S HD404368F FP-64B HD404368H FP-64A HD4043612S 12,288 DP-64S HD4043612F FP-64B HD4043612H FP-64A HD404369S 16,384 DP-64S HD404369F FP-64B HD404369H FP-64A HD40A4364S 4,096 DP-64S HD40A4364F FP-64B HD40A4364H FP-64A HD40A4368S 8,192 DP-64S HD40A4368F FP-64B HD40A4368H FP-64A HD40A43612S 12,288 DP-64S HD40A43612F FP-64B HD40A43612H FP-64A HD40A4369S 16,384 DP-64S HD40A4369F FP-64B HD40A4369H FP-64A HD407A4369S 16,384 DP-64S HD407A4369F FP-64B HD407A4369H FP-64A 3 HD404369 Series 52 53 54 55 56 57 58 59 60 61 62 1 51 2 50 3 49 4 48 5 47 6 46 7 45 8 44 9 43 FP-64B 10 42 35 18 34 19 32 17 31 36 30 16 29 37 28 15 27 38 26 14 25 39 24 13 23 40 22 12 21 41 20 11 33 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R00/SCK R72 R71 R70 R63 R62 R61 R60 RA1 R23 R22 R21 R20 R13 R12 R11 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 63 64 R71 R70 R63 R62 R61 R60 RA1 R23 R22 R21 R20 R13 R12 Pin Arrangement FP-64A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R41/AN5 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 4 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 R60 R61 R62 R63 R70 R71 R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AV CC 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 15 16 51 DP-64S 50 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 RA1 R23 R22 R21 R20 R13 R12 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 VCC HD404369 Series Pin Description Pin Number Item Symbol DP-64S FP-64B FP-64A I/O Function Power VCC 33 27 25 Applies power voltage Supply GND 16 10 8 Connected to ground Test TEST 12 6 4 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 13 7 5 I Resets the MCU Oscillator OSC1 14 8 6 I Input/output pin for the internal oscillator. Connect these pins to the ceramic oscillator or crystal oscillator, or OSC1 to an external oscillator circuit. OSC2 15 9 7 O X1 17 11 9 I X2 18 12 10 O D0-D13 34-47 28-41 26-39 I/O Input/output pins consisting of standard voltage pins addressed individually by bits RA1 64 58 56 I One-bit standard-voltage input port pin R00-R03, 1-11, 1-5, 1-3, I/O R30-R93 20-31, 14-25, 12-23, Four-bit input/output pins consisting of standard voltage pins 48-55 42-49, 40-47, Port Interrupt 59-64 57-64 Used with a 32.768-kHz crystal ocillator for clock purposes R10-R23 56-63 50-57 48-55 I/O Four-bit input/output pins consisting of intermediate voltage pins INT0, INT1 34, 35 28, 29 26, 27 I Input pins for external interrupts 38 32 30 I Input pin for transition from stop mode to active mode Stop clear STOPC Serial SCK 8 2 64 I/O Serial interface clock input/output pin Interface SI 9 3 1 I Serial interface receive data input pin SO 10 4 2 O Serial interface transmit data output pin TOC 11 5 3 O Timer output pin EVNB 36 30 28 I Event count input pin BUZZ 37 31 29 O Square waveform output pin Timer Alarm 5 HD404369 Series Pin Description (cont) Pin Number Item DP-64S FP-64B FP-64A I/O Function A/D AVCC converter 32 26 24 Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AVSS 19 13 11 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN0-AN11 20-31 14-25 12-23 6 Symbol I Analog input pins for the A/D converter HD404369 Series GND VCC X2 X1 OSC2 OSC1 STOPC TEST RESET Block Diagram D0 INT0 D1 System control Interrupt control D2 INT1 D3 RAM (512 x 4 bits) D4 D port D5 W (2 bits) Timer A D6 D7 D8 D9 X (4 bits) D10 D11 D12 D13 R0 port SPX (4 bits) R1 port SCK ALU AVSS R2 port SPY (4 bits) R3 port Serial interface SO Internal data bus SI Internal data bus Timer C TOC Internal address bus Y (4 bits) R4 port Timer B EVNB CA (1 bit) R6 port A (4 bits) AVCC B (4 bits) BUZZ Buzzer SP (10 bits) Data bus Intermediate voltage pin Directional signal line Instruction decoder PC (14 bits) ROM (16,384 x 10 bits) (12,288 x 10 bits) (8,192 x 10 bits) (4,096 x 10 bits) R7 port ST (1 bit) R8 port A/D converter R9 port * * * RA port * * * AN11 R5 port AN0 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R80 R81 R82 R83 R90 R91 R92 R93 RA1 7 HD404369 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404364, HD40A4364), $0000-$1FFF (HD404368, HD40A4368), $0000-$2FFF (HD4043612, HD40A43612), $0000-$3FFF (HD404369, HD40A4369, HD407A4369)): The entire ROM area can be used for program coding. $0000 $000F Vector address (16 words) $0010 Zero-page subroutine (64 words) $003F $0040 $0FFF $1000 $1FFF Program (4,096 words) For HD404364, HD40A4364 Program (8,192 words) For HD404368, HD40A4368 $2000 Program (12,288 words) $2FFF $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 $0006 $0007 $0008 $0009 JMPL instruction (jump to timer A routine) $000A $000B $000C $000D $000E $000F JMPL instruction (jump to timer C routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to A/D converter routine) JMPL instruction (jump to serial routine) For HD4043612, HD40A43612 $3000 Program (16,384 words) $3FFF Note: For HD404369, HD40A4369, HD407A4369 Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map RAM Memory Map The MCU contains 512-digit x 4 bit RAM areas. These RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described below. 8 HD404369 Series RAM Memory Map Initial values after reset $000 $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F RAM-mapped registers $040 Memory registers (MR) $050 Data (432 digits) $200 Not used Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000 Undefined Undefined 0000 0000 *2/0000 *1 Undefined 0000 0000 *2/0000 Undefined Not used $3C0 Stack (64 digits) (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W 0000 0000 1000 0000 -000 $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) $027 System clock selection register 1 (SSR1) $028 System clock selection register 2 (SSR2) W W W W W 0000 00-0 -000 000--00 Not used Port D0-D3 DCR (DCD0) W $016 $017 $018 $019 $01A $3FF A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 Not used $02C $02D Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). 2. Undefined. R: Read only W: Write only R/W: Read/write $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03F Port D4-D7 DCR Port D8-D11 DCR Port D12, D13 DCR Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR Not used (DCD1) (DCD2) W W 0000 0000 0000 (DCD3) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) W W W W W W W W W W W --00 0000 0000 0000 0000 0000 0000 0000 -000 0000 0000 $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map 9 HD404369 Series RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($050-$1FF) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 10 HD404369 Series Bit 3 Bit 2 Bit 1 Bit 0 $000 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $001 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $003 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) Interrupt control bits area Bit 2 Bit 1 Bit 0 $020 DTON (Direct transfer on flag) Bit 3 ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) IAOF (IAD off flag) ICEF (Input capture error flag) ICSF (Input capture status flag) $022 IF: IM: IE: SP: Not used $023 Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM LSON IAOF IF ICSF ICEF RAME RSP WDON ADSF DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 11 HD404369 Series Bit 3 Bit 2 Bit 1 Bit 0 $000 Interrupt control bits area $003 PMRA $004 D3 /BUZZ SMR $005 R00 /SCK R03/TOC R01/SI SRL $006 Serial data register (lower digit) SRU $007 Serial data register (upper digit) TMA $008 *1 TMB1 $009 *2 R02 /SO Serial transmit clock speed selection Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) TRBL/TWBL $00A Timer B register (upper digit) TRBU/TWBU $00B MIS $00C *3 TMC $00D *2 SO PMOS control Interrupt frame period selection Clock source selection (timer C) TRCL/TWCL $00E Timer C register (lower digit) TRCU/TWCU $00F Timer C register (upper digit) Not used ACR $016 Analog channel selection ADRL $017 A/D data register (lower digit) A/D data register (upper digit) ADRU $018 AMR1$019 R33/AN3 AMR2 $01A Not used R32/AN2 R31/AN1 R5/AN8-AN11 R4/AN4-AN7 R30/AN0 *4 Not used $020 Register flag area $023 PMRB $024 PMRC $025 D4/STOPC D2/EVNB TMB2 $026 Not used *7 SSR1 $027 *8 *9 SSR2 $028 D1/INT1 D0/INT0 *5 *6 Buzzer output EVNB detection edge selection Clock select Not used Clock division ratio selection Not used Not used DCD0 $02C Port D3 DCD Port D2 DCD Port D1 DCD Port D0 DCD DCD1 $02D Port D7 DCD Port D6 DCD Port D5 DCD Port D4 DCD DCD2 $02E Port D11 DCD Port D10 DCD Port D9 DCD Port D8 DCD DCD3 $02F DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 Not used Port D13 DCD Port D12 DCD Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR DCR4 $034 Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR DCR5 $035 Port R53 DCR Port R52 DCR Port R51 DCR Port R50 DCR DCR6 $036 Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR DCR7 $037 Not used Port R72 DCR Port R71 DCR Port R70 DCR DCR8 $038 Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR DCR9 $039 Port R93 DCR Port R92 DCR Port R91 DCR Port R90 DCR Not used Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Timer-A/time-base Auto-reload on/off Pull-up MOS control A/D conversion time SO output level control in idle states Serial clock source selection Input capture selection 32-kHz oscillation stop 32-kHz oscillation division ratio $03F Figure 5 Special Function Register Area 12 HD404369 Series Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1 $3C0 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC13 PC 12 PC11 $3FD PC 10 PC9 PC 8 PC7 $3FE CA PC6 PC 5 PC4 $3FF PC 3 PC2 PC 1 PC0 PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 13 HD404369 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 (ST) 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. 14 HD404369 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a low-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be low for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be low for at least two instruction cycles. Initial values after MCU reset are listed in table 1. Interrupts The MCU has 7 interrupt sources: two external signals (INT 0 and INT1), three timer/counters (timers A, B, and C), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in table 3. 15 HD404369 Series An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. 16 HD404369 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag flags/mask (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0DCD2) All bits 0 Turns output buffer off (to high impedance) (DCD3) - - 00 (DCR0- DCR6, DCR8, DCR9) All bits 0 (DCR7) - 000 Port mode register A (PMRA) 0000 Port mode register B bits 2-0 (PMRB2- 000 PMRB0) Refer to description of port mode register B Port mode register C (PMRC) 00 - 0 Refer to description of port mode register C (TMA) 0000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - 000 Refer to description of timer mode register B2 Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S (PSS) $000 -- Prescaler W (PSW) $00 -- Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer write register B (TWBU, TWBL) $X0 -- Timer write register C (TWCU, TWCL) $X0 -- 000 -- I/O Timer/count- Timer mode register A ers, serial interface Octal counter Refer to description of port mode register A 17 HD404369 Series Item A/D Abbr. Initial Value Contents A/D mode register 1 (AMR1) 0000 A/D mode register 2 (AMR2) - 000 A/D channel register (ACR) 0000 Refer to description of A/D channel register A/D data register (ADRL) 0000 Refer to description of A/D data register (ADRU) 1000 (LSON) 0 Bit registers Low speed on flag Others Refer to description of A/D mode register Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter IAD off flag (IAOF) 0 Refer to the description of A/D converter Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer B Input capture error flag (ICEF) 0 Refer to description of timer B Miscellaneous register (MIS) 0000 Refer to description of operating modes, I/O, and serial interface System clock select register 1 (SSR1) 000 - Refer to description of operating modes, and oscillation circuits System clock select register 2 (SSR2) - - 00 Refer to description of oscillation circuits Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Status After Cancellation of Stop Status After all Other Types of Mode by STOPC Input Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-mcu-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register B bit 3 (PMRB3) Pre-stop-mode values are retained 0 System clock select register 1 bit 3 (SSR13) 18 HD404369 Series Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A A/D 6 $000C Serial 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 19 HD404369 Series $ 000,0 IE INT0 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $ 000,2 IFO $ 000,3 IMO Vector address Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt $ 002,0 IFTB $ 002,1 IMTB Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC A/D interrupt $ 003,0 IFAD $ 003,1 IMAD Serial interrupt $ 003,2 IFS $ 003,3 IMS Note: $m,n is RAM address $m, bit number n. Figure 8 Interrupt Control Circuit 20 HD404369 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source INT0 INT1 Timer A Timer B Timer C A/D Serial IE 1 1 1 1 1 1 1 IF0 IM0 1 0 0 0 0 0 0 IF1 IM1 * 1 0 0 0 0 0 IFTA IMTA * * 1 0 0 0 0 IFTB IMTB * * * 1 0 0 0 IFTC IMTC * * * * 1 0 0 IFAD IMAD * * * * * 1 0 IFS IMS * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 9 Interrupt Processing Sequence 21 HD404369 Series Power on RESET = 0? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC) + 1 PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer-A interrupt? No PC $0008 Yes Timer-B interrupt? No PC $000A Yes Timer-C interrupt? No PC $000C Yes A/D interrupt? No PC $000E (serial interrupt) Figure 10 Interrupt Processing Flowchart 22 HD404369 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising edge of signals input to INT 0 and INT1, as listed in table 5. Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0) IF0, IF1 Interrupt Request 0 No 1 Yes External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1) IM0, IM1 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. 23 HD404369 Series Table 8 Timer A Interrupt Mask (IMTA: 001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) 24 HD404369 Series Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2) IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. Table 14 Serial Interrupt Mask (IMS: $003, Bit 3) Mask IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in table 15. Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 16. Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1) IMAD Interrupt Request 0 Enabled 1 Disabled (masked) 25 HD404369 Series Operating Modes The MCU has five operating modes as shown in table 17. The operations in each mode are listed in tables 18 and 19. Transitions between operating modes are shown in figure 11. Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC 1 and OSC2. Table 17 Operating Modes and Clock Status Mode Name Active Stop Activation method RESET cancellation, interrupt STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) SBY instruction STOP STOP INT0 or timer A instruction when instruction when interrupt request TMA3 = 0 TMA3 = 1 from watch mode Status System oscillator OP OP Stopped Stopped Stopped Subsystem OP oscillator OP *1 OP OP OP Cancellation method RESET input, RESET STOP/SBY instruction input, interrupt request Watch Subactive*2 Standby RESET input, RESET input, RESET input, STOPC input in INT0 or timer A STOP/SBY stop mode interrupt request instruction Note: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register 1 (SSR1: $027). 2. Subactive mode is an optional function; specify it on the function option list. 26 HD404369 Series Table 18 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Serial Reset Stopped OP OP A/D Reset Stopped OP Stopped I/O Reset Retained Retained OP Note: OP implies in operation Table 19 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode, Watch mode Stop Mode Active Mode, Subactive mode RA1 -- -- Input enabled D0-D13 , R0-R9 Retained or output of peripheral functions High impedance Input enabled 27 HD404369 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RESET1 RAME = 1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: o CPU: o CLK: o PER: fOSC: fX: o CPU: o CLK: o PER: SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR13 = 1) STOP fOSC: fX: o CPU: o CLK: o PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A*1 fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop *3 fOSC: fX: *2 Main oscillation frequency Subactive Suboscillation frequency STOP mode (TMA3 = 1, LSON = 1) for time-base Stop f : fOSC: Stop OSC *4 fOSC/4, fOSC/8, fOSC/16, fOSC/32 fcyc: Oscillate Oscillate f fX: : X (software selectable) INT0, o CPU: fSUB o CPU: Stop *1 fSUB: fX/8 or fX/4 timer A o CLK: fW o CLK: fW (software selectable) o o PER: Stop : f SUB PER fW: fX/8 o CPU: System clock o CLK: Clock for time-base Notes: 1. Interrupt source o PER: Clock for other 2. STOP/SBY (DTON = 1, LSON = 0) peripheral functions 3. STOP/SBY (DTON = 0, LSON = 0) LSON: Low speed on flag 4. STOP/SBY (DTON = Don't care, LSON = 1) DTON: Direct transfer on flag Figure 11 MCU Status Transitions 28 HD404369 Series Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12. 29 HD404369 Series Stop Standby Watch Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop No RESET = 0? Yes No RESET = 0? Yes IF0 * IM0 = 1? No No STOPC = 0? Yes IF1 * IM1 = 1? No Yes Yes IFTA * IMTA = 1? Yes RAME = 1 No IFTB * IMTB = 1? RAME = 0 No Yes IFTC * IMTC = 1? Yes No IFAD * IMAD = 1? Yes (SBY only) Restart processor clocks (SBY only) (SBY only) (SBY only) No IFS * IMS = 1? (SBY only) No Yes Restart processor clocks Execute next instruction No Reset MCU IF = 1, IM = 0, and IE = 1? Execute next instruction Yes Accept interrupt Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1: $027; operating: SSR13 = 0, stop: SSR13 = 1) (figure 23). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 37). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, 30 , HD404369 Series but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figures 14 and 15. Operation during mode transition is the same as that at standby mode cancellation (figure 12). Stop mode Oscillator Internal clock RESET or STOPC tres STOP instruction execution tres tRC (stabilization period) Figure 13 Timing of Stop Mode Cancellation Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR12) of the system clock select register 1 (SSR1: $027). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Interrupt Frame: In watch and subactive modes, oCLK is applied to timer A and the INT0 circuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 15). In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt 31 HD404369 Series frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) T tRC TX T: Interrupt frame length t RC : Oscillation stabilization period T + tRC < TX < 2T + tRC Figure 14 Interrupt Frame Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 16). Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC 32 HD404369 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 34. MIS1 MIS0 0 0 T*1 tRC * 1 Oscillation Circuit Conditions 0.24414 ms 0.12207 ms 0.24414 External clock input ms* 2 0 1 15.625 ms 7.8125 ms Ceramic oscillator 1 0 125 ms 62.5 ms Crystal oscillator 1 1 Not used -- Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 15 Miscellaneous Register (MIS) STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing t RC T TD T: tRC: tD: Interrupt frame length Oscillation stabilization period Transition time Figure 16 Direct Transition Timing Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by R ESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by R ESET. When stop mode is cancelled by R ESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is 33 HD404369 Series used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequence shown in figures 17 to 19. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 19. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBYinstruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 0 ? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 17 MCU Operating Sequence (Power On) 34 HD404369 Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 18 MCU Operating Sequence (MCU Operation Cycle) 35 HD404369 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Standby/watch mode No IF = 1 and IM = 0? Yes Stop mode No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle For IF and IM operation, refer to figure 12. Figure 19 MCU Operating Sequence (Low-Power Mode Operation) Note: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 20. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 21, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT0 longer than the interrupt frame 36 HD404369 Series INT0 Sampling High Low Low Figure 20 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low (a) High level period A: High B: High (b) Low level period Figure 21 Sampling Example 37 HD404369 Series Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 22. As shown in table 20, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Registers for Oscillator Circuit Operation System Clock Selection Register 1 (SSR1: $027): Four bit write-only register which sets the subsystem clock frequency (fSUB) division ratio, and sets the subsystem clock oscillation in stop mode. Bit 1 (SSR11) of system clock select register 1 must be set according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 23). Bit 1 (SSR11) and bit 2 (SSR12) are initialized to 0 on reset and in stop mode. Bit 3 (SSR13) is initialized to 0 only on reset. LSON OSC2 OSC1 System fOSC 1/4, 1/8, 1/16 or oscillator 1/32 division circuit*1 fX X1 Subsystem oscillator fcyc tcyc Timing generator circuit oCPU CPU with ROM, RAM, registers, flags, and I/O oPER Peripheral function interrupt System clock selection fSUB Timing 1/8 or 1/4 division t subcyc generator circuit circuit*2 TMA3 X2 1/8 division circuit fW tWcyc Timing generator circuit Time-base clock oCLK selection Time-base interrupt Notes: 1. 1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock select register 2 (SSR2: $028). 2. 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (SSR1: $027). Figure 22 Clock Generation Circuit 38 HD404369 Series System clock selection register 1 (SSR1: $027) Bit 3 2 1 0 Initial value 0 0 0 -- Read/Write W W W Bit name *1 SSR13 SSR12 -- *2 SSR11 Not used SSR11 System Clock Selection 0 0.4 to 1.0 MHz 1 1.6 to 5.0 MHz (HD404369 Series) 1.6 to 8.5 MHz (HD40A4369 Series) SSR12 0 fSUB = fX/8 1 fSUB = fX/4 SSR13 Notes: 1. 2. 32-kHz Oscillation Division Ratio Selection 32-kHz Oscillation Stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode. If fOSC = 0.4 to 1.0 MHz, SSR11 must be set 0; if fOSC = 1.6 to 8.5 MHz, SSR11 must be set to 1. Do not use fOSC = 1.0 to 1.6 MHz with 32-kHz oscillation. Figure 23 System Clock Selection Register 1 (SSR1) System Clock Selection Register 2 (SSR2: $028): Four bit write-only register which is used to select the system clock divisor (figure 24). The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2). The values of SSR20 and SSR21 are valid after the MCU enters watch mode. The system clock must be stopped when the division ratio is to be changed. There are two methods for changing the system clock divisor, as follows. * In active mode, set the divisor by writing to SSR20 and SSR21. At this point, the prior divisor setting will remain in effect. Now, switch to watch mode, and then return to active mode. When active mode resumes, the system clock divisor will have switched to the new value. * In subactive mode, set the divisor by writing to SSR20 and SSR21. Then return to active mode through watch mode. When active mode resumes, the system clock divisor will have switched to the new value. (The change will also take effect for direct transition to active mode.) 39 HD404369 Series SSR2 is initialized to $0 on reset or in stop mode. Notes on Usage If the system clock select register 1 (SSR1: $027) setting does not match the oscillator frequency, the subsystem using the 32.768-kHz oscillation will malfunction. System clock selection register 2 (SSR2: $028) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used SSR21 SSR20 SSR21 SSR20 0 0 1/4 division 0 1 1/8 division 1 0 1/16 division 1 1 1/32 division System Clock Division Ratio Figure 24 System Clock Selection Register 2 (SSR2) 40 HD404369 Series Table 20 Oscillator Circuit Examples Circut Configuration External clock operation Ceramic oscillator (OSC1, OSC2) Circut Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator: CSA4.00MG (Murata) C1 Rf = 1 M 20% OSC1 Ceramic C1 = C2 = 30 pF 20% Rf OSC2 C2 GND Crystal oscillator (OSC1, OSC2) Rf = 1 M 20% C1 C1 = C2 = 10 to 22 pF 20% OSC1 Crystal Crystal: Equivalent to circuit shown below Rf C0 = 7 pF max. OSC2 RS = 100 max. C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Crystal: 32.768 kHz: MX38T X1 (Nippon Denpa) C1 = C2 = 20 pF 20% Crystal RS = 14 k X2 C0 = 1.5 pF C2 GND L CS RS X1 X2 C0 Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, X1, X2 and elements should be as short as possible, and must not cross other wiring (see figure 25). 3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open. 41 HD404369 Series GND RESET OSC1 OSC2 GND X1 X2 AVSS Figure 25 Typical Layout of Crystal and Ceramic Oscillators 42 HD404369 Series Input/Output The MCU has 53 input/output pins (D0-D13, R0-R9) and an input pin (RA 1). The features are described below. * Eight pins (R1-R2) are high-current (15 mA max) input/output with intermediate voltage NMOS open drain pins. * The D0-D4, R0, R3-R5 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R02/SO pin can be set to NMOS opendrain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Each input/output pin except for R1 and R2 has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 26, programmable I/O circuits are listed in table 21, and I/O pin circuit types are shown in table 22. 43 HD404369 Series Table 21 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS 1 1 0 1 Note: -- indicates off status. HLT Pull-up control signal VCC Pull-up MOS MIS3 VCC Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 26 I/O Buffer Configuration 44 HD404369 Series Table 22 Circuit Configuration of I/O Pins I/O Pin Type Circuit Input/output pins Pins VCC Pull-up control signal Buffer control signal VCC HLT D0-D13 , MIS3 R00, R01, R03 DCD, DCR Output data R30-R93 PDR Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R02 MIS3 DCR MIS2 PDR Input data Input control signal HLT R10-R23 DCR Output data PDR Input data Input control signal Input pins Input data RA1 Input control signal Notes on next page. 45 HD404369 Series I/O Pin Type Circuit Pins Peripheral Input/output function pins pins VCC HLT VCC Pull-up control signal MIS3 Output data Input data Output pins VCC SCK SCK HLT VCC Pull-up control signal Output data MIS2 SO HLT VCC Pull-up control signal Output data Input pins VCC Input data TOC, BUZZ MIS3 TOC, BUZZ HLT SI, MIS3 PDR INT0, INT1, SI, INT0, INT1, EVNB, STOPC STOPC HLT VCC SO MIS3 PMOS control signal VCC SCK EVNB, AN0-AN11 MIS3 PDR A/D input Input control Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active, standby, watch, and subactive modes. 46 HD404369 Series Evaluation Chip Set and ZTAT/Mask ROM Product Differences As shown in figure 27, the NMOS intermediate-voltage open drain pin circuit in the evaluation chip set differs from that used in the ZTAT microcomputer and built-in mask ROM microcomputer products. Please note that although these outputs in the ZTAT microcomputer and built-in mask ROM microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs cannot be set to high impedance in the evaluation chip set. Table 23 Program Control of High Impedance States Register Set Value DCR 0 1 PDR * 1 Notes: * An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation. This applies to the ZTAT and built-in mask ROM microcomputer NMOS open drain pins. HLT VCC MIS3 VCC DCR PDR CPU input Input control signal (a) Evaluation Chip Set Circuit Structure HLT DCR PDR CPU input Input control signal (b) ZTAT and Built-In Mask ROM Microcomputer Circuit Structure Figure 27 NMOS Intermediate-Voltage Open Drain Pin Circuits 47 HD404369 Series D Port (D 0-D13): Consist of 14 input/output pins addressed by one bit. Pins D0-D 13 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD3: $02C-$02F) that are mapped to memory addresses (figure 28). Pins D0-D2, D4 are multiplexed with peripheral function pins INT0, INT 1, EVNB, and STOPC, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0- PMRB3) of port mode register B (PMRB: $024) (figure 29). Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 30). R Ports (R0 0-R93): 39 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR9: $030-$039) that are mapped to memory addresses (figure 28). Pin R0 0 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 31). Pins R01-R0 3 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function modes of these pins are selected by bits 0-2 (PMRA0-PMRA2) of port mode register A (PMRA: $004), as shown in figure 30. Port R3 is multiplexed with peripheral function pins AN 0-AN 3, respectively. The peripheral function modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019) (figure 32). Ports R4 and R5 are multiplexed with peripheral function pins AN4-AN 11, respectively. The peripheral function modes of these pins can be selected in 4-pin units by setting bits 1 and 2 (AMR21, AMR22) of A/D mode register 2 (AMR2: $01A) (figure 33). Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 21 and figure 34). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to V CC by their pull-up MOS transistors or by resistors of about 100 k. 48 HD404369 Series Data control register (DCD0 to 3: $02C to $02F) (DCR0 to 9: $030 to $039) DCD0 to DCD3, DCR0 to DCR9 Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W DCD03- DCD23, DCR03- DCR63, DCR83- DCR93 DCD02- DCD22, DCR02- DCR92 DCD01- DCD31, DCR01- DCR91 DCD00- DCD30, DCR00- DCR90 Bit name Bits 0 to 3 CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 D11 D10 D9 D8 DCD3 Not used Not used D13 D12 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR5 R53 R52 R51 R50 DCR6 R63 R62 R61 R60 DCR7 Not used R72 R71 R70 DCR8 R83 R82 R81 R80 DCR9 R93 R92 R91 R90 Figure 28 Data Control Registers (DCD, DCR) 49 HD404369 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 29 Port Mode Register B (PMRB) Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 30 Port Mode Register A (PMRA) 50 R02/SO Mode Selection HD404369 Series Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name R00/SCK Mode Selection SMR3 0 R00 1 SCK SMR2 SMR1 SMR0 Transmit clock selection. Refer to figure 62 in the serial interface section. Figure 31 Serial Mode Register (SMR) A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 32 A/D Mode Register 1 (AMR1) 51 HD404369 Series A/D mode register 2 (AMR2: $01A) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W AMR21 AMR20 Bit name 2 0 1 Not used AMR22 AMR20 AMR22 R5/AN8-AN11 Pin Selection Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4-AN7 Pin Selection 0 R5 0 R4 1 AN8-AN11 1 AN4-AN7 Figure 33 A/D Mode Register 2 (AMR2) Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W MIS3 MIS2 MIS1 MIS0 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 21) MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 PMOS active 1 PMOS off MIS1 tRC selection. Refer to figure 15 in the operation modes section. Figure 34 Miscellaneous Register (MIS) 52 MIS0 HD404369 Series Prescalers The MCU has the following two prescalers, S and W. The prescaler operating conditions are listed in table 24, and the prescaler output supply is shown in figure 35. The timer A-C input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 24 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W 32-kHz crystal oscillation MCU reset, software MCU reset, stop mode Subsystem clock fX/8 Prescaler W Timer A Timer B fX/4 or fX/8 Timer C System clock Clock selector Prescaler S Serial Buzzer output circuit Figure 35 Prescaler Output Supply 53 HD404369 Series Timers The MCU has four timer/counters (A to C). * Timer A: Free-running timer * Timer B: Multifunction timer * Timer C: Multifunction timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are listed in table 25. The operating modes are selected by software. Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 36. Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 37. 54 HD404369 Series Table 25 Timer Functions Functions Clock source Timer functions Timer output Timer A Timer B Timer C Prescaler S Available Available Available Prescaler W Available -- -- External event -- Available -- Free-running Available Available Available Time-base Available -- -- Event counter -- Available -- Reload -- Available Available Watchdog -- -- Available Input capture -- Available -- PWM -- -- Available Note: -- implies not available. 1/4 fW 1/2 tWcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) /2 /8 / 16 / 32 32.768-kHz oscillator 1/2 tWcyc Clock Timer counter A (TCA) Overflow System clock o PER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 36 Timer A Block Diagram 55 HD404369 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMA3 TMA2 TMA1 TMA0 TMA3 TMA2 TMA1 TMA0 0 0 0 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 PSW 1/2tWcyc 1 Inhibited 1 1 0 1 1 0 0 1 1 0 1 Don't care Source Input Clock Prescaler Frequency Operating Mode Timer A mode Time-base mode PSW and TCA reset Note: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 37 Timer Mode Register A (TMA) 56 HD404369 Series Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Input capture timer The block diagram for each operation mode of timer B is shown in figures 38 and 39. Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting the external event input as an input clock source. In this case, pin D2/EVNB must be set to EVNB by port mode register B (PMRB: $024). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2tcyc or longer. Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026). The other operation is basically the same as the free-running/reload timer operation. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVNB. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by timer mode register 2 (TMB2: $026). When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL: $00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. 57 HD404369 Series Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Free-running timer control signal Timer write register B lower (TWBL) /2 /4 /8 /32 /128 /512 /2048 Edge detector oPER 2 Overflow Timer write register B upper (TWBU) Selector EVNB System clock Timer counter B (TCB) 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control signal Timer mode register B2 (TMB2) Figure 38 Timer B Free-Running and Reload Operation Block Diagram 58 Internal data bus Clock HD404369 Series Input capture status flag (ICSF) Interrupt request flag of timer B (IFTB) Input capture error flag (ICEF) Error controller Timer read register BU (TRBU) Timer read register B lower (TRBL) Read signal Edge detector Clock Timer counter B (TCB) Overflow Input capture timer control signal Selector 3 /2 /4 /8 /32 /128 /512 /2048 System clock oPER 2 Internal data bus EVNB Timer mode register B1 (TMB1) Prescaler S (PSS) Edge detection control signal Timer mode register B2 (TMB2) Figure 39 Timer B Input Capture Operation Block Diagram Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $026) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register B (PMRB: $024) 59 HD404369 Series * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 40. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. Timer mode register B1 (TMB1: $009) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D2/EVNB (external event input) 1 1 0 1 Figure 40 Timer Mode Register B1 (TMB1) * Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of signals input to pin EVNB and input capture operation as shown in figure 41. It is reset to $0 by MCU reset. * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid (figures 42 and 43). Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. 60 HD404369 Series * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 44 and 45). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained. When the input capture timer operation is selected and if the count of timer B is read after a trigger is input, either the lower or upper digit can be read first. * Port mode register B (PMRB: $024): Write-only register that selects D2/EVNB pin function as shown in figure 46. It is reset to $0 by MCU reset. Timer mode register B2 (TMB2: $026) Bit 3 2 1 0 Initial value -- 0 0 0 -- W Read/Write Bit name Not used TMB22 W W TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling edge detection 0 Rising edge detection 1 Rising and falling edge detection 1 EVNB Edge Detection Selection Free-Running/Reload and Input Capture Selection TMB22 0 Free-running/reload 1 Input capture Figure 41 Timer Mode Register B2 (TMB2) Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 42 Timer Write Register B Lower Digit (TWBL) 61 HD404369 Series Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 43 Timer Write Register B Upper Digit (TWBU) Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 44 Timer Read Register B Lower Digit (TRBL) Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 45 Timer Read Register B Upper Digit (TRBU) 62 HD404369 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 46 Port Mode Register B (PMRB) 63 HD404369 Series Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (PWM output) The block diagram of timer C is shown in figure 47. System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL) Clock Timer output control signal /2 /4 /8 /32 /128 /512 /1024 /2048 Selector System clock oPER Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running timer control signal Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 47 Timer C Block Diagram 64 HD404369 Series Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C (TMC: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is shown in figure 48. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The PWM output modes can be selected for timer C by setting port mode register A (PMRA: $004). By selecting the timer output mode, pin R03/TOC is set to TOC. The output from TOC is reset low by MCU reset. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C (TMC: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 49. $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Reset Normal operation Figure 48 Watchdog Timer Operation Flowchart 65 HD404369 Series T x (N + 1) TMC3 = 0 (free-running timer) T T x 256 TMC3 = 1 (reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 49 PWM Output Waveform Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C (TMC: $00D) Port mode register A (PMRA: $004) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. 66 HD404369 Series Timer mode register C (TMC: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 50 Timer Mode Register C (TMC) * Port mode register A (PMRA: $004): Write-only register that selects R03/TOC pin function as shown in figure 51. It is reset to $0 by MCU reset. * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit (TWCL) and the upper digit (TWCU) as shown in figures 52 and 53. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit (TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 54 and 55). The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). 67 HD404369 Series Port mode register A (PMRA: $004) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection 0 R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 51 Port Mode Register A (PMRA) Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 52 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 53 Timer Write Register C Upper Digit (TWCU) 68 HD404369 Series Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 54 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 55 Timer Read Register C Upper Digit (TRCU) Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 26. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not change the timer C value. Timer C is changed to the value in timer write register B at the same time the upper digit (TWCU) is written to. 69 HD404369 Series Table 26 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High Timer Write Register is Updated during Low PWM Output PWM Output Timer write register updated to value N Reload T Interrupt request T x (255 - N) T Timer write register updated to value N T T x (255 - N) 70 Interrupt request T HD404369 Series Alarm Output Function The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the prescaler S's outputs, and the output frequency depends on the state of port mode register C (PMRC: $025). The duty cycle of the pulse output is fixed at 50%. Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as shown in figure 57. It is reset to $0 by MCU reset. BUZZ Alarm output control signal Alarm output controller System clock oPER 2 /2048 /1024 /512 /256 Selector Port mode register A (PMRA) Port mode register C (PMRC) Internal data bus Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as shown in figure 51. It is reset to $0 by MCU reset. Prescaler S (PSS) Figure 56 Alarm Output Function Block Diagram 71 HD404369 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write W W W W PMRC2 PMRC1 PMRC0 Bit name PMRC3 0 1 PMRC2 PMRC3 System Clock Divisor PMRC0 Serial Clock Division Ratio 0 /2048 0 Prescaler output divided by 2 1 /1024 1 Prescaler output divided by 4 0 /512 1 /256 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 57 Port Mode Register C (PMRC) 72 HD404369 Series Serial Interface The serial interface serially transfers and receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Four registers, an octal counter, and a selector are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register (SMR: $005) Port mode register A (PMRA: $004) Port mode register C (PMRC: $025) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 58. 73 HD404369 Series Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Internal data bus Serial data register (SR) Selector /2 /8 /32 /128 /512 /2048 3 System clock oPER Prescaler S (PSS) Serial mode register (SMR) Port mode register C (PMRC) Figure 58 Serial Interface Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: Table 27 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to the serial mode register. Note that the serial interface is initialized by writing data to the serial mode register. Refer to the following Serial Mode Register section for details. Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The R0 1/SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. 74 HD404369 Series The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SMR0- SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0) of port mode register C (PMRC: $025) as listed in table 28. Operating States: The serial interface has the following operating states; transitions between them are shown in figure 59. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. * Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. 75 HD404369 Series When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC: $025) to 0 or 1. The output level control example is shown in figure 60. Note that the output level cannot be controlled in transfer state. Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 61. Table 27 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Table 28 Serial Transmit Clock (Prescaler Output) PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 76 0 HD404369 Series If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode register (SMR: $005) again. * Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0. External clock mode STS wait state (octal counter = 000, transmit clock disabled) SMR write 04 00 06 01 MCU reset SMR write (IFS 1) STS instruction 02 Transmit clock Transmit clock wait state (octal counter = 000) 03 8 transmit clocks Transfer state (octal counter 000) 05 STS instruction (IFS 1) Internal clock mode STS wait state (octal counter = 000, transmit clock disabled) SMR write 18 Continuous clock output state (PMRA 0, 1 = 0, 0) 10 13 SMR write 14 11 STS instruction MCU reset 8 transmit clocks 16 SMR write (IFS 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (octal counter = 000) Transfer state (octal counter 000) 15 STS instruction (IFS 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 59 Serial Interface State Transitions 77 , HD404369 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states Dummy write for state transition Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 60 Example of Serial Interface Operation Sequence 78 HD404369 Series Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Yes Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000 Flag reset at transfer completion Transmit clock error detection procedure Figure 61 Transmit Clock Error Detection Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register (SMR: $005) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Port Mode Register C (PMRC: $025) Miscellaneous Register (MIS: $00C) 79 HD404369 Series Serial Mode Register (SMR: $005): This register has the following functions (figure 62). * * * * R0 0/SCK pin function selection Transmit clock selection Prescaler division ratio selection Serial interface initialization Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name SMR3 W W W W SMR3 SMR2 SMR1 SMR0 R00/SCK Mode Selection 0 R00 1 SCK Clock Source Output Prescaler Refer to table 28 0 Output System clock -- 1 Input External clock -- SMR1 SMR0 0 0 0 1 1 Prescaler Division Ratio SCK SMR2 0 1 1 0 0 1 1 Figure 62 Serial Mode Register (SMR) 80 HD404369 Series Port Mode Register C (PMRC: $025): This register has the following functions (figure 63). * Prescaler division ratio selection * Output level control in idle states Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer. By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle states. The output level changes at the same time that PMRC1 is written to. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write Bit name W W W W PMRC3 PMRC2 PMRC1 PMRC0 PMRC0 Alarm output function. Refer to figure 57. Serial Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 63 Port Mode Register C (PMRC) 81 HD404369 Series Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 64 and 65). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 66. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register (lower digit) (SRL: $006) Bit Initial value 1 2 3 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 64 Serial Data Register (SRL) Serial data register (upper digit) (SRU: $007) Bit 1 2 3 Initial value 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 65 Serial Data Register (SRU) Transmit clock 1 Serial output data 2 3 4 5 6 LSB Serial input data latch timing Figure 66 Serial Interface Output Timing 82 7 8 MSB HD404369 Series Port Mode Register A (PMRA: $004): This register has the following functions (figure 67). * R0 1/SI pin function selection * R0 2/SO pin function selection Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 67 Port Mode Register A (PMRA) 83 HD404369 Series Miscellaneous Register (MIS: $00C): This register has the following functions (figure 68). * R0 2/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS3 Pull-Up MOS On/Off Selection MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 Pull-up MOS off 0 PMOS active 1 Pull-up MOS on (refer to table 21) 1 PMOS off Bit name MIS1 tRC selection. Refer to figure 15 in the operation modes section. Figure 68 Miscellaneous Register (MIS) 84 MIS0 HD404369 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure twelve analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown in figure 69. 4 A/D mode register 1 (AMR1) A/D interrupt request flag (IFAD) 2 Selector Encoder + Comp - AVCC A/D controller Control signal for conversion time A/D start flag (ADSF) AVSS A/D mode register 2 (AMR2) A/D data register (ADRU, L) Internal data bus 4 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 A/D channel register (ACR) IAD off flag (IAOF) D/A Operating mode signal (1 in stop, watch, and subactive modes) Figure 69 A/D Converter Block Diagram 85 HD404369 Series Registers for A/D Converter Operation A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as shown in figure 70. A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 70 A/D Mode Register 1 (AMR1) A/D Mode register 2 (AMR2: $01A): Three-bit write-only register which is used to set the A/D conversion period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 1 and 2 select ports R4-R5 as pins AN4-AN11 in 4-pin units (figure 71). A/D mode register 2 (AMR2: $01A) Bit 3 2 1 0 Initial value -- 0 0 0 -- W Read/Write Bit name Not used AMR22 W W AMR21 AMR20 AMR20 AMR22 R5/AN8-AN11 Pin Selection Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4-AN7 Pin Selection 0 R5 0 R4 1 AN8-AN11 1 AN4-AN7 Figure 71 A/D Mode Register 2 (AMR2) 86 HD404369 Series A/D Channel Register (ACR: $016): Four-bit write-only register which indicates analog input pin information, as shown in figure 72. A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ACR3 ACR2 ACR1 ACR0 Bit name ACR3 ACR2 ACR1 ACR0 0 0 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 AN8 1 AN9 1 0 AN10 1 AN11 Don't care. Don't care. 0 1 1 0 1 1 0 1 Analog Input Selection 0 Not used Figure 72 A/D Channel Register (ACR) 87 HD404369 Series A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 73. A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W W R/W DTON ADSF WDON LSON LSON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of operating modes DTON WDON Refer to the description of operating modes Refer to the description of timers Figure 73 A/D Start Flag (ADSF) IAD Off Flag (IAOF: $021, Bit 2): By setting the IA D off flag to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 74. IAD off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name ICSF IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off Refer to the description of timers ICEF RAME Refer to the description of timers Refer to the description of operating modes Figure 74 IAD Off Flag (IAOF) 88 HD404369 Series A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 75, 76, and 77). ADRU: $018 3 2 1 ADRL: $017 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Figure 75 A/D Data Registers (ADRU, ADRL) A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R R R R ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 76 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 Bit name ADRU1 ADRU0 Figure 77 A/D Data Register Upper Digit (ADRU) 89 HD404369 Series Notes on Usage * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) * Do not write to the A/D start flag during A/D conversion * Data in the A/D data register during A/D conversion is undefined * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these modes, all current flowing through the converter's resistance ladder is cut off. * If the power supply for the A/D converter is to be different from VCC, connect a 0.1-F bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) * The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D converter operates stably, do not execute port output instructions during A/D conversion. * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog pin will remain pulled up (figure 78). HLT VCC MIS3 VCC AMR A/D mode register value DCR PDR CPU input Input control signal A/D input ACR A/D channel register value Figure 78 R Port/Analog Multiplexed Pin Circuit 90 HD404369 Series Pin Description in PROM Mode The HD407A4369 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-64S FP-64B FP-64A Pin I/O Pin I/O 1 59 57 R60 I/O 2 60 58 R61 I/O 3 61 59 R62 I/O 4 62 60 R63 I/O 5 63 61 R70 I/O 6 64 62 R71 I/O 7 1 63 R72 I/O 8 2 64 R00/SCK I/O VCC 9 3 1 R01/SI I/O VCC 10 4 2 R02/SO I/O O1 I/O 11 5 3 R03/TOC I/O O2 I/O 12 6 4 TEST I VPP 13 7 5 RESET I RESET 14 8 6 OSC1 I VCC 15 9 7 OSC2 O 16 10 8 GND -- GND 17 11 9 X1 I GND 18 12 10 X2 O 19 13 11 AVSS -- GND 20 14 12 R30/AN0 I/O O0 I/O 21 15 13 R31/AN1 I/O O1 I/O 22 16 14 R32/AN2 I/O O2 I/O 23 17 15 R33/AN3 I/O O3 I/O 24 18 16 R40/AN4 I/O O4 I/O 25 19 17 R41/AN5 I/O M0 I 26 20 18 R42/AN6 I/O M1 I 27 21 19 R43/AN7 I/O 28 22 20 R50/AN8 I/O 29 23 21 R51/AN9 I/O 30 24 22 R52/AN10 I/O I 91 HD404369 Series Pin Number MCU Mode PROM Mode DP-64S FP-64B FP-64A Pin I/O Pin 31 25 23 R53/AN11 I/O 32 26 24 AVCC -- VCC 33 27 25 VCC -- VCC 34 28 26 D0/INT0 I/O O3 I/O 35 29 27 D1/INT1 I/O O4 I/O 36 30 28 D2/EVNB I/O A1 I 37 31 29 D3/BUZZ I/O A2 I 38 32 30 D4/STOPC I/O 39 33 31 D5 I/O A3 I 40 34 32 D6 I/O A4 I 41 35 33 D7 I/O A9 I 42 36 34 D8 I/O VCC 43 37 35 D9 I/O 44 38 36 D10 I/O 45 39 37 D11 I/O 46 40 38 D12 I/O 47 41 39 D13 I/O 48 42 40 R80 I/O CE 49 43 41 R81 I/O OE I 50 44 42 R82 I/O A13 I 51 45 43 R83 I/O A14 I 52 46 44 R90 I/O 53 47 45 R91 I/O 54 48 46 R92 I/O 55 49 47 R93 I/O 56 50 48 R10 I/O A5 I 57 51 49 R11 I/O A6 I 58 52 50 R12 I/O A7 I 59 53 51 R13 I/O A8 I 60 54 52 R20 I/O A0 I 61 55 53 R21 I/O A10 I 62 56 54 R22 I/O A11 I 63 57 55 R23 I/O A12 I 64 58 56 RA1 I O0 I/O Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O4 consist of two pins each. Tie each pair together before using them. 92 I/O I HD404369 Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0, and M1 low, as shown in figure 79. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 29. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. CE, OE Control signals A14-A0 Address bus O7 O6 O5 O4-O0 O4-O0 O7-O0 Data bus M0 M1 RESET VCC GND VPP VCC GND VPP HD407A4369 PROM mode pins Socket adapter PROM programmer Figure 79 PROM Mode Connections Table 29 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacture Model Name DATA I/O corp 121 B DP-64S Hitachi HS4369ESS01H FP-64B AVAL corp PKW-1000 DP-64S FP-64B HS4369ESF01H Hitachi HS4369ESS01H HS4369ESF01H 93 HD404369 Series Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 30. For details of PROM programming, refer to the following Notes on PROM Programming section. Table 30 PROM Mode Selection Pin Mode CE OE VPP O0-O4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 94 HD404369 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 80 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Direct Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 80 RAM Addressing Modes 95 HD404369 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 81 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 83. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 82. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 96 HD404369 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B2 B1 Accumulator B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 81 ROM Addressing Modes 97 HD404369 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output Figure 82 P Instruction 98 2 If RO 9 = 1 HD404369 Series 256 (n - 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 83 Branching when the Branch Destination is on a Page Boundary 99 HD404369 Series Instruction Set The HD404369 Series has 101 instructions, classified into the following 10 groups: * Immediate instructions * Register-to-register instructions * RAM address instructions * RAM register instructions * Arithmetic instructions * Compare instructions * RAM bit manipulation instructions * ROM address instructions * Input/output instructions * Control instructions 100 HD404369 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V 1 Pin voltage VT -0.3 to VCC + 0.3 V 2 -0.3 to +15.0 V 3 Total permissible input current IO 105 mA 4 Total permissible output current -IO 50 mA 5 Maximum input current IO 4 mA 6, 7 30 mA 6, 8 7, 9 Maximum output current -IO 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD407A4369. 2. Applies to all standard voltage pins. 3. Applies to intermediate-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports D0 to D13 , R0, R3 to R9. 8. Applies to ports R1 and R2. 9. The maximum output current is the maximum current flowing from VCC to each I/O pin 101 HD404369 Series Electrical Characteristics DC Characteristics (HD407A4369: VC C = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A4369:V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Input high voltage VIH RESET, SCK, 0.8VCC -- VCC + 0.3 V SI 0.7 VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, SCK, -0.3 -- 0.2VCC V SI -0.3 -- 0.3VCC V OSC1 -0.3 -- 0.5 V Test Condition Notes INT0, INT1, STOPC, EVNB Input low voltage VIL INT0, INT1, STOPC, EVNB Output high voltage VOH SCK, SO, TOC VCC - 0.5 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK, SO, TOC -- -- 0.4 V IOL = 0.4 mA I/O leakage current |IIL| RESET, SCK, -- -- 1 A Vin = 0 V to VCC 1 -- -- 5.0 mA VCC = 5 V, 2, 5 SI, SO, TOC, OSC1, INT0, INT1, STOPC, EVNB Current dissipation in active mode ICC Current dissipation in standby mode ISBY Current dissipation in subactive mode ISUB Current dissipation in watch mode IWTC 102 VCC fOSC = 4 MHz VCC -- -- 2.0 mA VCC = 5 V, 3, 5 fOSC = 4 MHz VCC -- -- 100 A VCC = 5 V, 4 32 kHz oscillator VCC -- -- 20 A VCC = 5 V, 32 kHz oscillator 4 HD404369 Series Item Symbol Pins Min Typ Max Unit Test Condition Notes Current dissipation in stop mode ISTOP VCC -- -- 10 A VCC = 5V, Stop mode VSTOP retaining voltage 4 X1 = GND, X2 = Open VCC 2 -- -- V Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET, TEST at GND 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions:MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND D0-D13 , R0-R9, RA1 at VCC 4. This is the source current when no I/O current is flowing. Test conditions:Pins: RESET at VCC TEST at GND D0-D13 , R0-R9, RA1 at VCC 5. Current dissipation is in proportion to fOSC while the MCU is operating or in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 103 HD404369 Series I/O Characteristics for Standard Pins (HD407A4369: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A 4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH D0-D13 , 0.7VCC -- VCC + 0.3 V -0.3 -- 0.3VCC V VCC - 0.5 -- -- V -IOH = 0.5 mA R0, R3-R9 D0-D13 , -- -- 0.4 V IOL = 1.6 mA -- -- 1 A Vin = 0 V to VCC 30 150 300 A VCC = 5 V, R0, R3-R9, RA1 Input low voltage VIL D0-D13 , R0, R3-R9, RA1 Output high voltage Output low voltage VOH VOL D0-D13 , R0, R3-R9 Input leakage current |IIL| D0-D13 , R0, R3-R9, RA1 Pull-up MOS current -IPU D0-D13 , Vin = 0 V R0, R3-R9 Note: 1 1. Output buffer current is excluded. I/O Characteristics for Intermediate-Voltage Pins (HD407A4369: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/ HD40A4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Input high voltage VIH R1, R2 0.7VCC -- 12 V Input low voltage VIL R1, R2 -0.3 -- 0.3VCC V Output high voltage VOH R1, R2 11.5 -- -- V 500 k at 12 V Output low voltage VOL R1, R2 -- -- 0.4 V IOL = 0.4 mA -- -- 2.0 V IOL = 15 mA, Note VCC = 4.5 to 5.5 V I/O leakage current Note: 104 |IIL| R1, R2 1. Excludes output buffer current. -- -- 20 A Vin = 0 V to VCC 1 HD404369 Series A/D Converter Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20 to +75C;HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A 4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Analog supply voltage AVCC AVCC VCC - 0.3 VCC VCC + 0.3 V AN0-AN11 AVSS -- AVCC V -- -- 200 A -- -- 30 pF Resolution 8 8 8 Bit Number of input channels 0 -- 12 Chan nel Absolute accuracy -- -- 2.0 LSB Conversion time 34 -- 67 tcyc 1 -- -- M Analog input voltage AVin Current flowing between AVCC and AVSS IAD Analog input capacitance CAin Input impedance Note: AN0-AN11 AN0-AN11 Unit Test Condition Notes 1 VCC = AVCC = 5.0 V 1. Connect this to VCC if the A/D converter is not used. 105 HD404369 Series Standard fOSC = 5 MHz Version AC Characteristics (HD404364/HD404368/HD4043612/HD404369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C) Item Symbol Pins Min Typ Max Unit Test Condition Notes Clock oscillation frequency fOSC OSC1, OSC2 0.4 4 5.0 MHz 1/4 system clock division ratio 1 X1, X2 -- 32.768 -- kHz tcyc 0.8 1 10 s tsubcyc -- 244.14 -- s 32-kHz oscillator, 1/8 system clock division ratio -- 122.07 -- s 32-kHz oscillator, 1/4 system clock division ratio Instruction cycle time 1 Oscillation tRC stabilization time (ceramic oscillator) OSC1, OSC2 -- -- 7.5 ms 2 Oscillation stabilization time (crystal oscillator) OSC1, OSC2 -- -- 40 ms 2 X1, X2 -- -- 2 s 2 External clock high tCPH width OSC1 80 -- -- ns 3 External clock low tCPL width OSC1 80 -- -- ns 3 External clock rise tCPr time OSC1 -- -- 20 ns 3 External clock fall time tCPf OSC1 -- -- 20 ns 3 INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB 2 -- -- tcyc / 4 INT0, INT1, EVNB low widths tIL RESET low width tRSTL RESET 2 -- -- tcyc 5 STOPC low width tSTPL STOPC 1 -- -- tRC 6 RESET rise time tRSTr RESET -- -- 20 ms 5 STOPC rise time tSTPr STOPC -- -- 20 ms 6 Input capacitance Cin All input pins -- except R1 and R2 -- 15 pF R1, R2 -- tRC tsubcyc INT0, INT1, EVNB 2 -- -- tcyc / 4 tsubcyc -- f = 1 MHz, Vin = 0 V 30 pF f = 1 MHz, Vin = 0 V 106 HD404369 Series Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for fOSC must be applied. 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 5.0 MHz The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1: $027). 2. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 3. Refer to figure 84. 4. Refer to figure 85. 5. Refer to figure 86. 6. Refer to figure 87. 107 HD404369 Series High-Speed f OSC = 8.5 MHz Version AC Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD40A4364/HD40A4368/HD40A43612/HD40A4369: V CC = 2.7 to 6.0 V, GND = 0 V, T a = -20 to +75C) Item Symbol Pins Min Typ Max Unit Test Condition Notes Clock oscillation frequency fOSC OSC1, OSC2 0.4 4 5.0 MHz 1/4 system clock division ratio 1 0.4 4 8.5 MHz -- 32.768 -- kHz 0.8 1 10 s 1 0.47 1 10 s 2, 3 -- 244.14 -- s 32-kHz oscillator, 1/8 system clock division ratio -- 122.07 -- s 32-kHz oscillator, 1/4 system clock division ratio X1, X2 Instruction cycle time tcyc tsubcyc 2, 3 Oscillation tRC stabilization time (ceramic oscillator) OSC1, OSC2 -- -- 7.5 ms 4 Oscillation tRC stabilization time (ceramic oscillator) OSC1, OSC2 -- -- 40 ms 4 X1, X2 -- -- 2 s 4 OSC1 80 -- -- ns 5 47 -- -- ns 3, 5 80 -- -- ns 5 47 -- -- ns 3, 5 -- -- 20 ns 5 -- -- 15 ns 3, 5 -- -- 20 ns 5 -- -- 15 ns 3, 5 2 -- -- tcyc / 6 External clock high tCPH width External clock low tCPL width External clock rise tCPr time External clock fall time tCPf INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB low widths tIL 108 OSC1 OSC1 OSC1 INT0, INT1, EVNB INT0, INT1, EVNB tsubcyc 2 -- -- tcyc / tsubcyc 6 HD404369 Series Item Symbol Pins Min Typ Max Unit RESET low width tRSTL RESET 2 -- -- tcyc 7 STOPC low width tSTPL STOPC 1 -- -- tRC 8 RESET rise time tRSTr RESET -- -- 20 ms 7 STOPC rise time tSTPr STOPC -- -- 20 ms 8 Input capacitance Cin All input pins except -- TEST, R1 and R2 -- 15 pF TEST -- -- 15 pF 9 -- -- 180 pF 10 -- -- 30 pF R1, R2 Test Condition Notes f = 1 MHz, V in = 0 V f = 1 MHz, V in = 0 V Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for fOSC must be applied. 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 5.0 MHz The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1: $027). 2. When using the subsystem oscillator (32.768 kHz), one of the following relationships for fOSC must be applied. 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 8.5 MHz The operating range for fOSC can be set with bit 1 of system clock selection register 1 (SSR1: $027). 3. VCC = 4.5 to 5.5V 4. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 5. Refer to figure 84. 6. Refer to figure 85. 7. Refer to figure 86. 8. Refer to figure 87. 9. Applies to the HD40A4364, HD40A4368, HD40A43612, and HD40A4369. 10. Applies to the HD407A4369. 109 HD404369 Series Serial Interface Timing Characteristics (HD407A4369: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A 4369: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1 -- -- tcyc Load shown in figure 89 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc Load shown in figure 89 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc Load shown in figure 89 1 Transmit clock rise time tSCKr SCK -- -- 80 ns Load shown in figure 89 1 Transmit clock fall time tSCKf SCK -- -- 80 ns Load shown in figure 89 1 Serial output data delay time tDSO SO -- -- 300 ns Load shown in figure 89 1 Serial input data setup tSSI time SI 100 -- -- ns 1 Serial input data hold time SI 200 -- -- ns 1 tHSI During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK -- -- 80 ns 1 Transmit clock fall time tSCKf SCK -- -- 80 ns 1 Serial output data delay time tDSO SO -- -- 300 ns Serial input data setup tSSI time SI 100 -- -- ns 1 Serial input data hold time SI 200 -- -- ns 1 Note: 110 tHSI 1. Refer to figure 88. Test Condition Load shown in figure 89 Note 1 HD404369 Series OSC1 1/fCP VCC - 0.5 V tCPL tCPH 0.5 V tCPr tCPf Figure 84 External Clock Timing INT0, INT1, EVNB 0.8VCC tIL tIH 0.2VCC Figure 85 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 86 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 87 STOPC Timing 111 HD404369 Series t Scyc t SCKf SCK VCC - 0.5 V (0.8VCC )* 0.4 V (0.2VCC)* t SCKr t SCKL t SCKH t DSO VCC - 0.5 V 0.4 V SO t SSI t HSI 0.7V CC 0.3VCC SI Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 88 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 or equivalent Figure 89 Timing Load Circuit 112 HD404369 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404364, HD40A4364, HD404368, HD40A4368, HD4043612 and HD40A43612 as a 16-kword version (HD404369, HD40A4369). The 16-kword data sizes are required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. ROM 4-kword version: HD404364, HD40A4364 $0000 ROM 8-kword version: HD404368, HD40A4368 $000F $0010 Zero-page subroutine (64 words) $003F $0040 $000F $0010 Zero-page subroutine (64 words) $000F $0010 Zero-page subroutine (64 words) $003F $0040 $003F $0040 $0FFF $1000 Vector address Vector address Pattern & program (4,096 words) Pattern & program (12,288 words) Pattern & program (8,192 words) $2FFF $3000 $1FFF $2000 Not used $3FFF $0000 $0000 Vector address ROM 12-kword version: HD4043612, HD40A43612 Not used $3FFF Not used $3FFF Fill this area with 1s 113 HD404369 Series HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/ HD40A43612/HD40A4369 Option List Please check off the appropriate applications and enter the necessary information. 1. ROM size 5 MHz operation HD404364 4-kword 8.5 MHz operation HD40A4364 5 MHz operation HD404368 Customer 8-kword 8.5 MHz operation HD40A4368 5 MHz operation HD4043612 Department Name 12-kword 8.5 MHz operation HD40A43612 5 MHz operation Date of order ROM code name LSI number 16-kword HD404369 8.5 MHz operation HD40A4369 2. Optional Functions * With 32-kHz CPU operation, with time base for clock * Without 32-kHz CPU operation, with time base for clock Without 32-kHz CPU operation, without time base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4. System Oscillator (OSC1, OSC2) Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop mode 6. Package Used DP-64S Not used FP-64B FP-64A 114 HD404344 Series/HD404394 Series Rev. 5.0 March 1997 Description The HD404344 series and HD404394 series 4-bit microcomputers are products of the HMCS400 series, which is designed to make application systems compact while realizing higher performance and increasing program productivity. Each microcomputer has an A/D converter, two timers and a serial interface. The HD404344 series includes the HD404344 with on-chip 4-kword ROM, HD404342 with 2-kword ROM, and HD404341 with 1-kword ROM. The HD404394 series includes the HD404394 with on-chip 4-kword ROM, HD404392 with 2-kword ROM, and HD404391 with 1-kword ROM. The HD4074344 and HD4074394 are the PROM version ZTAT microcomputers. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd. Features * Input/output pins HD404344 series: 22 pins (CMOS input/output) HD404394 series: 21 pins (3 pins: intermediate-voltage NMOS open drain I/O; 5 pins: NMOS open drain I/O with 15-mA high-current driver) * Two timer/counters One timer output One event counter input (with programmable edge detection) * 8-bit clock-synchronous serial interface (1 channel) * On-chip A/D converter HD404344 series: 8 bit x 4 channel HD404394 series: 8 bit x 3 channel (with Vref pin) HD404344 Series/HD404394 Series * Built-in oscillator Ceramic oscillator External clock drive is also possible * Five interrupt sources One by external source (with programmable edge detection) Four by internal sources * Subroutine stack Maximum 16 levels including interrupts * Two low-power dissipation modes Standby mode Stop mode * One input signal to return from stop mode * Instruction cycle time 1 s (fOSC = 4 MHz) Type of Products Product Name Type HD404344 Series HD404394 Series ROM (words) RAM (digit) Package Mask ROM HD404341S HD404391S 1,024 256 DP-28S HD404342S HD404392S 2,048 HD404344S HD404394S 4,096 HD404341FP HD404391FP 1,024 HD404342FP HD404392FP 2,048 HD404344FP HD404394FP 4,096 HD404341FT HD404391FT 1,024 HD404342FT HD404392FT 2,048 HD404344FT HD404394FT 4,096 HD4074344S HD4074394S 4,096 HD4074344FP HD4074394FP FP-28DA HD4074344FT HD4074394FT FP-30D ZTAT 2 FP-28DA FP-30D DP-28S HD404344 Series/HD404394 Series Pin Arrangement HD404344 Series R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND R30/AN0 R31/AN1 R32/AN2 1 28 2 27 3 26 4 25 5 24 6 23 7 8 9 DP-28S FP-28DA 22 21 20 10 19 11 18 12 17 13 16 14 15 D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC R33/AN3 R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND NC R30/AN0 R31/AN1 R32/AN2 1 30 2 29 3 28 4 27 5 26 R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND NC Vref R3 1/AN1 R3 2/AN2 6 7 8 25 FP-30D 24 23 9 22 10 21 11 20 12 19 13 18 14 17 15 16 1 30 2 29 3 28 4 27 5 26 D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC NC R33/AN3 Top view HD404394 Series R10 R11 R12 R13 R20 R21 R22 R23 OSC1 OSC2 GND Vref R31/AN1 R32/AN2 1 28 2 27 3 26 4 25 5 24 6 23 7 8 9 DP-28S FP-28DA 22 21 20 10 19 11 18 12 17 13 16 14 15 D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC R33/AN3 6 7 8 25 FP-30D 24 23 9 22 10 21 11 20 12 19 13 18 14 17 15 16 D5 D4/STOPC D3 D2 D1 D0/INT0/EVNB R03/TOC R02/SO R01/SI R00/SCK RESET TEST/VPP VCC NC R33/AN3 Top view 3 HD404344 Series/HD404394 Series Pin Description HD404344 Series Pin Number Item Symbol DP-28S/ FP-28DA FP-30D Power supply VCC 16 18 Applies power voltage GND 11 11 Connects to ground Test TEST 17 19 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 18 20 I Resets the MCU Oscillator OSC1 9 9 I Input/output pins for the internal oscillator. Connect these pins to the ceramic oscillator, or OSC1 to an external oscillator circuit. OSC2 10 10 O D0-D5 23-28 25-30 I/O Input/output pins addressed individually by bits; pins D1 and D2 can sink 15 mA max. R00-R03, 1-8, 1-8, I/O Four-bit input/output pins. R10-R13, 12-15 13-16, R20-R23, 19-22 21-24 Port I/O Function Pins R10-R23 can sink 15 mA max. R30-R33 Interrupt INT0 23 25 I Input pin for external interrupts Stop clear STOPC 27 29 I Input pin for transition from stop mode to active mode Serial interface SCK 19 21 I/O Serial interface clock input/output pin SI 20 22 I Serial interface receive data input pin SO 21 23 O Serial interface transmit data output pin TOC 22 24 O Timer output pin EVNB 23 25 I Event count input pin AN0-AN3 12-15 13-16 I Analog input pins for the A/D converter Timer A/D converter 4 HD404344 Series/HD404394 Series HD404394 Series Pin Number Item Symbol DP-28S/ FP-28DA FP-30D Power supply VCC 16 18 Applies power voltage GND 11 11 Connects to ground Test TEST 17 19 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 18 20 I Resets the MCU Oscillator OSC1 9 9 I I/O Function Input/output pin for the internal oscillator. Connect these pins to the ceramic oscillator, or OSC1 to an external oscillator circuit Port OSC2 10 10 O D0-D5 23-28 25-30 I/O Input/output pins addressed individually by bits; pins D1 and D2 can sink 15 mA max. R00-R03, 1-8, 1-8, R10-R13, 13-15 14-16, R20-R23, 19-22 21-24 I/O Four-bit input/output pins. Pins R10-R12 are NMOS intermediate-voltage open drain pins. Pins R13-R23 are NMOS standard-voltage open drain pins which can sink 15 mA max. R31-R33 Interrupt INT0 23 25 I Input pin for external interrupts Stop clear STOPC 27 29 I Input pin for transition from stop mode to active mode Serial interface SCK 19 21 I/O Serial interface clock input/output pin SI 20 22 I Serial interface receive data input pin SO 21 23 O Serial interface transmit data output pin TOC 22 24 O Timer output pin EVNB 23 25 I Event count input pin Vref 12 13 AN1-AN3 13-15 14-16 Timer A/D converter Power supply for the internal ladder resistor in the A/D converter I Analog input pins for the A/D converter 5 HD404344 Series/HD404394 Series INT0 GND VCC OSC2 OSC1 STOPC TEST RESET HD404344 Series Block Diagram System control Interrupt control D0 D1 EVNB D port RAM (256 x 4 bits) W (2 bits) Timer B D2 D3 D4 D5 X (4 bits) Timer C R0 port R00 TOC SPX (4 bits) Y (4 bits) R01 R02 R03 AN0 AN1 AN2 A/D converter R1 port SPY (4 bits) R11 R12 R13 R20 ALU AN3 R2 port SCK R10 Internal data bus Serial interface Internal data bus SO Internal address bus SI R21 R22 R23 CA (1 bit) A (4 bits) SP (10 bits) Large-current pin Bidirectional signal line 6 Instruction decoder ROM (1,024 x 10 bits) (2,048 x 10 bits) (4,096 x 10 bits) R31 R32 R33 B (4 bits) Data bus R30 R3 port ST (1 bit) PC (14 bits) HD404344 Series/HD404394 Series INT0 GND VCC OSC2 OSC1 STOPC TEST RESET HD404394 Series Block Diagram System control Interrupt control D0 D1 EVNB D port RAM (256 x 4 bits) W (2 bits) Timer B D2 D3 D4 D5 X (4 bits) Timer C R0 port R00 TOC SPX (4 bits) AN1 AN2 AN3 SPY (4 bits) R1 port R10 R11 R12 R13 R20 A/D converter ALU Vref R2 port SCK R02 R03 Internal data bus Serial interface Internal data bus SI SO Internal address bus Y (4 bits) R01 R21 R22 R23 ST (1 bit) CA (1 bit) R3 port Data bus A (4 bits) Large-current pin R31 R32 R33 B (4 bits) Intermediatevoltage NMOS open drain pins SP (10 bits) Instruction decoder Standardvoltage NMOS open drain pins PC (14 bits) ROM (1,024 x 10 bits) (2,048 x 10 bits) (4,096 x 10 bits) Bidirectional signal line 7 HD404344 Series/HD404394 Series Memory Map ROM Memory Map The ROM memory map for the MCU is shown in figure 1 and explained as follows. 0 $0000 Vector address $0000 JMPL instruction (jump to RESET, STOPC routine) $0001 1 0 2 15 16 $000F $0010 Zero-page subroutine (64 words) 63 64 1023 1024 2047 2048 4095 4096 HD404341, HD404391 program/pattern (1,024 words) HD404342, HD404392 program/pattern (2,048 words) 5 Not used 6 $003F $0040 $07FF $0800 JMPL instruction (jump to timer C routine) $000A JMPL instruction (jump to A/D converter routine) $000C JMPL instruction (jump to serial routine) $000E 10 11 14 15 $0FFF $1000 $3FFF Figure 1 ROM Memory Map 8 $0006 $0008 Not used 16383 $0005 JMPL instruction (jump to timer B routine) 8 13 $0003 $0007 7 9 $03FF $0400 $0002 $0004 4 12 HD404344, HD404394, HD4074344, HD4074394 program/pattern (4,096 words) JMPL instruction (jump to INT0 routine) 3 $0009 $000B $000D $000F HD404344 Series/HD404394 Series Vector Address Area ($0000 to $000F): When an MCU reset or an interrupt process is executed, the program will begin executing from a vector address. The JMPL instructions which branch to the reset routine and interrupt routine should be programmed at these top addresses. Zero-Page Subroutine Area ($0000-$003F): This area is reserved for subroutines. The program branches to a subroutine in this area in response to a CAL instruction. Pattern Area: HD404341, HD404391--$0000 to $03FF HD404342, HD404392--$0000 to $07FF HD404344, HD404394, HD4074344, HD4074394--$0000 to $0FFF This area contains ROM data which can be referenced with the P instruction. Program Area: HD404341, HD404391--$0000 to $03FF HD404342, HD404392--$0000 to $07FF HD404344, HD404394, HD4074344, HD4074394--$0000 to $0FFF 9 HD404344 Series/HD404394 Series RAM Memory Map The MCU RAM contains 256 digits x 4 bits which is used for the memory registers, and the data and stack areas. The interrupt control bits area, special register area, and the register flag area are mapped into the RAM memory. The RAM memory area is shown in figure 2 and explained as follows. $000 RAM-mapped registers $040 Memory registers (MR) $050 Data (176 digits) $100 Not used $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Not used Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W R/W R/W W W R/W R/W Not used $3C0 Stack (64 digits) $3FF (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) W W W $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 Not used Not used Note: * Two registers are mapped on the same area ($00A, $00B, $00E, $00F). R: Read only W: Write only R/W: Read/write $02C $02D $030 $031 $032 $033 Port D0-D3 DCR Port D4 , D5 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR (DCD0) (DCD1) W W (DCR0) (DCR1) (DCR2) (DCR3) W W W W Not used $03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map 10 * HD404344 Series/HD404394 Series RAM Map Register Area ($000 to $03F): * Interrupt control bits area: $000 to $003 This area is made up of bits used for interrupt control as shown in figure 3. Each bit can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). Some bits however, have limitations along with certain instructions as shown in figure 4. * Special register area: $004 to $01F, $024 to $03F This area is made up of mode registers and data registers, such as for external interrupt, serial interface, timers, A/D converter, and data control for the I/O ports. Its configurations are shown in figures 2 and 5. These registers are categorized as write-only, read-only, and write/read. They can not be accessed by RAM bit manipulation instructions. * Register flag area: $020 to $023 This area is used for the WDON flag and other interrupt control flags. Its configuration is shown in figure 3. Each bit can be accessed only by the SEM/SEMD, REM/REMD, and TM/TMD instructions. Some bits however, have limitations along with certain instructions as shown in figure 4. Data Area ($040 to $0FF): Sixteen of the 176 digits in this area, from $040 to $04F, are memory registers. These registers can be accessed by the LAMR and XMRA instructions. Its configuration is shown in figure 6. Stack Area ($3C0 to $3FF): This area is used to hold the program counter (PC), the status flag (ST), and the carry flag (CA) for subroutine calls (CAL and CALL instructions) and interrupts. Since four digits are used for each level, this area can be used for stacking up to 16 subroutines. The stacking order of saved data and the storing of bits are shown in figure 6. The program counter is recovered by the RTN and RTNI instructions. The status and carry flags are recovered only by the RTNI instruction. Any area not used in the stack area is available for data storage. 11 HD404344 Series/HD404394 Series RAM Address Bit 3 Bit 2 Bit 1 Bit 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $0002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $0003 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) $0000 $0001 Interrupt control bits area Bit 3 $020 : Not used $021 IF: Interrupt request flag IE: Interrupt mask IM: Interrupt enable flag SP: Stack pointer RAME (RAM enable flag) Bit 2 Bit 1 ADSF (A/D start flag) WDON (Watchdog on flag) Bit 0 IAOF (IAD off flag) $022 $023 Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM IAOF IF RAME RSP WDON ADSF Not used SEM/SEMD REM/REMD TM/TMD Can be used Can be used Can be used Not processed Can be used Can be used Not processed Can be used Can be used Not processed Can be used Not processed Inhibited to access Not processed Inhibited to access Inhibited to access Can be used Inhibited to access * The WDON bit can be reset by an MCU reset or by stop mode release with STOPC. * Do not use REM/REMD for the ADSF bit during A/D conversion. * If the TM or TMD instruction is excuted for the inhibited or non-existing bits, the value in ST becomes invaild. Figure 4 Limitations for RAM Bit Manipulation Instructions 12 HD404344 Series/HD404394 Series Register name PMRA SMR SRL SRU TMB1 TRBL/TWBL TRBU/TWBU MIS TMC TRCL/TWCL TRCU/TWCU ACR ADRL ADRU AMR1 AMR2 PMRB PMRC TMB2 DCD0 DCD1 DCR0 DCR1 DCR2 DCR3 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F Bit 3 IM0 Bit 2 IF0 IMTC IMS IFTC IFS R03/TOC IMTB IMAD R01/SI Serial data transfer speed Serial data register (lower) Serial data register (upper) R00/SCK Reload control Pull-up control Reload control R33/AN3 RAME Bit 1 RSP Bit 0 IE IFTB IFAD R02/SO Timer B clock source Timer B register (lower) Timer B register (upper) SO PMOS control Timer C clock source Timer C register (lower) Timer C register (upper) A/D channel selection A/D data register (lower) A/D data register (upper) R31/AN1 R32/AN2 ADSF IAOF D4/STOPC R30/AN0* A/D conversion speed WDON D0/INT0/EVNB SO idle level Transmit clock EVNB edge detection D3 DCR D2 DCR D1 DCR D5 DCR D0 DCR D4 DCR R03 DCR R13 DCR R23 DCR R33 DCR R02 DCR R12 DCR R22 DCR R32 DCR R01 DCR R11 DCR R21 DCR R31 DCR R00 DCR R10 DCR R20 DCR R30 DCR* : Not used Note: * Applies to the HD404344 series. Does not apply to the HD404394 series. Figure 5 Special Register Area 13 HD404344 Series/HD404394 Series Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1 $3C0 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC 13 PC 12 PC 11 $3FD PC 10 PC 9 PC 8 PC 7 $3FE CA PC 6 PC 5 PC 4 $3FF PC 3 PC2 PC 1 PC0 PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Note: Since HD404344 series and HD404394 series have a 4-kword ROM, PC12 and PC13 are ignored. Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position 14 HD404344 Series/HD404394 Series Functional Description Registers and Flags The CPU has nine registers and two flags. Their configurations are shown in figure 7 and explained as follows. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 7 Registers and Flags 15 HD404344 Series/HD404394 Series Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers used for storing ALU operation results and data that is transferred between memory and I/O ports or between other registers. W Register (W), X Register (X), Y Register (Y): The W register is a 2-bit register and the X and Y registers are 4-bit registers. These are used for indirect addressing to RAM. The Y register is also used for addressing the D port. SPX Register (SPX), SPY Register (SPY): The SPX and SPY registers are 4-bit registers that supplement the X and Y registers, respectively. Carry Flag (CA): The carry flag latches the ALU overflow during an arithmetic instruction execution. It is controlled by the SEC, REC, ROTL, and ROTR instructions. The carry flag is stored during interrupt processing, then recovered from the stack by a RTNI instruction. (It is not affected by the RTN instruction.) Status Flag (ST): The status flag latches the overflow of ALU arithmetic instructions and compara tive instructions, and also the results of ALU non-zero and bit test instructions. It is then used for branch conditions of the BR, BRL, CAL, and CALL instructions. The status flag remains unchanged until the next arithmetic instruction, comparative instruction, or bit test is executed. After a BR, BRL, CAL, or CALL instruction is executed, the status flag will be set to 1 regardless if the instruction is executed or skipped. The contents of the status flag is stored on the stack during interrupt processing, then recovered from the stack by a RTNI instruction. Program Counter (PC): This 14-bit binary counter maintains ROM address information. Stack Pointer (SP): The stack pointer is a 10-bit register which contains the address of the next stack space to be used. It is initialized as $3FF by an MCU reset. When data is stored onto the stack, the SP is decremented by 4, and when data is pulled from the stack, it is incremented by 4. The top four bits of the stack pointer are fixed at 1111, so it can be used for a maximum of 16 levels. There are two ways of initializing the stack pointer to $3FF. One is by MCU reset and the other is by resetting the RSP bit with a REM or a REMD instruction. Reset An MCU reset is executed by setting RESET low. The RESET input must be more than t RC so as to keep the oscillator steady during power on or when stop mode is cancelled. For other cases, the MCU can be reset by a RESET input for a minimum of two instruction cycle times. Initialized values by MCU reset are listed in table 1. Certain bits in the interrupt control bits area and the register flag area can be set or reset by the SEM/SEMD or REM/REMD instructions. Also these can be tested by the TM/TMD instruction. The following specifies the limitations for each bit. 16 HD404344 Series/HD404394 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0, DCD1) All bits 0 Turns output buffer off (to high impedance) Interrupt flags/mask I/O (DCR0,- DCR3) All bits 0 Port mode register A (PMRA) - 000 Refer to description of port mode register A Port mode register B (PMRB) 0--0 Refer to description of port mode register B Port mode register C (PMRC) ---0 Refer to description of port mode register C Timer/ Timer mode register B1 (TMB1) counters, serial interface 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2 Timer mode register C (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 Refer to description of serial mode register Prescaler S (PSS) $000 -- Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer write register B (TWBU, TWBL) $X0 -- Timer write register C (TWCU, TWCL) $X0 -- 000 -- Octal counter 17 HD404344 Series/HD404394 Series Table 1 Initial Values After MCU Reset (cont) Item A/D Bit register Others Abbr. Initial Value Contents A/D mode register 1 (AMR1) 0000 Refer to description of A/D mode register A/D mode register 2 (AMR2) ---0 Refer to description of A/D mode register Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter IAD off flag (IAOF) 0 Refer to description of A/D converter Miscellaneous register (MIS) 00 - - Refer to description of I/O, and serial interface Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. Table 1 Initial Values After MCU Reset (cont) After Stop Mode Release by STOPC Input Carry (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRU, SRL) A/D data register (ADRU, ADRL) RAM After Stop Mode Release by RESET Input Program needs to initialize these registers. After Other Types of MCU Reset Program needs to initialize these registers. Data before entering stop mode are kept. RAM enable flag (RAME) 1 0 0 Port mode register B bit 3 (PMRB3) Data before entering stop mode are kept. 0 0 18 HD404344 Series/HD404394 Series Interrupts There are five kinds of interrupts: external INT 0, timer B, timer C, serial interface, and A/D converter. An interrupt request flag or an interrupt mask and vector address are used for each type of interrupt. They are used for storing interrupt requests and interrupt controls. An interrupt enable flag is also used for total interrupt control. Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped from $000 to $003 of RAM and can be accessed by RAM bit manipulation instructions. However, the interrupt request flag (IF) cannot be set by software. An MCU reset initializes the interrupt enable flag (IE) and the interrupt request flag (IF) to 0, and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 8. The interrupt priority order and vector addresses are listed in a table in the figure, along with the conditions for executing the interrupt processing of the five types of interrupt requests (table 2). An interrupt request occurs when the interrupt request flag is set to 1 and the interrupt mask to 0. If the interrupt enable flag is 1, interrupt processing has occurred. The vector address which corresponds to the interrupt source is generated from the priority PLA. The interrupt processing sequence is shown in figure 9 and the interrupt processing flowchart is shown in figure 10. After receiving an interrupt, the previous instruction is completed in the first cycle. The interrupt enable flag (IE) is reset after two cycles. The contents of the carry flag, status flag, and program counter are stored onto the stack at the second and third cycles. Instruction execution is restarted by jumping to the vector address during the third cycle. The JMPL instructions, which branch to the start addresses of the interrupt routines, should be programmed at each vector address area. The interrupt request which initiated the interrupt processing should be reset by software instructions in the interrupt routine. 19 HD404344 Series/HD404394 Series $000,0 IE Interrupt request * (RESET, STOPC ) $000,2 INT0 interrupt IF0 $000,3 IM0 $002,0 Timer B interrupt IFTB Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0008 3 $000A 4 $000C 5 $000E $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Note: * STOPC interrupt request is enabled only when the MCU is in stop mode. Figure 8 Interrupt Control Circuit, Vector Addresses, and Interrupt Priorities 20 HD404344 Series/HD404394 Series Table 2 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 Timer B Timer C A/D Serial IE 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 IFTB * IMTB * 1 0 0 0 IFTC * IMTC * * 1 0 0 IFAD * IMAD * * * 1 0 IFS * IMS * * * * 1 Note: * Can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking; IE reset Stacking; Vector address generation Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction. Figure 9 Interrupt Processing Sequence 21 HD404344 Series/HD404394 Series Power on RESET = 0? Yes No Interrupt request? No Yes No IE = 1? Yes Execute instruction Accept interrupt Reset MCU IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC) + 1 PC $0002 Yes INT0 interrupt? No PC $0008 Yes Timer B interrupt? No PC $000A Yes Timer C interrupt? No PC $000C Yes A/D interrupt? No PC $000E (serial interrupt) Figure 10 Interrupt Processing Flowchart 22 HD404344 Series/HD404394 Series Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag executes interrupt enable/disable for all interrupt requests as listed in table 3. It is reset by interrupt processing and set by the RTNI instruction. Table 3 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupt (INT0): INT0 input should be selected by using port mode register B (PMRB: $024), so that the external interrupt request flag (IF0) is set at the falling edge of the INT0 input. External Interrupt Request Flag (IF0: $000, Bit 2): The external interrupt request flag is set by the INT0 input edge, as listed in table 4. Table 4 External Interrupt Request Flag (IF0: $000, Bit 2) IF0 Interrupt Request 0 No 1 Yes External Interrupt Mask (IM0: $000, Bit 3): IM0 is a bit which masks the interrupt request caused by an external interrupt request flag, as listed in table 5. Table 5 External Interrupt Mask (IM0: $000, Bit 3) IM0 Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the overflow output of timer B, as listed in table 6. Table 6 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes 23 HD404344 Series/HD404394 Series Timer B Interrupt Mask (IMTB: $002, Bit 1): IMTB is a bit which masks the interrupt request caused by the timer B interrupt request flag, as listed in table 7. Table 7 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the overflow output of timer C, as listed in table 8. Table 8 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): IMTC is a bit which masks the interrupt request caused by the timer C interrupt request flag, as listed in table 9. Table 9 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $003, Bit 2): A serial interrupt request flag is set when the serial data transfer is completed or when the data transfer is suspended, as listed in table 10. Table 10 Serial Interrupt Request Flag (IFS: $003 Bit 2) IFS Interrupt Request 0 No 1 Yes 24 HD404344 Series/HD404394 Series Serial Interrupt Mask (IMS1: $003, Bit 3): IMS1 is a bit which masks the interrupt request caused by the serial interrupt request flag, as listed in table 11. Table 11 Serial Interrupt Mask (IMS: $003, Bit 3) IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 0): The A/D interrupt request flag is set after the A/D conversion is completed, as listed in table 12. Table 12 A/D Interrupt Request Flag (IFAD: $003, Bit 0) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 1): IMAD is a bit which masks the interrupt request caused by the A/D interrupt request flag, as listed in table 13. Table 13 A/D Interrupt Mask (IMAD: $003, Bit 1) IMAD Interrupt Request 0 Enabled 1 Disabled (masked) 25 HD404344 Series/HD404394 Series Operating Modes The MCU has three operating modes as shown in table 14. The transitions between the operating modes are shown in figure 11. Table 14 Operations in Each Operating Mode Function Active Mode Standby Mode Stop Mode System oscillator OP OP Stopped CPU OP Retained Reset RAM OP Retained Retained Timers B, C OP OP Reset Serial OP OP Reset A/D OP OP Reset I/O OP Retained* Reset Notes: OP implies in operation. * Since input/output circuits are in operation, the current will flow in/out depending on the pin status in standby mode. Note that this current is in addition to the standby mode dissipation current. Active mode SBY instruction STOP instruction Interrupt request Standby mode RESET = 0 Stop mode RESET = 1 RESET = 0 RESET = 0 MCU reset Figure 11 MCU Status Transition 26 HD404344 Series/HD404394 Series Active Mode: All functions operate in active mode. In active mode, the MCU is controlled by the oscillating circuit of OSC1 and OSC2. Standby Mode: The MCU switches to standby mode when an SBY instruction is executed. In standby mode, the oscillator continues operating, but the clocks related to instruction execution stops running. This causes the CPU to stop operating. However, the contents of RAM are retained. Also, the D and R ports, which are set as output, maintain their status before entering standby mode. The peripheral functions, such as interrupt, timers, serial interface, and A/D converter, continue operating. Power dissipation in standby mode is less than in active mode because of the CPU not operating. The MCU enters standby mode when the SBY instruction is executed in active mode. To terminate standby mode, provide a RESET input or an interrupt request. If a reset input is given, the MCU will be reset. If an interrupt request is given, the MCU will change to active mode and the next instruction will be executed. After the instruction execution, if the interrupt enable flag is 1, the interrupt operation is executed. If the interrupt enable flag is 0, normal instruction execution continues and the interrupt request is left pending. The standby mode flowchart is shown in figure 13. Stop Mode: The MCU enters stop mode when a STOP instruction is received. In stop mode, all MCU functions stop, except for maintaining RAM data. Power dissipation in this mode is therefore the lowest of all operating modes. In stop mode, the OSC1 and OSC2 oscillator is stopped. To terminate stop mode provide either a RESET or STOPC input as shown in figure 12. When terminating stop mode, it is important to ensure a proper oscillation stabilization period of at least t RC for the RESET or STOPC input. (Refer to the AC characteristics tables.) After clearing stop mode, the RAM maintains its data kept before entering stop mode. However, the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and the serial data register are not maintained. Clearing Stop Mode Using STOPC: The MCU is transition from stop mode to active mode by either a RESET or STOPC input. The MCU starts instruction execution from the start of the program at address 0. Then the RAM enable flag (RAME: $021, 3) is set accordingly, RAME = 0 for RESET input and RAME = 1 for STOPC input. A RESET input is effective when the MCU is in any mode. A STOPC input however, is effective only in stop mode and is ignored in other modes. So, when clearing stop mode with a STOPC input the program needs to identify the RAME status. (For example, when the RAM contents before entering stop mode is used after transition to active mode.) A TEST instruction for the RAM enable flag (RAME) should be executed at the beginning of the program. 27 , , HD404344 Series/HD404394 Series Table 15 Operating Modes and Transition Conditions Mode Conditions to Enter Mode Conditions to Exit Mode Active mode * RESET release * RESET input * Interrupt request * STOP/SBY instruction * STOPC release in stop mode * SBY instruction * RESET input * Interrupt request * RESET input * STOPC input in stop mode Standby mode * Stop mode STOP instruction Stop mode Oscillator Internal clock RESET or STOPC tres STOP instruction execution tres tRC (stabilization period) Figure 12 Timing of Stop Mode Cancellation 28 HD404344 Series/HD404394 Series Standby Stop Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop No RESET = 0? Yes Oscillator: Active Peripheral clocks: Active All other clocks: Stop RESET = 0? Yes No No IF0 * IM0 = 1? No STOPC = 0? Yes Yes IFTB * IMTB = 1? Yes No IFTC * IMTC = 1? Yes RAME = 1 No IFAD * IMAD = 1? No RAME = 0 Yes IFS * IMS = 1? No Yes Restart processor clocks Execute next instruction No Restart processor clocks IF = 1, IM = 0, and IE = 1? Yes Reset MCU Execute next instruction Interrupt accept Figure 13 MCU Process Flowchart 29 HD404344 Series/HD404394 Series MCU Operation Sequence: The MCU operates according to the flowcharts shown in figures 14 to 16. Since RESET is asynchronous input, the MCU will be reset in any mode that the MCU is operating in. The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 0? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 14 MCU Operation Sequence (Power On) 30 HD404344 Series/HD404394 Series MCU operation cycle IF = 1? No Yes No IM = 0 and IE = 1? Yes Instruction execution Yes SBY/STOP instruction? IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 15 MCU Operation Sequence (MCU Operation Cycle) 31 HD404344 Series/HD404394 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Standby mode (SBY) Stop mode * No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle Note: * For IF and IM operation, refer to figure 13. Figure 16 MCU Operation Sequence (Low Power Mode Operation) 32 HD404344 Series/HD404394 Series Oscillator Circuit Figure 17 shows a block diagram of the clock generation circuit. Ceramic oscillator can be connected to OSC1 and OSC2 as listed in table 16. An external clock can also be connected. OSC2 1/4 System fOSC division oscillator circuit fcyc tcyc Timing generator circuit System clock generation oCPU CPU with ROM, RAM, registers, flags, and I/O oPER Peripheral function interrupt OSC1 Figure 17 Clock Generation Circuit R23 OSC1 OSC2 GND : GND Figure 18 Typical Layout of Ceramic Oscillator 33 HD404344 Series/HD404394 Series Table 16 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation Ceramic oscillator (OSC1, OSC2) External oscillator OSC 1 Open OSC 2 Ceramic oscillator : CSA4.00MG (Murata) C1 OSC1 Ceramic oscillator Rf C1 = C2 = 30 pF 20% Ceramic oscillator: KBR-4.0MSA (Kyocera) OSC2 C2 Rf = 1 M 20% Rf = 1 M 20% C1 = C2 = 33 pF 20% GND Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 18). 34 HD404344 Series/HD404394 Series Input/Output The HD404344 series MCU has 22 input/output pins (D0-D5, R00-R3 3) and the HD404394 MCU has 21 input/output pins (D0-D5, R00-R2 3, R3 1-R3 3). These input/output pins have the following features: * All 22 pins for the HD404344 series have a CMOS output circuit. Ten pins D1, D2, and R10-R2 3 are large current input/output pins. * Three input/output pins of the 21 pins on the HD404394 series, R10-R12, have intermediate-voltage NMOS open drain output circuits. Five other input/output pins, R13 and R20-R23, have standard-voltage NMOS open drain output circuits. The remaining 13 input/output pins, D0-D5, R00-R0 3 and R31-R33, have CMOS output circuits. Ten pins D1, D2, and R10-R2 3 are high-current input/output pins. * Some input/output pins are multiplexed with peripheral functions, such as for the timers and serial interface. For these pins, the settings for peripheral functions are done prior to the D or R ports settings. If these pins are set as peripheral functions, the pin functions and input/output selections automatically switch according to the settings. * Program control of input/output port selection, as well as peripheral function selection. * All peripheral function output pins are CMOS output pins. However, the R0 2/SO pin can be programmed to be NMOS open drain output. * In stop mode, all peripheral function selections are cleared because of the MCU being reset. Also, the input/output pins go into a high-impedance state. * All input/output pins for both the HD404344 series and the HD404394 series except for pins R1 0-R2 3, have built-in pull-up MOS. Therefore they can be individually turned on or off by software. * When pin functions are set as peripheral functions after selecting the pins as pull-up MOS, the pins are maintained as pull-up MOS from the time of selection. Also, pull-up MOS can be selected by software after setting the pin functions as peripheral functions. The control of the input/output pins are shown in table 17 and the circuit configuration of each input/output pin is shown in table 18. Table 17 Programmable Control of Standard I/O Pins MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS 1 1 0 1 Note: -- indicates off. 35 HD404344 Series/HD404394 Series Table 18 Circuit Configurations of I/O Pins Pins I/O Pin Type Input/output pins Circuit VCC Pull-up control signal VCC HLT MIS3 Buffer control signal DCD, DCR Output data HD404344 Series HD404394 Series D0-D5, D0-D5, R00, R01 R00, R01 R03, R03, R10-R33 R31-R33 None R13, PDR Input data Input control signal VCC VCC Buffer control signal HLT R20-R23 DCR Output data (standard voltage pins) PDR Input data Input control signal VCC VCC Pull-up control signal HLT MIS3 R02 R02 None R10-R12 Buffer control signal Output data DCR MIS2 PDR Input data Input control signal HLT DCR PDR Input data Input control signal 36 (middle voltage pins) HD404344 Series/HD404394 Series Table 18 Circuit Configurations of I/O Pins (cont) Pins I/O Pin Type Peripheral function pins Circuit Input/ output pins VCC VCC HLT MIS3 Pull-up control signal Output data Input data Output pins VCC VCC HD404344 Series HD404394 Series SCK SCK SO SO TOC TOC SI, INT0, SI, INT0, EVNB, EVNB, STOPC STOPC AN0-AN3 AN1-AN3 SCK SCK HLT MIS3 Pull-up control signal PMOS control signal MIS2 Output data SO VCC VCC HLT MIS3 Pull-up control signal Output data Input pins TOC HLT MIS3 PDR VCC Input data SI, INT0, EVNB, STOPC HLT MIS3 PDR VCC A/D input Input control Note: In stop mode, the MCU is reset and the peripheral function selection is cancelled. Also, the HLT signal goes low, and input/output pins enter a high-impedance state. 37 HD404344 Series/HD404394 Series D Port The D port consists of six input/output pins each addressed by one bit. The D ports can be set and reset by SED/RED and SEDD/REDD instructions. Output data is stored in the port data register (PDR) for each pin. Also, all D ports can tested by the TD/TDD instructions. The on/off status of the output buffers is controlled by the D-port data control registers (DCD0, DCD1: $02C and $02D), which are mapped to memory addresses (figure 19). Pins D0 and D4 are multiplexed with peripheral function pins INT0/EVNB, and STOPC. Setting of the peripheral functions for these pins is executed by bits 3 and 0 (PMRB3, PMRB0) of port mode register B (PMRB: $024) (figure 20). Data control register (DCD0, DCD1: $02C, $02D) (DCR0 to DCR3: $030 to $033) DCD0, DCD1 DCR0 to DCR3 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W DCD03 DCD02 DCD01 to DCD11 DCD00 to DCD10 DCR03 to DCR33 DCR02 to DCR32 DCR01 to DCR31 DCR00 to DCR30 Bit name Bits 0 to 3 CMOS Buffer Control 0 CMOS buffer off (high impedance) 1 CMOS buffer on Correspondence between ports and DCR bits Register Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 -- -- D5 D4 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30* Note: * Available for the HD404344 series, but not available for the HD404394 series. Figure 19 Data Control Register (DCR) 38 HD404344 Series/HD404394 Series Port mode register B (PMRB: $024) Bit 3 2 1 Initial value 0 -- -- 0 Read/Write W -- -- W Bit name 0 PMRB3 Not used Not used PMRB0 PMRB3 D4/STOPC Mode Selection PMRB0 D0/INT0 /EVNB Mode Selection 0 D4 0 D0 1 STOPC 1 INT0 /EVNB Figure 20 Port Mode Register B (PMRB) 39 HD404344 Series/HD404394 Series R Port The R port consists of input/output pins each addressed by 4 bits. Input/output is controlled by the LAR and LBR instructions and the LRA and LRB instructions. The output data is stored in the port data register (PDR) of each pin. The on/off status of the output buffers is controlled by the R-port data control registers (DCR0-DCR3: $030-$033), which are mapped to memory addresses (figure 19). The R10-R1 2 ports of the HD404394 series are n-channel middle-voltage open drain input/output pins. The R00-R03 pins are also used as peripheral function pins: SCK, SI, SO, and TOC. Setting of the peripheral functions for these pins is executed by bit 3 (SMR3) of the serial mode register (SMR:$005) and by bits 2 to 0 (PMRA2-PMRA0) of port mode register A (PMRA: $004), as shown in figures 21 and 22. The R3 0-R3 3 pins of the HD404344 series are also used as AN0-AN3 peripheral function pins. Pins R31- R3 3 of the HD404394 series are also used as AN 1-AN3 peripheral function pins. The setting of peripheral functions for these pins is executed by bits 3 to 0 (AMR13-AMR10) of A/D mode register 1 (AMR1: $019). For the HD404394 series, the use of AMR10 is prohibited (figure 23). Port mode register A (PMRA: $004) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W Bit name 2 1 0 Not used PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC R02/SO Mode Selection 0 R02 1 SO PMRA1 R01/SI Mode Selection 0 R01 1 SI Figure 21 Port Mode Register A (PMRA) 40 HD404344 Series/HD404394 Series Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK SCK Clock Source Prescaler Division Ratio Output Prescaler See table 22. 0 Output System clock -- 1 Input External clock -- SMR2 SMR1 SMR0 0 0 0 1 0 1 1 1 0 0 1 1 Figure 22 Serial Mode Register (SMR) A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W AMR13 AMR12 AMR11 AMR10 AMR10* AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Note: * Available for the HD404344 series, but not available for the HD404394 series. Figure 23 A/D Mode Register 1 (AMR1) 41 HD404344 Series/HD404394 Series Pull-Up MOS Transistor Control Pull-up MOS, which can be controlled by software, is built into all input/output pins except R10-R2 3 of the HD404394 series. The on/off status of all pull-up MOS pins is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C) and the port data registers (PDR) of each pin. Each pin can therefore independently switch between with or without pull-up MOS (table 17 and figure 24). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W MIS3 MIS2 MIS1 MIS0 PMOS On/Off Selection for Pin R02/SO MIS3 Pull-Up MOS On/Off Selection MIS2 0 Pull-up MOS off 0 On 1 Pull-up MOS on 1 Off Programming MIS1 and MIS0 to 1 is prohibited. Figure 24 Miscellaneous Register How to Deal with Unused I/O Pins When input/output pins are not being used and are left floating, it is necessary to set these pins to VCC to reduce the possibility of LSI malfunctions due to noise. This can be done by selecting pull-up MOS for the pins or by connecting an external pull-up resistor of about 100 k at each unused pin. 42 HD404344 Series/HD404394 Series Prescaler The MCU has one built-in prescaler, S (PSS). This divides the system clock and outputs the divided clock to the peripheral function modules as shown in figure 25. Clocks for timers B and C except for external events, and clocks for serial interface except for the external clock are all selected from the prescaler output by programming each mode register. Prescaler S is an 11-bit counter which inputs the system clock. After an MCU reset clears the prescaler to $000, it begins dividing the system clock. Prescaler S stops operating due to either an MCU reset or stop mode. It cannot be stopped by any other mode. Timer B Timer C System clock Prescaler S Serial Figure 25 Prescaler Output Supply 43 HD404344 Series/HD404394 Series Timers The MCU has two built-in timers, B and C. The functions of each timer are listed in table 19. Table 19 Timer Functions Functions Clock source Timer functions Timer output Timer B Timer C Prescaler S Available Available External event Available -- Free-running Available Available Event counter Available -- Reload Available Available Watchdog -- Available PWM -- Available Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and event counter features. These are described as follows. * By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter. * By setting timer mode register B2 (TMB2: $026), timer B can be incremented by each edge detector of input signals at pin EVNB. * By setting timer write register BL, BU (TWBL, TWBU: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation. * By setting timer read register BL, BU (TRBL, TRBU: $00A, $00B), the contents of timer counter B can be read out. Timer B Operation * Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register B1 (TMB1: $009). Timer B is initialized to the data which is written to timer write register B (TWBL: $00A, TWBU: $00B) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input is continued after timer B is set to $FF, an overflow occurs. Timer B then begins counting again, setting the timer to the value in timer write register B (TWBL: $00A, TWBU: $00B) when the reload timer is selected, or reset to $00 when the free-running timer is selected. 44 HD404344 Series/HD404394 Series The timer B interrupt request flag is set by an overflow. Resetting the timer B interrupt request flag (IFTB: $002, bit 0) is executed by either software or by an MCU reset. * External event counter operation: By setting the external event input as an input clock source, timer B can operate as an external event counter. The D0/INT 0/EVNB pins are set to be INT0/EVNB pins by port mode register B (PMRB: $024). The detection edge of the external event counter for timer B is selected as rising edge, falling edge, or rising/falling edge by timer mode register B2 (TMB2: $026). When the rising/falling edge is selected, the period must be set to more than 2tcyc between the falling edge and the rising edge. Timer B is incremented by 1 using the edge selection in timer mode register B2 (TMB2: $026). Other functions are based on the free-running/reload timer. Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Timer counter B (TCB) Free-running timer control Overflow Timer write register B upper (TWBU) /2 /4 /8 /32 /128 /512 /2048 Edge detector System clock Timer write register B lower (TWBL) Selector EVNB oPER 2 Internal data bus Clock 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control Timer mode register B2 (TMB2) Figure 26 Timer B Free-Running and Reload Operation Block Diagram 45 HD404344 Series/HD404394 Series Using Timer B Registers Timer B sets the operation and the read/write data according to the following registers. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $026) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register B (PMRB: $024) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 27. It is reset to $0 by an MCU reset. Data written to timer mode register B1 is valid after two instruction cycles. The initial setting of timer B, which is set by writing to timer write register B (TWBL: $00A, TWBU: $00B), should be programmed only after a mode change has been effective. Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D0/INT0/EVNB (external event input) 1 1 0 1 Figure 27 Timer Mode Register B1 (TMB1) 46 HD404344 Series/HD404394 Series * Timer mode register B2 (TMB2: $026): Two-bit write-only register that sets the input edge detection of pin EVNB, as shown in figure 28. It is reset to $0 by an MCU reset. Timer mode register B2 (TMB2: $026) Bit 3 2 Initial value -- -- 0 0 Read/Write -- -- W W Bit name 0 1 Not used Not used TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Rising- and falling-edge detection 1 EVNB Edge Detection Selection Figure 28 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit value cannot be guaranteed. See figures 29 and 30. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 29 Timer Write Register B (lower) (TWBL) Timer write register B (upper) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 30 Timer Write Register B (upper) (TWBU) 47 HD404344 Series/HD404394 Series * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit. See figures 31 and 32. The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained. Timer read register B (lower) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 31 Timer Read Register B (lower) (TRBL) Timer read register B (upper) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 32 Timer Read Register B (upper) (TRBU) * Port mode register B (PMRB: $024): Write-only register that selects the D0/INT 0/EVNB pin as shown in figure 20. It is reset to $0 by an MCU reset. 48 HD404344 Series/HD404394 Series Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are selected and described as follows. * By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected. * By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled. * By setting timer write register CL, CU (TWCL, TWCU: $00E, $00F), timer counter C (TCC) can be written to. * By setting timer read register CL, CU (TRCL, TRCU: $00E, $00F), the contents of timer counter C can be read out. * An interrupt can be requested when timer counter C overflows. * Timer counter C can be used as a watchdog timer for detecting runaway programs. 49 HD404344 Series/HD404394 Series System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output controller Timer read register C lower (TRCL) Clock Timer output control /2 /4 /8 /32 /128 /512 /1024 /2048 Selector System clock oPER Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running/ reload timer control Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 33 Timer C Block Diagram Timer C Operation * Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source, and prescaler division ratio is done by timer mode register C (TMC: $00D). Timer C is initialized to the data, which is written to timer write register C (TWCL: $00E, TWCU: $00F) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input is continued after timer C is set to $FF, an overflow occurs. Timer C then begins counting again, setting the timer to the value in timer write register C (TWCL: $00E, TWCU: $00F) when the reload timer is selected, or reset to $00 when the free-running timer is selected. The timer C interrupt request flag is set by an overflow. Resetting the timer C interrupt request flag (IFTC: $002, bit 2) is executed by either software or by an MCU reset. 50 HD404344 Series/HD404394 Series * Watchdog timer operation: Timer C can be used as a watchdog timer for programs that may run out of control. A watchdog timer is enabled when the setting on the watchdog on flag (WDON: $020, bit 1) is 1. When timer C overflows, an MCU reset occurs. This usually controls programs running out of control by initializing timer C through software before timer C counts up to $FF (figure 34). $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Reset Normal operation Figure 34 Watchdog Timer Operation Flowchart * Timer output operation: Timer C can select the timer output mode by selecting the TOC pin after setting bit 2 (PMRA2) of port mode register A (PMRA: $004) to 1. The output of the TOC pin is initialized to 0 by an MCU reset. PWM output is a pulse output function of variable duty. The output wave differs by the contents of timer mode register C and timer write register C, as shown in figure 35. T x (N + 1) TMC3 = 0 (free-running timer) T T x 256 TMC3 = 1 (reload timer) T x (256 - N) Notes: T: Input clock period supplied to counter. (The clock input source and system clock division ratio are determined by timer mode register C.) N: Value in timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 35 PWM Output Waveform 51 HD404344 Series/HD404394 Series Using Timer C Registers Timer C sets the operation and the read/write data according to the following registers. Timer mode register C (TMC: $00D) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload timer, input clock, and prescaler division ratio, as shown in figure 36. It is reset to $0 by an MCU reset. The data written to timer mode register C is valid after two instructions cycles. The initial setting of timer C, which is set by writing to timer write register C (TWCL: $00E, TWCU: $00F), should be programmed to execute only after a mode change has been effective. Timer mode register C (TMC: $00D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 36 Timer Mode Register C (TMC) 52 HD404344 Series/HD404394 Series * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL: $00E) and an upper digit (TWCU: $00F), as shown in figures 37 and 38. The operation of this register is the same as that of timer write register B. Timer write register C (lower) (TWCL: $00E) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 37 Timer Write Register C (lower) (TWCL) Timer write register C (upper) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 38 Timer Write Register C (upper) (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL: $00E) and upper digit (TRCU: $00F), which allows the upper digit of timer C to be read directly (figures 39 and 40). The operation of this register is the same as that of timer read register B. Timer read register C (lower) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 39 Timer Read Register C (lower) (TRCL) Timer read register C (upper) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 40 Timer Read Register C (upper) (TRCU) 53 HD404344 Series/HD404394 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 20. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 20 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High Timer Write Register is Updated during Low PWM Output PWM Output Timer write register updated to value N Free running Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Reload Timer write register updated to value N T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 54 T x (N + 1) T HD404344 Series/HD404394 Series Serial Interface The MCU has a one-channel 8-bit serial interface built in with the following features. * One of 12 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. * During idle states, the serial output pin can be controlled as high or low output. * Transmit clock errors can be detected. * An interrupt request can be generated when any errors occurred or data transfer has completed. Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Internal data bus Serial data register (SR) Selector /2 /8 /32 /128 /512 /2048 3 System clock oPER Prescaler S (PSS) Serial mode register (SMR) Port mode register C (PMRC) Figure 41 Serial Interface Block Diagram 55 HD404344 Series/HD404394 Series Serial Interface Operation Selection and Changing of Serial Interface Operation Mode: The available settings for port mode register A (PMRA: $004) and the serial mode register (SMR: $005) are shown in table 21. To change the operating mode or to initialize the serial interface, write to the serial mode register. The R0 0/SCK pin is controlled by writing data to serial mode register (SMR: $005). The R01 /SI and R0 2/SO pins are controlled by writing data to port mode register A (PMRA: $004). Table 21 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Setting Serial Clock Source: The transmit clock is set by writing to the serial mode register (SMR: $005) and port mode register C (PMRC: $025). Serial Data Setting: Serial data is sent by writing to the serial data register (SRL: $006 and SRU: $007). Serial data can then be obtained by reading the serial data register. Serial data is shifted by the transmit clock. The output of the SO pin is undefined until the first serial data is output after an MCU reset, or until the output level control is performed during an idle state. Transfer Control: Serial interface operation is initiated by an STS instruction. The octal counter is reset by the STS instruction to 000 and then incremented by one by the rising edge of the transmit clock. If eight rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and the serial data transfer stops. As for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency can be from 4tcyc to 8192t cyc by setting bits 2 to 0 (SMR2-SMR0) of the serial mode register (SMR: $005) and bit 0 (PMRC0) of port mode register C (PMRC: $025). Writing to these registers for the setting of the transmit clock is shown in table 22. 56 HD404344 Series/HD404394 Series Table 22 Transmit Clock Selection (Prescaler Output) PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 0 Serial Interface Operating States: The serial interface has the following operating states shown in figure 42, both in external clock mode and internal clock mode. STS wait state Transmit clock wait state Transfer state Continuous clock output (internal clock mode only) * STS wait state: The serial interface is put into the STS wait state by an MCU reset (00, 10 in figure 42). While in this state, the serial interface is initialized and does not operate, even if a transmit clock is provided. If an STS instruction is executed while in this state (01, 11), the serial interface transfers to the transmit clock wait state. * Transmit clock wait state: Transmit clock wait state period starts from when an STS instruction is executed until the first transmit clock falling edge. While in the transmit clock wait state, if the transmit clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data register shifts, and the serial interface enters the transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). By writing to the serial mode register (SMR: $005) (04, 14) while in the transmit clock wait state, the serial interface changes to the STS wait state. * Transfer state: The transfer state period starts from the first falling edge of the transmit clock to the eighth rising edge of the transmit clock. While in the transfer state, if an STS instruction is executed or eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change. If an STS instruction is executed (05, 15), the state changes to the transmit clock wait state. After the 57 HD404344 Series/HD404394 Series eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock mode (03). Also, the state changes to the STS wait state for the internal clock mode (13). In the internal clock mode, the transmit clock stops after eight pulses of the transmit clock are output. While in the transfer state, if the serial mode register (SMR: $005) (06, 16) is written to, the serial interface is initialized and the state changes to the STS wait state. After the transfer state has changed to another state, the octal counter is reset to 000 and the serial interrupt request flag (IFS: $003, 2) is set. * Continuous clock output state (internal clock mode only): Continuous clock output state is the state in which only the transmit clock from the SCK pin is output without data transfer. This can be done only while in internal clock mode. When the status of the 1 and 0 bits (PMRA1, PMRA0) of port mode register A (PMRA: $004) is 00 while in transmit clock wait state, the state can be changed to continuous clock output state by enabling the transmit clock (17). By writing to the serial mode register (SMR: $005) while in continuous clock output state (18), the state will change to the STS wait state. STS wait state (Octal counter = 000, transmit clock disabled) MCU reset 00 SMR write (IFS 1) 06 SMR write 04 STS instruction 01 Transmit clock 02 Transfer state (Octal counter = 000) Transmit clock wait state (Octal counter = 000) 8 transmit clocks 03 or STS instruction 05 (IFS 1) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write 18 Continuous clock output state (PMRA 0, 1 = 0, 0) SMR write 14 STS instruction 11 MCU reset 10 8 transmit clocks 13 or SMR write (IFS 1) 16 Transmit clock 17 Transmit clock 12 Transmit clock wait state (Octal counter = 000) STS instruction 15 (IFS 1) Internal clock mode Note: Refer to the operating states section for the corresponding encircled numbers. Figure 42 Serial Interface State Transitions 58 Transfer state (Octal counter = 000) , HD404344 Series/HD404394 Series Output Level Control During Idle States: The output level of the SO pin can be set during either STS wait state or transmit clock wait state by software. During idle states, the output level is controlled by writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control during idle states is shown in figure 43. During transfer state, output level control cannot be executed. Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states Dummy write for state transition Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 43 Example of Serial Interface Operation Sequence 59 HD404344 Series/HD404394 Series Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock error of this type can be detected as shown in figure 44. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005) changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write Yes IFS = 1? Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000. Transmit clock error detection procedure Figure 44 Transmit Clock Error Detection 60 Flag reset at transfer completion. HD404344 Series/HD404394 Series Notes On Use: * Initializing after writing to registers: If port mode register A (PMRA: $004) is written to in the transmit clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode register (SMR: $005). * Serial interrupt request flag (IFS: $003, bit 2) set: For the serial interface, if the state is changed from transfer state to another by writing to serial mode register (SMR:$005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $003, bit 2) is not set. To set the serial interrupt request flag (IFS: $003, bit 2), a serial mode register (SMR: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written using the following registers: * * * * * Serial mode register (SMR: $005) Port mode register C (PMRC: $025) Serial data registers (SRL: $006 and SRU: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Serial Mode Register (SMRA: $005): This register has the following functions (figure 45): * * * * R0 0/SCK pin function selection Selection of transmit clock Selection of prescaler division ratio Serial interface initialization The write-only serial mode register is reset to $0 by an MCU reset. Writing to the serial mode register discontinues the transmit clock input to the serial data registers (SRL: $006 and SRU: $007) and the octal counter. The octal counter is then reset to 000. If the serial mode register is written to during serial interface operation, data transfer will be cut off and the serial interrupt request flag (IFS: $003, bit 2) will be set. Data in the serial mode register becomes effective after two instruction execution cycles from the time the serial mode register is written to. It is therefore necessary to program the STS instruction to be executed two cycles after the serial mode register is written to. 61 HD404344 Series/HD404394 Series Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK SCK Clock Source Prescaler Division Ratio Output Prescaler See table 22. 0 Output System clock -- 1 Input External clock -- SMR2 SMR1 SMR0 0 0 0 1 1 0 1 1 0 0 1 1 Figure 45 Serial Mode Register (SMR) Port Mode Register C (PMRC: $025): This register has the following functions: * Prescaler division ratio selection * Output level control during idle states Port mode register C is a two-bit write-only register, which cannot be changed during data transfer. Bit 0 (PMRC0) selects the prescaler division ratio. Only this bit is reset to 0 by an MCU reset. Bit 1 enables the output level control of the SO pin during an idle state. The output levels at the pins are therefore changed when writing to bit 1 (PMRC1). 62 HD404344 Series/HD404394 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value -- -- Undefined 0 Read/Write -- -- W W Bit name Not used Not used PMRC1 PMRC0 PMRC0 Transmit Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 46 Port Mode Register C (PMRC) 63 HD404344 Series/HD404394 Series Serial Data Register (SRL: $006, and SRU: $007): This register has the following functions (figures 47 and 48): * Transmission data write and shift * Receive data shift and read Data written to the serial data registers is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock. Also, data from the SI pin (from the LSB) is input synchronously with the rising edge of the transmit clock. Reading or writing to the serial data register should be performed after data transfer. Read/write operation to this register during data transfer does not guarantee valid data. The input/output timing chart for the transmit clock and the data are shown in figure 49. Serial data register (lower) (SRL: $006) Bit 2 3 Initial value 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 47 Serial Data Register (SRL) Serial data register (upper) (SRU: $007) Bit 2 3 Initial value 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 48 Serial Data Register (SRU) Ttransmit clock 1 Serial output data 2 3 4 5 LSB Serial input data latch timing Figure 49 Serial Interface Timing 64 6 7 8 MSB HD404344 Series/HD404394 Series Port Mode Register A (PMRA: 004): This register A has the following functions: * R0 1/SI pin function selection * R0 2/SO pin function selection Port mode register A is a three-bit write-only register and reset to 0 by an MCU reset, as listed in figure 50. Port mode register A (PMRA: $004) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W Bit name 2 1 0 Not used PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC R02/SO Mode Selection 0 R02 1 SO PMRA1 R01/SI Mode Selection 0 R01 1 SI Figure 50 Port Mode Register A (PMRA) Miscellaneous Register The miscellaneous register (MIS: $00C) has the following functions: * Control of R0 2/SO pin PMOS * Pull-up MOS on/off selection It is a two-bit write-only register and is reset to $0 by an MCU reset, as listed in figure 51. 65 HD404344 Series/HD404394 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W MIS3 MIS2 MIS1 MIS0 PMOS On/Off Selection for Pin R02/SO MIS3 Pull-Up MOS On/Off Selection MIS2 0 Pull-up MOS off 0 On 1 Pull-up MOS on 1 Off Programming MIS1 and MIS0 to 1 is prohibited. Figure 51 Miscellaneous Register 66 HD404344 Series/HD404394 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a register ladder. It can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. The following describes the features of the A/D converter. * A/D mode register 1 (AMR1: $019) is used to select digital or analog ports (figure 53). * A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed (figure 54). * The A/D channel register (ACR: $016) is used to select an analog input channel (figure 55). * A/D conversion is started by setting the A/D start flag (ADSF: $020, bit 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is cleared to 0 (figure 56). * By setting the IAD off flag (IAOF: $021, bit 2) to 1, the current flowing through the resistance ladder can be cut off even in standby or active mode (figure 57). * A/D data registers (ADRL: $017, ADRU: $018) are read-only registers used to store the conversion result. (ADRL: lower 4 bits, ADRU: upper 4 bits.) These registers cannot be cleared by a reset input. Also, data in these registers are not guaranteed during the conversion period. After the conversion is completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58, 59, and 60). Notes On Use: * Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF). * Do not write to the A/D start flag during A/D conversion. * Data in the A/D data register during A/D conversion is undefined. * Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power dissipation while in a stop mode, all current flowing through the converter's resistance ladder is cut off. * Output signal level from other ports should be fixed during A/D conversion. * The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC . When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up. 67 HD404344 Series/HD404394 Series 4 A/D mode register 1 (AMR1) 4 A/D mode register 2 (AMR2) Selector R33/AN3 R32/AN2 R31/AN1 Encoder A/D data registers (ADRU, L) *1 (R30/AN0) + Comp - D/A VCC (Vref)*2 A/D controller Control signal for conversion time A/D start flag (ADSF) A/D channel register (ACR) IAD off flag (IAOF) VSS Operating mode signal (1 in stop mode) Notes: 1. Available for the HD404344 series. Not available for the HD404394 series. 2. Connected to VCC for the HD404344 series. Connected to Vref for the HD404394 series. Figure 52 A/D Converter Block Diagram 68 Internal data bus A/D interrupt request flag (IFAD) HD404344 Series/HD404394 Series A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10* AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Note: * Available for the HD404344 series, but not available for the HD404394 series. Figure 53 A/D Mode Register 1 (AMR1) A/D mode register 2 (AMR2: $01A) Bit 3 2 1 Initial value -- -- -- 0 Read/Write -- -- -- W Bit name 0 Not used Not used Not used AMR20 AMR20 Conversion Time 0 34tcyc 1 67tcyc Figure 54 A/D Mode Register 2 (AMR2) 69 HD404344 Series/HD404394 Series A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W ACR3 ACR2 ACR1 ACR0 ACR3 ACR2 ACR1 ACR0 0 0 0 1 Analog Input Selection 0 AN0* 1 AN1 0 AN2 1 AN3 Note: * Available for the HD404344 series, but not available for the HD404394 series. Figure 55 A/D Channel Register (ACR) A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value -- 0 0 -- Read/Write -- R/W W -- Not used ADSF Bit name WDON Not used WDON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of timers Figure 56 A/D Start Flag (ADSF) 70 HD404344 Series/HD404394 Series IAD off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 -- -- Read/Write R/W R/W -- -- RAME IAOF Bit name Not used Not used IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off RAME Refer to the description of operating modes Figure 57 IAD Off Flag (IAOF) ADRU: $018 3 2 1 ADRL: $017 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Result Figure 58 A/D Data Register A/D data register lower (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R R R R ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 59 A/D Data Register Lower (ADRL) 71 HD404344 Series/HD404394 Series A/D data register upper (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 ADRU1 ADRU0 Bit name Figure 60 A/D Data Register Upper (ADRU) 72 HD404344 Series/HD404394 Series Pin Description in PROM Mode The HD4074344 and the HD4074394 are PROM versions of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-28S/FP-28DA FP-30D Pin I/O Pin I/O 1 1 R10 I/O A5 I 2 2 R11 I/O A6 I 3 3 R12 I/O A7 I 4 4 R13 I/O A8 I 5 5 R20 I/O A9 I 6 6 R21 I/O A10 I 7 7 R22 I/O A11 I 8 8 R23 I/O A12 I 9 9 OSC1 I OE I 10 10 OSC2 O 11 11 GND GND 12 NC 12 13 R30/AN0 or Vref I/O or Vref 13 14 R31/AN1 I/O M0 I 14 15 R32/AN2 I/O XON I I/O O0 I/O 15 Remarks 2 16 R33/AN3 17 NC 16 18 VCC 17 19 TEST I VPP I 18 20 RESET I RESET I 19 21 R00/SCK I/O O1 I/O 20 22 R01/SI I/O O2 I/O 21 23 R02/SO I/O O3 I/O 22 24 R03/TOC I/O O4 I/O 23 25 D0/INT0/EVNB I/O A0 I 24 26 D1 I/O A1 I 25 27 D2 I/O A2 I 26 28 D3 I/O A3 I 27 29 D4/STOPC I/O CE I 28 30 D5 I/O A4 I VCC Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. R30/AN0 is for the HD404344 and Vref for the HD404394 in MCU mode. 73 HD404344 Series/HD404394 Series Programmable ROM Operation The HD4074344 and HD4074394 on-chip PROMs are programmed in PROM mode. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a socket adapter as shown in figure 61. Table 23 lists the recommended PROM programmers and socket adapters. Since instructions of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputers incorporate a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit, an instruction is read or written to using two addresses, lower five bits and upper five bits. For example, if 4 kwords of on-chip PROM are programmed by a general-purpose PROM programmer, 8 kbytes of addresses ($0000-$1FFF) should be specified. CE, OE Control signals 2 A12-A0 A12-A0 3 O4-O0 A14 , A13 O4-O0 O7-O0 Data bus VCC GND VPP 28-to-28-pin socket adapter 30-to-28 pin socket adapter Figure 61 PROM Mode Connections 74 Address bus O7 -O5 XON M0 RESET VCC GND VPP HD4074344 HD4074394 A14-A0 PROM programmer HD404344 Series/HD404394 Series Table 23 PROM Programmer and Socket Adapter PROM Programmer Maker Type Name DATA I/O UNISITE AVAL Corp. PKW-3100 Socket Adapter Package Maker Type Name DP-28S Hitachi HS4344ESS01H FP-28DA HS4344ESP01H FP-30D HS4344ESF01H Programming and Verification The HD4074344 and HD4074394 can be high-speed programmed without causing voltage stress or affecting data reliability. Table 24 shows how programming and verification modes are selected. Table 24 PROM Mode Selection Pin Mode CE OE VPP O0-O4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance Precautions 1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer. If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Note that the plastic package type devices cannot be erased and reprogrammed. Set all data in unused addresses to $FF. 2. Be careful of not using the wrong PROM programmer or socket adapter, which may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and that the socket adapter is firmly fixed to the programmer. 3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the HD4074344 or HD4074394, the LSI may become permanently damaged. 12.5 V is Intel's 27256 VPP. 75 HD404344 Series/HD404394 Series Addressing Modes RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 digits from $040 to $04F, are accessed with the LAMR and XMRA instructions. ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. 10 3 W 9 0 3 X 7 0 3 Y 3 Instruction 0 Opcode 9 0 RAM address RAM address 0 0 0 1 0 0 Register Indirect Addressing Memory Register Addressing 9 Instruction 1st instruction 2nd instruction word word 09 0 Opcode 9 0 RAM address Direct Addressing Figure 62 RAM Addressing Modes 76 0 HD404344 Series/HD404394 Series Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000-$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction. 2nd instruction word 1st instruction word 9 3 Opcode 09 0 Opcode 9 5 Operand 13 0 Operand 0 13 Program counter 0 Program counter 0 0 0 0 0 0 0 0 Direct Addressing Zero-Page Addressing Operand Opcode 9 7 0 Operand 13 9 3 Opcode 0 Program counter * * * * * * 0 7 0 B 13 A 0 Program counter 0 0 Current Page Addressing Table Data Addressing Figure 63 ROM Addressing Modes 77 HD404344 Series/HD404394 Series Addressing Mode for P Instruction: By using the P instruction, the ROM data determined by table data addressing can be referenced. The lower-order 8 bits of ROM data are written in the accumulator and the B register when bit 8 of the ROM data is 1, and are written in the R1 and R2 port output registers when bit 9 is 1. If bit 8 and bit 9 are both 1, the ROM data is simultaneously written into the accumulator, the B register, and the R1 and R2 port output registers. (See figure 64.) The program counter is not affected by the P instruction. Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 Referenced ROM address B2 B1 Accumulator B0 A3 A2 RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A2 A1 A0 RO8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output Figure 64 P Instruction 78 A0 0 Address ROM data A1 RO9 = 1 HD404344 Series/HD404394 Series BR Branching Instruction at Page Boundary: When the BR instruction is at a page boundary (256n + 255), the address in the program counter is transferred over to point to the next page as done by the internal hardware. Therefore, executing the BR instruction at a page boundary will cause the program to branch to the next page. (See figure 65.) BR AAA NOP BR BR BBB AAA 256 (n - 1) + 255 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP Figure 65 BR Instruction at Page Boundary 79 HD404344 Series/HD404394 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V 1 Pin voltage VT -0.3 to VCC + 0.3 V 2 -0.3 to +15.0 V 3 Total permissible input current IO 100 mA 4 Total permissible output current -IO 30 mA 5 Maximum input current IO 30 mA 6, 7 4 mA 6, 8 9 Maximum output current -IO 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP) of the HD4074344 and HD4074394. 2. Applies to the following pins. HD404344 series: D0-D5, R0, R1, R2, R3 HD404394 series: D0-D5, R0, R13, R2, R31-R33 3. Applies to the following pins. HD404394 series: R10-R12 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to D1, D2, R1, and R2. 8. Applies to the following pins. HD404344 series: D0, D3-D5, R0, R3 HD404394 series: D0, D3-D5, R0, R31-R33 9. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 80 HD404344 Series/HD404394 Series Electrical Characteristics DC Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Input high voltage VIH RESET, SCK, 0.8VCC -- VCC + 0.3 V SI 0.7VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V RESET, SCK, -0.3 -- 0.2VCC V SI -0.3 -- 0.3VCC V OSC1 -0.3 -- 0.5 V Test Condition Notes INT0, STOPC, EVNB Input low voltage VIL INT0, STOPC, EVNB Output high voltage VOH SCK, SO, TOC VCC - 1.0 -- -- V -IOH = 0.5 mA Output low voltage VOL SCK, SO, TOC -- -- 0.4 V IOL = 0.5 mA I/O leakage current |IIL| RESET, SCK, -- -- 1 A Vin = 0 V to VCC 1 -- -- 3.5 mA VCC = 5 V, 2, 4 SI, SO, TOC, OSC1, INT0, STOPC, EVNB Current ICC1 dissipation in active mode VCC fOSC = 4 MHz ICC2 -- -- 0.4 mA VCC = 3 V, 2, 4 fOSC = 400 kHz ISBY1 Current dissipation in standby mode VCC -- -- 1.5 mA VCC = 5 V, 3, 4 fOSC = 4 MHz ISBY2 -- -- 0.2 mA VCC = 3 V, 3, 4 fOSC = 400 kHz Current ISTOP dissipation in stop mode VCC -- -- 10 A Vin (RESET) = VCC - 0.3 V to VCC, Vin (TEST) = 0 to 0.3 V Stop mode retaining voltage VSTOP VCC 2 -- -- V 81 HD404344 Series/HD404394 Series Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET, TEST at GND D0-D5, R0-R3 at VCC 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions:MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND D0-D5, R0-R3 at VCC 4. Current dissipation is in proportion to fOSC while the MCU is operating or in standby mode. The value of the dissipation current when fOSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 82 HD404344 Series/HD404394 Series I/O Characteristics for Standard Pins (V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Pins Item Symbol Input high voltage VIH HD404344 HD404394 Series Series Min Typ Max D0-D5, D0-D5, 0.7VCC -- VCC + 0.3 V R0-R3 R0, R13, R2, -0.3 -- 0.3VCC V VCC - 1.0 -- -- V -IOH = 0.5 mA Unit Test Condition Note R31-R33 Input low voltage VIL D0-D5, D0-D5, R0-R3 R0, R13, R2, R31-R33 Output high VOH voltage D0-D5, D0-D5, R0-R3 R0, R31-R33 Output low voltage VOL -- R13, R2 VCC - 0.5 -- -- V 500 k at VCC D0-D5, D0-D5, -- -- 0.4 V IOL = 0.5 mA R0-R3 R0, R13, R2, -- -- 2.0 V IOL = 15 mA, 2 R31-R33 Input leakage current |IIL| Pull-up MOS current -IPU D1, D2, D1, D2, R1, R2 R13, R2 D0-D5, D0-D5, R0-R3 R0, R13, R2, VCC = 4.5-5.5 V -- -- 1 30 150 300 A Vin = 0 V to VCC A VCC = 5 V, 1 R31-R33 D0-D5, D0-D5, R0-R3 R0, Vin = 0 V R31-R33 Notes: 1. Output buffer current and pull-up MOS current are excluded. 2. Applies to the HD404394 series. 83 HD404344 Series/HD404394 Series I/O Characteristics for NMOS Intermediate-Voltage Pins for HD404394 Series (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Input high voltage VIH R10-R12 Input low voltage VIL Output high voltage Output low voltage Min Typ Max Unit Test Condition Notes 0.7VCC -- 12.0 V 1 R10-R12 -0.3 -- 0.3VCC V 1 VOH R10-R12 11.5 -- -- V 500 k at 12 V 1 VOL R10-R12 -- -- 0.4 V IOH = 0.5 mA 1 R10-R12 -- -- 2.0 V IOL = 15 mA, 1 VCC = 4.5 to 5.5 V I/O leakage current |IIL| R10-R12 -- -- A 20 Vin = 0 V to 12 V 1, 2 Notes: 1. Applies to the HD404394 series. 2. Excludes output buffer current. A/D Converter Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Pins Min Analog reference voltage Vref Vref 0.5VCC -- Analog input voltage AN0-AN3 GND AN1-AN3 GND Current flowing between Vref and GND Symbol AVin Max Unit VCC V 2 -- VCC V 1 -- Vref V 2 -- -- 200 A AN0-AN3 -- 15 -- pF IAD Analog input capacitance CAin Typ Test Condition Note Vref = VCC = 5.0 V 2 Resolution -- 8 -- Bit Number of input channels 0 -- 4 Channel 1 0 -- 3 Channel 2 -- 2.5 LSB Absolute accuracy AN0-AN3 -2.5 Ta = 25C, 1 Vref = VCC = 5.0 V AN1-AN3 -3.0 Conversion time Input impedance 34 AN0-AN3 1 -- 3.0 LSB -- 67 tcyc -- -- M 2 fOSC = 1 MHz, Vin = 0 V Notes: 1. Applies to the HD404344 series. 2. Applies to the HD404394 series. 84 HD404344 Series/HD404394 Series AC Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) Item Symbol Pins Clock oscillation frequency fOSC OSC1, OSC2 Min Typ Max Unit 0.4 4 4.5 MHz 0.89 1 10 s Test Condition Note Instruction cycle time (ceramic oscillator) tcyc System clock divided by 4 Oscillation stabilization time (ceramic oscillator) tRC OSC1, OSC2 -- -- 2 ms 1 External clock high width tCPH OSC1 92 -- -- ns 2 External clock low width tCPL OSC1 92 -- -- ns 2 External clock rise time tCPr OSC1 -- -- 20 ns 2 External clock fall time tCPf OSC1 -- -- 20 ns 2 INT0, EVNB high widths tIH INT0, EVNB 2 -- -- tcyc 3 INT0, EVNB low widths tIL INT0, EVNB 2 -- -- tcyc 3 RESET low width tRSTL RESET 2 -- -- tcyc 4 STOPC low width tSTPL STOPC 1 -- -- tRC 5 RESET rise time tRSTr RESET -- -- 20 ms 4 STOPC rise time tSTPr STOPC -- -- 20 ms 5 Input capacitance Cin All input pins except TEST, -- -- 15 pF f = 1 MHz, Vin = 0 V Vref and R10-R12 TEST -- -- 15 pF f = 1 MHz, 6 Vin = 0 V -- -- 40 pF 7 Vref -- -- 30 pF 8 R10-R12 -- -- 30 pF Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 2.7 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC. When using a ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 66. 3. Refer to figure 67. 4. Refer to figure 68. 5. Refer to figure 69. 6. Applies to the HD404341, HD404342, HD404344, HD404391, HD404392, and HD404394. 7. Applies to the HD4074344 and HD4074394. 8. Applies to the HD404394 series. 85 HD404344 Series/HD404394 Series Serial Interface Timing Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20 to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Test Condition Min Typ Max Unit Note Transmit clock cycle time tScyc SCK Load shown in figure 71 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK Load shown in figure 71 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK Load shown in figure 71 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK Load shown in figure 71 -- -- 80 ns 1 Transmit clock fall time tSCKf SCK Load shown in figure 71 -- -- 80 ns 1 Serial output data delay time tDSO SO Load shown in figure 71 -- -- 300 ns 1 Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 Typ Max Unit Note During Transmit Clock Input Item Symbol Pins Test Condition Min Transmit clock cycle time tScyc SCK 1 -- -- tcyc 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc 1 Transmit clock rise time tSCKr SCK -- -- 80 ns 1 Transmit clock fall time tSCKf SCK -- -- 80 ns 1 -- -- 300 ns 1 Serial output data delay time tDSO SO Serial input data setup time tSSI SI 100 -- -- ns 1 Serial input data hold time tHSI SI 200 -- -- ns 1 Note: 86 1. Refer to figure 70. Load shown in figure 71 HD404344 Series/HD404394 Series OSC 1 1/fCP VCC - 0.5 V tCPL tCPH 0.5 V tCPr tCPf Figure 66 External Clock Timing INT0, EVNB 0.8VCC tIL tIH 0.2VCC Figure 67 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 68 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 69 STOPC Timing 87 HD404344 Series/HD404394 Series t Scyc t SCKf SCK t SCKr VCC - 0.5 V (0.8VCC )* 0.4 V (0.2VCC)* t SCKL t SCKH t DSO VCC - 0.5 V 0.4 V SO t HSI t SSI 0.7V CC 0.3VCC SI Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 70 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k Hitachi 1S2074 H or equivalent Figure 71 Timing Load Circuit 88 HD404344 Series/HD404394 Series Notes On ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions (HD404344 and HD404394). A 4-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 4-kword version. This limitation apply to the case of using EPROM and the case of using data base. ROM 2 kwords version: HD404342, HD404392 Address $0800 to $0FFF ROM 1 kwords version: HD404341, HD404391 Address $0400 to $0FFF $0000 $0000 Vector address Vector address $000F $0010 $000F $0010 Zero-page subroutine (64 words) $003F $0040 Zero-page subroutine (64 words) $003F $0040 Pattern and program (1024 words) Pattern and program (2048 words) $07FF $0800 $03FF $0400 Not used Not used $0FFF $0FFF Fill this area with all 1s 89 HD404344 Series/HD404394 Series HD404341/HD404342/HD404344 Option List Date of order Customer Department Name ROM code name LSI number 1. ROM size HD404341 1-kword HD404342 2-kword HD404344 4-kword 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. System oscillator (OSC1-OSC2) Ceramic oscillator f= MHz External clock f= MHz 4. Stop mode Used Not used 5. Package type DP-28S FP-28DA FP-30D 90 HD404344 Series/HD404394 Series HD404391/HD404392/HD404394 Option List Date of order Customer Department Name ROM code name LSI number 1. ROM size HD404391 1-kword HD404392 2-kword HD404394 4-kword 2. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 3. System oscillator (OSC1-OSC2) Ceramic oscillator f= MHz External clock f= MHz 4. Stop mode Used Not used 5. Package type DP-28S FP-28DA FP-30D 91 H44xx Family HD404439 Series Rev. 5.0 March 1997 Description The HD404439 is a 4-bit single-chip microcomputer incorporating five timers, two serial interfaces, an A/D converter, an input capture timer, and an output compare timer. It also includes a 32.768-kHz oscillator and low-power dissipation modes. A PROM version (ZTAT microcomputer) and mask ROM version are available as on-chip ROM. PROM versions can be programmed freely by the customer using a standard PROM writer. Mask ROM versions are available with high-voltage pins (HD404719) and standard-voltage pins (HD404439) on-chip. ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd. Features * 16,384-word x 10-bit ROM (HD404439, HD404719) 16,384-word x 10-bit PROM (HD4074719) ZTAT version is 27256-compatible * 960-digit x 4-bit RAM * 70 I/O pins including 36 high-voltage (40 V max.), high-current (15 mA max. ) pins (except for HD404439 which has only standard pins) * Five timer/counters * Two clock-synchronous 8-bit serial interfaces * 8-bit x 8-channel A/D converter * Voltage comparator (with one input channel) * Input capture timer/free-running counter * 16-bit output compare timer * Eight-level output buzzer line * 14 interrupt sources Six by external sources, including three edge programmable type sources Eight by internal sources * Subroutine stack up to 16 levels, including interrupts HD404439Series * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * Built-in oscillator Crystal or ceramic oscillator (external clock also enabled) main clock 32.768-kHz crystal subclock * Instruction cycle time: 0.89 s (VCC = 3.5 to 6 V), 1.78 s (VCC = 3.0 to 6 V) Ordering Information Type Product Name ROM (Words) Package Mask ROM HD404439FS 16,384 FP-80B 16,384 FP-80A HD4074719FS 16,384 FP-80B HD4074719H 16,384 FP-80A HD404719FS HD404439H HD404719H ZTAT The HD404439 is a CMOS 4-bit single-chip microcomputer with standard-voltage pins on chip. The description here covers the HD404719 series with high voltage pins on chip, as well as the PROM version HD4074719. 2 HD404439 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 2 63 3 62 61 4 5 60 6 59 7 58 8 57 9 56 10 55 11 12 13 14 15 16 FP-80B (Top view) 54 53 52 51 50 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R83/SI1 R82/SO1 R81/INT5 RD3/AN7 AGND R80/INT4 R73/INT3 RESET OSC1 R72/INT2 OSC2 R71/INT1 GND R70/INT0 CL1 R63/TOE2 CL2 R62/TOE1 TEST R61/Vref VCC R60/COMP D0 R53 D1 R52 D2 R51 D3 R50/Vdisp D4 R43 D5 R42 D6 R41 D7 R40 D8 R33 D9 R32 R31 R30 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 10 11 FP-80A (Top view) 52 51 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R81/INT5 R80/INT4 R73/INT3 R72/INT2 R71/INT1 R70/INT0 R63/TOE2 R62/TOE1 R61/Vref R60/COMP R53 R52 R51 R50/Vdisp R43 R42 R41 R40 R33 R32 D10 D11 D12 D13 D14 D15 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 1 D12 D13 D14 D15 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 RD1/AN5 RD2/AN6 RD3/AN7 AGND RESET OSC1 OSC2 GND CL1 CL2 TEST VCC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 RD2/AN6 RD1/AN5 RD0/AN4 RC3/AN3 RC2/AN2 RC1/AN1 RC0/AN0 AVCC RB1/TOD RB0/TOC RA3/BUZZ RA2/TOG RA1/ICT1 RA0/ICT0 R93/SO2 R92/SI2 R91/SCK2 R90/SCK1 R83/SI1 R82/SO1 RD0/AN4 RC3/AN3 RC2/AN2 RC1/AN1 RC0/AN0 AVCC RB1/TOD RB0/TOC RA3/BUZZ RA2/TOG RA1/ICT1 RA0/ICT0 R93/SO2 R92/SI2 R91/SCK2 R90/SCK1 Pin Arrangement 3 HD404439Series Pin Description Pin Number Pin Number FP-80B FP-80A Pin Name Input/ Output FP-80B FP-80A Pin Name Input/ Output 1 79 RD1/AN5 I 34 32 R11 I/O 2 80 RD2/AN6 I 35 33 R12 I/O 3 1 RD3/AN7 I 36 34 R13 I/O 4 2 AGND 37 35 R20 I/O 5 3 RESET I 38 36 R21 I/O 6 4 OSC1 I 39 37 R22 I/O 7 5 OSC2 O 40 38 R23 I/O 8 6 GND 41 39 R30 I/O 9 7 CL1 42 40 R31 I/O 10 8 CL2 O 43 41 R32 I/O 11 9 TEST I 44 42 R33 I/O 12 10 VCC 45 43 R40 I/O 13 11 D0 I/O 46 44 R41 I/O 14 12 D1 I/O 47 45 R42 I/O 15 13 D2 I/O 48 46 R43 I/O 16 14 D3 I/O 49 47 R50/Vdisp I 17 15 D4 I/O 50 48 R51 I 18 16 D5 I/O 51 49 R52 I 19 17 D6 I/O 52 50 R53 I 20 18 D7 I/O 53 51 R60/COMP I/O 21 19 D8 I/O 54 52 R61/Vref I/O 22 20 D9 I/O 55 53 R62/TOE1 I/O 23 21 D10 I/O 56 54 R63/TOE2 I/O 24 22 D11 I/O 57 55 R70/INT0 I/O 25 23 D12 I/O 58 56 R71/INT1 I/O 26 24 D13 I/O 59 57 R72/INT2 I/O 27 25 D14 I/O 60 58 R73/INT3 I/O 28 26 D15 I/O 61 59 R80/INT4 I/O 29 27 R00 I/O 62 60 R81/INT5 I/O 30 28 R01 I/O 63 61 R82/SO1 I/O 31 29 R02 I/O 64 62 R83/SI1 I/O 32 30 R03 I/O 65 63 R90/SCK 1 I/O 33 31 R10 I/O 66 64 R91/SCK 2 I/O 4 I HD404439 Series Pin Number Pin Number FP-80B FP-80A Pin Name Input/ Output FP-80B FP-80A Pin Name Input/ Output 67 65 R92/SI2 I/O 74 72 RB1/TOD I/O 68 66 R93/SO2 I/O 75 73 AVCC 69 67 RA0/ICT0 I/O 76 74 RC0/AN0 I 70 68 RA1/ICT1 I/O 77 75 RC1/AN1 I 71 69 RA2/TOG I/O 78 76 RC2/AN2 I 72 70 RA3/BUZZ I/O 79 77 RC3/AN3 I 73 71 RB0/TOC I/O 80 78 RD0/AN4 I 5 HD404439Series Pin Functions Power Supply VCC: Apply power voltage to this pin. GND: Connect to ground. TEST: Used for test purposes only. Connect it to VCC. RESET: Resets the MCU. Oscillators OSC 1, OSC2: Used as pins for the internal oscillator circuit. They can be connected to a crystal resonator or a ceramic resonator, or OSC1 can be connected to an external oscillator circuit. CL1, CL2: Used for a 32.768-kHz crystal oscillator that acts as a clock. Ports D0-D15 (D Port): Input/output port addressable by individual bits. Each port output consists of an opendrain PMOS which enables high-voltage, high-current drive ability for its pin. R0-RD (R Ports): Input/output ports addressable in 4-bit units. R5, RC, and RD are input-only ports. The R5 to RD port pins are standard pins, but the R0 to R4 pins are high-voltage pins. Each of the R0 to R4 output pins consists of an open-drain PMOS which enables high-voltage drive ability for its pin. The R6 to RD pins are multiplexed with peripheral pins. Note: The HD404439 has only standard pins. Interrupts INT0-INT5: Input external interrupts to the MCU. to R8 1, respectively. INT0 to INT5 are multiplexed with R7 0 to R73 and R80 Serial Interface SCK 1 , SCK 2 : Input/output serial interface clock pins that are multiplexed with pins R90 and R91 , respectively. SI1, SI2: Serial interface receiving data input pins that are multiplexed with pins R83 and R92, respectively. SO 1, SO2: Serial interface transmission data output pins that are multiplexed with pins R82 and R93, respectively. 6 HD404439 Series Timers TOC, TOD: Output variable-duty square waves. They are multiplexed with pins RB0 and RB1, respectively. TOE 1, TOE2: Output square waves from the PWM. They are multiplexed with pins R6 2 and R63, respectively. TOG: Outputs a square wave specified by the output compare function. It is multiplexed with pin RA2. Buzzer Buzz: Outputs a variable-duty square wave. It is multiplexed with RA3. A/D Converter AVCC: VCC power supply for the A/D converter. AGND: GND power supply for the A/D converter. AN0-AN7: Analog data input pins for A/D conversion that are multiplexed with pins RC 0 to RC3 and RD0 to RD3, respectively. Comparator COMP: Input pin for the comparator. It is multiplexed with pin R60. Vref: Inputs reference voltage for the analog comparator. It is multiplexed with pin R61. 7 8 R6 SPX (4) X (4) R5 SPY (4) Y (4) R4 ALU R3 ST Stack pointer 960 x 4-bit RAM Interrupt control CA R2 A (4) B (4) R1 Program counter 16384 x 10-bit ROM Instruction decoder External interrupt R0 INT0 INT2 IINT4 INT1 INT3 INT5 Output Comparator compare Input Buzzer Timer Timer Timer Timer Timer capture E D C B A TOG ICT1 BUZZ TOE2 TOD TOC INT1 INT4 ICT0 TOE1 D port System control R71/ R63/ R61/ R43 R53 R51 R41 R33 R31 R23 R21 R13 R11 R03 R01 TOE2 Vref INT1 R72/ R70/ R60/ R52 R50/ R42 R40 R32 R30 R22 R20 R12 R10 R02 R00 R62/ Vdisp* TOE1 COMP INT2 INT0 R7 W (2) A/D AVCC AN6 AN4 AN2 AN0 COMP Vref AGND AN7 AN5 AN3 AN1 Note: The Vdisp pin is used only in the HD404719, and is not provided in the HD404439 or HD4074719. R73/ INT3 R8 R9 SO2/R93 SI2/R92 SCK2 /R91 SCK1 /R90 SI1/R83 SO1/R82 INT5 /R81 INT4 /R80 RA BUZZ/RA3 TOG/RA2 ICT1/RA1 ICT0/RA0 TOC/RB0 RB RC AN3/RC3 AN2/RC2 AN1/RC1 AN0/RC0 TOD/RB1 RD AN7/RD3 AN6/RD2 AN5/RD1 AN4/RD0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC GND OSC1 OSC2 CL1 CL2 RESET TEST HD404439Series Block Diagram HD404439 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1, and the ROM is described in detail below. 0 $0000 0 1 Vector address 2 31 32 $001F $0020 4 Zero-page subroutine (64 words) 63 64 3 5 $003F $0040 6 7 $0000 JMPL instruction (jump to INT0 routine) $0002 JMPL instruction (jump to INT1 routine) $0004 JMPL instruction (jump to INT2 routine) $0006 8 JMPL instruction 9 (jump to input capture routine) Pattern (4096 words) 10 4095 4096 $0FFF $1000 11 12 13 Program (16384 words) 14 15 16 16383 JMPL instruction (jump to reset routine) $3FFF 17 18 19 24 25 26 27 28 29 $0005 $0007 $0008 $0009 $000A JMPL instruction (jump to timer B routine) $000C JMPL instruction (jump to timer C routine) $000E JMPL instruction (jump to timer D routine) $0010 JMPL instruction (jump to serial 1 routine) $0012 JMPL instruction (jump to A/D routine) $0014 JMPL instruction (jump to INT3 routine) $0016 JMPL instruction (jump to INT4 routine) $0018 JMPL instruction (jump to INT5 routine) $001A JMPL instruction (jump to serial 2 routine) $001C 21 23 $0003 JMPL instruction (jump to timer A routine) 20 22 $0001 $000B $000D $000F $0011 $0013 $0015 $0017 $0019 $001B $001D 30 $001E 31 $001F Figure 1 ROM Memory Map Vector Address Area ($0000-$001F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After an MCU reset or interrupt execution, the program starts from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to the subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Reserved for ROM data that is referenced as a pattern by the P instruction. Pr ogra m Ar ea ($0000-$3FFF): Used for program code. 9 HD404439Series RAM Memory Map The MCU contains a 960-digit x 4-bit RAM area for data and stack areas. In addition, interrupt control bits and special function registers are mapped onto the same RAM memory space outside this area. The RAM memory map is shown in figure 2 and the RAM area is described in detail below. 0 $000 RAM-mapped registers 64 $040 Memory registers (MR) (16 digits) 80 $050 Data (880 digits) 960 $3C0 Stack (64 digits) $3FF 1023 *: Two registers are mapped on the same address R: Read only W: Write only R/W: Read/write 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 Interrupt control bits area (1) B Port mode register A (PMRA) Serial mode register 1 (SMR1) Serial data register 1 lower (SR1L) Serial data register 1 upper (SR1U) Timer mode register A (TMA) Timer mode register B (TMB) (TCBL/TLRL) Timer B* (TCBL/TLRU) Miscellaneous register (MIS) Timer mode register C (TMC) (TCCL/TCRU) Timer C* (TCCU/TCRU) Timer mode register D (TMD) (TCDL/TDRL) Timer D* (TCDU/TDRU) Port mode register B (PMRB) Serial mode register 2 (SMR2) Serial data register 2 lower (SR2L) Serial data register 2 upper (SR2U) Input capture control register (ICC) Input capture status register (ICSR) Input capture register lower (ICRL) Input capture register upper (ICRU) A/D control register (ADCR) A/D mode register (AMR) A/D data register lower (ADRL) A/D data register upper (ADRU) A/D status register (ADSR) W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W W W R/W R/W W R/W R R W W R R R/W Interrupt control bits area (2) B Timer mode register E (TME) Timer buffer register E lower (TBEL) Timer buffer register E upper (TBEU) Not used Buzzer control register (BCR) Output compare control register (OCC) Output compare status register (OCSR) Timer load register G1 lower (TLG1L) Timer load register G1 upper (TLG1U) Timer load register G2 lower (TLG2L) Timer load register G2 upper (TLG2U) Port mode register C (PMRC) Interrupt mode register A (IMRA) Interrupt mode register B (IMRB) R/W W W Not used Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR Port RA DCR Port RB DCR (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) (DCRB) W W W W W W Not used Compare control register (CCR) Not used Figure 2 RAM Memory Map 10 W W W W W W W W W W W $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F HD404439 Series Interrupt Control Bits Area ($000-$003, $020-$024): Used for interrupt control (figure 3). It can be accessed only by RAM bit manipulation instructions. However, note that the interrupt request flag cannot be set by software, the RSP bit is used only to reset the stack pointer, the DTON, LSON, and WDON flags are accessed only by RAM bit manipulation instructions, and the WDON flag can only be set to 1 by the SEM and SEMD instructions. Special Function Registers Area ($004-$01F, $025-$03F): Used as mode registers for external interrupts, the serial interface, the timer/counters, and as data control registers and data registers for I/O ports. As shown in figure 2, there are three types of registers: read-only, write-only, and read/write. These registers cannot be accessed by RAM bit manipulation instructions. Data Area ($040-$04F, $050-$3BF): The memory registers (MR), which consist of 16 digits ($040- $04F), can also be accessed by the LAMR and XMRA instructions (figure 4). Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and interrupt processing. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The stack area and data to be saved in it are shown in figure 4. The program counter is popped from the stack by the RTN and RTNI instructions. The status and carry flags can only be popped from the stack by the RTNI instruction. Any unused area is available for data storage. 11 HD404439Series 0 1 2 3 Bit 3 IM0 (IM of INT0) IM2 (IM of INT2) IMTA (IM of timer A) IMTC (IM of timer C) DTON 32 (Direct transfer on flag) IMS1 33 (IM of serial 1) IM3 34 (IM of INT3) IM5 35 (IM of INT5) 36 IF: IM: IE: SP: Bit 2 IF0 (IF of INT0) IF2 (IF of INT2) IFTA (IF of timer A) IFTC (IF of timer C) IFS1 (IF of serial 1) IF3 (IF of INT3) IF5 (IF of INT5) Bit 1 Bit 0 RSP IE (Reset SP bit) (Interrupt enable flag) IM1 IF1 (IM of INT1) (IF of INT1) IMIC IFIC (IM of input capture) (IF of input capture) IMTB IFTB (IM of timer B) (IF of timer B) WDON (Watchdog on flag) IMTD (IM of timer D) IMAD (IM of A/D) IM4 (IM of INT4) IMS2 (IM of serial 2) LSON (Low speed on flag) IFTD (IF of timer D) IFAD (IF of A/D) IF4 (IF of INT4) IFS2 (IF of serial 2) $000 $001 $002 $003 $020 $021 $022 $023 $024 Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other instructions have no effect. However, note that the IF cannot be set by the SEM or SEMD instruction. If the RSP bit or a non-existent bit is tested by the TM or TMD instruction, its status is undefined. The WDON flag can only be used by the SEM or SEMD instruction (it is reset only by MCU reset). Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 12 HD404439 Series Memory registers 64 $040 MR (0) 65 $041 MR (1) 66 $042 MR (2) 67 $043 MR (3) 68 $044 MR (4) 69 $045 MR (5) 70 $046 MR (6) 71 $047 MR (7) 72 $048 MR (8) 73 $049 MR (9) 74 MR (10) $04A 75 MR (11) $04B 76 MR (12) $04C 77 MR (13) $04D 78 MR (14) $04E 79 MR (15) $04F Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC12 PC11 $3FC 1021 PC10 PC9 PC8 PC7 $3FD 1022 CA PC6 PC5 PC4 $3FE 1023 PC3 PC2 PC1 PC0 $3FF PC13-PC0: Program counter ST: Status flag CA: Carry flag Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position 13 HD404439Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 5 and described below. 3 0 A Accumulator 3 0 B B register 1 0 W 3 W register 0 X 3 X register 0 Y 3 Y register 0 SPX 3 SPX register 0 SPY 13 SPY register CA Carry flag ST Status flag 0 PC 9 Program counter 0 5 1 1 1 1 SP Figure 5 Registers and Flags 14 Stack pointer HD404439 Series Accumulator (A), B Register (B): Four-bit registers used to hold results from the arithmetic logic unit (ALU) and to transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is also affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt, and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that indicates an ALU overflow or ALU non-zero generated during an arithmetic or compare instruction, or the result of a bit test instruction. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is fetched, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt, and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): A 14-bit counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped from the stack. Since the top 4 bits of the SP are fixed to 1111, a stack of up to 16 levels can be used. The SP is initialized to $3FF in two ways: by MCU reset or by resetting the RSP bit with the REM or REMD instruction. 15 HD404439Series Reset The MCU is reset by setting the RESET pin high. At power-on or when stop mode is cancelled, RESET must be high for at least one t RC to enable the oscillator to stabilize. In other cases, a RESET input for two instruction cycles resets the MCU. Initial values of the registers and counters after MCU reset are listed in table 1. Table 1 Initial Values after MCU Reset Item Abbr. Initial Value Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer Contents (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Open-drain PMOS port data (PDR) register All bits 0 Enables output at level 0 Standard port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCR) All bits 0 Turns output buffer off (to high impedance) Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of port mode register B Port mode register C (PMRC) 0000 Refer to description of port mode register C Interrupt mode registers A, B (IMRA) 00 - - Refer to description of interrupt mode registers A and B (IMRB) 0000 Timer/ counters, Timer mode register A serial interface (TMA) 0000 Refer to description of timer mode register A Timer mode register B (TMB) 0000 Refer to description of timer mode register B Timer mode register C (TMC) 0000 Refer to description of timer mode register C Timer mode register D (TMD) 0000 Refer to description of timer mode register D Timer mode register E (TME) 0000 Refer to description of timer mode register E Interrupt flags/ mask I/O 16 HD404439 Series Item Abbr. Initial Value Timer/ counters, Serial mode register 1 serial interface (SMR1) 0000 Refer to description of serial mode register 1 Serial mode register 2 (SMR2) 0000 Refer to description of serial mode register 2 Prescaler S $000 -- Prescaler W $00 -- $00 -- Contents Timer counter A (TCA) Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer counter D (TCD) $00 -- Timer buffer register E (TBE) $00 Refer to description of timer buffer register E Timer load register B (TLR) $00 Refer to description of timer load register B Timer load register C (TCR) $00 Refer to description of timer load register C Timer load register D (TDR) $00 Refer to description of timer load register D Octal counter (x 2) (OC) 000 -- Timer load register G (TLG) $0000 Refer to description of timer load register G A/D control register (ADCR) 0000 Refer to description of A/D control register Input capture control register (ICC) 0000 Refer to description of input capture control register Input capture data register (ICSR) 0000 Refer to description of input capture data register Buzzer control register (BCR) 0000 Refer to description of buzzer control register Output compare control register (OCC) 0000 Refer to description of output compare control register Output compare status register (OCSR) - - 00 Refer to description of output compare status register A/D mode register (AMR) - - 00 Refer to description of A/D mode register A/D status register (ADSR) ---0 Refer to description of A/D status register A/D data register (ADR) $80 Refer to description of A/D data register $0000 -- 16-bit counter (timer counter (TCG) G) 17 HD404439Series Item Abbr. Initial Value Contents Timer/ counters, 8-bit counter (timer counter serial interface F) (TCF) $00 -- Compare control register (CCR) 0000 Refer to description of output compare control register Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C Direct transfer on flag (DTON) 0 Refer to description of operating modes (MIS) 0000 Refer to description of miscellaneous register Bit register Miscellaneous register Note: The status of other registers and flags after MCU reset are shown below. Item Abbr. Status after Cancellation of Stop Mode by MCU Reset In Other Cases at MCU Reset Carry flag (CA) Pre-MCU-reset values are not retained values must be initialized by software Pre-MCU-reset values are not retained values must be initialized by software Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial 1 data register (S1R) Serial 2 data register (S2R) RAM 18 Pre-MCU-reset (pre-STOPinstruction) values are retainedInterrupts HD404439 Series Interrupts The MCU has 14 interrupt sources: six external signals (INT0-INT 5), four timer/counters (timer A, timer B, timer C, and timer D), two serial interfaces (serial 1 and serial 2), an A/D converter, and an input capture. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 through $003 and $020 through $024 in RAM are reserved for the interrupt control bits which can only be accessed by RAM bit manipulation instructions. The interrupt request flags (IFs) can only be set by signals from interrupt sources. MCU reset initializes the interrupt enable flag (IE) and interrupt request flags (IFs) to 0 and the interrupt masks (IMs) to 1. A block diagram of the interrupt control circuit is shown in figure 6, interrupt priorities and vector addresses are listed in table 2, and the interrupt processing conditions for the 14 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, interrupt processing begins. A priority programmable logic array generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 7, and an interrupt processing flowchart is shown in figure 8. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt routine, and reset the IF by a software instruction within the interrupt routine. 19 HD404439Series Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET -- $0000 INT0 1 $0002 INT1 2 $0004 INT2 3 $0006 Input capture 4 $0008 Timer A 5 $000A Timer B 6 $000C Timer C 7 $000E Timer D 8 $0010 Serial 1 9 $0012 A/D 10 $0014 INT3 11 $0016 INT4 12 $0018 INT5 13 $001A Serial 2 14 $001C 20 HD404439 Series IE Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address IF0 Vector address IM0 IF1 Priority control logic IM1 IF2 IM2 IFIC IMIC IFTA IFS2 IMTA IMS2 IFTB IF5 IMTB IM5 IFTC IF4 IMTC IM4 IFTD IF3 IMTD IM3 IFS1 IFAD IMS1 IMAD Figure 6 Block Diagram of Interrupt Control Circuit 21 HD404439Series Table 3 Interrupt Conditions Interrupt Source Interrupt Control Bit INT0 INT1 INT2 Input Capture Timer A Timer B Timer C IE 1 1 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 0 0 IF1 * IM1 * 1 0 0 0 0 0 IF2 * IM2 * * 1 0 0 0 0 IFIC * IMIC * * * 1 0 0 0 IFTA * IMTA * * * * 1 0 0 IFTB * IMTB * * * * * 1 0 IFTC * IMTC * * * * * * 1 IFTD * IMTD * * * * * * * IFS1 * IMS1 * * * * * * * IFAD * IMAD * * * * * * * IF3 * IM3 * * * * * * * IF4 * IM4 * * * * * * * IF5 * IM5 * * * * * * * IFS2 * IMS2 * * * * * * * Note: * Bits marked by * can be either 0 or 1. Their values have no effect on operation. 22 HD404439 Series Interrupt Source Interrupt Control Bit Timer D Serial 1 A/D INT3 INT4 INT5 Serial 2 IE 1 1 1 1 1 1 1 IF0 * IM0 0 0 0 0 0 0 0 IF1 * IM1 0 0 0 0 0 0 0 IF2 * IM2 0 0 0 0 0 0 0 IFIC * IMIC 0 0 0 0 0 0 0 IFTA * IMTA 0 0 0 0 0 0 0 IFTB * IMTB 0 0 0 0 0 0 0 IFTC * IMTC 0 0 0 0 0 0 0 IFTD * IMTD 1 0 0 0 0 0 0 IFS1 * IMS1 * 1 0 0 0 0 0 IFAD * IMAD * * 1 0 0 0 0 IF3 * IM3 * * * 1 0 0 0 IF4 * IM4 * * * * 1 0 0 IF5 * IM5 * * * * * 1 0 IFS2 * IMS2 * * * * * * 1 Note: * Bits marked by * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 7 Interrupt Processing Sequence 23 HD404439Series PC $0002 Yes Interrupt INT0 ? No PC $0004 Yes INT1 ? No PC $0006 Yes INT2 ? No PC $0008 Yes Input capture? No PC $000A Yes Timer A? No PC $000C Yes Timer B? No PC $000E Yes Timer C? No PC $0010 Yes Timer D? No PC $0012 Yes Serial 1? No PC $0014 Yes A/D? No PC $0016 Yes INT3 ? No PC $0018 Yes INT4 ? No PC $001A Yes INT5 ? No PC $001C Serial 2 Active Figure 8 Interrupt Processing Flowchart 24 Interrupt acceptance IE 0 Stack (PC) Stack (CA) Stack (ST) HD404439 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls all interrupts (table 4). IE is reset to 0 by the interrupt processing and set to 1 by the RTNI instruction. Table 4 Interrupt Enable Flag IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0-INT5): The MCU has six external interrupt pins. The INT1 input can be used as a clock input for timer B in which case timer B increments at each edge selected by the interrupt mode register (IMRA) (figure 9). In this case, the external interrupt request flag (IM1) must be set to inhibit the INT1 interrupt request. The INT4 input can be used as an external trigger for the output compare timer. IMRA: $031 Initial value: 00--, R/W: W IMRA3 IMRA2 INT1 detection edge selection IMRB: $032 IMRB3 IMRB2 IMRB1 IMRB0 Initial value: 0000, R/W: W INT2 detection edge selection INT3 detection edge selection IMRA Bit 3 Bit 2 INT1 Detection Edge 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection 1 IMRB IMRB Bit 3 Bit 2 INT3 Detection Edge Bit 1 Bit 0 INT2 Detection Edge 0 0 No detection 0 0 No detection 1 Falling-edge detection 1 Falling-edge detection 0 Rising-edge detection 0 Rising-edge detection 1 Double-edge detection 1 Double-edge detection 1 1 Figure 9 Interrupt Mode Register 25 HD404439Series External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0; IF2: $001, Bit 2; IF3: $022, Bit 2; IF4: $023, Bit 0; IF5: $023, Bit 2): Set at the rising or falling edges of the corresponding INT0 to INT 5 inputs (table 5). IF0, IF4, and IF5 are set at the falling edges of INT0, INT 4, and INT5, respectively, and IF1, IF2, and IF3 are set at either the rising or falling edges of INT1, INT2, and INT3, respectively. The active edge is selected by the interrupt mode register (IMRA, IMRB). Table 5 External Interrupt Request Flags IF0-IF5 Interrupt Request 0 Disabled 1 Enabled External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1; IM2: $001, Bit 3; IM3: $022, Bit 3; IM4: $023, Bit 1; IM5: $023, Bit 3): Mask interrupt requests caused by the corresponding external interrupt request flags (table 6). Table 6 External Interrupt Masks IM0-IM5 Interrupt Request 0 Enabled 1 Disabled (Masked) Input Capture Interrupt Request Flag (IFIC: $002, Bit 0): Set by an overflow from timer/counter F if bit 0 of the input capture status register (ICSR) is 0, and an input capture input if bit 0 of ICSR is 1 (table 7). Table 7 Input Capture Interrupt Request Flag IFIC Interrupt Request 0 Disabled 1 Enabled Input Capture Interrupt Mask (IMIC: $002, Bit 1): Masks an interrupt request caused by the input capture interrupt request flag (table 8). Table 8 Input Capture Interrupt Mask IMIC Interrupt Request 0 Enabled 1 Disabled (Masked) 26 HD404439 Series Timer A Interrupt Request Flag (IFTA: $002, Bit 2): Set by an overflow from timer A (table 9). Table 9 Timer A Interrupt Request Flag IFTA Interrupt Request 0 Disabled 1 Enabled Timer A Interrupt Mask (IMTA: $002, Bit 3): Masks an interrupt request caused by the timer A interrupt request flag (table 10). Table 10 Timer A Interrupt Mask IMTA Interrupt Request 0 Enabled 1 Disabled (Masked) Timer B Interrupt Request Flag (IFTB: $003, Bit 0): Set by an overflow from timer B (table 11). Table 11 Timer B Interrupt Request Flag IFTB Interrupt Request 0 Disabled 1 Enabled Timer B Interrupt Mask (IMTB: $003, Bit 1): Masks an interrupt request caused by the timer B interrupt request flag (table 12). Table 12 Timer B Interrupt Mask IMTB Interrupt Request 0 Enabled 1 Disabled (Masked) Timer C Interrupt Request Flag (IFTC: $003, Bit 2): Set by an overflow from timer C (table 13). Table 13 Timer C Interrupt Request Flag IFTC Interrupt Request 0 Disabled 1 Enabled 27 HD404439Series Timer C Interrupt Mask (IMTC: $003, Bit 3): Masks an interrupt request caused by the timer C interrupt request flag (table 14). Table 14 Timer C Interrupt Mask IMTC Interrupt Request 0 Enabled 1 Disabled (Masked) Timer D Interrupt Request Flag (IFTD: $021, Bit 0): Set by an overflow from timer D (table 15). Table 15 Timer D Interrupt Request Flag IFTD Interrupt Request 0 Disabled 1 Enabled Timer D Interrupt Mask (IMTD: $021, Bit 1): Masks an interrupt request caused by the timer D interrupt request flag (table 16). Table 16 Timer D Interrupt Mask IMTD Interrupt Request 0 Enabled 1 Disabled (Masked) Serial Interrupt Request Flags (IFS1: $021, Bit 2; IFS2: $024, Bit 0): Set when the octal counter counts the eighth clock signal or when data transmission stops, resetting the octal counter (table 17). Table 17 Serial Interrupt Request Flags IFS1, IFS2 Interrupt Request 0 Disabled 1 Enabled 28 HD404439 Series Serial Interrupt Masks (IMS1: $021, Bit 3; IMS2: $024, Bit 1): Mask an interrupt request caused by the serial 1 and serial 2 interrupt request flags (table 18). Table 18 Serial Interrupt Masks IMS1, IMS2 Interrupt Request 0 Enabled 1 Disabled (Masked) A/D Interrupt Request Flag (IFAD: $022, Bit 0): Set by the completion of an A/D conversion (table 19). Table 19 A/D Interrupt Request Flag IFAD Interrupt Request 0 Disabled 1 Enabled A/D Interrupt Mask (IMAD: $022, Bit 1): Masks an interrupt request caused by the A/D interrupt request flag (table 20). Table 20 A/D Interrupt Mask IMAD Interrupt Request 0 Enabled 1 Disabled (Masked) 29 HD404439Series Operating Modes Five operating modes are available, specified by how the clock is used, as shown in table 21. The functions available in each mode are listed in table 22, operations are listed in table 23, and transitions between operating modes are listed in figure 10. Table 21 Low-Power Dissipation Modes System Clock ( CPU ) Non-time-base peripheral function clock ( PER) Operating Stopped Operating Active mode (LSON = 0) Standby mode Stopped Subactive mode (optional) (LSON = 1) Watch mode (TMA3 = 1) Stop mode (TMA3 = 0) Table 22 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Active Mode Subactive Mode *4 System oscillator Stopped Stopped OP OP Stopped 2 Subsystem oscillator OP * OP OP OP OP CPU operation Instruction ( CPU ) execution Stopped Stopped Stopped OP OP RAM Retained Retained Retained OP OP Registers, flags Reset Retained Retained OP OP I/O*3 Reset Retained Retained OP OP Reset Retained OP OP Retained Timer A Reset Retained OP OP Retained Timer B Reset Retained OP OP Retained Timer C Reset Retained OP OP Retained Timer D Reset Retained OP OP Retained Timer E (PWM) Reset Retained OP OP Retained Input capture Reset Retained OP OP Retained Output compare Retained OP OP Retained Peripheral INT0-INT5 functions, interrupts ( PER) 30 Reset HD404439 Series Function Peripheral Serial 1, functions, Serial 2 interrupts ( PER) A/D Time-base INT0 functions, interrupts ( CLK ) Time-base Notes: 1 2 3 4 5 6 Table 23 Stop Mode Watch Mode Standby Mode Active Mode Subactive Mode *4 Reset Retained OP OP Retained Reset Retained OP Reset OP* 5 Reset OP*5 OP* OP 6 OP*6 Retained 6 OP*5 OP*6 OP*5 OP* OP indicates operating. To reduce ICC, stop oscillation in external circuits. Refer to table 23. Subactive mode is an optional function. Refer to the Interrupt Frame section. If TMA3 is set to 1, timer A and INT0 are switched to time-base function and interrupt, respectively. Input/Output in Low-Power Dissipation Modes Output Standby Mode Input Stop/Watch/ Subactive Mode All Modes (input state) D0-D15 Retained/peripheral function High impedance output Input enabled R0-RD Retained/peripheral function High impedance output Input enabled Note: Applying a voltage of between (VCC - 0.3) and (GND + 0.3 V) to input-state pins increases the current dissipation. 31 HD404439Series Reset Standby mode Active mode Stop mode (TMA3 = 0) fOSC: fCL: oCPU: oCLK: oPER: Operating Operating Stopped = fcyc = fcyc SBY (Standby) Interrupt fOSC: fCL: oCPU: oCLK: oPER: Operating Operating = fcyc = fcyc = fcyc fOSC: fCL: oCPU: oCLK: oPER: STOP Stopped Operating Stopped Stopped Stopped TMA3 = 0 Watch mode TMA3 = 1 fOSC: fCL: oCPU: oCLK: oPER: Operating Operating Stopped = fSUB = fcyc SBY (Standby) Interrupt fOSC: fCL: oCPU: oCLK: oPER: Operating Operating = fcyc = fSUB = fcyc (TMA3 = 1, LSON = 0) STOP fOSC: fCL: oCPU: oCLK: oPER: INT0 Time-base*1 Stopped Operating Stopped = fSUB Stopped *2 Main oscillation Suboscillation for time-base fcyc: fOSC/4 fSUB: fCL/8 oCPU: System clock oCLK: Clock for time-base oPER: Clock for other peripheral functions LSON: Low speed on flag LSON = 0: oCPU = Main oscillator LSON = 1: oCPU = Suboscillator STOP/SBY fOSC: fCL: Notes: Subactive mode fOSC: fCL: oCPU: oCLK: oPER: Stopped Operating = fSUB = fSUB Stopped (TMA3 = 1, LSON = 1) INT0 Time-base*1 STOP/ SBY Stopped Operating Stopped = fSUB Stopped *1. Interrupt source *2. The mode changes shown above are the result of the STOP or SBY instruction while DTON (direct transfer on flag) is 1 and LSON is 0. Figure 10 MCU Status Transitions 32 fOSC: fCL: oCPU: oCLK: oPER: HD404439 Series Active Mode: The MCU operates according to the clock generated by the system oscillator. Standby Mode: The MCU enters standby mode if the SBY instruction is executed in active mode. In this mode, the oscillator remains active and peripheral functions such as interrupts, timer/counters, and the serial interface are enabled, although all instruction-control clocks stop. The stopping of these clocks stops the CPU, retaining all RAM and register contents and maintaining the current I/O pin status. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by a RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the instruction following the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and the program is resumed. A flowchart of operation in standby mode is shown in figure 11. 33 34 Figure 11 Flowchart of Watch and Standby Modes No Reset MCU Restart processor clocks Yes RESET? Yes IM0? Yes IF0? Oscillator: Active Peripheral clocks: Active All other clocks: Stopped Standby No No No No (SBY only) Yes IM1? Yes IF1? No No (SBY only) Yes IM2? Yes IF2? Oscillator: Stopped Suboscillator: Active Peripheral clocks: Stopped All other clocks: Stopped Watch No No Yes IMTA? Yes IFTA? Execute next instruction (SBY only) Yes IMIC? Yes IFIC? No No No No No No No (SBY only) Yes IMTC? Yes IFTC? IF = 1, IM = 0, and IE = 1? Yes Interrupt acceptance Execute next instruction (SBY only) Yes IMTB? Yes IFTB? No No No No (SBY only) Yes IMS1? IFS1? Yes Restart processor clocks (SBY only) Yes IMTD? Yes IFTD? No No (SBY only) Yes IMAD? IFAD? Yes No No (SBY only) Yes IM3? Yes IF3? No No (SBY only) Yes IM4? Yes IF4? No No No No (SBY only) Yes IMS2? Yes IFS2? (SBY only) Yes IM5? IF5? Yes HD404439Series HD404439 Series Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode while TMA3 = 0. In this mode, the system oscillator stops, causing all MCU functions to stop as well. Stop mode is terminated by a RESET input as shown in figure 12. RESET must be high for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). In stop mode, all RAM contents are retained. After stop mode is cancelled, the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register are not retained. Stop mode Oscillator Internal clock RESET tres STOP instruction execution tres tRC (stabilization time) Figure 12 Timing of Stop Mode Cancellation Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode while TMA3 = 1, or if the STOP/SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input, a timer A interrupt request, or a INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer A interrupt request or a INT0 interrupt request, the MCU enters active mode if LSON is 0 or subactive mode if LSON is 1. Any interrupt request generated during the transition to active mode is delayed for half the interrupt frame period (t RC) to give the oscillation time to stabilize (figure 14). Operation during mode transition is the same as that at standby mode cancellation (figure 11). 35 HD404439Series Subactive Mode: The CPU operates with a clock generated by the CL 1 and CL2 oscillation circuits. Functions which can operate in subactive mode are listed in table 22. The MCU enters active mode from subactive mode by the following steps. The MCU enters watch mode if the STOP or SBY instruction is executed in subactive mode while the LSON is reset and the DTON is set. At the next interrupt frame, the MCU waits for the oscillation time selected by the MIS to stabilize, and then enters active mode (figure 13). After that, the DTON is automatically reset (the DTON can be set only in subactive mode). Subactive mode is an optional function that the user must specify on the function option list. STOP/SBY execution Subactive mode Internal execution time (< T) Oscillation stabilization time Active mode Interrupt strobe Interrupt request tRC T tRC < transition < 3tRC time T = 2 x tRC: Interrupt frame period tRC: Oscillation stabilization time Figure 13 Timing of Subactive Mode Direct Transition Oscillation stabilization time Watch mode Active mode Interrupt strobe Interrupt request (only during transition to active mode) T T T = 2 x tRC: Interrupt frame period Figure 14 Interrupt Frame 36 tRC tRC = Oscillation stabilization time HD404439 Series Interrupt Frame: In watch and subactive modes, timer A and INT0 interrupts are generated in synchronism with the interrupt frame. The interrupt frame is repeated at the timing shown in figure 14. Three interrupt frame cycles can be selected by the settings of the miscellaneous register (figure 15). The period from the interrupt strobe to the interrupt request generation is used as the oscillation time to stabilize during the transition from watch mode to active mode. Operation during the transition from watch mode to active mode is the same as a standby mode cancellation. The overflow timing during the transition to active mode by the timer A interrupt request is the same as the interrupt strobe shown in figure 14. MIS: $00C MIS3 MIS2 MIS1 MIS0 Initial value: 0000, R/W:W tRC selection MIS Bit 1 Bit 0 T/2, tRC 0 0 0.12207 ms 1 7.8125 ms 0 62.5 ms 1 Not used 1 Note: Only when a 32.768-kHz oscillation is used. T: Interrupt frame period tRC: Oscillation stabilization time Figure 15 Miscellaneous Register 37 HD404439Series Direct Transfer: By controlling the DTON, the MCU would be placed directly from subactive to active mode. The detailed procedure is as follows: * Set the DTON flag in subactive mode while LSON = 0 * Execute the STOP or SBY instruction. * After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive to active mode (figure 13). Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag is always at reset. The transition time (tD) from subactive to active mode is tRC < tD < T + tRC. MCU Operation Sequence: The MCU operates in the sequence shown in figures 16 to 18. It is reset by a RESET input, regardless of its state. The low-power mode operation sequence is shown in figure 18. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 1? No Yes MCU operation cycle Reset MCU Figure 16 MCU Operation Flowchart (Power On) 38 HD404439 Series MCU operation cycle IF = 1? No Yes No IM = 0, IE = 1? Instruction execution Yes SBY/STOP instruction? Yes IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 17 MCU Operation Flowchart (MCU Operation Cycle) 39 HD404439Series Low-power mode operation cycle IF = 1, IM = 0? No Yes Standby/watch mode No Stop mode * IF = 1, IM = 0? Yes Hardware NOP execution Hardware NOP execution PC Next location PC Next location Instruction execution MCU operation cycle Note: * For IF and IM operation, refer to figure11. Figure 18 MCU Operation Flowchart (Low-Power Dissipation Mode Operation) 40 HD404439 Series Internal Oscillator Circuit A block diagram of the internal oscillator circuit is shown in figure 19. As shown in table 24, a crystal or a ceramic oscillator can be connected to OSC 1 and OSC2, and a crystal oscillator of 32.768-kHz can be connected to CL1 and CL2. External clock operation of the system oscillator is also available. If a subsystem oscillator is not used, fix the CL1 pin to VCC or GND. CL2 CL1 OSC1 OSC2 System oscillator Subsystem oscillator fCL fOSC Divider (1/4) Divider (1/8) tsubcyc Timing generator Timing generator TMA3 fcyc tcyc fSUB System clock selection Time-base clock selection oCLK Time-base/ interrupt oPER Peripheral functions/interrupts LSON oCPU CPU * ROM * RAM * I/O * Registers, flags Figure 19 Internal Oscillator Circuit 41 HD404439Series TEST CL2 CL1 GND OSC2 OSC1 RESET Figure 20 Pattern Layout Example of Oscillator Circuit 42 HD404439 Series Table 24 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation (OSC1, OSC2) External oscillator OSC1 Open Ceramic oscillator (OSC1, OSC2) OSC2 Ceramic oscillator: C1 Ceramic oscillator OSC1 CSA4.00MG (Murata) Rf = 1 M 20% Rf C1 = C2 = 33 pF 20% OSC2 C2 GND Crystal oscillator (OSC1, OSC2) Rf = 1 M 20% C1 Crystal OSC1 C1 = C2 = 22 pF 20% OSC2 Crystal: Equivalent to circuit shown at bottom left Rf C2 C0 = 7 pF, max. GND Rs = 100 , max. L CS RS OSC1 OSC2 f = 1.6 to 4.5 MHz C0 Crystal oscillator (CL1, CL2) C1 = C2 = 15 pF 5% C1 CL1 Crystal: MX38T Crystal (Nihon Dempa Kogyo) CL2 C0 = 1.5 pF, typ. C2 Rs = 14 k, typ. GND CL1 L CS RS CL2 f = 32.768-kHz C0 Notes: 1. The circuit constants given above are recommended values provided by the oscillator manufacturer. Since they may be affected by stray capacitances from the oscillator or board, consult the crystal oscillator or ceramic oscillator manufacturer to determine the actual circuit parameters required. 2. Wiring between the OSC1/OSC2 pins and other elements must be as short as possible, and must not cross other wiring. Refer to the recommended layout of the oscillation circuit in figure 20. 3. If not using a 32.768-kHz crystal oscillator, fix the CL1 pin to GND and leave the CL2 pin open. 43 HD404439Series Input/Output The MCU (mask ROM version) has 70 input/output pins, 33 of the input/output pins being standard pins whose circuits can be selected as with pull-up MOS (B) or without pull-up MOS (C) option. The HD404719 has 37 other high-voltage pins whose circuits can be selected as with pull-down MOS (E) or without pull-down MOS (D) option. If the former option is selected, the R50/Vdisp pin must be set as Vdisp by the mask option because the source of the pull-down MOS is connected to Vdisp. The HD404439 has no high-voltage pins. The pins corresponding to the HD404719 high-voltage pins are standard open-drain PMOS pins in the HD404439. The circuits must be without pull-down MOS (D). The R5 0 pin is only used as an input port. The HD4074719 has only the pins without pull-up MOS (C) and without pull-down MOS (D). D Port: The 16 out of 70 I/O pins that are discrete pins (D port), accessed individually. These pins are set by the SED and SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD instructions. Input/output pin types are shown in table 25. R Ports: Accessed in 4-bit units. Data is input to the ports by the LAR and LBR instructions and output from them by the LRA and LRB instructions. The R6 to RB output buffers are turned on and off by R-port data control registers (DCR6-DCRB). Input/output pin types are listed in table 25. Input/output buffer and pin mode selection registers are shown in figures 21 and 22. Mask Options: The circuits of the HD4074719 are either without pull-up MOS (C) or without pull-down MOS (D), as shown in table 25 and figure 21. Options either with pull-up MOS (B) or with pull-down MOS (E) can be selected for the HD404719, and an option with pull-up MOS (B) can be selected for the HD404439. However, note that these MCUs are not compatible with the HD4074719. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system must be fixed as follows to prevent LSI malfunctions due to noise. Note the following precautions: * For high-voltage pins, the without pull-down MOS option must be selected. The pins are connected to the VCC voltage of the user system. * For standard pins, the without pull-down MOS option must be selected. The pins are connected to the GND voltage of the user system. * Open-drain PMOS pins are connected to the VCC voltage of the user system. * Keep the contents of the PDR and DCR of unused I/O pins fixed to their initial values. Do not select these pins as peripheral function I/O pins. 44 HD404439 Series Table 25 (1) Pin Type Input/Output Pin Types: Standard Pins With Pull-Up MOS (B)/Without Pull-Up MOS (C) Input control I/O pins VCC Pin Name CPU input VCC MIS * HLT R60-R63 R70-R73 R80-R83 R90-R93 DCR RA0-RA3 RB0, RB1 PDR Note: * Applies to R82, R93 Input control CPU input VCC MIS * HLT DCR PDR Note: * Applies to R82, R93 VCC Input pins R51-R53 RC0-RC3 HLT Input control Input control Peripheral I/O pins CPU input CPU input SCK 1 Input control VCC RD0-RD3 CPU input SCK 2 SCK (output)*1 VCC HLT SCK 45 HD404439Series Pin Type With Pull-Up MOS (B)/Without Pull-Up MOS (C) SCK 1 Input control Peripheral I/O pins Pin Name CPU input SCK 2 SCK (output)*1 VCC HLT SCK Input control Peripheral output pins VCC CPU input VCC MIS SO1, SO2 TOC, TOD TOE1, TOE2 * TOG HLT BUZZ Output data Note: * Applies to SO1, SO2 Input control CPU input VCC MIS * HLT Output data Note: Peripheral input pins * Applies to SO1, SO2 SCK 1, SCK2 VCC (input)*1 Input control HLT SI1, SI2 Peripheral input INT0, INT1 CPU input INT4, INT5 INT2, INT3 ICT0, ICT1 Peripheral input Input control Note: 46 CPU input *1 If external clock mode is selected when the serial interface is used, SCK 1 and SCK 2 are used as input pins. HD404439 Series Pin Type Peripheral input pins With Pull-Up MOS (B)/Without Pull-Up MOS (C) Pin Name VCC AN0-AN7 Vref (R61) HLT A/D input or Vref Input control A/D input or Vref Input control Comparator I/O pins R60/COMP CPU input Input control Mode selection signal VCC VCC HLT DCR PDR Comparator CPU input Input control VCC Mode selection signal HLT DCR PDR 47 HD404439Series Table 25 (2) Pin Type Input/Output Pin Types: High-Voltage Pins (Open-Drain PMOS Pins)*2 Without Pull-Down MOS (D)/With Pull-Down MOS (E) Pin Name VCC I/O pins D0-D15 HLT R00-R03 PDR R10-R13 R20-R23 CPU input Input control R30-R33 R40-R43 VCC HLT PDR VCC Vdisp CPU input Input control Note: *2 The HD404439 has no high-voltage pins. The pins corresponding to the high-voltage pins are standard open-drain PMOS pins, therefore, the circuits must be used as with pull-down MOS (D). Option E cannot be selected. Table 25 (3) Input/Output Pin Types: High-Voltage Pins Pin Type Without Pull-Down MOS (D) Input pins Input control Pin Name R50 CPU input Notes: 3. In stop mode, the MCU is internally reset and peripheral functions are cancelled. The HLT signal goes high and the output pins are at high impedance. 4. In watch/subactive mode, the HLT signal goes high and the output pins are at high impedance. The input level of I/O pins selected for peripheral functions must be fixed since these pins are in input state. 5. Select the circuit type for a mask ROM MCU as shown below. A mask ROM MCU is compatible with a ZTAT MCU only when C- and D-type circuits are selected for the mask ROM MCU. Circuit Type 48 Product Type B C D E Mask ROM (HD404439) Optional Optional Fixed -- Mask ROM (HD404719) Optional Optional Optional Optional ZTAT (HD4074719) -- Fixed Fixed -- HD404439 Series VCC VCC HLT MIS* Pull-up MOS PMOS DCR Mask option (B) only NMOS PDR CPU input Input control Mask Option With Pull-Up MOS (B) DCR 0 PDR CMOS buffer Without Pull-Up MOS (C) 1 0 1 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- On On On -- -- -- -- Pull-up MOS (C) On --: Off Note: * For the R82/SO1 and R93/SO2 pins, the PMOSs are off when bits 2 and 3 of the miscellaneous register are set to 1. MIS MIS Bit 2 R82/SO1 PMOS Mode Bit 3 R93/SO2 PMOS Mode 0 On 0 On 1 Off 1 Off Figure 21 Input/Output Buffer 49 HD404439Series MIS: $00C Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R82/SO1 pin PMOS mode selection R93/SO2 pin PMOS mode selection SMR1: $005 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R90/SCK1 pin mode selection PMRA: $004 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R82/SO2 pin mode selection R83/SI1 pin mode selection R70/INT0 pin mode selection R71/INT1 pin mode selection SMR2: $014 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R91/SCK2 pin mode selection PMRB: $013 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R93/SO2 pin mode selection R92/SI2 pin mode selection RB0/TOC pin mode selection RB1/TOD pin mode selection PMRC: $030 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W R72/INT2 pin mode selection R73/INT3 pin mode selection R80/INT4 pin mode selection R81/INT5 pin mode selection Figure 22 Pin Mode Selection Registers 50 HD404439 Series Timers The MCU has two prescalers (S and W) and five timer/counters (A, B, C, D, and E). Block diagrams of the timers are shown in figures 23, 24, 26, and 29. Prescaler S: Eleven-bit counter that inputs the system clock signal. After being initialized to $000 by MCU reset, prescaler S divides the system clock frequency. Only at MCU reset or during watch and stop modes does prescaler S stop counting. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode register B (TMB), timer mode register C (TMC), and serial mode register (SMR), respectively. Prescaler W: Five-bit counter that inputs the CL 1 input clock signal divided by 8. Prescaler W output can be selected as a timer A input clock by timer mode register A. 51 HD404439Series tsubcyc Prescaler W (5 bits) /2 /8 /16 /32 1/2 1/4 Timer A MPX2 3 32-kHz crystal oscillator Timer mode register A (TMA, 4 bits) On: TMA3 = 1 Timer counter A (TCA, 8 bits) 3 On: TMA3 = 0 /2 /4 /8 /32 /128 /512 /1024 /2048 Timer A MPX1 System clock tcyc Prescaler S (11 bits) Figure 23 Block Diagram of Timer A 52 IFTA Interrupt request flag of timer A HD404439 Series Table 26 Timers A, B, and C Function Selection Timer A Condition Function TMA3 = 0 System clock-base interval timer TMA3 = 1 Clock time-base Timer B Condition Function TMB2-TMB0 111 Automatic reloading timer TMB2-TMB0 = 111 and PMRA3 = 1 Event counter (Pin R71/INT1 is specified as INT1) Timer C Condition Function WDON = 0 (PMRB2 = 1) Automatic reloading timer (Pin RB0/TOC is specified as TOC) WDON = 1 Watchdog timer 53 HD404439Series Internal data bus (S1) 4 Timer mode register B (TMB, 4 bits) INT1 Timer latch register B (TLB, 4 bits) 3 4 Timer counter B (TCB, 8 bits) Timer B MPX IFTB Timer B interrupt request flag /2048 /2 /4 /8 /32 /128 /512 Timer load register B (TLR, 8 bits) 4 4 Internal data bus (S2) Prescaler S (11 bits) /2 /4 /8 /32 /128 /512 /1024 /2048 System clock Internal data bus (S1) 4 TOC Timer latch register C (TLC, 4 bits) Timer C MPX 4 Timer C variable-duty pulse output IFTC Timer counter C (TCC, 8 bits) 3 MPX Timer mode register C (TMC, 4 bits) Timer load register C (TCR, 8 bits) 4 4 (Watchdog) Internal data bus (S2) WDON Watchdog on flag (Set only) Figure 24 Block Diagram of Timers B and C 54 Timer C interrupt request flag System reset HD404439 Series Timer A: Eight-bit timer which can be used as a clock time-base. Timer A is initialized to $00 by reset, then incremented by each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow that sets the timer A interrupt request flag (IFTA: $002, bit 2) is generated, and timer A restarts from $00. Timer A is an interval timer which overflows every 256 clock inputs. Timer A can also be used as a clock time-base when the TMA3 bit of timer mode register A (TMA) is set to 1. The timer is driven by the 32.768-kHz oscillator clock frequency divided by prescaler W. In this case, prescaler W and timer A can be initialized by software. The input clock of timer A is controlled by TMA. Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Eight-bit write-only timer load register (TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same address. The eight-bit configuration consists of lower and upper digits located at sequential addresses. Timer counter B is initialized by writing data to timer load register B (TLR). In this case, the lower digit must be written first. Both the upper and lower digits of TLR are loaded into the timer counter at the same time the upper digit is written to TLR. TLR is initialized to $00 by MCU reset. The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first; the count is latched at the same time the upper digit is read. An automatic reloading function, input clock source, and prescaler division ratio of timer B are selected by timer mode register B (TMB). When an external event input is used as the input clock source of timer B, the R71/INT1 pin must be specified as the INT1 pin by port mode register A (PMRA: $004) and the external interrupt mask (IM1) must be set to inhibit any INT1 interrupt request. Timer B is initialized to the value set in timer load register B (TLR) by software, and is then incremented by one every clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the automatic reloading function is enabled, timer B is initialized to its initial value; if reloading is disabled, the timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $003, bit 0). Timer C (TCCL: $00E, TCCU: $00F, TCRL: $00E, TCRU: $00F): Eight-bit write-only timer load register (TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same address. The eight-bit configuration consists of lower and upper digits located at sequential addresses. The operation of timer C is basically the same as that of timer B. An automatic reloading function and prescaler division ratio of timer C depend on the state of timer mode register C (TMC). Timer C is initialized to the value set in the TMC by software, and is then incremented by one every clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the automatic reloading function is enabled, timer C is initialized to its initial value; if the function is disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $003, bit 2). 55 HD404439Series Timer C also functions as a watchdog timer. The watchdog timer functions while the watchdog on (WDON) flag is set, and the MCU is reset by an overflow from timer C. If a program routine goes out of control, it can be detected by controlling the timer C reset before the count has reached $FF. Only a 1 can be written to the watchdog on flag. It can be cleared to 0 only by an MCU reset; it cannot be cleared by writing 0. Timer C has a variable-duty pulse output (TOC) whose output waveform depends on the status of timer mode register C (TMC) and timer load register C (TCR) as shown in figure 25. For pulse output, the RB0/TOC pins must be specified as TOC by port mode register B (PMRB). T x (TCR + 1) TMC3 = 0 T x 256 T TMC3 = 1 T x (256 - TCR) T: Period of clock input to the counter TCR: Value of timer load register C (0-255) Figure 25 Variable-Duty Pulse Output Waveform Timer Mode Register A (TMA: $008): Four-bit write-only register which controls timer A as shown in table 27. It is initialized to $0 by MCU reset. 56 HD404439 Series Table 27 Timer Mode Register A TMA Bit 3 Bit 2 Bit 1 Bit 0 Source Prescaler, Input Clock Period, Operating Mode 0 0 0 0 PSS, 2048 tcyc 1 PSS, 1024 tcyc 0 PSS, 512 tcyc 1 PSS, 128 tcyc 0 PSS, 32 tcyc 1 PSS, 8 tcyc 0 PSS, 4 tcyc 1 PSS, 2 tcyc 0 PSW, 32 tsubcyc 1 PSW, 16 tsubcyc 0 PSW, 8 tsubcyc 1 PSW, 2 tsubcyc 0 PSW, TCA reset 1 1 0 1 1 0 0 1 1 0 Timer A mode Time-base mode 1 1 0 1 Notes: 1. 2. 3. 4. tsubcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) tcyc = 0.9536 s (when a 4.1943-MHz crystal oscillator is used) Timer counter overflow output period(s) = Input clock period(s) x 256 The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Timer Mode Register B (TMB: $009): Four-bit write-only register which selects the automatic reloading function, input clock source, and the prescaler division ratio for timer B as shown in table 28. It is initialized to $0 by MCU reset. Changes made to TMB are valid from the second instruction cycle after the write instruction is executed. Timer B must be programmed so that it is initialized by a write instruction to timer load register B (TLR) after a mode change becomes valid. Table 28 Timer Mode Register B TMB Bit 3 Automatic Reloading 0 Disabled 1 Enabled 57 HD404439Series TMB Bit 2 Bit 1 Bit 0 Input Clock Period and Input Clock Source 0 0 0 2048 tcyc 1 512 tcyc 0 128 tcyc 1 32 tcyc 0 8 tcyc 1 4 tcyc 0 2 tcyc 1 INT1 (external event input) 1 1 0 1 Note: tcyc = 0.9536 s (when a 4.1943-MHz crystal oscillator with 1/4 division is used) Timer Mode Register C (TMC: $00D): Four-bit write-only register which selects the automatic reloading function and the prescaler division ratio for timer C as shown in table 29. It is initialized to $0 by MCU reset. Changes made to TMC are valid from the second instruction cycle after the write instruction is executed. Timer C must be programmed so that it is initialized by a write instruction to timer load register C (TCR) after a mode change becomes valid. Table 29 Timer Mode Register C TMC Bit 3 Automatic Reloading 0 Disabled 1 Enabled TMC Bit 2 Bit 1 Bit 0 Input Clock Period 0 0 0 2048 tcyc 1 1024 tcyc 0 512 tcyc 1 128 tcyc 0 32 tcyc 1 8 tcyc 0 4 tcyc 1 2 tcyc 1 1 0 1 Note: tcyc = 0.9536 s (when a 4.1943-MHz crystal oscillator with 1/4 division is used) 58 HD404439 Series Timer D (TCDL: $011, TCDU: $012, TDRL: $011, TDRU: $012): Eight-bit write-only timer load register (TDRL and TDRU) and read-only timer counter (TCDL and TCDU) located at the same address. The eight-bit configuration consists of lower and upper digits located at sequential addresses. An automatic reloading function and prescaler division ratio of timer D are selected by timer mode register D (TMD). Timer D is initialized to the value set in timer load register D (TDR) by software, and is then incremented by one every clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the automatic reloading function is enabled, timer D is initialized to its initial value; if reloading is disabled, the timer is initialized to $00. The overflow sets the timer D interrupt request flag (IFTD: $021, bit 0). Timer D has a variable-duty pulse output (TOD), whose output waveform depends on the states of timer mode register D (TMD) and timer load register D (TDR) as shown in figure 27. For pulse output, the RB1/TOD pin must be specified as TOD by port mode register B (PMRB). Timer Mode Register D (TMD: $010): Four-bit write-only register which selects the automatic reloading function and the prescaler division ratio for timer D as shown in figure 28. It is initialized to $0 by MCU reset. Changes made to TMD are valid from the second instruction cycle after the write instruction is executed. Timer D must be programmed so that it is initialized by a write instruction to timer load register D (TDR) after a mode change becomes valid. Internal data bus Prescaler S (11 bits) /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 System clock Timer latch register D (TLD, 4 bits) TOD Timer D MPX Timer mode register D (TMD, 4 bits) Timer counter D (TCD, 8 bits) IFTD Timer load register D (TDR, 8 bits) Internal data bus Figure 26 Block Diagram of Timer D 59 HD404439Series T x (TDR + 1) TMD3 = 0 T x 256 T TMD3 = 1 T x (256 - TDR) T: Period of clock input to the counter TDR: Value of timer load register D (0-255) Figure 27 Variable-Duty Pulse Output Waveform TMD: $010 Bit 3 Bit 1 Bit 2 Bit 0 Initial value: 0000, R/W: W Timer D input clock selection Automatic reloading selection Bit 2 Bit 1 Bit 0 Input Clock Period 0 0 0 2048 tcyc 1 1024 tcyc 0 512 tcyc 1 128 tcyc 0 32 tcyc 1 8 tcyc 0 4 tcyc 1 2 tcyc 1 1 0 1 Bit 3 Automatic Reloading Function 0 Disabled 1 Enabled Figure 28 Timer Mode Register D 60 HD404439 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 30. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 30 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Reload Timer write register updated to value N T Interrupt request T x (255 - N) T Timer write register updated to value N T x (N + 1) Interrupt request T T x (255 - N) T Timer E: Outputs two variable-duty pulses (PWM). The duty ratio can be selected by the setting of the load register (figure 30). To write data into the load register, timer buffer register E must be written to first. Data written to the buffer register is transferred to the load register by an overflow from the prescaler. Since the two channels use the same buffer register, the destination load register is selected by the bit 2 setting of the timer mode register E (TME). The completion of data transfer from the buffer register to the load register can be checked by reading bit 3 of TME. Timer Mode Register E (TME: $025): Four-bit register including three write-only bits and one read-only bit which selects the port and the load register and indicates the buffer register status (figure 31). 61 HD404439Series Timer Buffer Register E (TBEL: $026, TBEU: $027): Eight-bit write-only register. The lower digit must be written first. When the upper digit is written, bit 3 of timer mode register E is automatically set to 1. When the data in timer mode register E is loaded to the load register, bit 3 of timer mode register E is automatically reset to 0. Prescaler output Decodes $FF Compare circuit (1) Compare circuit (2) Timer load register (1) (TLE1, 8 bits) S R R S Q Timer load register (2) (TLE2, 8 bits) Q (TME bit 2) Timer buffer register E (TBE, 8 bits) R 4 4 S (TME bit 3) R63/TOE2 TOE2 R62/TOE1 TOE1 Q Internal data bus Figure 29 Block Diagram of Timer E (TLE + 1)tcyc TOE1, TOE2 256tcyc TLE: Value of timer load register tcyc: System clock period Figure 30 Variable-Duty Pulse Output Waveform 62 HD404439 Series TME: $025 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: R/W R62/TOE1 pin mode selection R63/TOE2 pin mode selection Buffer register load destination selection Buffer register status Bit 0 R62/TOE1 Pin Mode Selection 0 R62 port 1 TOE1 output Bit 1 R63/TOE2 Pin Mode Selection 0 R63 port 1 TOE2 output Bit 2 Buffer Register Load Destination Selection 0 TLE1 1 TLE2 Bit 3 Buffer Register Status Set When the upper 4 bits are written Reset After the data has been loaded to the load register Figure 31 Timer Mode Register E Input Capture Timer: Eight-bit counter and 8-bit input capture register. The block diagram is shown in figure 32. Free-running counter operation or input capture operation can be selected by setting the input capture status register. When the free-running counter operation is selected, the counter is incremented by one every prescaler clock input, whose division ratio is specified by the input capture control register. If an overflow is generated from the counter, the input capture interrupt request flag is set, and the counter is initialized to $00. It is then incremented. When the input capture operation is selected, the count of the 8-bit counter is loaded into the input capture register by every trigger edge input of ICT0 or ICT1. At this point, the input capture interrupt request flag and input capture status flag are set and the counter is initialized to $00, and is then incremented. An external trigger input while the status flag is 1 or an overflow from the counter (when the counter continues to increment without receiving trigger input) sets bit 3 of the status register. Input Capture Control Register (ICC: $017): Four-bit write-only register which selects the pin function and the prescaler division ratio. Input Capture Status Register (ICSR: $018): Four-bit register which selects the input capture operation and the trigger input edge, and holds the operation status. 63 HD404439Series Input Capture Register (ICRL: $019, ICRU: $01A): Eight-bit read-only register which loads the contents of the counter by a trigger edge input of ICT0 or ICT1. Internal data bus $017 ICRL $019 ICC 2 ICRU $01A $018 Input capture register 2 ICSR ICT0 Edge detector ICT1 R 8-bit counter Input capture MPX System clock OVF Free running IFIC Prescaler S Figure 32 Block Diagram of Input Capture Timer ICC: $017 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W RA0/ICT0 pin mode selection RA1/ICT1 pin mode selection Prescaler division ratio selection Bit 0 RA0/ICT0 Pin Mode Selection Bit 1 RA1/ICT1 Pin Mode Selection 0 RA0 port 0 RA1 port 1 ICT0 input 1 ICT1 input Bit 3 Bit 2 Prescaler Division Ratio 0 0 /128 1 /32 0 /8 1 /2 1 Note: Setting both bits 0 and 1 to 1 is inhibited. Figure 33 Input Capture Control Register 64 HD404439 Series ICSR: $018 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: R/W Input capture enable (EIC) Detection edge selection Input capture status flag Error flag Bit 0 Input Capture Enable (EIC) Bit 1 Detection Edge Selection 0 Free-running counter operation enabled 0 Rising edge 1 Input capture operation enabled 1 Falling edge Bit 2 Input Capture Status Flag Set When executing the input capture operation by external trigger input Note: Read enabled. Only zero write enabled. Bit 3 Error Flag Set By an external trigger input while the status flag is 1. By an overflow from the counter. Note: Read enabled. Only zero write enabled. Figure 34 Input Capture Status Register 65 HD404439Series Output Compare Timer: A 16-bit counter and 16-bit register. The output compare timer outputs a wave whose form changes at a specified timing. This timing to change the waveform can be selected as an overflow from the 16-bit counter, an input edge of INT4, or a trigger by software. The block diagram is shown in figure 35. An output of 1, an output of 0, or a toggle (inversion of the previous output value) can be selected as the output of pin TOG. Timer counter G, the counter for output compare, is a 16-bit counter. The system clock or the system clock divided by 2 can be selected as the clock source. Timer counter G is a reloading counter. At the time of a counter overflow, an INT4 edge input, or a software trigger, the contents of timer load register G are loaded into timer counter G. An output compare interrupt is generated at the falling edge of INT4 or a counter overflow, depending on the selection set with bit 3 of the output compare control register. When selecting a software trigger, set both bits 2 and 3 of the output compare control register to 1 (figure 36). At the same time the bits are set, pin TOG outputs a specified value and the contents of the load register are loaded into the counter. Internal data bus 4 OCC: $02A System clock /2 Output compare control register Timer load register G (TLG) (TLG1L) (TLG1U) (TLG2L) (TLG2U) MPX Timer counter G (TCG) 4 OCSR: $02B Output compare status register OVF Reload control Output control TOG INT4 Edge detector Figure 35 Block Diagram of Output Compare Timer 66 IF4 INT request HD404439 Series OCC: $02A Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W RA2/TOG pin mode selection Timer counter G clock source selection Software trigger Output change trigger source/ interrupt request flag set Bit 0 RA2/TOG Pin Mode Selection Bit 1 Timer Counter G Clock Source Selection 0 RA2 port 0 System clock 1 TOG (output compare) output 1 System clock / 2 Bit 2 Bit 3 Software Trigger 1 1 TOG output value changes as specified by software Bit 3 Output Change Trigger Source/Interrupt Request Flag Set 0 INT4 input is valid 1 Overflow from the counter is valid Figure 36 Output Compare Control Register OCSR: $02B Bit 3 Bit 2 Bit 1 Bit 0 Initial value: --00, R/W: W Output level selection Not used Bit 1 Bit 0 Output Level Selection 0 0 0 1 1 0 Toggle (inverting at every triggering) 1 Inhibited 1 Figure 37 Output Compare Status Register Buzzer Output Function: Outputs a wave which has a duty ratio of 50% of the clock rate specified by the buzzer control register (BCR). To output a buzzer, the RA3/BUZZ pin must be fixed as BUZZ by setting bit 3 of the buzzer control register. The block diagram of buzzer output is shown in figure 38. Buzzer Control Register (BCR: $029): Four-bit write-only register which selects the port and the output wave frequency (figure 39). 67 HD404439Series System clock / 2048 / 1024 / 512 / 128 / 256 / 32 / 64 / 16 Prescaler S / 2 MPX RA3/BUZZ 3 Buzzer control register (BCR, 4 bits) Internal data bus Figure 38 Block Diagram of Buzzer Output BCR: $029 Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W RA3/BUZZ pin mode selection Output wave period Bit 0 RA3/BUZZ Pin Mode Selection 0 RA3 port 1 BUZZ output Bit 3 Bit 2 Bit 1 Output Wave Period 0 0 0 4096 tcyc 1 2048 tcyc 0 1024 tcyc 1 512 tcyc 0 256 tcyc 1 128 tcyc 0 64 tcyc 1 32 tcyc 1 1 0 1 Figure 39 Buzzer Control Register 68 BUZZ HD404439 Series Serial Interface The MCU has two clock-synchronous 8-bit serial interfaces (serial interface 1 and serial interface 2). The clock source is a prescaler, which is also used by the timers. Serial Interface 1: Used to serially transmit and receive 8-bit data. It consists of serial data register 1 (SR1), serial mode register 1 (SMR1), port mode register A (PMRA), an octal counter, and a multiplexer as shown in figure 40. The R90/SCK 1 pin and the transmit clock are controlled by writing data to SMR1. The transmit clock shifts the contents of SR1, which can be read and written to by software. In this way, 8-bit data is transferred. Serial interface 1 is activated by the STS instruction. The octal counter is reset to $0 by the STS instruction, it starts counting at the falling edge of the transmit clock (SCK1), and it increments at the rising edge of the clock. When the eighth transmit clock signal is input (serial interface 1 is reset) or when serial transmission is discontinued (octal counter is reset), the serial 1 interrupt request flag (IFS1) is set. System clock Octal counter (OC, 3 bits) Prescaler S (11 bits) IFS1 /2 /8 /32 /128 /512 /2048 Interrupt request flag of serial interface 1 Internal data bus (S1) /2 Serial MPX SROF MPX 4 SCK1 4 Serial data register 1 (SR1, 8 bits) Serial mode register 1 (SMR1, 4 bits) 4 Port mode register A (PMRA, 4 bits) 4 Internal data bus (S2) 4 4 Internal data bus (S2) SCK1 2 R90/SCK1 port SCK1 R83/SI1 port SI1 R82/SO1 port SO1 Figure 40 Serial Interface 1 Block Diagram 69 HD404439Series Serial Mode Register 1 (SMR1: $005): Four-bit write-only register which controls the R90/SCK 1 pin, transmit clock, and prescaler division ratio for serial interface 1 as shown in figure 41. Writing to SMR1 initializes serial interface 1. A write signal input to SMR1 discontinues the input of the transmit clock to serial data register 1 (SR1) and the octal counter. Therefore, if a write occurs during data transmission, the octal counter is reset to $0 to stop transmission, and, at the same time, the serial 1 interrupt request flag (IFS1) is set. The contents of the serial mode register are not valid until the second instruction cycle after the write instruction execution. The user must program the STS instruction to be executed after this instruction cycle. The serial mode register is initialized to $0 by MCU reset. SMR1: $005 SMR13 SMR12 SMR11 SMR10 Initial value: 0000, R/W: W Transmit clock selection R90/SCK1 pin mode selection SMR13 R90/SCK1 Pin 0 R90 port input/output pin 1 SCK1 input/output pin Transmit Clock SMR12 SMR11 SMR10 R90/SCK1 Pin 0 0 1 1 0 1 Clock Source Prescaler Division Ratio Transmit Clock Period 0 SCK1 output Prescaler / 2048 4096 tcyc 1 SCK1 output Prescaler / 512 1024 tcyc 0 SCK1 output Prescaler / 128 256 tcyc 1 SCK1 output Prescaler / 32 64 tcyc 0 SCK1 output Prescaler /8 16 tcyc 1 SCK1 output Prescaler /2 4 tcyc 0 SCK1 output System clock 1 SCK1 input External clock Figure 41 Serial Mode Register 1 70 tcyc HD404439 Series Serial Data Register 1 (SR1L: $006, SR1U: $007): Eight-bit read/write register separated into lower and upper digits located at sequential addresses. Data in this register is output from the SO 1 pin LSB first, synchronously with the falling edge of the transmit clock, and data is input to the LSB first through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 42. Data cannot be read or written during serial data transmission. If data is read or written during transmission, it cannot be guaranteed. Selecting and Changing Operating Modes: The operating modes of serial interface 1 are shown in table 31. The combination of port mode register A (PMRA) and serial mode register 1 (SMR1) must be specified as shown in the table. To change the operating mode of serial interface 1, internally initialize serial interface 1 by writing to SMR1. Table 31 Operating Modes of Serial Interface 1 SMR1 PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 42 Serial Interface 1 Timing Serial Interface 1 Operation: Three operating modes are provided for serial interface 1; transitions between them are shown in figure 43. In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed, serial interface 1 enters transmit clock wait state. In transmit clock wait state, input of the transmit clock increments the octal counter, shifts serial data register 1 (SR1), and starts serial transmission. However, note that if continuous clock output mode is selected, the transmit clock is continuously output, but data is not transmitted. 71 HD404439Series During transmission, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and serial interface 1 enters transmit clock wait state. If an external transmit clock is further applied, serial interface 1 enters the transfer state. In this state, if the internal clock has been selected, the serial 1 interrupt flag is set, serial interface 1 enters STS instruction wait state, and serial transmission is stopped after the eighth clock is output. If port mode register A (PMRA) is written to in transmit clock wait state or during transmission, serial mode register 1 (SMR1) must be written to, to initialize serial interface 1, after which serial interface 1 enters STS wait state. STS instruction wait state (octal counter = 000, transmit clock disabled) SMR1 write (IFS1 1) SMR1 write (IFS1 1) 8 transmit clocks (internal clock) (IFS1 1) STS instruction Transmit clock Transmit clock wait state (octal counter = 000) (IFS1 1) Transfer state (octal counter 000) 8 transmit clocks (external clock) STS instruction Figure 43 Serial Interface 1 Mode Transitions Transmit Clock Error Detection: Serial interface 1 will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock. Such errors can be detected as shown in figure 44. If more than eight transmit clocks are input in transmit clock wait state, serial interface 1's state changes to transfer state, transmit clock wait state, then back to transfer state. When serial interface 1 is set to STS wait state by writing data to SMR1 during transmission after the serial 1 interrupt request flag (IFS1) has been reset, the flag is set again. 72 HD404439 Series Transmit/receive (IFS1 1) Interrupts inhibited IFS1 0 SMR1 write IFS1 = 1 ? Yes Transmit clock error processing No Normal end Figure 44 Transmit Clock Error Detection Serial Interface 2: Used to serially transmit and receive 8-bit data. It consists of serial data register 2 (SR2), serial mode register 2 (SMR2), port mode register B (PMRB), an octal counter, and a multiplexer as shown in figure 45. The R91/SCK 2 pin and the transmit clock are controlled by writing data to SMR2. The transmit clock shifts the contents of the SR2, which can be read and written to by software, and then transmission starts between two MCUs. Serial interface 2 is activated by a read instruction for SMR2. The octal counter is reset to $0 by the read instruction for SMR2, it starts counting at the falling edge of the transmit clock (SCK2), and it increments at the rising edge of the clock. When the eighth transmit clock signal is input (serial interface 2 is reset) or when serial transmission is discontinued (octal counter is reset), the serial 2 interrupt request flag (IFS2) is set. To start serial interface 2 by an SMR2 read, execute a compare instruction on SMR2 and the accumulator. Note that 0000 is read when write-only register SMR2 is accessed. 73 HD404439Series System clock Octal counter (OC, 3 bits) Prescaler S (11 bits) IFS2 /2 /8 /32 /128 /512 /2048 Interrupt request flag of serial interface 2 Internal data bus (S1) /2 Serial MPX SROF MPX 4 SCK2 4 Serial data register 2 (SR2, 8 bits) Serial mode register 2 (SMR2, 4 bits) 4 Port mode register B (PMRB, 4 bits) 4 Internal data bus (S2) 4 4 Internal data bus (S2) SCK2 2 R91/SCK2 port SCK2 R92/SI2 port SI2 R93/SO2 port SO2 Figure 45 Serial Interface 2 Block Diagram Serial Mode Register 2 (SMR2: $014): Four-bit write-only register which controls the R91/SCK 2 pin, transmit clock, and prescaler division ratio as shown in figure 46. Writing to SMR2 initializes serial interface 2. A write signal input to SMR2 discontinues the input of the transmit clock to serial data register 2 (SR2) and the octal counter. Therefore, if a write occurs during data transmission, the octal counter is reset to $0 to stop transmission, and, at the same time, the serial 2 interrupt request flag (IFS2) is set. The contents of the serial mode register are not valid until the second instruction cycle after the write instruction execution. The user must program the SMR2 read instruction to be executed after this instruction cycle. The serial mode register is initialized to $0 by MCU reset. 74 HD404439 Series SMR2: $014 SMR23 SMR22 SMR21 SMR20 Initial value: 0000, R/W: W Transmit clock selection R91/SCK2 pin mode selection SMR23 R91/SCK2 0 R91 port input/output pin 1 SCK2 input/output pin Transmit Clock SMR22 SMR21 SMR20 R91/SCK2 Pin 0 0 1 1 0 1 Clock Source Prescaler Division Ratio Transmit Clock Period 0 SCK2 output Prescaler / 2048 4096 tcyc 1 SCK2 output Prescaler / 512 1024 tcyc 0 SCK2 output Prescaler / 128 256 tcyc 1 SCK2 output Prescaler / 32 64 tcyc 0 SCK2 output Prescaler /8 16 tcyc 1 SCK2 output Prescaler /2 4 tcyc 0 SCK2 output System clock 1 SCK2 input External clock tcyc Figure 46 Serial Mode Register 2 Serial Data Register 2 (SR2L: $015, SR2U: $016): Eight-bit read/write register separated into lower and upper digits located at sequential addresses. Data in this register is output from the SO 2 pin LSB first, synchronously with the falling edge of the transmit clock, and data is input, LSB first through the SI2 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 47. Data cannot be read or written during serial data transmission. If data is read or written during transmission, it cannot be guaranteed. Transmit clock 1 Serial output data 2 3 4 5 6 7 LSB 8 MSB Serial input data latch timing Figure 47 Serial Interface 2 Timing 75 HD404439Series Selecting and Changing Operating Modes: Table 32 lists the operating modes of serial interface 2. The combination of port mode register B (PMRB) and serial mode register 2 (SMR2) must be specified as shown in the table. To change the operating mode of serial interface 2, internally initialize serial interface 2 by writing to SMR2. Table 32 Operating Modes of Serial Interface 2 SMR2 PMRB Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Serial Interface 2 Operation: Three operating modes are provided for serial interface 2; transitions between them are shown in figure 48. In SMR2 read wait state, serial interface 2 is initialized and the transmit clock is ignored. If an SMR2 read is executed, serial interface 2 enters transmit clock wait state. In transmit clock wait state, input of the transmit clock increments the octal counter, shifts serial data register 2 (SR2), and starts serial transmission. However, note that if continuous clock output mode is selected, the transmit clock is continuously output, but data is not transmitted. During transmission, the input of 8 clocks or a SMR2 read sets the octal counter to 000, and serial interface 2 enters transmit clock wait state. If an external transmit clock is further applied, serial interface 2 enters transfer state. If the internal clock has been selected, the serial 2 interrupt flag is set, serial interface 2 enters SMR2 read wait state, and serial transmisson is stopped after the eighth clock is output. If port mode register B (PMRB) is written to in transmit clock wait state or during transmission, SMR2 must be written to, to initialize serial interface 2, after which serial interface 2 enters SMR2 read (serial start) wait state. 76 HD404439 Series SMR2 read wait state (octal counter = 000, transmit clock disabled) SMR2 write (IFS2 1) SMR2 write (IFS2 1) 8 transmit clocks (internal clock) (IFS2 1) SMR2 dummy read (serial 2 start) Transmit clock Transmit clock wait state (octal counter = 000) (IFS2 1) Transfer state (octal counter 000) 8 transmit clocks (external clock) SMR2 dummy read Figure 48 Serial Interface 2 Mode Transitions Transmit Clock Error Detection: Serial interface 2 will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock. Such errors can be detected as shown in figure 49. If more than eight transmit clocks are input in transmit clock wait state, serial interface 2's state changes to transfer state, transmit clock wait state, then back to transfer state. When serial interface 2 is set to SMR2 read wait state by writing data to SMR2 at transfer state after the serial interface 2 interrupt request flag (IFS2) has been reset, the flag is set again. 77 HD404439Series Transmit/receive (IFS2 1) Interrupts inhibited IFS2 0 SMR2 write Yes IFS2 = 1 ? Transmit clock error processing No Normal end Figure 49 Transmit Clock Error Detection 78 HD404439 Series A/D Converter The MCU has an 8-bit A/D converter that uses a sequential comparison method with a resistor ladder. It has eight input channels. The block diagram is shown in figure 50. Internal data bus A/D control register (ADCR) A/D status register (ADSR) A/D data register (ADR) 3 (Channel select) (Port select) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D mode register (AMR) 2 IFAD MPX + COMP - Control logic Counter AVCC AGND D/A Figure 50 Block Diagram of A/D Converter 79 HD404439Series A/D Control Register (ADCR: $01B): Selects the analog input pin or digital input port and selects one of eight analog input channels (figure 51). The eight input pins (RC 0/AN0-RC3/AN3, RD0/AN4- RD3/AN7) must not include analog input mode pins and port input mode pins at the same time; all the pins must be set to the same mode. When selecting analog input mode for these pins, select without pull-up MOS option for the pins. ADCR: $01B Bit 3 Bit 1 Bit 2 Bit 0 Initial value: 0000, R/W: W Analog input pin selection Digital/analog port selection Bit 2 Bit 1 Bit 0 Analog Input Pin Selection 0 0 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 1 1 0 1 Bit 3 Digital/Analog Selection 0 Digital input pins (RC0-RC3, RD0-RD3) 1 Analog input pins (AN0-AN7) Figure 51 A/D Control Register A/D Status Register (ADSR: $01F): A/D conversion is started by setting 1 to the A/D start flag. At conversion completion, the converted data is set to the A/D data register and the A/D start flag is reset (figure 52). ADSR: $01F Bit 3 Bit 2 Bit 1 Bit 0 Initial value: ---0, R/W: R/W A/D start flag (ADSF) Not used Bit 0 A/D Start Flag (ADSF) 0 A/D conversion completion 1 A/D conversion start Figure 52 A/D Status Register 80 HD404439 Series A/D Mode Register (AMR: $01C): Two-bit write-only register which selects the A/D conversion speed (figure 53). AMR: $01C Bit 3 Bit 1 Bit 2 Bit 0 Initial value: --00, R/W: W Conversion cycles Not used Bit 1 Bit 0 Conversion Cycles 0 0 34 tcyc 1 68 tcyc Figure 53 A/D Mode Register A/D Data Register (ADRL: $01D, ADRU: $01E): Eight-bit read-only register separated into lower and upper digits (figure 54). Eight-bit A/D converted data is set to the register at conversion completion, and is held until the next conversion starts. Data read during conversion is invalid. The register cannot be cleared by MCU reset. ADRU: $01E 3 2 1 ADRL: $01D 0 3 2 1 0 MSB LSB Bit 7 Bit 0 Figure 54 A/D Data Register 81 HD404439Series Comparator The block diagram of the comparator is shown in figure 55. The comparator compares input voltage with the reference voltage. Internal voltage or external input voltage can be selected as the reference. Internal reference voltage is selected from seven levels. When bits 0, 1, and 2 of the compare control register are 0, external reference voltage is input. The LAR instruction executes a voltage comparison. When the COMP input voltage is higher than the reference voltage, data 0 is read from port R60. The power supply for the comparator is the digital V CC and GND. When using the comparator, select without pull-up MOS option for pins R6 0 and R61. Vcc SW1 R61/Vref 3R + SW2 R MPX Comparator - R R60/COMP 2R SW3 3 CCR 4 Internal data bus SW1: SW2: SW3: Turned on when comparator operation is selected. Turned off when comparator operation is not selected. Selects external Vref when bits 0-2 of CCR are 000. Connected to comparator output when comparator operation selected. Figure 55 Block Diagram of the Comparator 82 HD404439 Series Compare Control Register (CCR: $03E): Four-bit write-only register which enables comparator operation and selects internal reference voltage sources (figure 56). CCR: $03E Bit 3 Bit 2 Bit 1 Bit 0 Initial value: 0000, R/W: W Reference voltage selection Comparator operation selection Bit 2 Bit 1 Bit 0 Reference Voltage Selection 0 0 0 External Vref 1 2/11 VCC 1 0 3/11 VCC 1 4/11 VCC 0 5/11 VCC 1 6/11 VCC 0 7/11 VCC 1 8/11 VCC 1 0 1 Bit 3 Comparator Operation Selection 1 Analog compare mode: comparator operation selected (comparator output is read by the read instruction) 0 Digital input mode: comparator operation not selected (R60 port is read by the read instruction) Figure 56 Compare Control Register 83 HD404439Series Programmable ROM (HD4074719) The HD4074719 is a ZTAT microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin Number MCU Mode PROM Mode Pin Number FP-80B FP-80A Pin Name I/O Pin Name I/O FP-80B 1 79 RD1/AN5 I 2 80 RD2/AN6 3 1 RD3/AN7 4 2 AGND 5 3 RESET I RESET 6 4 OSC1 I GND 7 5 OSC2 O 8 6 GND 9 7 CL1 I 10 8 CL2 O 11 9 TEST I 12 10 VCC 13 11 D0 14 12 15 MCU Mode PROM Mode FP-80A Pin Name I/O Pin Name I/O 28 29 R02 I/O A3 I I 29 30 R03 I/O A4 I I 30 31 R10 I/O A5 I 31 32 R11 I/O A6 I 32 33 R12 I/O A7 I 33 34 R13 I/O A8 I 34 35 R20 I/O A0 I GND 35 36 R21 I/O A10 I GND 36 37 R22 I/O A11 I 37 38 R23 I/O A12 I 38 39 R30 I/O A13 I 39 40 R31 I/O A14 I I/O 40 41 R32 I/O D1 I/O 41 42 R33 I/O 13 D2 I/O 42 43 R40 I/O 16 14 D3 I/O 43 44 R41 I/O 17 15 D4 I/O 44 45 R42 I/O 18 16 D5 I/O 45 46 R43 I/O 19 17 D6 I/O 46 47 R50 I 20 18 D7 I/O 47 48 R51 I VCC 21 19 D8 I/O 48 49 R52 I VPP 22 20 D9 I/O 49 50 R53 I A9 I 23 21 D10 I/O 50 51 R60/COMP I/O CE I 24 22 D11 I/O 51 52 R61/Vref I/O OE I 25 23 D12 I/O 52 53 R62/TOE1 I/O VCC 26 24 D13 I/O 53 54 R63/TOE2 I/O VCC 27 25 D14 I/O 54 55 R70/INT0 I/O O0 GND TEST VCC I I Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. O0-O4 each have 2 pins; connect each pair together for use. 84 I/O HD404439 Series Pin Number MCU Mode PROM Mode Pin Number FP-80B FP-80A Pin Name I/O Pin Name I/O FP-80B 55 26 D15 I/O 56 27 R00 I/O A1 57 28 R01 I/O 58 59 R80/INT4 59 60 60 MCU Mode PROM Mode FP-80A Pin Name I/O Pin Name I/O 68 56 R71/INT1 I/O O1 I/O I 69 57 R72/INT2 I/O O2 I/O A2 I 70 58 R73/INT3 I/O O3 I/O I/O O4 I/O 71 69 RA2/TOG I/O O7 I/O R81/INT5 I/O O4 I/O 72 70 RA3/BUZZ I/O 61 R82/SO1 I/O O3 I/O 73 71 RB0/TOC I/O M0 I 61 62 R83/SI1 I/O O2 I/O 74 72 RB1/TOD I/O M1 I 62 63 R90/SCK 1 I/O O1 I/O 75 73 AVCC 63 64 R91/SCK 2 I/O O0 I/O 76 74 RC0/AN0 I 64 65 R92/SI2 I/O 77 75 RC1/AN1 I 65 66 R93/SO2 I/O 78 76 RC2/AN2 I 66 67 RA0/ICT0 I/O O5 I/O 79 77 RC3/AN3 I 67 68 RA1/ICT1 I/O O6 I/O 80 78 RD0/AN4 I VCC Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. O0-O4 each have 2 pins; connect each pair together for use. 85 HD404439Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode which is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 57. In PROM mode, the MCU stops, and the PROM is programmed in the same way as a 27256 EPROM using a standard PROM programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 34. Since an HMCS400-series instruction is ten bits long, the MCU has a built-in conversion circuit for a general-purpose PROM programmer. This circuit splits each instruction into lower 5 bits and upper 5 bits that are read from or written to two consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Programming and Verification: The built-in PROM of the MCU can be programmed at high- speed programming sequence without voltage stress or damage to data reliability. Programming and verification modes are selected as shown in table 33. For details of PROM programming, refer to the preface on PROM Programming section. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are inserted correctly (in the correct direction), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltage settings (VPP): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21 V setting will damage them. 12.5 V is the Intel's 27256 setting. Table 33 PROM Mode Selection Pin Mode CE OE VPP O0-O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 86 HD404439 Series Table 34 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Manufacturer Model Name DATA I/O Corp. 29B Unisite FP-80A Hitachi HS471ESH01H FP-80B Hitachi HS471ESF01H PKW-1000 FP-80A Hitachi HS471ESH01H PKW-3100 FP-80B Hitachi HS471ESF01H AVAL Data Corp. VCC VCC VCC RESET TEST M0 M1 VPP VPP O0 to O7 Data O0-O7 A0 to A14 Address A0-A14 OE OE CE CE GND Figure 57 Connections for PROM Mode 87 HD404439Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 58 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), located in 16 digits from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 58 RAM Addressing Modes 88 m3 m2 HD404439 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 59, and the P instruction shown in figure 60. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transmits the PC contents to the next physical page, as shown in figure 61. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced by the P instruction as shown in figure 60. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 89 HD404439Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 59 ROM Addressing Modes 90 B2 B1 Accumulator HD404439 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Specification ROM data RO9 1 Accumulator, B register ROM data 1 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 60 P Instruction 91 HD404439Series BR AAA NOP BR BR BBB 256(n - 1) + 255 AAA 256n AAA 256n + 254 BBB 256n + 255 256(n + 1) NOP Figure 61 Branching when Branch Destination is on a Page Boundary 92 HD404439 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V Pin voltage VT -0.3 to VCC + 0.3 V 1 VCC - 45 to VCC + 0.3 V 2 Total permissible input current Io 50 mA 3 Total permissible output current -Io 150 mA 4 Maximum input current Io 15 mA 5, 6 Maximum output current -Io 4 mA 7, 8 30 mA 7, 9 Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. All voltages are with respect to GND. 1. Standard pins. 2. High-voltage pins. 3. The total permissible input current is the total of input currents simultaneously flowing in from all I/O pins to GND. 4. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 5. The maximum input current is the maximum current flowing from any I/O pin to GND. 6. Applies to R5-RD. 7. The maximum output current is the maximum current flowing from VCC to any I/O pin. 8. Applies to R6-RB. 9. Applies to D0-D15 and R0-R4. 93 HD404439Series HD404719 Electrical Characteristics DC Characteristics HD404439: V CC = 3.0 to 6.0 V, GND = 0.0 V, T a = -20 to +75C; HD404719: V CC = 3.0 to 6.0 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC, T a = -20 to +75C; HD4074719: V CC = 3.0 to 5.5 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC , Ta = -20 to +75C, unless otherwise specified. Item Symbol Pin(s) Input high voltage VIH Min RESET, SCK 1, 0.85VCC Typ Max Unit -- VCC + 0.3 V Test Condition SCK 2, INT0-INT5 SI1, SI2 0.7VCC -- VCC + 0.3 V OSC1 VCC - 0.5 -- VCC + 0.3 V HD404439, HD404719: VCC = 3.5 to 6.0 V, HD4074719: VCC = 3.5 to 5.5 V VCC - 0.3 Input low voltage VIL RESET, SCK 1, -0.3 -- VCC + 0.3 V -- 0.2VCC V SCK 2, INT0-INT5 SI1, SI2 -0.3 -- 0.3VCC V OSC1 -0.3 -- 0.5 V HD404439, HD404719: VCC = 3.5 to 6.0 V HD4074719: VCC = 3.5 to 5.5 V Output high VOH voltage SCK 1, SCK 2, -0.3 -- 0.3 V VCC - 1.0 -- -- V -IOH = 1.0 mA; SO1, SO2, HD404439, HD404719: BUZZ, TOC, VCC = 3.5 to 6.0 V; TOD, TOE1, HD4074719: TOE2, TOG VCC = 3.5 to 5.5 V VCC - 0.5 -- -- V -IOH = 0.5 mA; HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V -IOH = 0.3 mA 94 Notes HD404439 Series Item Symbol Pin(s) Output low VOL voltage SCK 1, SCK 2, Min Typ Max Unit Test Condition -- -- V IOL = 1.6 mA; 0.4 SO1, SO2, HD404439, HD404719: BUZZ, TOC, VCC = 3.5 to 6.0 V; TOD, TOE1, HD4074719: TOE2, TOG VCC = 3.5 to 5.5 V Notes IOL = 0.4 mA I/O leakage |IIL| current RESET, SCK 1, -- SCK 2,SI1, SI2, -- 1 A Vin = 0 V to VCC 1 -- 8.0 mA VCC = 5 V, 2, 5 SO1, SO2, BUZZ, OSC1, TOC, TOD, TOE1, TOE2, TOG ICC Current dissipation in active mode VCC -- fOSC = 4 MHz, digital input mode -- -- 4.5 mA VCC = 3 V, 2, 5 fOSC = 2 MHz, digital input mode ICMP -- -- 12.0 mA VCC = 5 V, 3, 5 fOSC = 4 MHz, analog compare mode -- -- 7.0 mA VCC = 3 V, 3, 5 fOSC = 2 MHz, analog compare mode ISBY Current dissipation in standby mode VCC -- -- 3.0 mA VCC = 5 V, 4, 5 fOSC = 4 MHz -- -- 1.5 mA VCC = 3 V, 4, 5 fOSC = 2 MHz ISUB Current dissipation in subactive mode VCC -- -- 70 A HD404439, HD404719: 6, 7 Vin (TEST) = VCC - 0.3 V to VCC Vin (RESET) = 0 to 0.3 V, VCC = 3 V, 32.768-kHz crystal oscillator 95 HD404439Series Item Symbol Pin(s) ISUB Current dissipation in subactive mode VCC Min Typ Max Unit Test Condition Notes -- -- A 6 150 HD4074719: Vin (TEST) = VCC - 0.3 V to VCC, Vin (RESET) = 0 to 0.3 V, VCC = 3 V, 32.768-kHz crystal oscillator IWTC Current dissipation in watch mode VCC -- -- 15 A HD404439, HD404719: 6, 7, 8 Vin (TEST) = VCC - 0.3 V to VCC, Vin (RESET) = 0 to 0.3 V, VCC = 3 V, 32.768-kHz crystal oscillator -- -- 15 A HD4074719: 6 Vin (TEST) = VCC - 0.3 V to VCC, Vin (RESET) = 0 to 0.3 V, VCC = 3 V, 32.768-kHz crystal oscillator Istop Current dissipation in stop mode VCC -- -- 10 A HD404439, HD404719: 6 Vin (TEST) = VCC - 0.3 V to VCC, Vin (RESET) = 0 to 0.3 V, no 32.768-kHz oscillator -- -- 15 A HD4074719: 6 Vin (TEST) = VCC - 0.3 V to VCC, Vin (RESET) = 0 to 0.3 V, no 32.768-kHz oscillator Watch mode retaining voltage VWTC VCC 3.5 -- 6.0 V HD404439, HD404719: VCC = 3.5 to 6.0 V 3.0 -- 6.0 V HD404439, HD404719 3.5 -- 5.5 V HD4074719: VCC = 3.5 to 5.5 V 3.0 -- 5.5 V HD4074719: 2 Stop mode Vstop retaining voltage VCC -- -- V No 32.768-kHz oscillator Input high voltage VIHA R60/COMP VCref + 0.1 -- -- V Analog compare mode Input low voltage VILA R60/COMP -- VCref - 0.1 V Analog compare mode 96 -- 6, 7, 8 HD404439 Series Item Symbol Pin(s) VCref Range of comparator input reference voltage Allowable error of VOFS internal reference voltage R61/Vref Min Typ Max Unit 0 -- VCC - 1.2 V -100 -- +100 mV Test Condition Notes VOFS = reference voltage - VCref 9 Notes: 1. Excluding output buffer current. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at VCC R51-RD at VCC D0-D15 , R0-R4, R50 at GND for HD404439, and at Vdisp for HD404719, HD4074719 3. ICMP is the source current when no I/O current is flowing while the R6 0/COMP pin is in analog input mode. Test conditions:Pins: R60/COMP, R61/Vref at GND 4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions:MCU: I/O same as at reset Standby mode Pins: RESET at GND TEST at VCC R51-RD at VCC D0-D15 , R0-R4, R50 at GND for HD404439, and at Vdisp for HD404719, HD4074719 5. Power dissipation, while the MCU is operating or in standby mode, is in proportion to fOSC. The value of the dissipation current when fOSC = MHz is given by the following equation: Maximum value (fOSC = MHz) = /4 x maximum value (fOSC = 4 MHz) 6. Source current when no I/O current is flowing. Test conditions:Pins: R51-RD at VCC D0-D15 , R0-R4, R50 at GND 7. Applies when `32-kHz CPU operation' is selected as an optional function. 8. Applies when `no 32-kHz CPU operation with clock time base' is selected as an optional function. 9. The reference voltage is the expected internal V ref voltage selected by the compare control register (CCR). Example: when CCR = $9, reference voltage is 2/11 x VCC. 97 HD404439Series A/D Converter HD404439, HD404719: V CC = 3.0 to 6.0 V, AGND = GND, Ta = -20 to +75C, HD4074719: V CC = 3.0 to 5.5 V, AGND = GND, Ta = -20 to +75C, unless otherwise specified. Item Symbol Pin(s) Min Analog supply voltage AVCC AVCC Analog input voltage AVin AN0-AN7 AGND Typ VCC - 0.3 VCC -- Max Unit Test Condition Note HD404439, HD404719 1 VCC + 0.3 V AVCC V HD4074719 Current between AVCC and AGND IAD AVCC -- -- 150 A AVCC = 5V, Vin (RESET) = 0 to 0.3 V, Vin (TEST) = VCC - 0.3 V to VCC -- -- 10 A HD404439, HD404719: Vin (RESET) = 0 to 0.3 V, Vin (TEST) = VCC - 0.3 V to VCC, stop mode, no 32.768kHz crystal oscillator -- -- 15 A HD4074719: Vin (RESET) = 0 to 0.3 V, Vin (TEST) = VCC - 0.3 V to VCC, stop mode, no 32.768kHz crystal oscillator Analog input capacitance AN0-AN7 -- -- 30 pF Resolution -- -- 8 Bit Number of input channels 0 -- 8 Channel Absolute error -- -- 2.5 LSB Note: 98 CAin Ta = 25C, AVCC = 5 V 1. Select without pull-up MOS option for pins RC and RD when using these pins as analog input pins. HD404439 Series Input/Output Characteristics for Standard Pins HD404439: V CC = 3.0 to 6.0 V, GND = 0.0 V, T a = -20 to +75C; HD404719: V CC = 3.0 to 6.0 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC, T a = -20 to +75C; HD4074719: V CC = 3.0 to 5.5 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC , Ta = -20 to +75C, unless otherwise specified. Item Symbol Pin(s) Min Typ Max Unit Input high voltage VIH R51-RD 0.7VCC -- VCC + 0.3 V Input low voltage VIL R51-RD -0.3 -- 0.3VCC V R6-RB VCC - 1.0 -- -- V Output high VOH voltage Test Condition Note -IOH = 1.0 mA; HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V VCC - 0.5 -- -- V -IOH = 0.5 mA; HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V -IOH = 0.3 mA Output low VOL voltage R6-RB -- -- 0.4 V IOL = 1.6 mA; HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V IOL = 0.4 mA Input/output |IIL| leakage current R51 to RD -- -- 1 A HD404439: 1 Vin = 0 V to VCC R6-RD, -- -- 1 A -- -- 20 A R51-R53 R52 HD404719, HD4074719: Vin = 0 V to VCC HD4074719: Vin = 0 V to VCC Pull-up MOS current IPU R51-RD 30 80 160 A HD404439, HD404719: 2 VCC = 5 V, Vin = 0 V 10 30 60 HD404439, HD404719: VCC = 3 V, Vin = 0 V Notes: 1. Excluding output buffer current. 2. Applies to I/O pins selected as with pull-up MOS by mask option. 99 HD404439Series Input/Output Characteristics for Open-Drain PMOS Pins (HD404439) VCC = 3.0 to 6.0 V, GND = 0.0 V, T a = -20 to + 75C, unless otherwise specified. Item Symbol Pins Min Typ Max Unit Test Condition Input high voltage VIH D0-D15 , 0.7VCC -- VCC + 0.3 V 0.3 -- 0.3VCC V VCC - 3.0 -- -- V Note R0-R4, R50 Input low voltage VIL D0-D15 , R0-R4, R50 Output high voltage VOH D0-D15 , -IOH = 15 mA, VCC = 4 to 6 V R0-R4 VCC - 2.0 -- -- V -IOH = 10 mA, VCC = 4 to 6 V Input/output leakage current Notes: 100 |IIL| D0-D15 , R0-R4, R50 1. Excluding output buffer current. VCC - 1.0 -- -- V -IOH = 4 mA -- -- 4 A Vin = 0 V to VCC 1 HD404439 Series Input/Output Characteristics for High-Voltage Pins (HD404719, HD4074719) HD404719: V CC = 3.0 to 6.0 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC, T a = -20 to + 75C, HD4074719: V CC = 3.0 to 5.5 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC , Ta = -20 to +75C, unless otherwise specified. Item Symbo Pins l Min Typ Max Input high voltage VIH 0.7VCC -- VCC + 0.3 V Input low voltage VIL VCC - 40 -- 0.3VCC V Output high voltage VOH VCC - 3.0 -- -- V D0-D15 , Unit Test Condition Note R0-R4, R50 D0-D15 R0-R4, R50 D0-D15 , R0-R4 -IOH = 15 mA; HD404719: VCC = 4 to 6 V; HD4074719: VCC = 4 to 5.5 V VCC - 2.0 -- -- V -IOH = 10 mA; HD404719: VCC = 4 to 6 V; HD4074719: VCC = 4 to 5.5 V Output low voltage VOL D0-D15 , VCC - 1.0 -- -- V -IOH = 4 mA -- -- VCC - 37 V HD404719: 1 Vdisp = VCC - 40 V R0-R4 -- -- VCC - 37 V HD404719: 2 150 k at VCC - 40 V -- -- VCC - 37 V HD4074719: 150 k at VCC - 40 V Input/output leakage current |IIL| Pull-down IPD MOS current Notes: D0-D15 , -- -- 20 A Vin = VCC - 40 V to VCC 3 200 400 800 A Vdisp = VCC - 35 V, 1 R0-R4, R50 D0-D15 , R0-R4 Vin = VCC 1. Applied to I/O pins selected as with pull-up MOS by mask option. 2. Applied to I/O pins selected as without pull-up MOS (PMOS open drain) by mask option. 3. HD404719: Pull-down MOS current and output buffer current are excluded. HD4074719: Output buffer current is excluded. 101 HD404439Series AC Characteristics HD404439:V CC = 3.0 to 6.0 V, GND = 0.0 V, T a = -20 to +75C; HD404719: V CC = 3.0 to 6.0 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC, T a = -20 to +75C; HD4074719: V CC = 3.0 to 5.5 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC , Ta = -20 to +75C, unless otherwise specified. Item Symbol Pin(s) Clock oscillation fOSC frequency (1/4 division) OSC1, OSC2 Min Typ Max Unit Test Condition 1.6 4 4.5 MHz HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V 1.6 Clock oscillation fCL frequency (1/8 division) Note CL1, CL2 -- Instruction cycle tcyc time 0.89 2 2.25 MHz 32.768 -- kHz 1 s 2.5 HD404439, HD404719: VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V Instruction cycle tsubcyc time tRC Oscillation stabilization time (crystal oscillator) tRC Oscillation stabilization time (ceramic oscillator) OSC1, OSC2 2.5 s 1.78 2 -- 244.14 -- s -- -- ms 40 6 HD404439, HD404719: 1 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V OSC1, OSC2 -- -- 60 ms -- -- 20 ms 1 HD404439, HD404719: 1 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V -- -- 60 ms 1 Oscillation tRC stabilization time CL1, CL2 -- -- 2 s 2 External clock high width OSC1 -- -- ns tCPH 92 HD404439, HD404719: 3 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V External clock low width tCPL OSC1 203 -- -- ns 92 -- -- ns 3 HD404439, HD404719: 3 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V 203 102 -- -- ns 3 HD404439 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Note External clock rise time tcpr OSC1 -- -- 20 ns HD404439, HD404719: 3 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V External clock fall time tcpf OSC1 -- -- 20 ns -- -- 20 ns 3 HD404439, HD404719: 3 VCC = 3.5 to 6.0 V; HD4074719: VCC = 3.5 to 5.5 V -- -- 20 ns 3 INT0 high width tIH INT0 2 -- -- tcyc / tsubcyc 4, 6 INT0 low width INT0 2 -- -- tcyc / tsubcyc 4, 6 INT high width tIH INT1-INT5 2 -- -- tcyc 4 INT low width tIL INT1-INT5 2 -- -- tcyc 4 RESET high width tRSTH RESET 2 -- -- tcyc 5 Input capacitance Cin All pins -- except R52 -- 30 pF f = 1 MHz, V in = 0 V R52 -- 30 pF HD404439, HD404719: tIL -- f = 1 MHz, V in = 0 V -- -- 180 pF HD4074719: f = 1 MHz, V in = 0 V Analog comparator stabilization time tCSTB R60/COMP -- -- 2 tcyc 7 Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 3.0 V (3.5 V if VCC = 3.5 to 6.0 V (HD404439, HD404719), or VCC = 3.5 to 5.5 V (HD4074719)) at power-on or after RESET input goes high after stop mode is cancelled (figure 62). At power-on and when stop mode is cancelled, RESET must remain high for at least tRC to ensure the oscillation stabilization time. If using an oscillator, contact the oscillator manufacturer to determine the circuit constants, since the stabilization time depends on the circuit constants and stray capacitances. 2. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 3.0 V at power-on (figure 63). If using a crystal oscillator, contact the manufacturer to determine the circuit constants, since the stabilization time depends on the circuit constants and stray capacitances. 3. Refer to figure 64. 4. Refer to figure 65. 5. Refer to figure 66. The MCU will malfunction if noise interferes with the falling edge of the RESET signal when releasing from reset state. The reset circuit must be sufficiently evaluated in the application system. 103 HD404439Series 6. The tsubcyc unit applies when the MCU is in watch or subactive mode. tsubcyc = 244.14 s (32.768-kHz crystal) 7. The analog comparator stabilization time is the period required for the analog comparator to stabilize and to read correct data after pin R60 switches to analog input mode. Serial Interface Timing Characteristics HD404439: V CC = 3.0 to 6.0 V, GND = 0.0 V, T a = -20 to +75C; HD404719: V CC = 3.0 to 6.0 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC, T a = -20 to +75C; HD4074719: V CC = 3.0 to 5.5 V, GND = 0.0 V, Vdisp = VCC - 40 V to VCC , Ta = -20 to +75C, unless otherwise specified. Item Symbol Pins Output transmit clock cycle time tScyc Output transmit clock high width Typ Max Unit Test Condition Note SCK 1, SCK 2 1 -- -- tcyc tSCKH SCK 1, SCK 2 0.4 -- -- tScyc 1 Output transmit clock low width tSCKL SCK 1, SCK 2 0.4 -- -- tScyc 1 Output transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 80 ns 1 Output transmit clock fall time tSCKf SCK 1, SCK 2 -- -- 80 ns 1 Input transmit clock cycle time tScyc SCK 1, SCK 2 2 -- -- tcyc 1 Input transmit clock high width tSCKH SCK 1, SCK 2 0.4 -- -- tScyc 1 Input transmit clock low width tSCKL SCK 1, SCK 2 0.4 -- -- tScyc 1 Input transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 80 ns 1 Input transmit clock fall time tSCKf SCK 1, SCK 2 -- -- 80 ns 1 Serial output data delay time tDSO SO1, SO2 -- -- 600 ns Serial input data setup time tSSI SI1, SI2 200 -- -- ns 1 Serial input data hold time tHSI SI1, SI2 400 -- -- ns 1 Note: 104 1. Refer to figure 67. Min Load shown in figure 68 Load shown in figure 68 1 1 HD404439 Series Serial Interface Timing Characteristics HD404439, HD404719: V CC = 3.5 to 6.0 V HD4074719: VCC = 3.5 to 5.5 V Item Symbol Pins Output transmit clock cycle time tScyc Output transmit clock high width Typ Max Unit Test Condition Note SCK 1, SCK 2 1 -- -- tcyc 1 tSCKH SCK 1, SCK 2 0.4 -- -- tScyc 1 Output transmit clock low width tSCKL SCK 1, SCK 2 0.4 -- -- tScyc 1 Output transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 40 ns 1 Output transmit clock fall time tSCKf SCK 1, SCK 2 -- -- 40 ns 1 Input transmit clock cycle time tScyc SCK 1, SCK 2 2 -- -- tcyc 1 Input transmit clock high width tSCKH SCK 1, SCK 2 0.4 -- -- tScyc 1 Input transmit clock low width tSCKL SCK 1, SCK 2 0.4 -- -- tScyc 1 Input transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 40 ns 1 Input transmit clock fall time tSCKf SCK 1, SCK 2 -- -- 40 ns 1 Serial output data delay time tDSO SO1, SO2 -- -- 300 ns Serial input data setup time tSSI SI1, SI2 100 -- -- ns 1 Serial input data hold time tHSI SI1, SI2 200 -- -- ns 1 Note: Min Load shown in figure 68 Load shown in figure 68 1 1. Refer to figure 67. 105 HD404439Series Crystal oscillator Ceramic oscillator C1 C1 OSC1 Crystal Ceramic Rf OSC2 GND C2 Crystal: Equivalent to the circuit below Rf: 1 M 20% C1: 22 pF 20% C2: 22 pF 20% L OSC1 Cs GND Rf OSC2 C2 Ceramic filter: CSA4.00MG (Murata) Rf: 1 M 20% C1: 33 pF 20% C2: 33 pF 20% Rs Co Co = 7 pF, max. Rs = 100 , max. f = 1.6 to 4.5 MHz Figure 62 Oscillation Circuits (1) C1 CL1 L Crystal GND Rs Co CL2 C2 Crystal: MX38T (Nihon Dempa Kogyo) Equivalent to the circuit on the right Co = 1.5 pF, max. Rs = 14 k, max. f = 32.768 kHz C1: 15 pF 5% C2: 15 pF 5% Figure 63 Oscillation Circuits (2) 106 Cs HD404439 Series VCC = 3.5 to 6.0 V (HD404719/HD404439) VCC = 3.5 to 5.5 V (HD4074719) 1/fCP VCC - 0.5 V OSC1 tCPH tCPL 0.5 V tCPr tCPf VCC = 3.0 to 3.5 V 1/fCP VCC - 0.3 V OSC1 tCPH tCPL 0.3 V tCPr tCPf Figure 64 Oscillator Waveforms 0.85VCC INT0-INT5 tIH tIL 0.2VCC Note: tcyc is used while the MCU is in standby mode or active mode. Figure 65 Interrupt Timing RESET 0.85VCC 0.2VCC tRSTH Figure 66 Reset Timing 107 HD404439Series tScyc tSCKf tSCKr tSCKL SCK1, VCC - 2.0 V (0.85VCC)* 0.8 V (0.2VCC)* SCK2 tSCKH tDSO VCC - 2.0 V 0.8 V SO1, SO2 tSSI 0.7VCC 0.3VCC SI1, SI2 * VCC - 2.0 V and 0.8 V are applied when transmit clock is output. 0.85VCC and 0.2VCC are applied when transmit clock is input. tDSO, tSSI, and tHSI are determined by the voltage at transmit clock input. Figure 67 Serial Interface Timing VCC RL = 2.6 k Test point C 30 pF R 1S2074 H or equivalent 12 k Figure 68 Load Circuit for Timing Measurement 108 tHSI HD404439 Series HD404439 Option List Please check off the appropriate applications and enter the necessary information. Order date 1. Optional Functions Department Customer name * 32-kHz CPU operation Name * No 32-kHz CPU operation with clock time-base ROM code No 32-kHz CPU operation no clock time-base LSI type HD404439 Note: *Options marked with an asterisk require a subsystem crystal oscillator (CL1, CL2). 2. I/O Options (shaded options are not available) B: With pull-up MOS C: Without pull-up MOS Pin name I/O I/O option B C D E Pin name D: Without pull-down MOS I/O I/O option B C D E Pin name E: With pull-down MOS I/O I/O option B C D E Standard pins Standard pins Open-drain PMOS pins Open-drain PMOS pins D0 I/O R8 R80 I/O R2 R20 I/O D1 I/O R81 I/O R21 I/O D2 I/O R82 I/O R22 I/O D3 I/O R83 I/O R23 I/O D4 I/O R9 R90 I/O I/O R3 R30 D5 I/O R91 I/O R31 I/O D6 I/O R92 I/O R32 I/O D7 I/O R93 I/O R33 I/O I/O D8 I/O R4 R40 RA RA0 I/O R41 D9 I/O RA1 I/O I/O R42 D10 I/O RA2 I/O I/O I/O R43 D11 I/O RA3 I/O D12 I/O RB RB0 I I/O R5 R50 R51 D13 I/O RB1 I I/O RC RC0 R52 D14 I/O I I *2 R53 D15 I/O RC1 I I R0 R00 RC2 R6 R60 I/O I I/O *1 R61 R01 I/O I I/O RC3 R62 R02 RD RD0 I/O I I/O *2 R63 R03 I/O I I/O RD1 R1 R10 RD2 R7 R70 I/O I I/O R71 R11 I/O I I/O RD3 R12 R72 I/O I/O R73 R13 I/O I/O Note: 1. When a comparator is used, select pins R60/COMP and R61/Vref without pull-up MOS (I/O option C). 2. When pins RC and RD are used for analog input, select them without pull-up MOS (I/O option C). 3. ROM Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. Stop Mode 4. OSC1 and OSC2 Oscillator 6. Package Ceramic oscillator f= MHz Used FP-80A Crystal oscillator f= MHz Not used FP-80B External clock f= MHz 109 HD404449 Series Rev. 5.0 March 1997 Description The HD404449 Series is a HMCS400-series microcomputer designed to increase program productivity with large-capacity memory. Each microcomputer has four timers, two serial interfaces, A/D converter, input capture circuit, 32-kHz oscillator for clock, and four low-power dissipation modes. The HD404449 Series includes three chips: the HD404448 with 8-kword ROM; the HD404449 with 16kword ROM; and HD4074449 with 16-kword PROM (ZTAT version). The HD4074449 is a PROM version (ZTAT microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTAT version is 27256-compatible.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features * 8,192-word x 10-bit ROM (HD404448) 16,384-word x 10-bit ROM (HD404449 and HD4074449) * 1,152-digit x 4-bit RAM * 64 I/O pins, including 10 high-current pins (15 mA, max) * Four timer/counters * Eight-bit input capture circuit * Three timer outputs (including two PWM outputs) * Two event counter inputs (including one double-edge function) * Two clock-synchronous 8-bit serial interfaces * A/D converter (4-channel x 8-bit) * Built-in oscillators Main clock: 4-MHz ceramic oscillator or crystal (an external clock is also possible) Subclock: 32.768-kHz crystal * Eleven interrupt sources Four by external sources, including two double-edge function Seven by internal sources HD404449 Series * Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time: 1 s (fOSC = 4 MHz) * Two operating modes MCU mode (HD404448, HD404449) MCU/PROM mode (HD4074449) Ordering Information Type Product Name Model Name ROM (Words) Package Mask ROM HD404448 HD404448H 8,192 80-pin plastic QFP (FP-80A) HD404448TF HD404449 HD404449H 80-pin plastic QFP (TFP-80F) 16,384 HD404449TF ZTAT HD4074449 HD4074449H HD4074449TF 2 80-pin plastic QFP (FP-80A) 80-pin plastic QFP (TFP-80F) 16,384 80-pin plastic QFP (FP-80A) 80-pin plastic QFP (TFP-80F) HD404449 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AN1 AN0 AVCC VCC RC3 RC2 RC1 RC0 RB3 RB2 RB1 RB0 RA3 RA2 RA1 RA0 R93 R92 R91 R90 Pin Arrangement FP-80A TFP-80F 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 R83 R82 R81 R80 R73 R72 R71 R70 R63 R62 R61 R60 R53/SO2 R52/SI2 R51/SCK2 R50 R43/SO1 R42/SI1 R41/SCK1 R40/EVND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D10 D11 D12/STOPC D13/INT0 R00/INT1 R01/INT2 R02/INT3 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30/TOB R31/TOC R32/TOD R33/EVNB AN2 AN3 AVSS TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 (Top view) 3 HD404449 Series Pin Description Item Symbol Pin Number I/O Function Power supply VCC 77 Applies power voltage GND 10 Connected to ground Test TEST 4 I Used for factory testing only: Connect this pin to VCC Reset RESET 7 I Resets the MCU Oscillator OSC1 5 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator, crystal, or connect OSC1 to an external oscillator circuit OSC2 6 O X1 8 I X2 9 O D0-D11 11-22 I/O Input/output pins addressed by individual bits; pins D0-D9 are high-current pins that can each supply up to 15 mA D12, D13 23, 24 I R00-RC3 25-76 I/O Input/output pins addressable in 4-bit units INT0, INT1, 24-27 I Input pins for external interrupts Input pin for transition from stop mode to active mode Port Interrupt Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to VCC and leave the X2 pin open. Input pins addressable by individual bits INT2, INT3 Stop clear STOPC 23 I Serial SCK 1, SCK 2 42, 46 I/O Serial clock input/output pin interface SI1, SI2 43, 47 I Serial receive data input pin SO1, SO2 44, 48 O Serial transmit data output pin TOB, TOC, TOD 37-39 O Timer output pins EVNB, EVND 40, 41 I Event count input pins AVCC 78 Power pin for A/D converter: Connect it to the same potential as VCC, as physically close to the VCC pin as possible AVSS 3 Ground for AVCC: Connect it to the same potential as GND, as physically close to the GND pin as possible AN0-AN3 79, 80, 1, 2 Timer A/D converter 4 I Analog input pins for A/D converter HD404449 Series RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND Block Diagram System control External interrupt W (2 bits) Timer A TOC Timer C EVND TOD Timer D SI 1 SO 1 SCK 1 Serial interface 1 SI2 SO2 SCK2 Serial interface 2 AVCC AVSS AN0 AN1 AN2 AN3 A/D converter X (4 bits) SPX (4 bits) Y (4 bits) Internal address bus Timer B Internal data bus EVNB TOB D port RAM (1,152 x 4 bits) SPY (4 bits) ALU CPU ST CA (1 bit) (1 bit) A (4 bits) B (4 bits) SP (10 bits) Instruction decoder PC (14 bits) ROM (16,384 x 10 bits) (8,192 x 10 bits) RC port RB port RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port INT 0 INT 1 INT 2 INT 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 D 12 D 13 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RA0 RA1 RA2 RA3 RB 0 RB 1 RB 2 RB 3 RC 0 RC 1 RC 2 RC 3 High current pins : Data bus : Signal line 5 HD404449 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. 0 $0000 Vector address $000F 15 $0010 16 Zero-page subroutine (64 words) 63 $003F 64 $0040 Pattern (4,096 words) 0 JMPL instruction 1 (Jump to RESET, STOPC routine) JMPL instruction 2 (Jump to INT0 routine) 3 JMPL instruction 4 (Jump to INT1 routine) 5 6 7 8 9 $1000 10 11 12 8,191 $1FFF 13 14 15 8,192 $2000 $0FFF 4,095 4,096 HD404448 Program (8,192 words) JMPL instruction (Jump to timer A routine) $0000 $0001 $0002 $0003 $0004 $0005 JMPL instruction (Jump to timer D, A/D routine) $0006 $0007 $0008 $0009 $000A $000B $000C $000D JMPL instruction (Jump to serial 1, serial 2 routine) $000E $000F JMPL instruction (Jump to timer B, INT2 routine) JMPL instruction (Jump to timer C, INT3 routine) HD404449, HD4074449 Program (16,384 words) 16,383 $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF (HD404448), $0000-$3FFF (HD404449, HD4074449)): Used for program coding. RAM Memory Map The MCU contains a 1,152-digit x 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows. 6 HD404449 Series 0 $000 RAM-mapped registers 64 Memory registers (MR) 80 $040 $050 Not used $090 144 Data (464 digits x 2) V = 0 (bank 0) V = 1 (bank 1) Note $260 608 Data (144 digits) 752 960 $2F0 Not used $3C0 Stack (64 digits) $3FF 1023 $090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) $25F Note: The data area has two banks: bank 0 (V = 0) to bank 1 (V = 1) R: Read only W: Write only R/W: Read/Write * Two registers are mapped on the same area. 10 11 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 Interrupt control bits area Port mode register A (PMRA) Serial mode register 1A (SM1A) Serial data register 1 lower (SR1L) Serial data register 1 upper (SR1U) Timer mode register A (TMA) Timer mode register B1 (TMB1) (TRBL/TWBL) Timer B (TRBU/TWBU) (MIS) Miscellaneous register Timer mode register C1 (TMC1) (TRCL/TWCL) Timer C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer D (TRDU/TWDU) Timer mode register B2 (TMB2) Timer mode register C2 (TMC2) Timer mode register D2 (TMD2) A/D data register (AMR) A/D data register lower (ADL) A/D data register upper (ADU) W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R R Not used Serial mode register 2A Serial mode register 2B Serial data register 2 lower Serial data register 2 upper Not used (SM2A) W (SM2B) W (SR2L) R/W (SR2U) R/W Register flag area Port mode register B Port mode register C (PMRB) (PMRC) Detection edge select register 1 (ESR1) Detection edge select register 2 (ESR2) Serial mode register 1B (SMRB) System clock select register (SSR) W W W W W W Not used Port D0 -D 3 DCR Port D4 -D 7 DCR Port D8 and D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR Port RA DCR Port RB DCR Port RC DCR Not used V register $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) (DCRB) (DCRC) W W W W W W W W W W W W W $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C R/W $03F * Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B 14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E 15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012 Figure 2 RAM Memory Map 7 HD404449 Series RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface 1, serial interface 2, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090-$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $2EF is accessed without setting the bank register. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 8 HD404449 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $002 3 IMS1 (IM of serial interface 1) IFS1 (IF of serial interface 1) IMTD (IM of timer D) IFTD (IF of timer D) $003 Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 32 DTON (Direct transfer on flag) ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $020 33 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $021 34 IM3 (IM of INT3) IF3 (IF of INT3) IM2 (IM of INT2) IF2 (IF of INT2) $022 35 IMS2 (IM of serial interface 2) IFS2 (IF of serial interface 2) IMAD (IM of A/D) IFAD (IF of A/D) $023 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 9 HD404449 Series IE IM LSON IF ICSF ICEF RAME RSP WDON ADSF DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 10 HD404449 Series Bit 3 Bit 2 PMRA $004 R52/SI2 R53/SO2 SM1A $005 R41/SCK1 $000 $003 Bit 0 Bit 1 Interrupt control bits area R42/SI1 R43/SO1 Serial transmit clock speed selection 1 SR1L $006 Serial data register 1 (lower digit) SR1U $007 Serial data register 1 (upper digit) TMA $008 *1 TMB1 $009 *2 Timer B register (upper digit) TRBU/TWBU $00B TMC1 $00D Clock source selection (timer B) Timer B register (lower digit) TRBL/TWBL $00A MIS $00C Clock source selection (timer A) *3 *2 R43/SO1 PMOS control Interrupt frame period selection Clock source selection (timer C) TRCL/TWCL $00E Timer C register (lower digit) TRCU/TWCU $00F Timer C register (upper digit) TMD1 $010 Timer D register (lower digit) Timer D register (upper digit) TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 AMR $016 Clock source selection (timer D) *2 TRDL/TWDL $011 Not used Not used Not used Timer-B output mode selection Timer-C output mode selection Timer-D output mode selection *4 Analog channel selection Not used ADRL $017 A/D data register (lower digit) ADRU $018 A/D data register (upper digit) *5 Not used SM2A $01B R51/SCK2 SM2B $01C Not used Serial transmit clock speed selection 2 *6 R53/SO2 PMOS control *7 SR2L $01D Serial data register 2 (lower digit) SR2U $01E Serial data register 2 (upper digit) LOR3 $01F Not used $020 Register flag area $023 PMRB $024 Not used R02/INT3 R01/INT2 R00/INT1 PMRC $025 D13/INT0 D12/STOPC R40/EVND R33/EVNB ESR1 $026 INT3 detection edge selection ESR2 $027 EVND detection edge selection SM1B $028 Not used Not used *8 *9 *10 *11 *12 Not used DCD0 $02C Port D3 DCR Port D2 DCR Port D1 DCR Port D0 DCR DCD1 $02D Port D7 DCR Port D6 DCR Port D5 DCR Port D4 DCR DCD2 $02E Port D11 DCR Port D10 DCR Port D9 DCR Port D8 DCR SSR $029 INT2 detection edge selection Not used Not used Not used DCR0 $030 Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR DCR1 $031 Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR DCR2 $032 Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR DCR3 $033 Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR DCR4 $034 Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR DCR5 $035 Port R53 DCR Port R52 DCR Port R51 DCR Port R50 DCR DCR6 $036 Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR DCR7 $037 Port R73 DCR Port R72 DCR Port R71 DCR Port R70 DCR DCR8 $038 Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR DCR9 $039 Port R93 DCR Port R92 DCR Port R91 DCR Port R90 DCR DCRA $03A Port RA3 DCR Port RA2 DCR Port RA1 DCR Port RA0 DCR DCRB $03B Port RB3 DCR Port RB2 DCR Port RB1 DCR Port RB0 DCR DCRC $03C Port RC3 DCR Port RC2 DCR Port RC1 DCR Not used Port RC0 DCR V $03F Not used Not used Not used *13 Notes: 1. Timer-A/time-base 2. Auto-reload on/off 3. Pull-up MOS control 4. Input capture selection 5. A/D conversion time 6. SO2 ouput control in idle states 7. Serial clock source selection 2 8. SO1 output level control in idle states 9. Serial clock source selection 1 10. 32-kHz oscillation stop 11. 32-kHz oscillation division ratio 12. System clock selection 13. Bank 0, 1 selection Figure 5 Special Function Register Area 11 HD404449 Series Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC 12 PC11 $3FC 1021 PC 10 PC9 PC 8 PC7 $3FD 1022 CA PC6 PC 5 PC4 $3FE 1023 PC 3 PC2 PC 1 PC0 $3FF PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position Bank register (V: $03F) Bit 3 2 1 0 Initial value -- -- -- 0 Read/Write -- -- -- R/W Bit name V0 Not used Not used Not used V0 Bank area selection 0 Bank 0 is selected 1 Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Figure 7 Bank Register (V) 12 HD404449 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W 0 (B) 1 W register Initial value: Undefined, R/W 0 (W) 3 X register Initial value: Undefined, R/W Y register Initial value: Undefined, R/W 0 (X) 3 0 (Y) 3 SPX register Initial value: Undefined, R/W 0 (SPX) 3 SPY register Initial value: Undefined, R/W 0 (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Initial value: 1, no R/W (ST) 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 8 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. 13 HD404449 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1. 14 HD404449 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag flags/mask (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0- DCD2) All bits 0 Turns output buffer off (to high impedance) (DCR0- DCRC) All bits 0 Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B (PMRB) - 000 Refer to description of port mode register B Port mode register C (PMRC) 0000 Refer to description of port mode register C Detection edge select register 1 (ESR1) 0000 Disables edge detection Detection edge select register 2 (ESR2) 00 - - Disables edge detection Timer mode register A (TMA) 0000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2 Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A Serial mode register 1B (SM1B) - - 00 Refer to description of serial mode register 1B Serial mode register 2A (SM2A) 0000 Refer to description of serial mode register 2A Serial mode register 2B (SM2B) - 000 Refer to description of serial mode register 2B Prescaler S (PSS) $000 -- Prescaler W (PSW) $00 -- I/O Timer/ counters, serial interface Contents 15 HD404449 Series Abbr. Initial Value Contents Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer counter D (TCD) $00 -- Timer write register B (TWBU, TWBL) $X0 -- Timer write register C (TWCU, TWCL) $X0 -- Timer write register D (TWDU, TWDL) $X0 -- 000 -- (AMR) 00 - 0 Refer to description of A/D mode register (LSON) 0 Refer to description of operating modes Item Timer/ counters, serial interface Octal counter A/D A/D mode register Bit register Low speed on flag Others Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes, and oscillator circuit System clock select register bits 2-0 (SSR2- SSR0) 00 - Refer to description of operating modes, and oscillator circuit Bank register (V) ---0 Refer to description of RAM memory map Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. 16 HD404449 Series Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Status After Status After Cancellation of Stop Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Status After all Other Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Serial data register (SRL, SRU) A/D data register (ADRL, ADRU) RAM RAM enable flag Pre-stop-mode values are retained (RAME) Port mode register (PMRC12) 1 bit 2 1 0 0 Pre-stop-mode values are retained 0 0 System clock (SSR3) select register bit 3 Interrupts The MCU has 11 interrupt sources: four external signals (INT0 , INT1, INT 2, INT 3), four timer/counters (timers A, B, C, and D), two serial interfaces (serial 1, serial 2), and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and INT 3, timer D and A/D converter, and serial interface 1 and serial interface 2. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. 17 HD404449 Series An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* -- $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B, INT2 4 $0008 Timer C, INT3 5 $000A Timer D, A/D 6 $000C Serial 1, Serial 2 7 $000E Note: * The STOPC interrupt request is valid only in stop mode 18 HD404449 Series $ 000,0 IE INT0 interrupt Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $ 000,2 IF0 $ 000,3 IM0 Vector address Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt Timer C interrupt Timer D interrupt $ 002,0 IFTB $ 022,0 IF2 INT2 interrupt $ 002,1 IMTB $ 022,1 IM2 $ 002,2 IFTC $ 022,2 IF3 INT3 interrupt $ 002,3 IMTC $ 022,3 IM3 $ 003,0 IFTD $ 023,0 IF A/D interrupt A/D $ 023,1 IM A/D $ 023,2 Serial 2 interrupt IFS2 $ 003,1 IMTD $ 003,2 Serial 1 interrupt IFS1 $ 003,3 $ 023,3 IMS2 IMS1 Note: $m,n is RAM address $m, bit number n. Figure 9 Interrupt Control Circuit 19 HD404449 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer B or Timer C or Timer D or Serial 1 or INT3 A/D Serial 2 INT2 IE 1 1 1 1 1 1 1 IF0 IM0 1 0 0 0 0 0 0 . . IF1 IM1 * 1 0 0 0 0 0 . IFTA IMTA * * 1 0 0 0 0 . * * * 1 0 0 0 * * * * 1 0 0 * * * * * 1 0 * * * * * * 1 IFTB IMTB . + IF2 IM2 IFTC . IMTC . + IF3 IM3 IFTD . IMTD . + IFAD IMAD IFS1 . IMS1 . + IFS2 IMS2 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: *The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 10 Interrupt Processing Sequence 20 Execution of instruction at start address of interrupt routine HD404449 Series Power on RESET = 1? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC) + 1 PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer-A interrupt? No PC $0008 Yes Timer-B/INT2 interrupt? No PC $000A Yes Timer-C/INT3 interrupt? No PC $000C Yes Timer-D/A-D interrupt? No PC $000E (Serial 1, serial 2 interrupt) Figure 11 Interrupt Processing Flowchart 21 HD404449 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1, INT2, INT3): Four external interrupt signals. External Interrupt Request Flags (IF0, IF1, IF2, IF3: $000, $001, $022): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2 and IF3 are set at the rising or falling edge of signals input to INT2 and INT 3, as listed in table 5. The INT2 and INT 3 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0-IF3: $000, $001, $022) IF0-IF3 Interrupt Request 0 No 1 Yes Detection edge selection register 1 (ESR1: $026) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W ESR13 ESR12 ESR11 ESR10 Bit name INT3 detection edge ESR13 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 INT2 detection edge ESR11 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: *Both falling and rising edges are detected. Figure 12 Detection Edge Selection Register 1 (ESR1) 22 HD404449 Series Detection edge selection register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 -- -- Read/Write W W -- -- Bit name ESR23 ESR22 Not used Not used EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: *Both falling and rising edges are detected. Figure 13 Detection Edge Selection Register 2 (ESR2) External Interrupt Masks (IM0, IM1, IM2, IM3: $000, $001, $022): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0-1M3: $000, $001, $022) IM0-IM3 Interrupt Request 0 Enabled 1 Disabled (Masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes 23 HD404449 Series Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (Masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (Masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes 24 HD404449 Series Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (Masked) Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 13. Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0 No 1 Yes Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request 0 Enabled 1 Disabled (Masked) Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2) Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15 Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2) IFS1, IFS2 Interrupt Request 0 No 1 Yes 25 HD404449 Series Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3) IMS1, IMS2 Interrupt Request 0 Enabled 1 Disabled (Masked) A/D Interrupt Request Flag (IFAD: $023, Bit 0): Set at the completion of A/D conversion, as listed in table 17. Table 17 A/D Interrupt Request Flag (IFAD: $023, Bit 0) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $023, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 18. Table 18 A/D Interrupt Mask (IMAD: $023, Bit 1) IMAD Interrupt Request 0 Enabled 1 Disabled (Masked) 26 HD404449 Series Operating Modes The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables 20 and 21. Transitions between operating modes are shown in figure 14. Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Table 19 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive*2 SBY instruction STOP STOP Activation method RESET instruction when instruction when cancellation, TMA3 = 0 TMA3 = 1 interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) INT0 or timer A interrupt request from watch mode Status System oscillator OP OP Stopped Stopped Stopped Subsystem OP oscillator OP OP*1 OP OP Cancellation method RESET input, STOP/SBY instruction RESET input, RESET input, RESET input, RESET input, interrupt request STOPC input in INT0 or timer A STOP/SBY stop mode interrupt request instruction Note: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 27 HD404449 Series Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Timer D Reset Stopped OP OP Stopped* OP OP Stopped OP Stopped Retained Retained OP Serial 1, 2 Reset A/D Reset I/O 3 1 Reset* Note: OP implies in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. However, all interrupts stop. Table 21 I/O Status in Low-Power Dissipation Modes Output Input Standby mode, watch mode Stop mode Active mode, subactive mode D0-D11 Retained High impedance Input enabled D12-D13 -- -- Input enabled R0-RC Retained or output of peripheral functions High impedance Input enabled 28 HD404449 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR3 = 0) RAME = 0 RAME = 1 RESET1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: o CPU: o CLK: o PER: fOSC: fX: o CPU: o CLK: o PER: SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR3 = 1) STOP fOSC: fX: o CPU: o CLK: o PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A*1 fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop *3 fOSC: fX: Main oscillation frequency Suboscillation frequency for time-base fOSC/4 fcyc: fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU: System clock o CLK: Clock for time-base o PER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag *2 Subactive mode fOSC: fX: o CPU: o CLK: o PER: STOP Stop Oscillate fSUB fW fSUB Notes: 1. 2. 3. 4. *4 INT0, timer A*1 (TMA3 = 1, LSON = 1) fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1) Figure 14 MCU Status Transitions 29 HD404449 Series Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15. Stop Standby Watch Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop No RESET = 1? Yes RESET = 1? No Yes IF0 * IM0 = 1? No No STOPC = 0? Yes IF1 * IM1 = 1? No Yes Yes IFTA * IMTA = 1? Yes RAME = 1 No IFTB * IMTB + IF2 * IM2 = 1? RAME = 0 Yes No IFTC * IMTC + IF3 * IM3 = 1? Yes No IFTD * IMTD + IFAD * IMAD = 1? Yes (SBY only) (SBY only) Restart processor clocks (SBY only) (SBY only) Restart processor clocks Execute next instruction No Reset MCU IF = 1, IM = 0, and IE = 1? Yes Execute next instruction Figure 15 MCU Operation Flowchart 30 Accept interrupt No IFS1* IMS1 + IFS2 * IMS2 = 1? (SBY only) Yes No , HD404449 Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Operation of the X1 and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029; operating: SSR3 = 0, stop: SSR3 = 1) (figure 26). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 41). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres tRC (stabilization period) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figure 17. Operation during mode transition is the same as that at standby mode cancellation (figure 15). 31 HD404449 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) T t RC Tx Interrupt frame length T: t RC : Oscillation stabilization period Figure 17 Interrupt Frame Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR2) of the system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, oCLK is applied to timer A and the INT0 circuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. 32 HD404449 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 38. MIS1 MIS0 0 0 T*1 tRC*1 0.24414 ms 0.12207 ms Oscillation circuit conditions External clock input 0.24414 ms*2 0 1 15.625 ms 1 0 125 ms 1 1 Not used 7.8125 ms Ceramic oscillator or crystal 62.5 ms -- Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (Figure 19). Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC 33 HD404449 Series STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T t RC Interrupt frame length T: t RC : Oscillation stabilization period Figure 19 Direct Transition Timing Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. 34 HD404449 Series Power on RESET = 1 ? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 20 MCU Operating Sequence (Power On) 35 HD404449 Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 21 MCU Operating Sequence (MCU Operation Cycle) 36 HD404449 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Standby/Watch mode Stop mode * No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle Note: * For IF and IM operation, refer to figure 15. Figure 22 MCU Operating Sequence (Low-Power Mode Operation) Note: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Edge detection is shown in figure 23. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 24, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. 37 HD404449 Series When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 23 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low (a) High level period Figure 24 Sampling Example 38 A: High B: High (b) Low level period HD404449 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 25. As shown in table 22, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock select register (SSR: $029) must be selected according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 26). Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency, subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 1/4 System fOSC division oscillator circuit fcyc tcyc Timing generator circuit OSC1 fX X1 Subsystem oscillator oCPU CPU with ROM, RAM, registers, flags, and I/O oPER Peripheral function interrupt System clock selection fSUB 1/8 or 1/4 Timing division tsubcyc generator circuitNote circuit TMA3 X2 1/8 division circuit fW tWcyc Timing generator circuit Time-base clock oCLK selection Time-base interrupt Note: 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (SSR: $029). Figure 25 Clock Generation Circuit 39 HD404449 Series System clock select register (SSR: $029) Bit 3 2 1 0 Initial value 0 0 0 -- Read/Write W W W -- SSR3 SSR2 SSR1 Not used Bit name SSR2 32-kHz oscillation division ratio selection 0 fSUB = fX/8 1 fSUB = fX/4 SSR3 SSR1 System clock selection 0 0.4 to 1.0 MHz 1 1.6 to 4.0 MHz 32-kHz oscillation stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode Figure 26 System Clock Select Register D0 GND X2 X1 RESET OSC2 OSC1 TEST AVSS GND Figure 27 Typical Layouts of Crystal and Ceramic Oscillator 40 HD404449 Series Table 22 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator (OSC1, OSC2) Ceramic oscillator: CSA4.00MG (Murata) C1 Rf = 1 M 20% OSC1 Ceramic oscillator C1 = C2 = 30 pF 20% Rf OSC2 C2 GND Rf = 1 M 20% C1 Crystal oscillator (OSC1, OSC2) C1 = C2 = 10-22 pF 20% OSC1 Ceramic oscillator Crystal: Equivalent to circuit shown below Rf C0 = 7 pF max OSC2 RS = 100 max C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Ceramic: 32.768 kHz: MX38T X1 (Nippon Denpa Kogyo) C1 = C2 = 20 pF 20% Crystal RS: 14 k X2 C0: 1.5 pF C2 GND L CS RS X1 X2 C0 Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, X1, X2, and elements should be as short as possible, and must not cross other wiring (see figure 27). 3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be open. 41 HD404449 Series Input/Output The MCU has 64 input/output pins (D 0-D 11, R00-RC 3) and 2 input pins (D12, D13). The features are described below. * 10 pins (D0-D9) are high-current input/output pins. * The D12, D13, R00-R0 2, and R3 0-R5 3 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R43/SO1 and R5 3/SO 2 pins can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 28, programmable I/O circuits are listed in table 23, and I/O pin circuit types are shown in table 24. Table 23 Programmable I/O Circuits MIS3 (Bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS Note: -- indicates off status. 42 1 1 0 1 HD404449 Series HLT Pull-up control signal VCC Pull-up MOS MIS3 VCC Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 28 I/O Buffer Configuration 43 HD404449 Series Table 24 Circuit Configurations of I/O Pins I/O Pin Type Circuit Input/output pins Pins VCC VCC Pull-up control signal Buffer control signal HLT D0-D11 , R00-R03 MIS3 R10-R13, R20-R23 DCD, DCR R50-R52, R60-R63 Output data PDR RB0-RB3, RC0-RC3 Input control signal HLT VCC R70-R73, R80-R83 R90-R93, RA0-RA3 Input data VCC R30-R33, R40-R42 Pull-up control signal Buffer control signal R43, R53 MIS3 DCR MIS2, SM2B2 PDR Output data Input data Input control signal Input data Input pins D12, D13 Input control signal Peripheral Input/ output function pins pins VCC HLT VCC Pull-up control signal MIS3 Output data Input data Output pins VCC SCK 1 , SCK 2 SCK 1 , SCK 2 HLT VCC Pull-up control signal Output data VCC Output data 44 MIS2, SM2B2 SO 1 , SO 2 HLT Pull-up control signal SO1, SO2 MIS3 PMOS control signal VCC SCK 1, SCK 2 MIS3 TOB, TOC, TOD TOB, TOC, TOD HD404449 Series I/O Pin Type Circuit Input pins Pins SI1, SI2, INT1, VCC HLT MIS3 PDR Input data Input data INT2, INT3, EVNB, EVND SI1, SI2,, INT1, etc INT0 , STOPC INT0, STOPC Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes. D Port (D 0-D13): Consist of 12 input/output pins and 2 input pins addressed by one bit. D0-D11 are highcurrent I/O pins, and D12 and D13 are input-only pins. Pins D0-D 11 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 29). Pins D 12 and D13 are multiplexed with peripheral function pins STOPC and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 30). R Ports (R0 0-RC3): 52 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCRC: $030-$03C) that are mapped to memory addresses (figure 29). Pins R00-R02 are multiplexed with peripheral pins INT1-INT 3, respectively. The peripheral function modes of these pins are selected by bits 0-2 (PMRB0-PMRB2) of port mode register B (PMRB: $024) (figure 31). Pins R30-R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34). Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 30). Pins R41-R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36. 45 HD404449 Series Ports R51-R5 3 are multiplexed with peripheral function pins SCK 2, SI2, SO2, respectively. The function modes of these pins can be selected by individual pins, by 2A setting bit 3 (SM2A3) of serial mode register 2A (SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 36 and 37). Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 12 and D13 . The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 23 and figure 38). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. 46 HD404449 Series Data control register (DCD0 to 2: $02C to $02E) (DCR0 to C: $030 to $03C) DCD0, DCD1 Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 DCD2 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W DCD23 DCD22 DCD21 DCD20 3 2 1 0 DCR0 to DCRC Bit Initial value 0 0 0 0 Read/Write W W W W Bit name DCR03- DCR02- DCR01- DCR00- DCRC3 DCRC2 DCRC1 DCRC0 All Bits CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 D11 D10 D9 D8 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR5 R53 R52 R51 R50 DCR6 R63 R62 R61 R60 DCR7 R73 R72 R71 R70 DCR8 R83 R82 R81 R80 DCR9 R93 R92 R91 R90 DCRA RA3 RA2 RA1 RA0 DCRB RB3 RB2 RB1 RB0 DCRC RC3 RC2 RC1 RC0 Figure 29 Data Control Registers (DCD, DCR) 47 HD404449 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 W W Read/Write Bit name W PMRC3 PMRC2* PMRC1 W PMRC0 PMRC0 R33/EVNB mode selection 0 R33 1 EVNB PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D12/STOPC mode selection 0 D12 1 STOPC PMRC3 D13/INT0 mode selection 0 D13 1 INT0 Note: *PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value. Figure 30 Port Mode Register C (PMRC ) 48 HD404449 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value -- 0 0 0 -- W W W Read/Write Bit name Not used PMRB2 PMRB1 PMRB0 PMRB0 R00/INT1 mode selection 0 R00 1 INT1 PMRB1 R01/INT2 mode selection 0 R01 1 INT2 PMRB2 R02/INT3 mode selection 0 R02 1 INT3 Figure 31 Port Mode Register B (PMRB) Timer mode register B2 (TMB2: $013) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- R/W R/W Bit name Not used Not used TMB21 TMB20 R30/TOB mode selection TMB21 TMB20 0 0 R30 R30 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 Figure 32 Timer Mode Register B2 (TMB2) 49 HD404449 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- R/W R/W R/W TMC21 TMC20 Bit name Not used TMC22 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 -- Inhibited TOC PWM output 1 1 0 R31/TOC mode selection 1 1 0 1 Figure 33 Timer Mode Register C2 (TMC2) 50 HD404449 Series Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 Bit name R32/TOD mode selection TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 TOD Inhibited TOD PWM output R32 Input capture (R32 port) 1 1 0 1 1 0 1 1 Don't care Don't care Don't care Figure 34 Timer Mode Register D2 (TMD2) 51 HD404449 Series Serial mode register 1A (SM1A: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W SM1A3 SM1A2 SM1A1 SM1A0 Bit name SM1A3 R41/SCK1 mode selection 0 R41 1 SCK1 SM1A2 SM1A1 SM1A0 SCK1 Clock source Prescaler division ratio 0 0 0 Output Prescaler /2048 1 Output Prescaler /512 0 Output Prescaler /128 1 Output Prescaler /32 0 Output Prescaler /8 1 Output Prescaler /2 0 Output System clock -- 1 Input External clock -- 1 1 0 1 Figure 35 Serial Mode Register 1A (SM1A) 52 HD404449 Series Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 R43/SO1 mode selection 0 R43 1 SO1 PMRA1 R42/SI1 mode selection 0 R42 1 SI1 PMRA2 R53/SO2 mode selection 0 R53 1 SO2 PMRA3 R52/SI2 mode selection 0 R52 1 SI2 Figure 36 Port Mode Register A (PMRA) 53 HD404449 Series Serial mode register 2A (SM2A: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W SM2A3 SM2A2 SM2A1 SM2A0 Bit name SM2A3 R51/SCK2 mode selection 0 R51 1 SCK2 SM2A2 SM2A1 SM2A0 SCK2 Clock source Prescaler division ratio 0 0 0 Output Prescaler /2048 1 Output Prescaler /512 0 Output Prescaler /128 1 Output Prescaler /32 0 Output Prescaler /8 1 Output Prescaler /2 0 Output System clock -- 1 Input External clock -- 1 1 0 1 Figure 37 Serial Mode Register 2A (SM2A) Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R43/SO1 Bit name MIS3 Pull-up MOS on/off selection 0 Off 0 On 1 On 1 Off MIS1 tRC selection. Refer to figure 18 in the operation modes section. Figure 38 Miscellaneous Register (MIS) 54 MIS0 HD404449 Series Prescalers The MCU has the following two prescalers, S and W. The prescaler operating conditions are listed in table 25, and the prescaler output supply is shown in figure 39. The timer A-D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in stop, watch, and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), Subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W 32-kHz crystal oscillation Software MCU reset, stop mode Subsystem clock fX /8 Prescaler W fX /4 or fX /8 Timer A Timer B Timer C System clock Clock selector Prescaler S Timer D Serial 1 Serial 2 Figure 39 Prescaler Output Supply 55 HD404449 Series Timers The MCU has four timer/counters (A to D). * * * * Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers, whose functions are listed in table 26. The operating modes are selected by software. Table 26 Timer Functions Functions Clock source Timer functions Timer outputs Timer A Timer B Timer C Timer D Prescaler S Available Available Available Available Prescaler W Available -- -- -- External event -- Available -- Available Free-running Available Available Available Available Time-base Available -- -- -- Event counter -- Available -- Available Reload -- Available Available Available Watchdog -- -- Available -- Input capture -- -- -- Available Toggle -- Available Available Available 0 output -- Available Available Available 1 output -- Available Available Available PWM -- -- Available Available Note: -- means not available. 56 HD404449 Series Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 40. 1/4 fW 1/2 twcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) /2 /8 / 16 / 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow System clock o PER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 40 Timer A Block Diagram Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. 57 HD404449 Series Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 41. Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMA3 TMA2 TMA1 TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 PSW 1/2tWcyc 1 Inhibited Don't care Timer A mode Time-base mode PSW and TCA reset Notes: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 41 Timer Mode Register A (TMA) 58 HD404449 Series Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs) The block diagram of timer B is shown in figure 42. Timer B interrupt request flag (IFTB) Timer output control logic TOB Timer read register BU (TRBU) Timer output control Timer read register BL (TRBL) Clock System clock o PER / 2048 EVNB /2 /4 /8 / 32 / 128 / 512 Selector Timer write register BU (TWBU) Prescaler S (PSS) Free-running/ Reload control Timer write register BL (TWBL) Internal data bus Timer counter B (TCB) Overflow 3 Timer mode register B1 (TMB1) 2 Timer mode register B2 (TMB2) Figure 42 Timer B Block Diagram 59 HD404449 Series Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. Other operations are basically the same as the free-running/ reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 43. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low. 60 HD404449 Series Toggle output waveform (timers B, C, and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 - N) clock cycles (256 - N) clock cycles PWM output waveform (timers C and D) T x (N + 1) TMC13 = 0 TMD13 = 0 T T x 256 TMC13 = 1 TMD13 = 1 T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 52 and 59) N: The value of the timer write register Figure 43 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44. It is reset to $0 by MCU reset. 61 HD404449 Series Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-running/reload timer selection TMB12 TMB11 TMB10 0 Free-running timer 0 0 0 2048tcyc 1 Reload timer 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R33/EVNB (External event input) 1 1 0 1 Input clock period and input clock source Figure 44 Timer Mode Register B1 (TMB1) * Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 45. It is reset to $0 by MCU reset. 62 HD404449 Series Timer mode register B2 (TMB2: $013) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- R/W R/W Bit name Not used Not used TMB21 TMB20 TMB21 TMB20 0 0 R30 R30 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 R30/TOB mode selection Figure 45 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU) as shown in figures 46 and 47. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TWBL3 TWBL2 TWBL1 TWBL0 Figure 46 Timer Write Register B Lower Digit (TWBL) Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 47 Timer Write Register B Upper Digit (TWBU) 63 HD404449 Series * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 48 and 49). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained. Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 48 Timer Read Register B Lower Digit (TRBL) Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 49 Timer Read Register B Upper Digit (TRBU) * Port mode register C (PMRC: $025): Write-only register that selects R33/EVNB pin function as shown in figure 50. It is reset to $0 by MCU reset. 64 HD404449 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRC3 PMRC2 PMRC1 PMRC0 PMRC0 R33/EVNB mode selection 0 R33 1 EVNB PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D12/STOPC mode selection 0 D12 1 STOPC PMRC3 D13/INT0 mode selection 0 D13 1 INT0 Figure 50 Port Mode Register C (PMRC) Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 51. 65 HD404449 Series System reset signal Watchdog on flag (WDON) Timer C interrupt request flag (IFTC) Watchdog timer control logic Timer output control logic TOC Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Timer counter C (TCC) Timer write register CU (TWCU) /2 /4 /8 /32 /128 /512 /1024 /2048 Selector System oPER clock Prescaler S (PSS) Overflow Free-running /Reload control Timer write register CL (TWCL) Internal data bus Clock 3 Timer mode register C1 (TMC1) 3 Timer mode register C2 (TMC2) Figure 51 Timer C Block Diagram Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. 66 HD404449 Series The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 43. Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and prescaler division ratio as shown in figure 52. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. * Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 53. It is reset to $0 by MCU reset. 67 HD404449 Series * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) as shown in figures 54 and 55. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures 56 and 57. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). Timer mode register C1 (TMC1: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC13 TMC12 TMC11 TMC10 Bit name TMC13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 52 Timer Mode Register C1 (TMC1) 68 Input clock period TMC12 HD404449 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value -- 0 0 0 -- R/W Read/Write Bit name R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 TOC Inhibited TOC PWM output 1 1 0 R31/TOC mode selection 1 0 1 1 Figure 53 Timer Mode Register C2 (TMC2) Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 54 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 55 Timer Write Register C Upper Digit (TWCU) 69 HD404449 Series Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 56 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 57 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 58 (A) and (B). 70 HD404449 Series Timer D interrupt request flag (IFTD) Timer output control logic TOD Timer read register DU (TRDU) Timer output control Timer read register DL (TRDL) Clock Timer write register DU (TWDU) System clock oPER /2048 Edge detection logic /2 /4 /8 /32 /128 /512 Selector EVND Overflow Free-running/ Reload control Timer write register DL (TWDL) 3 Prescaler S (PSS) Internal data bus Timer counter D (TCD) Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 58 (A) Timer D Block Diagram (Free-Running/Reload Timer) 71 HD404449 Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Timer counter D (TCD) Overflow Selector System clock /2048 /2 /4 /8 /32 /128 /512 3 Timer mode register D1 (TMD1) oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 58 (B) Timer D Block Diagram (Input Capture Timer) 72 Internal data bus Input capture timer control HD404449 Series Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). 73 HD404449 Series When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. * Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset. 74 HD404449 Series Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name TMD13 W W W W TMD13 TMD12 TMD11 TMD10 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period and input clock source TMD12 TMD11 TMD10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R40/EVND (External event input) 1 1 0 1 Figure 59 Timer Mode Register D1 (TMD1) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) as shown in figures 61 and 62. The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) as shown in figures 63 and 64. The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 50. It is reset to $0 by MCU reset. * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset. 75 HD404449 Series Timer mode register D2 (TMD2: $015) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 Bit name TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 -- Inhibited TOD PWM output R32 Input capture (R32 port) 1 1 0 R32/TOD mode selection 1 0 1 1 1 Don't care Don't care Don't care Figure 60 Timer Mode Register D2 (TMD2) Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TWDL3 TWDL2 TWDL1 TWDL0 Figure 61 Timer Write Register D Lower Digit (TWDL) Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 62 Timer Write Register D Upper Digit (TWDU) 76 HD404449 Series Timer read register D (lower digit) (TRDL: $011) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write Bit name R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 63 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit 3 Initial value 2 0 1 Undefined Undefined Undefined Undefined Read/Write Bit name R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 64 Timer Read Register D Upper Digit (TRDU) Detection edge register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 -- -- W -- -- Read/Write W Bit name ESR23 ESR22 Not used Not used EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 65 Detection Edge Select Register 2 (ESR2) Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. 77 HD404449 Series Table 27 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Timer write register updated to value N Reload T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 78 T x (N + 1) T HD404449 Series Serial Interface The MCU has two channels of serial interface. The transfer and receive start instructions differ according to the serial interface channel, but other functions are the same. The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as follows. Serial interface 1 * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector Serial interface 2 * * * * * * Serial data register 2 (SR2L: $01D, SR2U: $01E) Serial mode register 2A (SM2A: $01B) Serial mode register 2B (SM2B: $01C) Port mode register A (PMRA: $004) Octal counter (OC) Selector The block diagram of serial interfaces 1 and 2 are shown in figure 66. 79 HD404449 Series Serial interrupt request flag (IFS1, IFS2) Octal counter (OC1, OC2) Idle control logic SO1 , SO2 SCK1 , SCK2 Transfer control 1/2 1/2 System clock oPER 3 /2048 /8 /32 /128 /512 /2 Selector Selector SI1 , SI 2 Internal data bus Serial data register (SR1L/U, SR2L/U) Clock I/O control logic Prescaler S (PSS) Serial mode register 1A, 2A (SM1A, SM2A) Serial mode register 1B, 2B (SM1B, SM2B) Figure 66 Serial Interfaces 1 and 2 Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: Tables 28 (A) and 28 (B) list the serial interfaces' operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), serial mode register 1A (SM1A: $005), and serial mode register 2A (SM2A: $01B) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A; and to change the operating mode of serial interface 2, always initialize the serial interface internally by writing data to serial mode register 2A. Note that serial interface 80 HD404449 Series 1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data to serial mode register 2A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R5 1/SCK 2 pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R42/SI 1, R4 3/SO 1, R5 2/SI 2, and R5 3/SO 2 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2 (SR2L: $01D, SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. Receive data of serial interface 2 is obtained by reading the contents of serial data register 2. The serial data is shifted by each serial interface transmit clock and is input from or output to an external system. The output level of the SO1 and SO2 pins is invalid until the first data of each serial interface is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by a dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The octal counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at the rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial 2 interrupt request flag (IFS2: $023, bit 2) for serial interface 2 are set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0-SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 29. When the prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM2A0- SM2A2) of serial mode register 2A (SM2A: $01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C). Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that compares serial mode register 2A (SM2A: $01B) with the accumulator. Serial mode register 2A (SM2A: $01B) is a read-only register, so $0 can be read. 81 HD404449 Series Table 28 (A) Serial Interface 1 Operating Modes SM1A PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Table 28 (B) Serial Interface 2 Operating Modes SM2A PMRA Bit 3 Bit 3 Bit 2 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Table 29 Serial Transmit Clock (Prescaler Output) SM1B/ SM2B SM1A/ SM2A Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 82 0 HD404449 Series Operating States: The serial interface has the following operating states; transitions between them are shown in figure 67. STS wait state (serial interface 2 is in SM2A read wait state) Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1. * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state. External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SM1A write 00 MCU reset 06 SM1A write (IFS 1) 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Transfer state (Octal counter = 000) 05 STS instruction (IFS 1) Internal clock mode STS wait state (Octal counter = 000, transmit clock disabled) SM1A write 18 Continuous clock output state (PMRA 0, 1 = 00) 10 13 SM1A write 8 transmit clocks 14 11 STS instruction MCU reset 16 SM1A write (IFS 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 15 STS instruction (IFS 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 67 Serial Interface State Transitions * Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the 83 HD404449 Series serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state and when serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin, SO1 and SO2, can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1, or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example of serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state. 84 , HD404449 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SM1A write Output level control in idle states Dummy write for state transition Output level control in idle states SM1B write Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB MSB IFS1 External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SM1A write Output level control in idle states SM1B write Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB MSB IFS1 Internal clock mode Flag reset at transfer completion Figure 68 Example of Serial Interface 1 Operation Sequence 85 HD404449 Series Transmit Clock Error Detection (In External Clock Mode): Each serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 69. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS1 is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag (IFS1: $003, bit 2) is set again, and therefore the error can be detected. The same applies to serial interface 2. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) and serial mode register 2A (SM2A: $01B) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) and serial 2 interrupt request flag (IFS2: $023, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (IFS1: $003, bit 2) is not set. In the same way for serial interface 2, if the state is changed from transfer state to another by writing to serial mode register 2A (SM2A: $01B) or by executing the STS instruction during the first low pulse of the transmit clock, the serial 2 interrupt request flag (IFS2: $023, bit 2) is not set. To set the serial 1 interrupt request flag (IFS1: $003, bit 2), a serial mode register 1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. To set the serial 2 interrupt request flag (IFS2: $023, bit 2), a serial mode register 2A (SM2A: $01B) write or SM2A instruction execution must be programmed to be executed after confirming that the SCK 2 pin is at 1, that is, after executing the input instruction to port R5. 86 HD404449 Series Transfer completion (IFS1 1) Interrupts inhibited IFS1 0 SM1A write Yes IFS1 = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State SCK 1 pin (input) 1 2 Transfer state Noise 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. SM1A write IFS1 Flag set because octal counter reaches 000. Flag reset at transfer completion. Transmit clock error detection procedures Figure 69 Transmit Clock Error Detection 87 HD404449 Series Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. For serial interface 1 * Serial mode register 1A (SM1A: $005) * Serial mode register 1B (SM1B: $028) * Serial data register 1 (SR1L: $006, SR1U: $007) * Port mode register A (PMRA: $004) * Miscellaneous register (MIS: $00C) For serial interface 2 * Serial mode register 2A (SM2A: $01B) * Serial mode register 2B (SM2B: $01C) * Serial data register 2 (SR2L: $01D, SR2U: $01E) * Port mode register A (PMRA: $004) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 70). * * * * R4 1/SCK 1 pin function selection Serial interface 1 transmit clock selection Serial interface 1 prescaler division ratio selection Serial interface 1 initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 88 HD404449 Series Serial mode register 1A (SM1A: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SM1A3 SM1A2 SM1A1 SM1A0 Bit name SM1A3 R41/SCK1 mode selection 0 R41 1 SCK1 Prescaler division ratio SM1A2 SM1A1 SM1A0 SCK1 Clock source 0 0 0 Output Prescaler Refer to table 29 0 Output System clock -- 1 Input External clock -- 1 1 0 1 1 0 0 1 1 Figure 70 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 71). * Serial interface 1 prescaler division ratio selection * Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to. 89 HD404449 Series Serial mode register 1B (SM1B: $028) Bit 3 2 1 0 Initial value -- -- Undefined 0 Read/Write -- -- W W Bit name Not used Not used SM1B1 SM1B1 Output level control in idle states SM1B0 SM1B0 Transmit clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 71 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 72 and 73) * Serial interface 1 transmission data write and shift * Serial interface 1 receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 74. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register 1 (lower digit) (SR1L: $006) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR13 SR12 SR11 SR10 Figure 72 Serial Data Register 1 (SR1L) 90 HD404449 Series Serial data register 1 (upper digit) (SR1U: $007) Bit Initial value 1 2 3 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR17 SR16 SR15 SR14 Figure 73 Serial Data Register 1 (SR1U) Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 74 Serial Interface Output Timing 91 HD404449 Series Port Mode Register A (PMRA: $004): This register has the following functions (figure 75). * * * * R4 2/SI 1 pin function selection R4 3/SO 1 pin function selection R5 2/SI 2 pin function selection R5 3/SO 2 pin function selection Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 R43/SO1 mode selection 0 R43 1 SO1 PMRA1 R42/SI1 mode selection 0 R42 1 SI1 PMRA2 R53/SO2 mode selection 0 R53 1 SO2 PMRA3 R52/SI2 mode selection 0 R52 1 SI2 Figure 75 Port Mode Register A (PMRA) 92 HD404449 Series Miscellaneous Register (MIS: $00C): This register has the following functions (figure 76). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS1 MIS0 0 0 tRC 0.12207 ms 0.24414 ms* 1 MIS2 1 7.8125 ms 0 62.5 ms 1 Not used R43/SO1 PMOS on/off selection 0 On 1 Off MIS3 Pull-up MOS on/off selection 0 Off 1 On Note: *This value is valid only for direct transfer operation. Figure 76 Miscellaneous Register (MIS) Serial Mode Register 2A (SM2A: $01B): This register has the following functions (figure 77). * * * * R5 1/SCK 2 pin function selection Serial interface 2 transmit clock selection Serial interface 2 prescaler division ratio selection Serial interface 2 initialization Serial mode register 2A (SM2A: $01B) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 2A (SM2A: $01B) discontinues the input of the transmit clock to serial data register 2 (SR2L: $01D, SR1U: $01E) and the octal counter, and the octal counter is reset to 93 HD404449 Series 000. Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the SM2A read instruction must be executed at least two cycles after that. Serial mode register 2A (SM2A: $01B) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SM2A3 SM2A2 SM2A1 SM2A0 Bit name SM2A3 R51/SCK2 mode selection 0 R51 1 SCK2 Prescaler division ratio SM2A2 SM2A1 SM2A0 SCK2 Clock source 0 0 0 Output Prescaler Refer to table 29 0 Output System clock -- 1 Input External clock -- 1 1 0 1 1 0 0 1 1 Figure 77 Serial Mode Register 2A (SM2A) Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78). * Serial interface 2 prescaler division ratio selection * Serial interface 2 output level control in idle states * R5 3/SO 2 pin PMOS control Serial mode register 2B (SM2B: $01C) is a 3-bit write-only register. It cannot be written during serial interface 2 data transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) is reset to $0 by MCU reset. By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is selected. By resetting bit 1 (SM2B1), the output level of the SO2 pin is controlled in idle states of serial interface 2. The output level changes at the same time that SM2B1 is written to. 94 HD404449 Series Serial mode register 2B (SM2B: $01C) Bit 3 2 1 0 Initial value -- 0 Undefined 0 Read/Write -- W W W SM2B1 SM2B0 Bit name SM2B2 Not used SM2B2 R53/SO2 PMOS SM2B0 Transmit clock division ratio 0 On 0 Prescaler output divided by 2 1 Off 1 Prescaler output divided by 4 SM2B1 Output level control in idle states 0 Low level 1 High level Figure 78 Serial Mode Register 2B (SM2B) Serial Data Register 2 (SR2L: $01D, SR2U: $01E): This register has the following functions (figures 79 and 80). * Serial interface 2 transmission data write and shift * Serial interface 2 receive data shift and read Writing data in this register is output from the SO2 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI2 pin at the rising edge of the transmit clock. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register 2 (lower digit) (SR2L: $01D) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR23 SR22 SR21 SR20 Figure 79 Serial Data Register 2 (SR2L) 95 HD404449 Series Serial data register 2 (upper digit) (SR2U: $007) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR27 SR26 SR25 SR24 Figure 80 Serial Data Register 2 (SR2U) 96 HD404449 Series A/D Converter The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register. Internal bus line (S2) Internal bus line (S1) 4 4 A/D mode register (AMR) 2 A/D start flag (ADSF) 4 A/D data register (ADRU, ADRL) 2 8 IFAD AN 1 AN 2 AN 3 Selector AN 0 A/D interrupt request flag + Control logic COMP - AVCC AVSS Encoder D/A 8 Operating mode signal (set to 0 in stop mode, watch mode, and subactive mode) Figure 81 A/D Converter Block Diagram A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 2 and 3 select a channel, as shown in figure 82. A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 86. A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85). 97 HD404449 Series Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed. The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock. During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input. A/D mode register (AMR: $016) Bit 3 2 1 0 Initial value 0 0 -- 0 Read/Write W W -- W Bit name AMR3 AMR2 Not used Analog input selection AMR0 AMR3 AMR2 0 0 AN0 0 34tcyc 0 1 AN1 1 67tcyc 1 0 AN2 1 1 AN3 AMR0 Conversion time Figure 82 A/D Mode Register (AMR) ADRU: $018 3 2 1 ADRL: $017 0 3 1 0 MSB LSB Bit 7 Bit 0 Figure 83 A/D Data Registers 98 2 HD404449 Series A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R R R R ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 84 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 Bit name ADRU1 ADRU0 Figure 85 A/D Data Register Upper Digit (ADRU) 99 HD404449 Series A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W DTON ADSF WDON LSON Bit name LSON Refer to the description of operating modes WDON Refer to the description of timers ADSF (A/D start flag) 1 A/D conversion started 0 A/D conversion completed DTON Refer to the description of operating modes Figure 86 A/D Start Flag (ADSF) 100 HD404449 Series Notes on Mounting Assemble all parts including the HD404449 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS . * When not using an A/D converter VCC AVCC AN 0 0.1 F AN 1 AN 2 AN 3 AVSS GND * When using pins AN0 and AN1 but not using AN2 and AN3 AVCC VCC AN 0 AN 1 AN 2 AN 3 AVSS GND 0.1 F x 3 * When using all analog pins VCC AVCC AN 0 AN 1 AN 2 AN 3 GND AVSS 0.1 F x 5 Figure 87 Example of Connections (1) 101 HD404449 Series Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 88. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. VCC VCC C1 GND C2 GND Figure 88 Example of Connections (2) 102 HD404449 Series Programmable ROM (HD4074449) The HD4074449 is a ZTAT microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description MCU Mode PROM Mode Pin No. Pin Name I/O Pin Name 1 AN2 2 AN3 3 AVSS 4 TEST I TEST 5 OSC1 I VCC 6 OSC2 O 7 RESET I RESET 8 X1 I GND 9 X2 O 10 GND 11 D0 I/O CE 12 D1 I/O OE 13 D2 I/O 14 D3 I/O 15 D4 16 D5 17 MCU Mode I/O PROM Mode Pin No. Pin Name I/O Pin Name I/O I 31 R12 I/O A7 I I 32 R13 I/O A8 I GND I I 33 R20 I/O A0 I 34 R21 I/O A10 I 35 R22 I/O A11 I 36 R23 I/O A12 I 37 R30/TOB I/O 38 R31/TOC I/O 39 R32/TOD I/O 40 R33/EVNB I/O I 41 R40/EVND I/O I 42 R41/SCK 1 I/O VCC 43 R42/SI1 I/O VCC 44 R43/SO1 I/O I/O 45 R50 I/O I/O 46 R51/SCK 2 I/O D6 I/O 47 R52/SI2 I/O 18 D7 I/O 48 R53/SO2 I/O 19 D8 I/O 49 R60 I/O A1 I 20 D9 I/O 50 R61 I/O A2 I 21 D10 I/O A13 I 51 R62 I/O A3 I 22 D11 I/O A14 I 52 R63 I/O A4 I 23 D12/STOPC I A9 I 53 R70 I/O O0 I/O 24 D13/INT0 I VPP 54 R71 I/O O1 I/O 25 R00/INT1 I/O M0 I 55 R72 I/O O2 I/O 26 R01/INT2 I/O M1 I 56 R73 I/O O3 I/O 27 R02/INT3 I/O 57 R80 I/O O4 I/O 28 R03 I/O 58 R81 I/O O5 I/O 29 R10 I/O A5 I 59 R82 I/O O6 I/O 30 R11 I/O A6 I 60 R83 I/O O7 I/O GND 103 HD404449 Series MCU Mode PROM Mode MCU Mode PROM Mode Pin No. Pin Name I/O Pin Name I/O Pin No. Pin Name I/O Pin Name 61 R90 I/O O4 I/O 71 RB2 I/O 62 R91 I/O O3 I/O 72 RB3 I/O 63 R92 I/O O2 I/O 73 RC0 I/O 64 R93 I/O O1 I/O 74 RC1 I/O 65 RA0 I/O O0 I/O 75 RC2 I/O 66 RA1 I/O VCC 76 RC3 I/O 67 RA2 I/O 77 VCC VCC 68 RA3 I/O 78 AVCC VCC 69 RB0 I/O 79 AN0 I 70 RB1 I/O 80 AN1 I Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using, each pair must be connected together. 104 I/O HD404449 Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 89. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD4074449 are listed in table 31. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 30. For details of PROM programming, refer to the following section, Notes on PROM Programming. Table 30 PROM Mode Selection Pin Mode CE OE VPP O0-O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 105 HD404449 Series Table 31 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Manufacturer Package Model Name DATA I/O Corp. 121B Hitachi FP-80A HS444ESH01H TFP-80F HS4449ESN01H FP-80A HS444ESH01H TFP-80F HS4449ESN01H 29B AVAL Corp. PKW-1000 Hitachi VCC VCC AVCC VCC VCC RESET TEST M0 VPP M1 O0 to O7 Data O0 to O7 A0 to A14 Address A0 to A14 VPP HD4074449 VCC OSC1 D2 D3 RA1 X1 AVSS GND Figure 89 PROM Mode Connections 106 OE OE CE CE HD404449 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 90 and described below. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Direct Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 90 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. 107 HD404449 Series Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 91 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 93. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 92. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 108 HD404449 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B2 B1 Accumulator B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 91 ROM Addressing Modes 109 HD404449 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 92 P Instruction 256 (n - 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 93 Branching when the Branch Destination is on a Page Boundary 110 HD404449 Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC -0.3 to +7.0 V Programming voltage VPP -0.3 to +14.0 V Pin voltage VT -0.3 to (VCC + 0.3) V Total permissible input current Io 100 mA 2 Total permissible output current -Io 50 mA 3 Maximum input current Io 4 mA 4, 5 30 mA 4, 6 7, 8 Maximum output current -Io 4 mA Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Notes 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal opera-tion must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D13 (VPP ) of the HD4074449. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D10 , D11 , and R0-RC. 6. Applies to D0-D9. 7. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 8. Applies to D0-D11 and R0-RC. 111 HD404449 Series Electrical Characteristics DC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074449: V CC = 2.7 to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH RESET, STOPC, 0.9VCC -- VCC + 0.3 V -- OSC1 VCC - 0.3 -- VCC + 0.3 V External clock operation RESET, STOPC, -0.3 -- 0.1VCC V -- OSC1 -0.3 -- 0.3 V External clock operation SCK 1, SO1, VCC - 1.0 -- -- V -IOH = 0.5 mA -- -- 0.4 V IOL = 0.4 mA -- -- 1.0 A Vin = 0 V to VCC 1 -- 5 9 mA VCC = 5.0 V, 2, 4 INT0, INT1, INT2, INT3, SCK 1, SI1, SCK 2, SI2, EVNB, EVND Input low voltage VIL INT0, INT1, INT2, INT3, SCK 1, SI1, SCK 2, SI2, EVNB, EVND Output high VOH voltage SCK 2, SO2, TOB, TOC, TOD Output low VOL voltage SCK 1, SO1, SCK 2, SO2, TOB, TOC, TOD I/O leakage | IIL | current RESET, STOPC, INT0, INT1, INT2, INT3, SCK 1, SI1, SCK 2, SI2, SO1, SO2, EVNB, EVND, OSC1, TOB, TOC, TOD ICC1 Current dissipation in active mode VCC ICC2 VCC fOSC = 4 MHz -- 0.6 1.8 mA VCC = 3.0 V, fOSC = 800 kHz 112 2, 4 HD404449 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Current dissipation in standby mode ISBY1 VCC -- 1.2 3 mA VCC = 5.0 V, 3, 4 fOSC = 4 MHz ISBY2 VCC -- 0.2 0.7 mA VCC = 3.0 V, 3, 4 fOSC = 800 kHz Current dissipation in subactive mode ISUB VCC -- 35 70 A VCC = 3.0 V, 5 32-kHz oscillator -- 70 150 A VCC = 3.0 V, 6 32-kHz oscillator Current dissipation in watch mode IWTC Current dissipation in stop mode ISTOP VCC -- 8 15 A VCC = 3.0 V, 7 32-kHz oscillator Stop mode retaining VSTOP voltage VCC -- 1 10 A VCC = 3.0 V, 7 no 32-kHz oscillator VCC 2 -- -- V No 32-kHz oscillator 8 Notes: 1. Output buffer current is excluded. 2. ICC1 and ICC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions:MCU: Reset Pins: RESET at VCC (VCC - 0.3 V to VCC) TEST at VCC (VCC - 0.3 V to VCC) 3. ISBY1 and ISBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (VCC - 0.3 V to VCC) 4. The current dissipation is in proportion to fOSC while the MCU is operating or is in active and standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 5. Applies to HD404448 and HD404449. 6. Applies to HD4074449. 7. These are the source currents when no I/O current is flowing. Test conditions:Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (VCC - 0.3 V to VCC) D13 (VPP ) at VCC (VCC - 0.3 V to VCC) for the HD4074449 8. RAM data retention. 113 HD404449 Series I/O Characteristics for Standard Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = - 20C to +75C; HD4074449: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH D10-D13 , 0.7VCC -- VCC + 0.3 V -- Input low voltage VIL -0.3 -- 0.3VCC V -- Output high voltage VOH VCC - 1.0 -- -- V -IOH = 0.5 mA Output low voltage VOL -- -- 0.4 V IOL = 0.4 mA I/O leakage current IIL -- -- 1 A Vin = 0 V to VCC 1, 2 -- -- 1 A Vin = 0 V to VCC 1, 3 D13 -- -- 1 A Vin = VCC - 0.3 V to VCC 1, 3 D13 -- -- 20 A Vin = 0 V to 0.3 V D10, D11 , 5 30 90 A R0-RC D10-D13 , R0-RC D10, D11 , R0-RC D10, D11 , R0-RC D10-D13 , R0-RC D10-D12 , R0-RC Pull-up MOS -IPU current R0-RC Notes: 1. Output buffer current is excluded. 2. Applies to HD404448 and HD404449. 3. Applies to HD4074449. 114 VCC = 3.0 V, Vin = 0 V 1, 3 HD404449 Series I/O Characteristics for High-Current Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D0-D9 0.7VCC -- VCC + 0.3 V -- Input low voltage VIL D0-D9 -0.3 -- 0.3VCC V -- Output high voltage VOH D0-D9 VCC - 1.0 -- -- V -IOH = 0.5 mA Output low voltage VOL D0-D9 -- -- 0.4 V IOL = 0.4 mA -- -- 2.0 V IOL = 15 mA, Notes VCC 4.5 V IIL D0-D9 -- -- 1 A Vin = 0 V to VCC Pull-up MOS current -IPU D0-D9 5 30 90 A VCC = 3.0 V, I/O leakage current 1 Vin = 0 V Notes: 1. Output buffer current is excluded. A/D Converter Characteristics (HD404448, HD404449: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Min Typ Analog power voltage AVCC AVCC VCC - 0.3 VCC Analog input voltage AVin AN0-AN3 AVSS Current between AVCC and AVSS IAD -- Analog input capacitance Max Unit Test Condition Notes VCC + 0.3 V -- 1 -- AVCC V -- -- 50 150 A VCC = AVCC = 5.0 V CAin AN0-AN3 -- 15 -- pF -- Resolution -- -- 8 8 8 Bit Number of inputs -- -- 0 -- 4 Channel -- Absolute accuracy -- -- -- -- 2.0 LSB Ta = 25C, VCC = 4.5 V to 5.5 V Conversion time -- -- 34 Input impedance -- AN0-AN3 1 -- 67 tcyc -- -- -- M fOSC = 1 MHz, Vin = 0 V Note: 1. AVCC 2.7 V 115 HD404449 Series AC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Clock oscillation frequency fOSC OSC1, OSC2 0.4 4.0 MHz 1/4 division 1 X1, X2 -- 32.768 -- kHz -- tcyc -- 1.0 -- 10 s -- tsubcyc -- -- 244.14 -- s 32-kHz oscillator, Instruction cycle time 1 1/8 division -- 122.07 -- s 32-kHz oscillator, 1/4 division Oscillation stabilization time (ceramic) tRC OSC1, OSC2 -- -- 7.5 ms HD404448, HD404449 VCC=3.0 to 6.0V HD4074449 VCC=3.5 to 5.5V 2 Oscillation stabilization time (crystal) tRC OSC1, OSC2 -- -- 40 ms -- 2 -- -- 60 ms -- 2 X1, X2 -- -- 3 s Ta = -10C to +60C 3 External clock high tCPH width OSC1 105 -- -- ns -- 4 External clock low tCPL width OSC1 105 -- -- ns -- 4 External clock rise tCPr time OSC1 -- -- 20 ns -- 4 External clock fall time OSC1 -- -- 20 ns -- 4 INT0-INT3, EVNB, tIH EVND high widths INT0-INT3, 2 -- -- tcyc / -- 5 INT0-INT3, EVNB, tIL EVND low widths INT0-INT3, -- 5 RESET high width tRSTH RESET 2 -- -- tcyc -- 6 STOPC low width tSTPL STOPC 1 -- -- tRC -- 7 RESET fall time tRSTf RESET -- -- 20 ms -- 6 STOPC rise time tSTPr STOPC -- -- 20 ms -- 7 116 tCPf EVNB, EVND tsubcyc 2 -- -- EVNB, EVND tcyc / tsubcyc HD404449 Series Item Symbol Pin(s) Input capacitance Cin Min Typ Max Unit Test Condition All pins except D13 -- -- 15 pF f = 1 MHz, V in = 0 V D13 -- 15 pF HD404448, -- Notes HD404449: f = 1 MHz, Vin = 0 V -- -- 180 pF HD4074449: f = 1 MHz, Vin = 0 V Notes: 1. If the 32.768-kHz oscillator is used for the subsystem oscillator, fOSC must be set as 0.4 MHz fOSC 1.0 MHz or 1.6 MHz fOSC 4.0 MHz, and bit 1 of the system clock selector register (SSR: $029) must be set to 0 or 1, respectively. 2. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) according to the system oscillation of the oscillation stabilization time. 3. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when the 32-kHz oscillator stops in stop mode and stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. Refer to figure 94. 5. Refer to figure 95. The tcyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. 6. Refer to figure 96. 7. Refer to figure 97. 117 HD404449 Series Serial Interface Timing Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = - 20C to +75C; HD4074449: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output Item Symbol Pin Transmit clock cycle time tScyc Transmit clock high width Transmit clock low width Typ Max Unit Test Condition SCK 1, SCK 2 1.0 -- -- tcyc Load shown in figure 99 1 tSCKH SCK 1, SCK 2 0.5 -- -- tScyc Load shown in figure 99 1 tSCKL SCK 1, SCK 2 0.5 -- -- tScyc Load shown in figure 99 1 Transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 200 ns Load shown in figure 99 1 Transmit clock fall time SCK 1, SCK 2 -- -- 200 ns Load shown in figure 99 1 Serial output data delay tDSO time SO1, SO2 -- -- 500 ns Load shown in figure 99 1 Serial input data setup time tSSI SI1, SI2 300 -- -- ns -- 1 Serial input data hold time tHSI SI1, SI2 300 -- -- ns -- 1 Min Typ Max Unit Test Condition Note Note: tSCKf Min Note 1. Refer to figure 98. During Transmit Clock Input Item Symbol Pin Transmit clock cycle time tScyc SCK 1, SCK 2 1.0 -- -- tcyc -- 1 Transmit clock high width tSCKH SCK 1, SCK 2 0.5 -- -- tScyc -- 1 Transmit clock low width tSCKL SCK 1, SCK 2 0.5 -- -- tScyc -- 1 Transmit clock rise time tSCKr SCK 1, SCK 2 -- -- 200 ns -- 1 Transmit clock fall time SCK 1, SCK 2 -- -- 200 ns -- 1 Serial output data delay tDSO time SO1, SO2 -- -- 500 ns Load shown in figure 99 1 Serial input data setup time tSSI SI1, SI2 300 -- -- ns -- 1 Serial input data hold time tHSI SI1, SI2 300 -- -- ns -- 1 Note: 118 tSCKf 1. Refer to figure 98. HD404449 Series 1/fCP OSC1 VCC - 0.3 V 0.3 V tCPL tCPH tCPr tCPf Figure 94 External Clock Timing INT0 to INT3, EVNB, EVND 0.9VCC 0.1VCC tIH tIL Figure 95 Interrupt Timing RESET 0.9VCC 0.1VCC tRSTH tRSTf Figure 96 Reset Timing STOPC 0.9VCC tSTPL 0.1VCC tSTPr Figure 97 STOPC Timing 119 HD404449 Series t Scyc t SCKf SCK 1 VCC - 2.0 V (0.9VCC )* 0.4 V (0.1VCC)* SCK 2 t SCKr t SCKL t SCKH t DSO VCC - 0.5 V 0.4 V SO1 SO2 t SSI t HSI 0.9V CC 0.1VCC SI1 SI2 Note: * VCC - 2.0 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input. Figure 98 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k 1S2074 H or equivalent Figure 99 Timing Load Circuit 120 HD404449 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404449). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a16-kword version. This limitation applies when using an EPROM or a data base. ROM 8-kword version: HD404448 Address $2000-$3FFF $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF Fill this area with 1s 121 HD404449 Series HD404448, HD404449 Option List Please check off the appropriate applications and enter the necessary information. Date of order Customer 1. ROM size Department HD404448 8-kword Name HD404449 16-kword ROM code name LSI number HD40444 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4. Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop mode Used Not used 6. Package FP-80A TFP-80F 122 HD404459 Series Rev. 5.0 March 1997 Description The HD404459 Series is a member of the 4-bit HMCS400-series microcomputers with large-capacity memory and architecture providing high program productivity. Each microcomputer has a 32-kHz oscillator for clock, low-voltage (1.8 V) operating mode, and four low-power dissipation modes. The HD404459 Series includes three chips: the HD404458 with an 8-kword ROM; the HD404459 with a 16-kword ROM; and the HD4074459 with a 16-kword PROM (ZTATTM version). The HD4074459 is a PROM version (ZTATTM microcomputer). A program can be written to the PROM by a PROM writer, thus dramatically shortening system development periods and turnaround time (ZTAT TM versions are 27256-compatible). ZTAT TM: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd. Features * 8,192-word x 10-bit ROM (HD404458) 16,384-word x 10-bit ROM (HD404459 and HD4074459) * 512-digit x 4-bit RAM (HD404458) 768-digit x 4-bit RAM (HD404459 and HD4074459) * 56 I/O pins, including seven input pins * Four timer/counters * 1-channel x 8-bit input capture circuit * Three timer outputs (including two PWM outputs) * Two event counter inputs (including one double-edge function) * 8-bit clock-synchronous serial interface * Eight wakeup inputs * Four-channel voltage comparator (external or internal reference power supply can be selected) * Built-in oscillators Main clock: 4-MHz ceramic or crystal oscillator (an external clock is also possible) Subclock: 32.768-kHz crystal HD404459 Series * Ten interrupt sources Five by external sources, including two double-edge function Five by internal sources * Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes (transition time shortened) Stop mode Standby mode Watch mode Subactive mode (optional) * One external input for transition from stop mode to active mode * Instruction cycle time For HD404458/HD404459: 1, 2, 4, 8 s (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio) For HD4074459: 1, 2, 4, 8 s (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.7 V or higher) 2, 4, 8, 16 s (fOSC = 2 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.2 V or higher) * Two general operating conditions MCU or PROM mode for HD4074459 MCU mode only for HD404458/HD404459 Ordering Information Type Product Name Model Name ROM (Words) RAM (Digits) Package Mask ROM HD404458 HD404458H 8,192 512 64-pin plastic QFP (FP-64A) HD404459 HD404459H 16,384 768 64-pin plastic QFP (FP-64A) HD4074459 HD4074459H 16,384 768 64-pin plastic QFP (FP-64A) ZTATTM 2 HD404459 Series 49 50 51 52 53 54 55 56 57 58 59 60 61 62 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 FP-64A 9 40 32 31 30 29 28 27 26 25 24 33 23 34 16 22 35 15 21 36 14 20 37 13 19 38 12 18 39 11 17 10 R53 (WU3) R52 (WU2) R51 (WU1) R50 (WU0) R43/SO R42/SI R41/SCK R40/EVND R33/EVNB R32/TOD R31/TOC R30/TOB R23 R22 R21 R20 D5 D6 D7 D8 D9 D10 D11/STOPC VCC R00/INT0 R01/INT1 R02/INT2 R03/INT3 R10 R11 R12 R13 RA0/COMP0 RA1/COMP1 RA2/COMP2 RA3/COMP3 TEST OSC1 OSC2 GND X2 X1 RESET D0 D1 D2 D3 D4 63 64 R93/VCref R92 R91 R90 R83 R82 R81 R80 R73 R72 R71 R70 R63 (WU7) R62 (WU6) R61 (WU5) R60 (WU4) Pin Arrangement 3 HD404459 Series Pin Description Pin Number Item Symbol Power supply VCC FP-64A I/O Function 24 Power voltage GND 8 Ground Test TEST 5 I Used for factory testing only: Connect this pin to VCC Reset RESET 11 I Resets the MCU Oscillator OSC1 6 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic, crystal, or connect only OSC1 to an external oscillator circuit OSC2 7 O X1 10 I X2 9 O D0-D9 12-21 I/O Input/output pins addressable by individual bits D10, D11 22, 23 I Input pins addressable by individual bits R00-R93 25-64 I/O Input/output pins addressable in 4-bit units. The R9 3 port is an input-only pin. RA0-RA3 1-4 I Input pins addressable in 4-bit units INT0, INT1, 25-28, 45-52 I Input pins for external interrupts Ports Interrupts Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to VCC and leave the X2 pin open. INT2, INT3, WU0-WU7 Stop clear STOPC 23 I Input pin for transition from stop mode to active mode Serial interface SCK 42 I/O Serial clock input/output pin SI 43 I Serial receive data input pin SO 44 O Serial transmit data output pin TOB, TOC, 37-39 O Timer output pins 40, 41 I Event count input pins 1-4 I Analog input pins for voltage comparator 64 I Standard voltage pin for inputting the threshold voltage of analog input pins Timers TOD EVNB, EVND Voltage comparator COMP0 - COMP3 VCref 4 HD404459 Series RESET TEST STOPC OSC 1 OSC 2 X1 X2 VCC GND Block Diagram System control External interrupt W (2 bits) Timer A TOC Timer C EVND TOD Timer D SI SO SCK Serial interface VCref COMP0 COMP1 COMP2 COMP3 Comparator SPX (4 bits) Y (4 bits) Internal address bus Timer B X (4 bits) Internal data bus EVNB TOB D port RAM (512 x 4 bits) (768 x 4 bits) SPY (4 bits) ALU CPU ST CA (1 bit) (1 bit) A (4 bits) B (4 bits) SP (10 bits) Instruction decoder PC (14 bits) RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port INT 0 INT 1 INT 2 INT 3 WU0 to WU7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RA 0 RA 1 RA 2 RA 3 ROM (8,192 x 10 bits) (16,384 x 10 bits) 5 HD404459 Series Memory Map ROM Memory Map See the ROM memory map of figure 1. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF for HD404458, $0000-$3FFF for HD404459/HD4074459): Used for program coding. $0000 $0000 Vector address JMPL instruction $0001 (jump to RESET, STOPC routine) $0002 $000F $0010 $0003 $0004 Zero-page subroutine (64 words) $003F $0040 $0005 $0006 $0007 $0008 Pattern (4,096 words) $0009 $000A $000B $0FFF $1000 $000C $000D HD404458 program (8,192 words) $000E $000F $1FFF $2000 HD404459, HD4074459 program (16,384 words) $3FFF Figure 1 ROM Memory Map 6 JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer D routine) JMPL instruction (jump to timer A, INT2 routine) JMPL instruction (jump to timer B, INT3 routine) JMPL instruction (jump to timer C, serial routine) JMPL instruction (jump to wakeup routine) HD404459 Series RAM Memory Map The HD404458 MCU contains a 512-digit x 4-bit RAM area. The HD404459 and HD4074459 MCUs contain 768-digit x 4-bit RAM areas. Both of these RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space labeled as the RAM-mapped register area. See the RAM memory map of figure 2. RAM-Mapped Register Area ($000-$03F): * Interrupt control bits area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. For limitations on using the instructions, refer to figure 4. * Special function register area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, and as data control registers for I/O ports. See figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register flag area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. For limitations on using the instructions, refer to figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). See figure 6. Data Area ($050-$1FF for HD404458, $050-$2FF for HD404459/HD4074459) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. See figure 6 for the data to be saved and the save conditions. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area can be used for data storage. 7 HD404459 Series 0 $000 RAM-mapped register 64 Memory register (MR) $040 $050 80 HD404458 Data (432 digits) 512 $200 HD404459, HD4074459 Data (688 digits) 768 $300 Not used 960 $3C0 Stack (64 digits) 1023 $3FF Note: * Two registers are mapped onto the same address ($00A, $00B, $00E, $00F, $011, and $012). R: Read only W: Write only R/W: Read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Interrupt control bits area (PMRA) (SMRA) (SRL) (SRU) (TMA) (TMB1) (TRBL/TWBL) Timer B (TRBU/TWBU) (MIS) Miscellaneous register (TMC1) Timer mode register C1 (TRCL/TWCL) Timer C (TRCU/TWCU) (TMD1) Timer mode register D1 (TRDL/TWDL) Timer D (TRDU/TWDU) (TMB2) Timer mode register B2 (TMC2) Timer mode register C2 (TMD2) Timer mode register D2 (CCR) Comparator control register (CER) Comparator enable register (WSR) Wakeup select register Port mode register A Serial mode register A Serial data register lower Serial data register upper Timer mode register A Timer mode register B1 Not used Register flag area Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register B System clock select register 1 System clock select register 2 Not used Port D0 to D3 DCR Port D4 to D7 DCR Port D8 to D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR (PMRB) (PMRC) (ESR1) (ESR2) (SMRB) (SSR1) (SSR2) W W W W W W W (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) W W W W W W W W W W Not used 10 Timer read register B lower (TRBL) 11 Timer read register B upper (TRBU) R R Timer write register B lower (TWBL) Timer write register B upper (TWBU) W W $00A $00B 14 Timer read register C lower (TRCL) 15 Timer read register C upper (TRCU) R R Timer write register C lower (TWCL) Timer write register C upper (TWCU) W W $00E $00F 17 Timer read register D lower (TRDL) 18 Timer read register D upper (TRDU) R R Timer write register D lower (TWDL) Timer write register D upper (TWDU) W W $011 $012 Figure 2 RAM Memory Map 8 W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R/W R $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F * HD404459 Series Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTD (IM of timer D) IFTD (IF of timer D) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMTB (IM of timer B) IFTB (IF of timer B) IMTA (IM of timer A) IFTA (IF of timer A) $002 3 IMWU (IM of wakeup) IFWU (IF of wakeup) IMTC (IM of timer C) IFTC (IF of timer C) $003 Register flag area Bit 3 Bit 2 Bit 1 Bit 0 32 DTON (Direct transfer on flag) CMSF (Comparator start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $020 33 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $021 34 IM3 (IM of INT3) IF3 (IF of INT3) IM2 (IM of INT2) IF2 (IF of INT2) $022 35 Not used Not used IMS (IM of serial) IFS (IF of serial) $023 IF: Interrupt request flag IM: Interrupt mask SP: Stack pointer Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM LSON IF ICSF ICEF RAME RSP WDON CMSF DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for CMSF during comparator operation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes undefined. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 9 HD404459 Series Bit 3 Bit 2 Bit 1 Bit 0 $000 Interrupt control bits area $003 PMRA $004 SMRA $005 SRL $006 Not used Timer-A/timer-base Serial data register (upper digit) Clock source selection (timer A) Clock source selection (timer B) Auto-reload on/off TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL$00E R4 3 /SO Serial data register (lower digit) SRU $007 TMA $008 TMB1 $009 R42/SI Serial transmit clock speed selection Not used R41/SCK Timer B register (lower digit) Timer B register (upper digit) Pull-up MOS control Auto-reload on/off SO PMOS control Interrupt frame period selection Clock source selection (timer C) Timer C register (lower digit) TRCU/TWCU $00F TMD1 $010 Auto-reload on/off TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 Not used Not used Input capture selection Timer C register (upper digit) CCR $016 CER $017 Voltage comparison result WSR $018 WU7 enable Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer B output mode selection Not used Timer C output mode selection Timer D output mode selection Internal reference voltage level selection Reference power supply selection COMP0 to COMP3 selection WU6 enable WU5 to WU4 enable WU3 to WU0 enable Not used $020 Register flag area $023 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SMRB $028 SSR1 $029 SSR2 $02A R03 /INT 3 R02 /INT 2 R01 /INT 1 Not used D11 /STOPC INT 3 detection edge selection EVND detection edge selection Not used 32-kHz oscillation stop Not used R00 /INT 0 R40 /EVND R33 /EVNB INT 2 detection edge selection Not used Not used Not used SO output level control in idle states Serial clock source selection Not used 32-kHz oscillation division ratio selection 32-kHz oscillation sampling selection OSC division ratio selection Not used Not used DCD0 $02C DCD1 $02D DCD2 $02E Port D3 DCR Port D7 DCR Port D2 DCR Port D6 DCR Not used Not used DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR5 $035 DCR6 $036 DCR7 $037 DCR8 $038 DCR9 $039 Port R0 3 DCR Port R1 3 DCR Port D1 DCR Port D5 DCR Port D9 DCR Port D0 DCR Port D4 DCR Port D8 DCR Port R0 2 DCR Port R1 2 DCR Port R2 2 DCR Port R0 1 DCR Port R1 1 DCR Port R2 1 DCR Port R0 0 DCR Port R1 0 DCR Port R2 0 DCR Port R3 2 DCR Port R4 2 DCR Port R3 1 DCR Port R4 1 DCR Port R3 0 DCR Port R4 0 DCR Port R5 2 DCR Port R6 2 DCR Port R7 2 DCR Port R8 2 DCR Port R5 1 DCR Port R6 1 DCR Port R7 1 DCR Port R8 1 DCR Port R5 0 DCR Port R6 0 DCR Port R7 0 DCR Port R8 0 DCR Port R9 2 DCR Port R9 1 DCR Port R9 0 DCR Not used Port R2 3 DCR Port R3 3 DCR Port R4 3 DCR Port R5 3 DCR Port R6 3 DCR Port R7 3 DCR Port R8 3 DCR Not used Not used $03F Figure 5 Special Function Register Area 10 HD404459 Series Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC 12 PC11 $3FC 1021 PC 10 PC9 PC 8 PC7 $3FD 1022 CA PC6 PC 5 PC4 $3FE 1023 PC 3 PC2 PC 1 PC0 $3FF PC13 -PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position 11 HD404459 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations (figure 7). 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status Initial value: 1, no R/W 0 (SPX) 3 0 (SPY) 0 (CA) 0 (ST) 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. 12 HD404459 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF also by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. See table 1 for initial values after MCU reset. Interrupts The MCU has 10 interrupt sources: four external signals (INT0 , INT1, INT2, INT 3), four timer/counters (timers A, B, C, and D), serial interface, and wakeup. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer A and INT2, timer B and INT3, timer C and serial interface. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. 13 HD404459 Series Refer to figure 8 for the block diagram of the interrupt control circuit, table 2 for interrupt priorities and vector addresses, and table 3 for interrupt processing conditions for the 10 interrupt sources. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. For the interrupt processing sequence, see figure 9, and figure 10 for an interrupt processing flowchart. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. 14 HD404459 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag flags/mask (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0, DCD1) All bits 0 Turns output buffer off (to high impedance) (DCD2) - - 00 (DCR0- DCR8) All bits 0 (DCR9) - 000 Port mode register A (PMRA) - - 00 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of port mode register B I/O Timers/ counters, serial interface Contents Port mode register C bits (PMRC1, 00 1, 0 PMRC0) Refer to description of port mode register C Detection edge select register 1 (ESR1) 0000 Disables edge detection Detection edge select register 2 (ESR2) 00 - - Disables edge detection Timer mode register A (TMA) 0000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2 Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register A (SMRA) 0000 Refer to description of serial mode register A Serial mode register B (SMRB) - - 00 Refer to description of serial mode register B 15 HD404459 Series Abbr. Initial Value Contents Prescaler S (PSS) $000 -- Prescaler W (PSW) $00 -- Timer counter A (TCA) $00 -- Timer counter B (TCB) $00 -- Timer counter C (TCC) $00 -- Timer counter D (TCD) $00 -- Timer write register B (TWBU, TWBL) $X0 -- Timer write register C (TWCU, TWCL) $X0 -- Timer write register D (TWDU, TWDL) $X0 -- 000 -- (WSR) 0000 -- Voltage Comparator enable comparator register (CER) 0000 -- Comparator control register (CCR) 0000 -- (LSON) 0 Refer to description of operating modes Item Timers/ counters, serial interface Octal counter I/O Wakeup set register Bit register Low speed on flag Others Watchdog timer on flag (WDON) 0 Refer to description of timer C Comparator start flag (CMSF) 0 Refer to description of voltage comparator Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes, and oscillator circuit System clock select register 1 bits 2, 1 (SSR12- 00 SSR11) Refer to description of operating modes, and oscillator circuit System clock select register 2 (SSR2) Switches OSC division ratio - - 00 Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. 16 HD404459 Series Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Status After Status After Cancellation of Stop Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Status After all Other Types of Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 0 Port mode register C bit 2 (PMRC) Pre-stop-mode values are retained 0 0 System clock select (SSR13) register1 bit 3 Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* -- $0000 INT0 1 $0002 INT1 2 $0004 Timer D 3 $0006 Timer A, INT2 4 $0008 Timer B, INT3 5 $000A Timer C, serial 6 $000C Wakeup 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 17 HD404459 Series $000,0 Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address IE $000,2 INT0 interrupt IF0 $000,3 IM0 Vector address Priority control PLA $001,0 INT1 interrupt IF1 $001,1 IM1 $001,2 Timer D interrupt IFTD $001,3 IMTD Timer A interrupt Timer B interrupt Timer C interrupt $002,0 $022,0 IFTA IF2 $002,1 $022,1 IMTA IM2 $002,2 $022,2 IFTB IF3 $002,3 $022,3 IMTB IM3 $003,0 $023,0 IFTC IFS $003,1 $023,1 IMTC IMS $003,2 Wakeup interrupt IFWU $003,3 IMWU Figure 8 Interrupt Control Circuit 18 INT2 interrupt INT3 interrupt Serial interrupt HD404459 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer D Timer A or Timer B or Timer C or INT3 Serial Wakeup INT2 IE 1 1 1 1 1 1 1 IF0 * IM0 1 0 0 0 0 0 0 IF1 * IM1 * 1 0 0 0 0 0 IFTD * IMTD * * 1 0 0 0 0 IFTA * IMTA * * * 1 0 0 0 * * * * 1 0 0 * * * * * 1 0 * * * * * * 1 + IF2 * IM2 IFTB * IMTB + IF3 * IM3 IFTC * IMTC + IFS * IMS IFWU * IMWU Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 9 Interrupt Processing Sequence 19 HD404459 Series Power on RESET = 1? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Execute instruction Interrupt accept PC (PC) + 1 IE 0 Stack (PC) Stack (CA) Stack (ST) PC $0002 Yes INT0 interrupt? No PC $0004 Yes INT1 interrupt? No PC $0006 Yes Timer D interrupt? No PC $0008 Yes Timer-A/INT2 interrupt? No PC $000A Yes Timer-B/INT 3 interrupt? No PC $000C Yes Timer-C/serial interrupt? No PC $000E Figure 10 Interrupt Processing Flowchart 20 (wakeup interrupt) HD404459 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction. Refer to table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0 , INT1, INT2, INT3, WU0-WU7): Five external interrupt signals. External Interrupt Request Flags (IF0, IF1, IF2, IF3, IFWU: $000, $001, $003, $022): IF0, IF1, and IFWU are set at the falling edge of input signals, and IF2 and IF3 are set at the rising or falling edge or both rising and falling edges of input signals (table 5). INT2 and INT3 interrupt edges are selected by the detection edge select register (ESR1: $026) (figure 11). Table 5 External Interrupt Request Flags (IF0-IF3, IFWU: $000, $001, $003, $022) IF0-IF3, IFWU Interrupt Request 0 No 1 Yes Detection edge selection register 1 (ESR1: $026) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W ESR13 ESR12 ESR11 ESR10 Bit name INT3 detection edge ESR13 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 INT2 detection edge ESR11 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 11 Detection Edge Selection Register 1 (ESR1) 21 HD404459 Series External Interrupt Masks (IM0, IM1, IM2, IM3, IMWU: $000, $001, $003, $022): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags (table 6). Table 6 External Interrupt Masks (IM0-1M3, IMWU: $000, $001, $003, $022) IM0-IM3, IMWU Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $002, Bit 0): Set by overflow output from timer A (table 7). Table 7 Timer A Interrupt Request Flag (IFTA: $002, Bit 0) IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer A interrupt request flag (table 8). Table 8 Timer A Interrupt Mask (IMTA: $002, Bit 1) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 2): Set by overflow output from timer B (table 9). Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 2) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer B interrupt request flag (table 10). Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 3) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) 22 HD404459 Series Timer C Interrupt Request Flag (IFTC: $003, Bit 0): Set by overflow output from timer C (table 11). Table 11 Timer C Interrupt Request Flag (IFTC: $003, Bit 0) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer C interrupt request flag (table 12). Table 12 Timer C Interrupt Mask (IMTC: $003, Bit 1) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) Timer D Interrupt Request Flag (IFTD: $001, Bit 2): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used (table 13). Table 13 Timer D Interrupt Request Flag (IFTD: $001, Bit 2) IFTD Interrupt Request 0 No 1 Yes Timer D Interrupt Mask (IMTD: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer D interrupt request flag (table 14). Table 14 Timer D Interrupt Mask (IMTD: $001, Bit 3) IMTD Interrupt Request 0 Enabled 1 Disabled (masked) 23 HD404459 Series Serial Interrupt Request Flags (IFS: $023, Bit 0): Set when data transfer is completed or when data transfer is suspended (table 15). Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 0) IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $023, Bit 1): Prevents (masks) an interrupt request caused by the serial interrupt request flag (table 16). Table 16 Serial Interrupt Mask (IMS: $023, Bit 1) IMS Interrupt Request 0 Enabled 1 Disabled (masked) Wakeup Interrupt Request Flag (IFWU: $003, Bit 2): Set by the falling edge of signals input to wakeup (table 17). Table 17 Wakeup Interrupt Request Flag (IFWU: $003, Bit 2) IFWU Interrupt Request 0 No 1 Yes Wakeup Interrupt Mask (IMWU: $003, Bit 3): Prevents (masks) an interrupt request caused by the wakeup interrupt request flag (table 18). Table 18 Wakeup Interrupt Mask (IMWU: $003, Bit 3) IMWU Interrupt Request 0 Enabled 1 Disabled (masked) 24 HD404459 Series Wakeup Function: Detects the falling edge of wakeup input signals and sets the wakeup interrupt request flag (IFWU: $003, bit 2). Refer to figure 12 for a block diagram showing the wakeup interrupt. The wakeup select register (WSR: $018) can select from one to eight wakeup inputs (WU0-WU 7) (figure 13). The wakeup function can operate in any mode other than stop mode. When the wakeup interrupt is received, the CPU generates an independent vector address ($000E). Note: The wakeup select register (WSR: $018) controls whether the wakeup input is to be valid or invalid, but it can not switch the pin inputs between the R ports and wakeup. When using the pins only as R ports, nullify wakeup input or set the wakeup interrupt mask (IMWU: $003, bit 3). R50/WU0 R51/WU1 R52/WU2 R53/WU3 Falling-edge detection R60/WU4 Wakeup interrupt request flag R61/WU5 R62/WU6 R63/WU7 4 WSR (4 bits) Wakeup selection register 4 Internal bus Figure 12 Wakeup Interrupt 25 HD404459 Series Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W WSR3 WSR2 WSR1 WSR0 WSR0 WU0 to WU3 control 0 Invalid 1 Valid WSR1 WU4 to WU5 control 0 Invalid 1 Valid WSR2 WU6 control 0 Invalid 1 Valid WSR3 WU7 control 0 Invalid 1 Valid Figure 13 Wakeup Select Register (WSR) 26 HD404459 Series Operating Modes The MCU has five operating modes (table 19). Refer to tables 20 and 21 for the operations in each mode, and figure 14 for the transitions between operating modes. Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Table 19 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive*2 SBY instruction STOP STOP Activation method RESET instruction when instruction when cancellation, TMA3 = 0 TMA3 = 1 interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) INT0, timer A or wakeup interrupt request from watch mode Status System oscillator OP OP Stopped Stopped Stopped Subsystem OP oscillator OP OP*1 OP OP Cancellation method RESET input, STOP/SBY instruction RESET input, RESET input, RESET input, RESET input, interrupt request STOPC input in INT0, timer A or STOP/SBY stop mode wakeup interrupt instruction request Note: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR1 : $029). 2. Subactive mode is an optional function; specify it on the function option list. 27 HD404459 Series Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Timer D Reset Stopped OP OP Stopped* OP OP Stopped OP Stopped Retained Retained SCI Reset Comparator Reset I/O 3 1 Reset* Note: OP implies in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function to be specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. However, all interrupts stop. Table 21 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode, Watch Mode Stop Mode Active Mode, Subactive Mode D0-D9 Retained High impedance Input enabled D10-D11 -- -- Input enabled R0-R8 Retained or output of peripheral functions High impedance Input enabled -- -- Input enabled R90, R91, R92 R93, RA 28 HD404459 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RAME = 1 RESET1 PC O ST Active mode Standby mode STOPC RESET2 Oscillate Oscillate Stop fcyc fcyc SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop Stop Stop P O ST fOSC: fX: o CPU: o CLK: o PER: fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR13 = 1) STOP fOSC: fX: o CPU: o CLK: o PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fW fcyc SBY Interrupt Main oscillation frequency Suboscillation frequency for time-base fOSC/4, fOSC/8, fOSC/16, fcyc: fOSC/32 (software selectable) fW: fX/8 fX/8 or fX/4 fSUB: (software selectable) o CPU: System clock o CLK: Clock for time-base o PER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag fOSC: fX: fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fW fcyc STOP INT0, WU0 to WU7, timer A*1 *2 Subactive mode fOSC: fX: o CPU: o CLK: o PER: (TMA3 = 1, LSON = 0) Notes: 1. 2. 3. 4. Stop Oscillate Stop fW Stop ST OP *3 Stop Oscillate fSUB fW fSUB fOSC: fX: o CPU: o CLK: o PER: *4 INT0, WU0 to WU7 , timer A*1 (TMA3 = 1, LSON = 1) fOSC: fX: o CPU: o CLK: o PER: Stop Oscillate Stop fW Stop Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1) Figure 14 MCU Status Transitions 29 HD404459 Series Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode since the CPU halts. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by RESET input or an interrupt request. If it is terminated by RESET, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. See figure 15 for the flowchart of operation in standby mode. Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop No Watch Standby Stop RESET = 1? Yes Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop RESET = 1? No Yes IF0 * IM0 = 1? No No STOPC = 0? Yes IF1 * IM1 = 1? No Yes Yes No IFTD * IMTD = 1? Yes RAME = 1 IFTA * IMTA + IF2 * IM2 = 1? RAME = 0 Yes* No IFTB * IMTB + IF3 * IM3 = 1? Yes No IFTC * IMTC + IFS * IMS = 1? No Yes IFWU * IMWU = 1? (SBY only) (SBY only) (SBY only) Restart processor clocks Execute next instruction No Reset MCU Accept interrupt Figure 15 MCU Operation Flowchart 30 Yes Restart processor clocks IF = 1, IM = 0, and IE = 1? Yes Execute next instruction (SBY only) No Note: * The INT2 interrupt is valid only by standby mode cancellation. , HD404459 Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC 2 oscillator stops. Operation of the X1 and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR1: $029; operating: SSR13 = 0, stop: SSR13 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is terminated by RESET input or STOPC input (figure 16). RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres tRC (stabilization period) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operate but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and is also convenient when only clock display is used. In this mode, the OSC1 and OSC 2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input, timer A interrupt request, INT0 interrupt request, or wakeup interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer A interrupt request, an INT0 nterrupt request, or wakeup interrupt request, the MCU enters active mode if LSON is 0 or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT0 interrupt, as shown in figure 17. Operation during mode transition is the same as that at standby mode cancellation (figure 15). 31 HD404459 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) T t RC Tx Interrupt frame length T: t RC : Oscillation stabilization period T + t RC < Tx < 2T + t RC Figure 17 Interrupt Frame Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the voltage comparator operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, o CLK is applied to timer A and the INT0 and WU0-WU 7 circuits. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, a timer A/ INT0 wakeup interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 and WU0-WU7 signals is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. 32 HD404459 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 39. MIS1 MIS0 0 0 T *1 tRC *1 0.24414 ms 0.12207 ms Oscillation circuit conditions External clock input 0.24414 ms*2 1 1 15.625 ms 0 125 ms 1 Not used 7.8125 ms 62.5 ms Ceramic or crystal oscillator -- Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: 1. Set LSON to 0 and DTON to 1 in subactive mode. 2. Execute the STOP or SBY instruction. 3. The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. The transition time (TD) from subactive mode to active mode is: tRC < TD < T + tRC 33 HD404459 Series STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T t RC Interrupt frame length T: t RC : Oscillation stabilization period Figure 19 Direct Transition Timing Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (i.e., when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: See figures 20 to 22 for the MCU operation sequences. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. 34 HD404459 Series Power on RESET = 1? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 20 MCU Operating Sequence (Power On) 35 HD404459 Series MCU operation cycle IF = 1? No Yes No IM = 0 and IE = 1? Yes Instruction execution Yes SBY, STOP instruction? IE 0 Stack (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC Next location PC Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 21 MCU Operating Sequence (MCU Operation Cycle) 36 HD404459 Series Low-power mode operation cycle IF = 1 and IM = 0? * No Yes Standby/Watch mode No IF = 1 and IM = 0? Yes Stop mode No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC Next Iocation PC Next Iocation Reset MCU Instruction execution MCU operation cycle Note: * For IF and IM operation, refer to figure 15. Figure 22 MCU Operating Sequence (Low-Power Mode Operation) 37 HD404459 Series Notes on Use: * When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 and WU0-WU 7 is shorter than the interrupt frame, INT 0 and WU0-WU 7 will not be detected. Also, if the low level period after the falling edge of INT0 and WU0-WU 7 is shorter than the interrupt frame, INT0 and WU0-WU 7 will not be detected. Edge detection is shown in figure 23. The level of the INT 0 and WU0-WU 7 signals are sampled by a sampling clock. When this sampled value changes from high to low, a falling edge is detected. In figure 24, the level of the INT0 and WU0-WU 7 signals are sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge will not be detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge will not be detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level periods of INT 0 and WU 0-WU 7 longer than interrupt frame. INT0, WU0-WU7 Sampling High Low Low Figure 23 Edge Detection INT0, WU0-WU7 INT0, WU0-WU7 Interrupt frame Interrupt frame A: Low B: Low a. High level period Figure 24 Sampling Example 38 A: High B: High b. Low level period HD404459 Series Internal Oscillator Circuit Clock Generation Circuit See figure 25 for a block diagram of the clock generation circuit. A ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2 (table 22). The system oscillator can also be operated by an external clock. Bit 1 (SSR11) of system clock select register 1 (SSR1: $029) must be selected according to the frequency of the oscillator connected to OSC1 and OSC2(figure 26). Note: If the system clock select register 1 (SSR1: $029) setting does not match the oscillator frequency, subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 OSC1 1/4, 1/8, System fOSC 1/16, or oscillator 1/32 division circuit*1 fX X1 X2 Subsystem oscillator fcyc tcyc Timing generator circuit CPU with ROM, RAM, registers, flags, and I/O oCPU System clock selection circuit oPER Peripheral function interrupt fSUB Timing 1/8 or 1/4 tsubcyc generator division circuit circuit*2 1/8 division circuit fW tWcyc Timing generator circuit TMA3 Time-base clock o CLK selection circuit Time-base interrupt Notes: 1. 1/4, 1/8, 1/16, or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock select register 2 (SSR2). 2. 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (SSR1). Figure 25 Clock Generation Circuit 39 HD404459 Series Selection of Division Ratio Division Ratio of the System Clock: 1/4, 1/8, 1/16, or 1/32 division ratio of the system clock can be selected by setting bits 0 and 1 (SSR20 and SSR21) of system clock select register 2 (SSR2: $02A). The values of SSR20 and SSR21 become valid when entering the watch mode after making the ratio selection. (However, the value of SSR2 becomes valid immediately after the selection.) Therefore, when changing the division ratio, the system clock must be stopped. There are two methods for selecting the division ratio of the system clock as follows. * Division ratio is selected by writing to SSR20 and SSR21 in active mode. The selected values of SSR20 and SSR21 are valid before the MCU enters watch mode. The division ratio of the system clock becomes the written value when the MCU returns to the active mode from the watch mode. * Division ratio is selected by writing to SSR20 and SSR21 in subactive mode. The division ratio of the system clock becomes the selected value when the MCU returns to active mode after entering watch mode. Note: SSR2 is cleared in the reset and stop modes. Therefore, 1/4 division ratio of the system clock is selected when the MCU returns from stop mode after reset. Division Ratio of the Subsystem Clock: 1/4 or 1/8 division ratio of the subsystem clock can be selected by setting bit 2 (SSR12) of system clock select register 1 (SSR1: $029). The value of SSR12 becomes valid immediately after the ratio selection. When the value of SSR12 is changed, the MCU must be in active mode. If the value of SSR12 is changed in subactive mode, the MCU may malfunction. 40 HD404459 Series System clock select register 1 (SSR1: $029) Bit 3 2 1 0 Initial value 0 0 0 -- Read/Write W W W -- SSR13* SSR12 Bit name SSR11 Not used SSR11 System oscillation frequency selection 0 1.6 to 4.0 MHz 1 0.4 to 1.0 MHz SSR12 32-kHz oscillation division ratio selection 0 fsub = fx/8 1 fsub = fx/4 SSR13 32-kHz oscillation stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode Note: * SSR13 is reset to 0 only by RESET input. When STOPC is input in stop mode, SSR13 is not reset but retains its value. SSR13 is not reset in stop mode. Figure 26 System Clock Select Register 1 (SSR1: $029) System clock select register 2 (SSR2: $02A) Bit 3 2 Initial value -- -- 0 0 Read/Write -- -- W W Bit name 1 0 Not used Not used SSR21 SSR20 SSR21 SSR20 0 0 1/4 1 1/8 0 1/16 1 1/32 1 System clock division ratio selection Figure 27 System Clock Select Register 2 (SSR2: $02A) 41 HD404459 Series RESET X1 X2 GND OSC2 OSC1 TEST GND Figure 28 Typical Layout of Crystal and Ceramic Oscillators 42 HD404459 Series Table 22 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator (OSC1, OSC2) Ceramic oscillator: CSA4.00MG (Murata) C1 Rf = 1 M 20% OSC1 Ceramic C1 = C2 = 30 pF Rf OSC2 C2 GND Rf = 1 M 20% C1 Crystal oscillator (OSC1, OSC2) C1 = C2 = 10-22 pF 20% OSC1 Crystal Crystal: Equivalent to circuit shown below Rf C0: 7 pF max. OSC2 RS: 100 max. C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Crystal: 32.768 kHz: MX38T X1 (Nippon Denpa Kogyo) C1 = C2 = 15 pF 5% Crystal RS: 14 k X2 C0: 1.5 pF C2 GND L CS RS X1 X2 C0 Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, X1, X2, and elements should be as short as possible, and must not cross other wiring (figure 28). 3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be open. 43 HD404459 Series Input/Output The MCU has 49 input/output pins (D0-D9, R0-R8, R90-R92) and 7 input pins (D 10, D11, R93, RA). The features are described as follows. * The D11, R0, R3-R6, R93, and RA pins are multiplexed with peripheral function pins such as those for timers or the serial interface. See table 24. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. However, pins input to the wakeup function are not switched. Only the valid/invalid statuses of wakeup input are controlled. * Peripheral function output pins are CMOS out-put pins. See table 23. Only the SO pin and R4 3 port can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are set at high-impedance. * Each input/output pin has a built-in pull-up MOS (figure 29), which can be individually turned on or off by software. 44 HD404459 Series Table 23 Programmable I/O Circuits MIS3 (Bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS -- -- -- On -- -- -- On NMOS -- -- On -- -- -- On -- -- -- -- -- -- On -- On CMOS buffer Pull-up MOS 1 1 0 1 Note: -- indicates off status. HLT Pull-up control signal VCC Pull-up MOS MIS3 VCC Buffer control signal DCD, DCR Output data PDR Input data Input control signal Figure 29 I/O Buffer Configuration 45 HD404459 Series Table 24 Circuit Configurations of I/O Pins I/O Pin Type Input/output pins Circuit Pins VCC VCC Pull-up control signal Buffer control signal HLT D0-D9, R00-R03, MIS3 R10-R13, R20-R23, DCD, DCR R30-R33, R40-R42, R50-R53, R60-R63, Output data PDR R70-R73, R80-R83, R90-R92 Input data Input control signal HLT VCC VCC Pull-up control signal Buffer control signal Output data R43 MIS3 DCR MIS2 PDR Input data Input control signal Input data Input pins D10, D11 , R93, RA0-RA3 Input control signal Peripheral function pins Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC Pull-up control signal Output data VCC SO MIS3 MIS2 SO HLT Pull-up control signal Output data 46 SCK SCK PMOS control signal VCC MIS3 HLT VCC SCK MIS3 TOB, TOC, TOD TOB, TOC, TOD HD404459 Series I/O Pin Type Peripheral function pins Input pins Circuit Pins SI, INT0, INT1, VCC HLT MIS3 PDR INT0, etc Input data STOPC INT2, INT3, WU0-WU7, EVNB, EVND STOPC Notes: 1. In stop mode, the MCU is reset and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes. D Port (D0-D 11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D 0-D 9 are input/output pins, and D10 and D11 are input-only pins. Pins D0-D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D11 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 30). Pin D11 is multiplexed with peripheral function pin STOPC. The peripheral function mode of this pin is selected by bit 2 (PMRC2) of port mode register C (PMRC: $025) (figure 35). 47 HD404459 Series R Ports (R0-RA): 39 input/output pins and 5 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR9: $030-$039) that are mapped to memory addresses (figure 30). Data control register (DCD0 to DCD2: $02C to $02E) (DCR0 to DCR9: $030 to $039) DCD0, DCD1 Bit 3 2 1 Initial value 0 0 0 0 Read/Write W W W W Bit name 0 DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 DCD2 Bit 3 2 1 Initial value -- -- 0 0 Read/Write -- -- W W Bit name 0 Not used Not used DCD21 DCD20 DCR0 to DCR8 Bit 3 2 1 Initial value 0 0 0 0 Read/Write W W W W Bit name 0 DCR03- DCR02- DCR01- DCR00- DCR83 DCR82 DCR81 DCR80 DCR9 Bit 3 2 1 Initial value -- 0 0 0 Read/Write -- W W W DCR91 DCR90 Bit name Not used DCR92 0 All Bits CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 -- -- D9 D8 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR5 R53 R52 R51 R50 DCR6 R63 R62 R61 R60 DCR7 R73 R72 R71 R70 DCR8 R83 R82 R81 R80 DCR9 -- R92 R91 R90 Bit 0 Figure 30 Data Control Registers (DCD, DCR) 48 HD404459 Series Pins R00-R03 are multiplexed with peripheral pins INT0-INT 3, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0-PMRB3) of port mode register B (PMRB: $024) (figure 31). Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write Bit name W PMRB3 PMRB2 PMRB1 PMRB0 PMRB0 R00/INT0 mode selection 0 R00 1 INT0 PMRB1 R01/INT1 mode selection 0 R01 1 INT1 PMRB2 R02/INT2 mode selection 0 R02 1 INT2 PMRB3 R03 /INT3 mode selection 0 R03 1 INT3 Figure 31 Port Mode Register B (PMRB) 49 HD404459 Series Pins R30-R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34). Timer mode register B2 (TMB2: $013) Bit 3 2 1 0 Initial value -- -- 0 0 -- -- R/W Read/Write Bit name R/W Not used Not used TMB21 TMB20 TMB21 TMB20 0 0 R30 R30 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 R30/TOB mode selection Figure 32 Timer Mode Register B2 (TMB2) Timer mode register C2 (TMC2: $014) Bit 3 Initial value -- 0 0 0 Read/Write -- R/W R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 TOC Not used 1 TOC Not used 0 TOC Not used 1 TOC PWM output Bit name 2 1 1 1 0 1 0 R31/TOC mode selection Figure 33 Timer Mode Register C2 (TMC2) 50 HD404459 Series Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 TOD Not used 1 TOD Not used 0 TOD Not used 1 TOD PWM output R32 Input capture (R32 port) 1 1 0 1 1 Don't care Don't care Don't care R32/TOD mode selection Figure 34 Timer Mode Register D2 (TMD2) 51 HD404459 Series Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 35). Port mode register C (PMRC: $025) Bit 3 Initial value -- 0 0 0 Read/Write -- W W W Bit name 2 1 Not used PMRC2* PMRC1 0 PMRC0 PMRC0 R33/EVNB mode selection 0 R33 1 EVNB PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D11/STOPC mode selection 0 D11 1 STOPC Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value. Figure 35 Port Mode Register C (PMRC) 52 HD404459 Series Pins R41-R4 3 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and 1 (PMRA0, PMRA1) port mode register A (PMRA: $004) (figures 36 and 37). Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used PMRA1 PMRA0 PMRA0 R43/SO mode selection 0 R43 1 SO PMRA1 R42/SI mode selection 0 R42 1 SI Figure 36 Port Mode Register A (PMRA) Serial mode register A (SMRA: $005) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write Bit name SMRA3 W SMRA3 SMRA2 SMRA1 SMRA0 R41/SCK mode selection 0 R41 port 1 SCK SMRA2 0 SMRA1 SMRA0 0 1 1 0 1 SCK Clock source Prescaler division ratio 0 Output Prescaler /2048 1 Output Prescaler /512 0 Output Prescaler /128 1 Output Prescaler /32 0 Output Prescaler /8 1 Output Prescaler /2 0 Output System clock -- 1 Input External clock -- Figure 37 Serial Mode Register A (SMRA) 53 HD404459 Series Ports R5 and R6 are multiplexed with pins WU0-WU 7. The wakeup modes of these pins can be selected by the wakeup select register (WSR: $019). Even if wakeup input is valid, the R port functions normally (figure 38). Wakeup select register (WSR: $018) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W WSR3 WSR2 WSR1 WSR0 WSR0 WU0 to WU3 control 0 Invalid 1 Valid WSR1 WU4 to WU5 control 0 Invalid 1 Valid WSR2 WU6 control 0 Invalid 1 Valid WSR3 WU7 control 0 Invalid 1 Valid Figure 38 Wakeup Select Register (WSR) 54 HD404459 Series Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 10, D11, R93, and RA 0-RA3. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin-- enabling on/off control of that pin alone (table 23 and figure 39). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R43/SO Bit name MIS3 Pull-up MOS on/off selection 0 Off 0 On 1 On 1 Off MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 39 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (those that remain floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. 55 HD404459 Series Prescalers The MCU has two prescalers, S and W. See table 25 and figure 40. Both the timers A-D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. 32-kHz crystal oscillator fX/8 Prescaler W Timer A Timer B fX/4 or fX/8 Timer C Timer D Clock selector System clock Prescaler S Serial Figure 40 Prescaler Output Supply Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), Subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W 32-kHz crystal oscillation MCU reset, software MCU reset, stop mode 56 HD404459 Series Timers The MCU has four timer/counters (A to D). Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers (table 26). The operating modes are selected by software. Table 26 Timer Functions Functions Clock source Timer functions Timer outputs Timer A Timer B Timer C Timer D Prescaler S Available Available Available Available Prescaler W Available -- -- -- External event -- Available -- Available Free-running Available Available Available Available Time-base Available -- -- -- Event counter -- Available -- Available Reload -- Available Available Available Watchdog -- -- Available -- Input capture -- -- -- Available Toggle -- Available Available Available 0 output -- Available Available Available 1 output -- Available Available Available PWM -- -- Available Available Note: -- means not available. 57 HD404459 Series Timer A Timer A Functions: Timer A (figure 41) has the following functions. * Free-running timer * Clock time-base 1/4 1/2 2 fW fW tWcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) /2 /8 / 16 / 32 32.768-kHz oscillator 1/2 tWcyc Clock Timer counter A (TCA) Overflow System clock o PER /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 41 Block Diagram of Timer A Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $002, bit 0). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. 58 HD404459 Series Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source (figure 42). Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMA3 TMA2 TMA1 TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 PSW 1/2tWcyc 1 Not used Don't care Timer A mode Time-base mode PSW and TCA reset Note: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 42 Timer Mode Register A (TMA) 59 HD404459 Series Timer B Timer B Functions: Timer B (figure 43) has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs) Timer B interrupt request flag (IFTB) Timer output control logic TOB Timer read register BU (TRBU) Timer output control Timer read register BL (TRBL) System clock o PER / 2048 EVNB /2 /4 /8 / 32 / 128 / 512 Selector Timer/event counter B (TCB) Overflow Timer write register BU (TWBU) Prescaler S (PSS) Free-running/ Reload control Timer write register BL (TWBL) 3 Timer mode register B1 (TMB1) 2 Timer mode register B2 (TMB2) Figure 43 Block Diagram of Timer B 60 Internal data bus Clock HD404459 Series Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 2). IFTB can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operations are basically the same as the free-running/ reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for a buzzer. Refer to figure 44 for the output waveform. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low. 61 HD404459 Series Toggle output waveform (timers B, C, and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 - N) clock cycles (256 - N) clock cycles PWM output waveform (timers C and D) T x (N + 1) TMC13 = 0 TMD13 = 0 T T x 256 TMC13 = 1 TMD13 = 1 T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 45, 53, and 60) N: The value of the timer write register (figures 55, 56, 62, and 63) Figure 44 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 45). It is reset to $0 by MCU reset. 62 HD404459 Series The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid. Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-running/reload timer selection TMB12 TMB11 TMB10 0 Free-running timer 0 0 0 2048tcyc 1 Reload timer 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R33/EVNB (external event input) 1 1 0 1 Input clock period and input clock source Figure 45 Timer Mode Register B1 (TMB1) 63 HD404459 Series * Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode (figure 46). It is reset to $0 by MCU reset. Timer mode register B2 (TMB2: $013) Bit 3 2 Initial value -- -- 0 0 Read/Write -- -- R/W R/W Bit name 0 1 Not used Not used TMB21 TMB20 TMB21 TMB20 0 0 R30 R30 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 R30/TOB mode selection Figure 46 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit (TWBL) and an upper digit (TWBU) (figures 47 and 48). The lower digit is reset to $0 by MCU reset, but the upper digit value is undefined. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 47 Timer Write Register B Lower Digit (TWBL) 64 HD404459 Series Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 48 Timer Write Register B Upper Digit (TWBU) * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of a lower digit (TRBL) and an upper digit (TRBU) that holds the count of the timer B upper digit. The upper digit (TRBU) must be read first, which will result in the count of the timer B upper digit to be obtained and the count of the timer B lower digit to be latched to the lower digit (TRBL). Then by reading TRBL, the count of timer B can be obtained when TRBU is read. Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 49 Timer Read Register B Lower Digit (TRBL) Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 50 Timer Read Register B Upper Digit (TRBU) 65 HD404459 Series * Port mode register C (PMRC: $025): Write-only register that selects the R33/EVNB pin function (figure 51). It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- W W W Bit name Not used PMRC2 PMRC1 PMRC0 PMRC0 R33/EVNB mode selection 0 R33 1 EVNB PMRC1 R40/EVND mode selection 0 R40 1 EVND PMRC2 D11/STOPC mode selection 0 D11 1 STOPC Figure 51 Port Mode Register C (PMRC) 66 HD404459 Series Timer C Timer C Functions: Timer C (figure 52) has the following functions. Free-running/reload timer Watchdog timer Timer output operation (toggle, 0, 1, and PWM outputs) System reset signal Watchdog on flag (WDON) TOC Timer C interrupt request flag (IFTC) Watchdog timer control logic Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Timer counter C (TCC) Timer write register CU (TWCU) /2 /4 /8 /32 /128 /512 /1024 /2048 Selector System oPER clock Prescaler S (PSS) Overflow Free-running /reload control Timer write register CL (TWCL) Internal data bus Clock 3 Timer mode register C1 (TMC1) 3 Timer mode register C2 (TMC2) Figure 52 Block Diagram of Timer C 67 HD404459 Series Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $003, bit 0). IFTC can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output (figure 44): When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/ reload timer function, input clock source, and prescaler division ratio (figure 53). It is reset to $0 by MCU reset. 68 HD404459 Series The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMC13 TMC12 TMC11 TMC10 Bit name TMC13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period TMC12 TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 53 Timer Mode Register C1 (TMC1) 69 HD404459 Series * Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode (figure 54). It is reset to $0 by MCU reset. Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value -- 0 0 0 Read/Write -- R/W R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 TOC Not used TOC PWM output Bit name 1 1 0 R31/TOC mode selection 1 0 1 1 Figure 54 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) (figures 55 and 56). The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 55 Timer Write Register C Lower Digit (TWCL) 70 HD404459 Series Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 56 Timer Write Register C Upper Digit (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit(figures 57 and 58). The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU:$00B). Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 57 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 58 Timer Read Register C Upper Digit(TRCU) Timer D Timer D Functions: Timer D (figures 59 (A) and (B)) has the following functions. Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer 71 HD404459 Series Timer D interrupt request flag (IFTD) Timer output control logic TOD Timer read register DU (TRDU) Timer output control Timer read register DL (TRDL) Clock Timer write register DU (TWDU) System clock oPER /2048 Edge detection logic /2 /4 /8 /32 /128 /512 Selector EVND Overflow Free-running/ Reload control Timer write register DL (TWDL) 3 Prescaler S (PSS) Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 59(A) Block Diagram of Timer D (Free-Running/Reload Timer) 72 Internal data bus Timer counter D (TCD) HD404459 Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Timer counter D (TCD) Overflow Selector System clock /2048 /2 /4 /8 /32 /128 /512 3 Timer mode register D1 (TMD1) Internal data bus Input capture timer control oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 59(B) Block Diagram of Timer D (Input Capture Timer) 73 HD404459 Series Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $001, bit 2). IFTD can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output. * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). 74 HD404459 Series When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $001, bit 2) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF can be reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 60). It is reset to $0 by MCU reset. The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. 75 HD404459 Series Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMD13 TMD12 TMD11 TMD10 TMD13 Free-running/reload timer selection TMD12 TMD11 TMD10 0 Free-running timer 0 0 0 2048tcyc 1 Reload timer 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R40/EVND (external event input) 1 1 0 1 Input clock period and input clock source Figure 60 Timer Mode Register D1 (TMD1) 76 HD404459 Series * Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation (figure 61). It is reset to $0 by MCU reset. Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 TOD Not used TOD PWM output R32 Input capture (R32 port) 1 1 0 R32/TOD mode selection 1 0 1 1 1 Don't care Don't care Don't care Figure 61 Timer Mode Register D2(TMD2) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) (figures 62 and 63). The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWDL3 TWDL2 TWDL1 TWDL0 Bit name Figure 62 Timer Write Register D Lower Digit (TWDL) 77 HD404459 Series Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 63 Timer Write Register D Upper Digit (TWDU) * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) (figures 64 and 65). The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 64 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 65 Timer Read Register D Upper Digit (TRDU) * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function (figure 51). It is reset to $0 by MCU reset. 78 HD404459 Series * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND (figure 66). It is reset to $0 by MCU reset. Detection edge register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 -- -- Read/Write W W -- -- Bit name ESR23 ESR22 Not used Not used EVND detection edge ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 66 Detection Edge Select Register 2 (ESR2) 79 HD404459 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 27 PWM Output following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T x (255 - N) T x (N + 1) Interrupt request T x (N' + 1) T x (255 - N) Reload Timer write register updated to value N T Interrupt request T x (255 - N) T Timer write register updated to value N Interrupt request T T x (255 - N) 80 T x (N + 1) T HD404459 Series Serial Interface The MCU has a serial interface (figure 67). The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector 81 HD404459 Series Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK Clock I/O controller Serial data register (SR) 1/2 Selector 1/2 Transfer control signal Internal data bus SI Selector /2 /8 /32 /128 /512 /2048 3 System clock PER Prescaler S (PSS) Serial mode register A (SMRA) Serial mode register B (SMRB) Figure 67 Serial Interface Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings (table 28); to change the operating mode of the serial interface, always initialize the serial interface internally by writing data to serial mode register A. Note that the serial interface is initialized by writing data to serial mode register A. Refer to the following section, Registers for Serial Interface, for details. Pin Setting: The R41/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). Pins R4 2/SI and R4 3/SO are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section, Registers for Serial Interface, for details. Transmit Clock Source Setting: The transmit clock source of the serial interface is set by writing data to serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following section, Registers for Serial Interface, for details. Data Setting: Transmit data of the serial interface is set by writing data to the serial data register (SRL: $006, SRU: $007). Receive data of the serial interface is obtained by reading the contents of the serial data register. The serial data is shifted by each serial interface transmit clock and is input from or output to an external system. 82 HD404459 Series The output level of the SO pins is undefined until the first data of each serial interface is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by the STS instruction and is incremented at the rising edge of the transmit clock for the serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 2) for serial interface is set, and the transfer stops. When the prescaler output is selected as the transmit clock of the serial interface, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SMRA0-SMRA2) of serial mode register A (SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) (table 29). Table 28 Serial Interface Operating Mode SMRA PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 Table 29 Serial Transmit Clock (Prescaler Output) SMRB SMRA Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 / 2048 4096tcyc 1 / 512 1024tcyc 0 / 128 256tcyc 1 / 32 64tcyc 0 /8 16tcyc 1 /2 4tcyc 0 / 4096 8192tcyc 1 / 1024 2048tcyc 0 / 256 512tcyc 1 / 64 128tcyc 0 / 16 32tcyc 1 /4 8tcyc 1 1 1 0 0 0 1 1 0 83 HD404459 Series Operating States: The serial interface has the following operating states, which allow transitions to occur between them (figure 68). STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMRA write 00 MCU reset 06 SMRA write (IFS 1) 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Transfer state (Octal counter = 000) 05 STS instruction (IFS 1) Internal clock mode SMRA write 18 Continuous clock output state (PMRA 0, 1 = 0, 0) STS wait state (Octal counter = 000, transmit clock disabled) 10 13 SMRA write 14 11 STS instruction MCU reset 8 transmit clocks 16 SMRA write (IFS 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 15 STS instruction (IFS 1) Note: Refer to the Operating States section for the explanations on the corresponding encircled numbers. Figure 68 Serial Interface State Transitions * STS wait state: The serial interface enters STS wait state by MCU reset (00 and 10 in figure 68). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01 and 11), the serial interface enters transmit clock wait state. 84 HD404459 Series * Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02 and 12) increments the octal counter, shifts the serial data register (SRL: $006, SRU: $007), and enters the serial interface in transfer state. However, note that if continuous clock output state is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04 and 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05 and 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, or STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register A (SMRA: $005) (06 and 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 0) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: When the serial interface is in STS instruction wait state and transmit clock wait state, the output of serial output pin SO can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB: $028) to 0 or 1. See figure 69 for an output level control example of the serial interface. Note that the output level cannot be controlled in transfer state. 85 , HD404459 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMRA write Output level control in idle states Dummy write for state transition Output level control in idle states SMRB write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMRA write Output level control in idle states SMRB write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 69 Example of Serial Interface Operation Sequence 86 HD404459 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected (figure 70). If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 0) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is again entered. After the transfer is completed and IFS is reset, writing to serial mode register A (SMRA: $005) then changes the state from transfer to STS wait. However, during the time the serial interface was in the transfer state with the serial interrupt request flag (IFS: $023, bit 0) being set again, the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register A (SMRA: $005) again. * Serial interrupt request flag (IFS: $023, bit 0) set: For the serial interface, if the state is changed from transfer state to another by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $023, bit 0) is not set. To set the serial interrupt request flag (IFS: $023, bit 0), a serial mode register A (SMRA: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R4. 87 HD404459 Series Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMRA write Yes IFS = 1? Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State SCK pin (input) Transfer state Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMRA is written, IFS is set. SMRA write IFS Flag set because octal counter reaches 000. Transmit clock error detection procedures Figure 70 Transmit Clock Error Detection 88 Flag reset at transfer completion. HD404459 Series Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Serial data register (SRL: $006, SRU: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Serial Mode Register A (SMRA: $005): This register has the following functions (figure 71). * * * * R4 1/SCK pin function selection Transmit clock selection Prescaler division ratio selection Serial interface initialization Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to the serial data register (SRL: $006, SRU: $007) and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $023, bit 0) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 89 HD404459 Series Serial mode register A (SMRA: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name SMRA3 SMRA3 SMRA2 SMRA1 SMRA0 R41/SCK mode selection 0 R41 1 SCK SMRA2 0 SMRA1 SMRA0 0 SCK Clock source Output Prescaler Refer to table 29 0 Output System clock -- 1 Input External clock -- 0 1 1 Prescaler division ratio 0 1 1 0 0 1 1 Figure 71 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: $028): This register has the following functions (figure 72). * Prescaler division ratio selection * Output level control in idle states Serial mode register B (SMRB: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle states of the serial interface. The output level changes at the same time that SMRB1 is written to. 90 HD404459 Series Serial mode register B (SMRB: $028) Bit 3 2 1 0 Initial value -- -- Undefined 0 Read/Write -- -- W W Bit name Not used Not used SMRB1 SMRB1 Output level control in idle states SMRB0 SMRB0 Serial clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 72 Serial Mode Register B (SMRB) Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 73 and 74). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock (figure 75); data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register (lower digit) (SRL: $006) Bit Initial value 3 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 73 Serial Data Register Lower Digit (SRL) 91 HD404459 Series Serial data register (upper digit) (SRU: $007) Bit Initial value 1 2 3 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 74 Serial Data Register Upper Digit (SRU) Transmit clock 1 Serial output data 2 3 4 5 6 LSB Serial input data latch timing Figure 75 Serial Interface Output Timing 92 7 8 MSB HD404459 Series Port Mode Register A (PMRA: $004): This register has the following functions (figure 76). * R4 2/SI pin function selection * R4 3/SO pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value -- -- 0 0 Read/Write -- -- W W Bit name Not used Not used PMRA1 PMRA0 PMRA0 R43/SO mode selection 0 R43 1 SO PMRA1 R42/SI mode selection 0 R42 1 SI Figure 76 Port Mode Register A (PMRA) 93 HD404459 Series Miscellaneous Register (MIS: $00C): This register has the following functions (figure 77). * R4 3/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS1 MIS0 0 0 0.12207 ms 1 7.8125 ms 0 62.5 ms 1 Not used Bit name 1 MIS2 R43/SO PMOS on/off selection 0 On 1 Off MIS3 tRC Pull-up MOS on/off selection 0 Off 1 On Figure 77 Miscellaneous Register (MIS) 94 HD404459 Series Comparator The comparator (figure 78) compares an analog input voltage with a reference voltage. Either a 16-level internal or external reference power supply can be selected. The voltage comparison is started by writing 1 to the comparator start flag (CMSF: $020, bit 2), and is completed after 4t cyc. The comparison result is stored into bit 3 (CER: $017, bit 3) of the comparator enable register, and can be read by the bit test instruction (TM or TMD). The comparison result must be read after confirming that the comparator start flag (CMSF: $020, bit 2) is at 0 (figure 79). Internal data bus 4 3 1 Comparator control register (CCR) Comparator start flag (CMSF) 4 1 Comparator enable register (CER) 1 1 Selector Selector 2 R93/VCref RA0/COMP0 RA1/COMP1 RA2/COMP2 RA3/COMP3 Selector COMP Figure 78 Block Diagram of Comparator 95 HD404459 Series Comparator start flag Write cycle 4tcyc (RA port must not be used) Internal system clock Comparator start flag (CMSF) Voltage comparison result (CER3) Figure 79 Comparator Operation Timing 96 HD404459 Series Comparator Control Register (CCR: $016): Four-bit write-only register which selects a 16-level internal reference power supply (figure 80). The comparator control register (CCR: $016) is reset to $0 by MCU reset. Comparator control register (CCR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W CCR3 CCR2 CCR1 CCR0 CCR3 CCR2 CCR1 CCR0 0 0 0 0 1/17 VCC 1 2/17 VCC 0 3/17 VCC 1 4/17 VCC 0 5/17 VCC 1 6/17 VCC 0 7/17 VCC 1 8/17 VCC 0 9/17 VCC 1 10/17 VCC 0 11/17 VCC 1 12/17 VCC 0 13/17 VCC 1 14/17 VCC 0 15/17 VCC 1 16/17 VCC Bit name 1 1 0 1 1 0 0 1 1 0 1 Reference power supply selection Figure 80 Comparator Control Register (CCR) Comparator Enable Register (CER: $017): This register consists of a 3-bit write-only register and a 1-bit read-only register. It selects the analog input pins and reference voltage, and indicates the voltage comparison result. The comparison result output is 0 when an analog input voltage is lower than the reference voltage, and is 1 when an analog input voltage is higher than the reference voltage. The comparison result is read by the bit test instruction (TM or TMD). The comparator enable register (CER: $017) is reset to $0 by MCU reset. 97 HD404459 Series Comparator enable register (CER: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R W W W CER3 CER2 CER1 CER0 Bit name CER1 CER0 0 0 COMP0 1 COMP1 0 COMP2 1 COMP3 1 CER2 Analog input mode selection Reference power supply selection 0 External reference power supply 1 Internal reference power supply CER3 Voltage comparison result 0 Analog input voltage is lower than reference voltage 1 Analog input voltage is higher than reference voltage Figure 81 Comparator Enable Register (CER) Comparator Start Flag (CMSF: $020, Bit 2): Starts the comparator operation. The comparator starts the voltage comparison by writing 1 to the comparator start flag (CMSF: $020, bit 2), and automatically completes the voltage comparison after 4tcyc. The comparator start flag is then reset to 0. The comparison result must be read after confirming that the comparator start flag is at 0. The comparator start flag is reset to 0 by MCU reset. Notes on Use: RA0/COMP0-RA3/COMP3 pins are used only for the comparator during voltage comparison. These pins cannot be used for R ports. The comparator operates only in the active and standby modes. The switch for the internal power supply is turned on when the internal power supply is selected. The switch is turned off except in active and standby modes. When the external power supply is used for a reference voltage, R93/VCref must not be used as an R port. 98 HD404459 Series Notes on Mounting Assemble all parts including the HD404458/HD404459 on a board, noting the points described below. Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 82. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. VCC VCC C1 GND C2 GND Figure 82 Example of Connections 99 HD404459 Series Programmable ROM (HD4074459) The HD4074459 is a ZTAT TM microcomputer with a built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode Pin No. MCU Mode FP-64A Pin Name I/O FP-64A Pin Name I/O Pin Name I/O 1 RA0/COMP0 I 29 R10 I/O A5 I 2 RA1/COMP1 I 30 R11 I/O A6 I 3 RA2/COMP2 I 31 R12 I/O A7 I 4 RA3/COMP3 I 32 R13 I/O A8 I 5 TEST I TEST 33 R20 I/O A0 I 6 OSC1 I VCC 34 R21 I/O A10 I 7 OSC2 O 35 R22 I/O A11 I 8 GND -- 36 R23 I/O A12 I 9 X2 O 37 R30/TOB I/O 10 X1 I GND 38 R31/TOC I/O 11 RESET I RESET I 39 R32/TOD I/O 12 D0 I/O O0 I/O 40 R33/EVNB I/O 13 D1 I/O O1 I/O 41 R40/EVND I/O 14 D2 I/O O2 I/O 42 R41/SCK I/O 15 D3 I/O O3 I/O 43 R42/SI I/O 16 D4 I/O O4 I/O 44 R43/SO I/O 17 D5 I/O O5 I/O 45 R50/(WU0) I/O 18 D6 I/O O6 I/O 46 R51/(WU1) I/O 19 D7 I/O O7 I/O 47 R52/(WU2) I/O 20 D8 I/O A13 I 48 R53/(WU3) I/O 21 D9 I/O A14 I 49 R60/(WU4) I/O CE I 22 D10 I VPP I 50 R61/(WU5) I/O OE I 23 D11/STOPC I A9 I 51 R62/(WU6) I/O VCC 24 VCC -- VCC 52 R63/(WU7) I/O VCC 25 R00/INT0 I/O M0 I 53 R70 I/O A1 I 26 R01/INT1 I/O M1 I 54 R71 I/O A2 I 27 R02/INT2 I/O 55 R72 I/O A3 I 28 R03/INT3 I/O 56 R73 I/O A4 I 100 PROM Mode Pin Name GND I/O I -- PROM Mode HD404459 Series Pin No. MCU Mode PROM Mode Pin No. MCU Mode FP-64A Pin Name I/O Pin Name 57 R80 I/O 58 R81 59 60 PROM Mode I/O FP-64A Pin Name I/O Pin Name I/O O4 I/O 61 R90 I/O O0 I/O I/O O3 I/O 62 R91 I/O VCC R82 I/O O2 I/O 63 R92 I/O R83 I/O O1 I/O 64 R93/VCref I Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using them, each pair must be connected together. 101 HD404459 Series Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. This PROM mode is set by pulling TEST, M0, and M1 low, and RESET high (figure 83). In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 64-to-28-pin socket adapter. Refer to table 31 for the Recommended PROM programmers and socket adapters of the HD4074459. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package versions cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTATTM devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be program med at high speed without risk of voltage stress or damage to data reliability. Refer to table 30 for programming and verification modes. For details of PROM programming, refer to the preface section, Notes on PROM Programming. Table 30 PROM Mode Selection Pin Mode CE OE VPP O0-O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance 102 HD404459 Series Table 31 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Model Name Manufacturer DATA I/O Corp. 121B FP-64A HS4459ESH01H Hitachi AVAL Corp. PKW-1000 FP-64A HS4459ESH01H Hitachi VCC VCC RESET VCC TEST M0 VPP M1 O0 to O7 Data O0 to O7 A0 to A14 Address A0 to A14 VPP HD4074459H VCC OSC1 R62 R63 OE OE CE CE R91 X1 GND Figure 83 PROM Mode Connections 103 HD404459 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes (figure 84). Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used for RAM addressing. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used for RAM addressing. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 84 RAM Addressing Modes 104 m3 m2 HD404459 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes (figure 85). Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13- PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page (figure 87). This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction (figure 86). If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 105 HD404459 Series 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 a5 Opcode 0 0 0 a4 a3 a2 a1 a0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 85 ROM Addressing Modes 106 B2 B1 Accumulator HD404459 Series Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R2 3 R2 2 R21 R2 0 R1 3 R12 R11 R10 If RO 9 = 1 Pattern Output Figure 86 P Instruction 256 (n - 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 87 Branching when the Branch Destination is on a Page Boundary 107 HD404459 Series Absolute Maximum Ratings (HD404458/HD404459) Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +4.0 V Pin voltage VT -0.3 to (VCC + 0.3) V Total permissible input current Io 50 mA 2 Total permissible output current -Io 50 mA 3 Maximum input current Io 4 mA 4, 5 Maximum output current -Io 4 mA 5, 6 Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Absolute Maximum Ratings (HD4074459) Item Symbol Value Unit Notes Supply voltage VCC -0.3 to +4.0 V Programming voltage VPP -0.3 to +14.0 V Pin voltage VT -0.3 to (VCC + 0.3) V Total permissible input current Io 50 mA 2 Total permissible output current -Io 50 mA 3 Maximum input current Io 4 mA 4, 5 Maximum output current -Io 4 mA 5, 6 Operating temperature Topr -20 to +75 C 7 Storage temperature Tstg -55 to +125 C 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D10 (VPP ) of the HD4074459. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D0-D9, R0-R8, and R90-R92. 6. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 7. Depends on the supply voltage. 108 HD404459 Series Electrical Characteristics DC Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified. Item Symbol Pin(s) Min Typ Max Input high voltage VIH 0.9VCC -- VCC + 0.3 V -- OSC1 VCC - 0.3 -- VCC + 0.3 V External clock operation RESET, STOPC, -0.3 -- 0.1VCC V -- OSC1 -0.3 -- 0.3 V External clock operation Output high VOH voltage SCK, SO, VCC - 0.5 -- -- V -IOH = 0.3 mA Output low voltage SCK, SO, -- -- 0.4 V IOL = 0.4 mA -- -- 1.0 A Vin = 0 V to VCC 1 -- 3 6 mA HD404458, 2, 4 RESET, STOPC, Unit Test Condition Notes INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, EVNB, EVND Input low voltage VIL INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, EVNB, EVND VOL TOB, TOC, TOD TOB, TOC, TOD I/O leakage | IIL | current RESET, STOPC, INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, SO, EVNB, EVND, OSC1, TOB, TOC, TOD Current dissipation in active mode ICC VCC HD404459: VCC = 3.0 V, fOSC = 4 MHz -- 5 9 mA HD4074459: 2, 4 VCC = 3.0 V, fOSC = 4 MHz 109 HD404459 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Current dissipation in standby mode ISBY -- 1.2 3 mA VCC = 3.0 V, 3, 4 VCC fOSC = 4 MHz ISUB Current dissipation in subactive mode VCC -- 35 70 A HD404458, HD404459: VCC = 3.0 V, 32-kHz oscillator -- 70 150 A HD4074459: VCC = 3.0 V, 32-kHz oscillator Current dissipation in watch mode IWTC Current dissipation in stop mode ISTOP VCC -- 8 15 A VCC = 3.0 V, 5 32-kHz oscillator Stop mode VSTOP retaining voltage VCC -- 1 10 A VCC = 3.0 V, 5 no 32-kHz oscillator VCC 1.5 -- -- V No 32-kHz oscillator 6 Notes: 1. Output buffer current is excluded. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at VCC (0.9VCC to VCC) TEST at VCC (0.9VCC to VCC) 3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (0.9VCC to VCC) 4. The current dissipation is in proportion to fOSC while the MCU is operating or is in standby mode. The value of the dissipation current when f OSC = x MHz is given by the following equation: Maximum value (fOSC = x MHz) = x/4 x maximum value (fOSC = 4 MHz) 5. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (0.9VCC to VCC) D10* at VCC (0.9VCC to VCC) Note: * Applies to HD4074459 6. RAM data retention is the voltage required for retaining RAM data. 110 HD404459 Series I/O Characteristics for Standard Pins HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified. Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D0-D11 , 0.7VCC -- VCC + 0.3 V -- -0.3 -- 0.3VCC V -- VCC - 0.5 -- -- V -IOH = 0.3 mA -- -- 0.4 V IOL = 0.4 mA -- -- 1 A HD404458, Note R0-RA Input low voltage VIL D0-D11 , R0-RA Output high voltage VOH D0-D9, R0-R8, R90-R92 Output low voltage VOL D0-D9, R0-R8, R90-R92 I/O leakage current | IIL | D0-D11 , R0-RA 1 HD404459: Vin = 0 V to VCC D0-D9, D11 , -- -- 1 A 1 Vin = 0 V to VCC R0-RA D10 HD4074459: -- -- 1 A HD4074459: 1 Vin = VCC - 0.3 to VCC -- -- 20 A HD4074459: 1 Vin = 0 V to 0.3 V Pull-up MOS current -IPU D0-D9, 5 R0-R8, 40 90 A VCC = 3.0 V, Vin = 0 V R90-R92 Note: 1. Output buffer current is excluded. 111 HD404459 Series Voltage Comparator Characteristics HD404458, HD404459: VCC = 2.0 to 3.6 V, GND = 0 V, Ta = -10 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -10 to +75C, f OSC = 0.4 to 4.0 MHz,unless otherwise specified. Item Symbol Pin(s) Min Typ Max Unit Test Condition Note Input high voltage VIHA COMP0- COMP3 Vref + 0.17 -- -- V -- 1 Input low voltage VILA COMP0- COMP3 -- -- Vref - 0.03 V -- 1 Analog input standard voltage range VCref VCref 0 -- VCC V -- Note: 112 1. When an internal reference voltage is selected, the standard voltage is an expected voltage of internal Vref specified by the comparator control register (CCR). HD404459 Series AC Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified. Item Symbol Pin(s) Min Typ Max Unit Test Condition Clock oscillation frequency fOSC OSC1, OSC2 0.4 -- 4.0 MHz HD404458, HD404459: Notes 1/4division, VCC = 1.8 V to 3.6 V HD4074459: 1/4 division, VCC = 2.7 V to 3.6 V 0.4 -- 2.0 MHz HD4074459: 1/4 division, VCC = 2.2 V to 2.7 V Instruction cycle time tcyc X1, X2 -- 32.768 -- kHz -- -- 1.0 -- s HD404458, HD404459: 10 VCC = 1.8 V to 3.6 V HD4074459: 1/4 division, VCC = 2.7 V to 3.6 V 2.0 -- 10 s HD4074459: 1/4 division, VCC = 2.2 V to 2.7 V tsubcyc -- -- 244.14 -- s 32-kHz oscillator, 1/8 division -- 122.07 -- s 32-kHz oscillator, 1/4 division Oscillation tRC stabilization time (ceramic oscillator) OSC1, OSC2 -- -- 60 ms -- 1 Oscillation stabilization time (crystal oscillator) OSC1, OSC2 -- -- 60 ms -- 1 X1, X2 -- -- 3 s Ta = -10C to+60C 2 External clock high tCPH width OSC1 105 -- -- ns fOSC = 4 MHz 3 External clock low tCPL width OSC1 105 -- -- ns fOSC = 4 MHz 3 tRC 113 HD404459 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes External clock rise tCPr time OSC1 -- -- 20 ns -- 3 External clock fall time OSC1 -- -- 20 ns -- 3 INT0-INT3, 2 -- -- tcyc / -- 4, 7 -- 4, 7 tCPf INT0-INT3, EVNB, tIH WU0-WU7, EVND high widths INT0-INT3, EVNB, tIL WU0-WU7, EVND low widths WU0-WU7, tsubcyc EVNB, EVND INT0-INT3, 2 -- -- WU0-WU7, tcyc / tsubcyc EVNB, EVND RESET high width tRSTH RESET 2 -- -- tcyc -- 5 STOPC low width tSTPL STOPC 1 -- -- tRC -- 6 RESET fall time tRSTf RESET -- -- 20 ms -- 5 STOPC rise time tSTPr STOPC -- -- 20 ms -- 6 Input capacitance Cin All pins except -- for D10 -- 15 pF f = 1 MHz, V in = 0 V D10 -- 15 pF HD404458, HD404459: -- f = 1MHz, Vin = 0 V -- -- 180 pF HD4074459: f = 1 MHz, V in = 0 V Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic or crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of the system oscillation. 2. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. 3. Refer to figure 88. 4. Refer to figure 89. The tcyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. 5. Refer to figure 90. 6. Refer to figure 91. 7. In watch or subactive mode, the periods when the INT0 and WU0-WU7 signals are high and when these signals are low must be equal to the interrupt frame period or longer. 114 HD404459 Series Serial Interface Timing Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified. During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1.0 -- -- tcyc Load shown in figure 93 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc Load shown in figure 93 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc Load shown in figure 93 1 Transmit clock rise time tSCKr SCK -- -- 200 ns Load shown in figure 93 1 Transmit clock fall time SCK -- -- 200 ns Load shown in figure 93 1 Serial output data delay tDSO time SO -- -- 500 ns Load shown in figure 93 1 Serial input data setup time tSSI SI 300 -- -- ns -- 1 Serial input data hold time tHSI SI 300 -- -- ns -- 1 Note: tSCKf 1. Refer to figure 92. During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1.0 -- -- tcyc -- 1 Transmit clock high width tSCKH SCK 0.4 -- -- tScyc -- 1 Transmit clock low width tSCKL SCK 0.4 -- -- tScyc -- 1 Transmit clock rise time tSCKr SCK -- -- 200 ns -- 1 Transmit clock fall time SCK -- -- 200 ns -- 1 Serial output data delay tDSO time SO -- -- 500 ns Load shown in figure 93 1 Serial input data setup time tSSI SI 300 -- -- ns -- 1 Serial input data hold time tHSI SI 300 -- -- ns -- 1 Note: tSCKf 1. Refer to figure 92. 115 HD404459 Series OSC1 1/fCP VCC - 0.3 V 0.3 V tCPL tCPH tCPr tCPf Figure 88 External Clock Timing WU0 to WU7, INT0 to INT3, EVNB, EVND 0.9VCC tIH tIL 0.1VCC Figure 89 Interrupt Timing RESET 0.9VCC tRSTH 0.1VCC tRSTf Figure 90 Reset Timing 116 HD404459 Series STOPC 0.9VCC tSTPL 0.1VCC tSTPr Figure 91 STOPC Timing t Scyc t SCKf SCK t SCKr VCC - 0.5 V (0.9VCC )* 0.4 V (0.1VCC)* t SCKL t SCKH t DSO VCC - 0.5 V 0.4 V SO t HSI t SSI 0.9V CC 0.1VCC SI Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input. Figure 92 Serial Interface Timing VCC RL = 2.6 k Test point C= 30 pF R= 12 k 1S2074 H or equivalent Figure 93 Timing Load Circuit 117 HD404459 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404459). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. ROM 8-kword version: HD404458 Address $2000-$3FFF $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF 118 Fill this area with 1s HD404459 Series HD404458, HD404459 Option List Please check off the appropriate applications and enter the necessary information. Date of order Customer 1. ROM size Department HD404458 8-kword Name HD404459 16-kword ROM code name LSI number 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM code media Please specify the first type listed below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4. Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop mode Used Not used 6. Package FP-64A 119