General Purpose Microcomputer HD404019R Series
Data Sheet HD404054 Series/HD404094 Series
Compact Microcomputer
H42××Family Data Sheet HD404202 Series/HD404222 Series
A/D Converter On-Chip
H43××Family Data Sheet HD404304 Series
HD404318 Series
HD404328 Series
HD404339 Series
HD404358 Series
HD404369 Series
HD404344 Series/HD404394 Series
Improved Timers, System Control
H44××Family Data Sheet HD404439
HD404449 Series
HD404459 Series
•Index 05.09.1997 10:59 Uhr Page 1
Preface
The HMCS400 Series is made up of the microcomputer families listed below, each with functions geared
for applications in specific fields.
The Hitachi 4-bit Single-Chip Microcomputer Databook is divided into two separate databooks, no. 1 and
no. 2. Databook no. 1 includes information from general purpose microcomputers to the H44XX family,
while no. 2 includes information from the H46XX family to the H48XX family. Use databooks no. 1 and
no. 2 accordingly.
General purpose
microcomputer
H42XX Family
H43XX Family
H44XX Family
H46XX Family
H47XX Family
H48XX Family
28 pin compact microcomputer
Built-in A/D converter
Enhanced timer function
Built-in DTMF generator/receiver
VFD display controller/driver
LCD display controller/driver
No. 1
No. 2
HMCS400
Series
Contents
■General Information
●Function Overview........................................................................................................................... 2
●Introduction of Packages.............................................................................................................. 22
●Reliability and Quality Assurance .............................................................................................. 36
●Reliability Test Data of Microcomputer ................................................................................... 44
●Programmable ROM (ZTAT™) Microcomputer ....................................................................... 66
●Program Development Procedure and Support Systems.................................................... 71
●Instruction Set .................................................................................................................................. 77
■Data Sheets
●General Purpose Microcomputer
HD404019R............................................................................................................................................ 248
HD40L4019R.......................................................................................................................................... 248
HD4074019 ............................................................................................................................................ 248
HD407L4019 .......................................................................................................................................... 248
HD404052 .............................................................................................................................................. 368
HD404054 .............................................................................................................................................. 368
HD4074054 ............................................................................................................................................ 368
HD404092 .............................................................................................................................................. 368
HD404094 .............................................................................................................................................. 368
HD4074094 ............................................................................................................................................ 368
●H42XX Family
HD404201 .............................................................................................................................................. 461
HD40L4201 ............................................................................................................................................ 461
HD404202 .............................................................................................................................................. 461
HD40L4202 ............................................................................................................................................ 461
HD404222 .............................................................................................................................................. 461
HD40L4222 ............................................................................................................................................ 461
HD4074224 ............................................................................................................................................ 461
●H43XX Family
HD404302R............................................................................................................................................ 579
HD404304 .............................................................................................................................................. 579
HD4074308 ............................................................................................................................................ 579
HD404314 .............................................................................................................................................. 632
HD404316 .............................................................................................................................................. 632
HD404318 .............................................................................................................................................. 632
HD4074318 ............................................................................................................................................ 632
HD404324 .............................................................................................................................................. 696
HD404324U............................................................................................................................................ 696
HD404326 .............................................................................................................................................. 696
HD404326U............................................................................................................................................ 696
HD404328 .............................................................................................................................................. 696
HD404328U............................................................................................................................................ 696
HD4074329 ............................................................................................................................................ 696
HD4074329U.......................................................................................................................................... 696
HD404334 .............................................................................................................................................. 775
HD404336 .............................................................................................................................................. 775
HD404338 .............................................................................................................................................. 775
HD4043312 ............................................................................................................................................ 775
HD404339 .............................................................................................................................................. 775
HD4074339 ............................................................................................................................................ 775
HD404354 .............................................................................................................................................. 845
HD404356 .............................................................................................................................................. 845
HD404358 .............................................................................................................................................. 845
HD40A4354............................................................................................................................................ 845
HD40A4356............................................................................................................................................ 845
HD40A4358............................................................................................................................................ 845
HD407A4359.......................................................................................................................................... 845
HD404364 .............................................................................................................................................. 939
HD404368 .............................................................................................................................................. 939
HD4043612 ............................................................................................................................................ 939
HD404369 .............................................................................................................................................. 939
HD40A4364............................................................................................................................................ 939
HD40A4368............................................................................................................................................ 939
HD40A43612.......................................................................................................................................... 939
HD40A4369............................................................................................................................................ 939
HD407A4369.......................................................................................................................................... 939
HD404341 ..............................................................................................................................................1043
HD404342 ..............................................................................................................................................1043
HD404344 ..............................................................................................................................................1043
HD4074344 ............................................................................................................................................1043
HD404391 ..............................................................................................................................................1043
HD404392 ..............................................................................................................................................1043
HD404394 ..............................................................................................................................................1043
HD4074394 ............................................................................................................................................1043
●H44XX Family
HD404439 ..............................................................................................................................................1194
HD404448 ..............................................................................................................................................1295
HD404449 ..............................................................................................................................................1295
HD4074449 ............................................................................................................................................1295
HD404458 ..............................................................................................................................................1405
HD404459 ..............................................................................................................................................1405
HD4074459 ............................................................................................................................................1405
Function Overview
General-purpose products: H40XX Family
Series No. Type No. ROM
(byte) RAM
(digit) Supply
voltage (V)
Min.
operation
(µs)
Max.
operating
Freq (MHz) 8-bit timer
(channels) SCI
(channels) I/O
port Comparator Package
HD404054 Mask
ROM HD404052 2k 512 1.8-6.0 1 fOSC=4 3 – 35 2 DP-42S,
FP-44A
HD404054 4k
HD40A4052 2k 4.0-6.0 0.5 fOSC=8
HD40A4054 4k
ZTAT HD4074054 4k 2.7-5.5 1 fOSC=4
HD404094 Mask
ROM HD404092 2k 512 1.8-6.0 1 fOSC=4 3 – 35 2 DP-42S,
FP-44A
HD404094 4k
ZTAT HD4074094 4k 2.7-5.5 1 fOSC=4
HD404019 Mask
ROM HD404019R 16k 992 3.5-6.0 0.89 fOSC=4.5 2 1 58 – DP-64S,
FP-64A,
FP-64B
HD40L4019R 3.5-6.0 0.89 fOSC=4.5 DP-64S,
FP-64A
2.7-6.0 1.12 fOSC=3.58
ZTAT HD4074019 16k 4.5-5.5 0.89 fOSC=4.5 DP-64S,
FP-64A,
FP-64B,
DC-64S
HD407L4019 4.5-5.5 0.89 fOSC=4.5 DP-64S,
FP-64A
3.0-5.5 1.12 fOSC=3.58
*: Under development
Compact products: H42XX Family
Series No. Type No. ROM
(byte) RAM
(digit) Supply
voltage (V)
Min.
operation
(µs)
Max.
operating
Freq (MHz) 8-bit timer
(channels) SCI
(channels) I/O
port Comparator Package
HD404202 Mask
ROM HD404201 1k 64 3.5-6.0 0.89 fOSC=4.5 1 – 22 – DP-28S,
FP-28DA,
FP-30D
HD40L4201 2.5-6.0 3.55 fOSC=1.125
HD404202 2k 3.5-6.0 0.89 fOSC=4.5
HD40L4202 2.5-6.0 3.55 fOSC=1.125
HD404222 Mask
ROM HD404222 2k 128 3.5-6.0 0.89 fOSC=4.5 2 1 22 2 DP-28S,
FP-28DA,
FP-30D
HD40L4222 2.5-6.0 3.55 fOSC=1.125
ZTAT HD4074224 4k 3.5-5.5 0.89 fOSC=4.5
2.5-5.5 3.55 fOSC=1.125
Function Overview
2
Built-in A/D converter products: H43XX Family
Series No. Type No. ROM
(byte) RAM
(digit)
Supply
voltage
(V)
Min.
opera-
tion
(µs)
Max.
operating
Freq
(MHz)
8-bit
timer
(chan-
nels)
SCI
(chan-
nels) I/O
port A/D con-
verter
High
voltage
terminal
Medium
voltage
terminal Input
capture LCD
controller Package
HD404304 Mask
ROM HD404302R 2k 160 4.5-5.5 1.78 fOSC=4.5 2 – 33 4 25 – – – DP-42,
DP-42S,
FP-54
HD404304 4k
ZTAT HD4074308 8k
HD404318 Mask
ROM HD404314 4k 384 4.0-5.5 0.89 fOSC=4.5 3 1 34 8 21 – Available – DP-42S,
FP-44A
HD404316 6k
HD404318 8k
ZTAT HD4074318 8k
HD404328 Mask
ROM HD404324 4k 280 2.7-6.0 1.78 fOSC=4.5 3 1 35 4 – – – 24seg ×
4com DP-64S,
FP-64B,
FP-64A
HD404324U*
HD404326 6k
HD404326U*
HD404328 8k
HD404328U*
ZTAT HD4074329 16k 536 2.9-5.5 DP-64S,
FP-64B
HD4074329U*
HD404339 Mask
ROM HD404334 4k 512 4.0-5.5 0.89 fOSC=4.5 3 1 54 12 30 – Available – DP-64S,
FP-64B
HD404336 6k
HD404338 8k
HD4043312 12k
HD404339 16k
ZTAT HD4074339 16k
HD404358 Mask
ROM HD404354 4k 384 2.7-6.0 0.8 fOSC=5 3 1 34 8 – 4 Available – DP-42S,
FP-44A
HD404356 6k
HD404358 8k
HD40A4354 4k 4.5-5.5 0.47 fOSC=8.5
HD40A4356 6k
HD40A4358 8k
ZTAT HD407A4359 16k 512
HD404369 Mask
ROM HD404364 4k 512 2.7-6.0 0.8 fOSC=5 3 1 54 12 – 8 Available – DP-64S,
FP-64B,
FP-64A
HD404368 8k
HD4043612 12k
HD404369 16k
HD40A4364 4k 4.5-5.5 0.47 fOSC=8.5
HD40A4368 8k
HD40A43612 12k
HD40A4369 16k
ZTAT HD407A4369 16k
HD404344 Mask
ROM HD404341 1k 256 2.7-5.5 0.89 fOSC=4.5 2 1 22 4 – – – – DP-28S,
FP-28DA,
FP-30D
HD404342 2k
HD404344 4k
ZTAT HD4074344 4k
HD404394 Mask
ROM HD404391 1k 256 2.7-5.5 0.89 fOSC=4.5 2 1 21 3 – 3 – – DP-28S,
FP-28DA,
FP-30D
HD404392 2k
HD404394 4k
ZTAT HD4074394 4k
*: External LCD voltage divider type
Function Overview
3
Improved timer functionality products: H44XX Family
Series No. Type No. ROM
(byte) RAM
(digit) Supply
voltage (V)
Min.
operation
(µs)
Max.
operating
Freq (MHz) 8-bit timer
(channels)SCI
(channels) I/O
port A/D
converter Comparator Package
HD404439 Mask
ROM HD404439 16k 960 3.5-6.0 0.89 fOSC=4.5 5 2 70 8 – FP-80A,
FP-80B
3.0-6.0 1.78 fOSC=2.25
HD404449 Mask
ROM HD404448 8k 1152 2.7-6.0 1 fOSC=4 4 2 64 4 – FP-80A,
TFP-80F
HD404449 16k
ZTAT HD4074449 16k 2.7-5.5
HD404459 Mask
ROM HD404458 8k 512 1.8-3.6 1 fOSC=4 4 1 56 – Available FP-64A
HD404459 16k 768
ZTAT HD4074459 16k 2.2-2.7 2 fOSC=2
2.7-3.6 1 fOSC=4
Built-in DTMF circuit products: H46XX Family
Series No. Type No. ROM
(byte) RAM
(digit)
Supply
voltage
(V)
Min.
opera-
tion
(µs)
Max.
operating
Freq
(MHz)
8-bit
timer
(chan-
nels)
SCI
(chan-
nels) I/O
port
DTMF
genera-
tor DTMF
receiver LCD
controller A/D
converter Compara-
tor Package
HD404618 Mask
ROM HD404612 2k 1184 2.7-6.0 5 fOSC=0.8 3 1 30 Available – 32seg ×
4com – Available FP-80A,
FP-80B,
TFP-80
HD404614 4k
HD404616 6k
HD404618 8k
ZTAT HD4074618 8k 3.0-5.5
HD404629R Mask
ROM HD404628R 8k 1876 3.0-6.0 1 fOSC=4 4 1 44 Available – 52seg ×
4com 4 – FP-100A,
FP-100B,
TFP-100B
2.7-6.0 2 fOSC=2
HD4046212R 12k 3.0-6.0 1 fOSC=4
2.7-6.0 2 fOSC=2
HD404629R 16k 3.0-6.0 1 fOSC=4
2.7-6.0 2 fOSC=2
ZTAT HD4074629 16k 3.5-5.5 1 fOSC=4
2.7-5.5 2 fOSC=2
HD404639R Mask
ROM HD404638R 8k 1152 2.7-6.0 1 fOSC=4 4 2 68 Available – – – Available FP-80B
HD404639R 16k
HD40A4638R 8k 4.0-6.0 0.5 fOSC=8
HD40A4639R 16k
ZTAT HD407A4639R 16k 2.7-5.5 1
4.0-5.5 0.5
HD404654 Mask
ROM HD404652 2k 512 1.8-6.0 1 fOSC=4 3 1 32 Available – – – Available DP-42S,
FP-44A
HD404654 4k
ZTAT HD4074654 4k 2.7-5.5 1
HD404669 Mask
ROM HD404668 8k 1152 1.8-5.5 1 fOSC=4 3 1 52 Available – – – Available FP-64A
HD4046612 12k
HD404669 16k
HD40A4668 8k 4.0-5.5 0.5 fOSC=8
HD40A46612 12k
HD40A4669 16k
ZTAT HD407A4669 16k 2.2-5.5 1 fOSC=4
4.0-5.5 0.5 fOSC=8
HD404678 Mask
ROM HD404676 6k 512 4.5-5.5 1.91 fOSC=4.2 4 2 48 – Available – – – FP-64A
HD404678 8k
HD4074678
Function Overview
4
VFD controller/driver products: H47XX Family
Series No. Type No. ROM
(byte) RAM
(digit)
Supply
voltage
(V)
Min.
opera-tion
(µs)
Max.
operating
Freq (MHz) 8-bit timer
(channels) SCI
(channels) I/O port
High
voltage
terminal A/D
converter VFD
controller Package
HD404719 Mask
ROM HD404719 16k 960 3.0-6.0 0.89 fOSC=4.5 5 2 70 36 8 – FP-80A,
FP-80B
ZTAT HD4074719 16k 3.0-5.5
HD404729 Mask
ROM HD404728 8k 576 3.0-6.0 0.89 fOSC=4.5 3 2 56 32 – Available DP-64S,
FP-64A,
FP-64B
HD404729 16k
ZTAT HD4074729 16k 3.0-5.5
LCD controller/driver products: H48XX Family
Series No. Type No. ROM
(byte) RAM
(digit)
Supply
voltage
(V)
Min.
opera-tion
(µs)
Max.
operating
Freq (MHz) 8-bit timer
(channels) SCI
(channels) I/O
port LCD
controller A/D
converter ComparatorPackage
HD404818 Mask
ROM HD404812 2k 1184 4.0-6.0 0.95 fOSC=4.2 3 1 30 32seg ×
4com – Available FP-80A,
FP-80B,
TFP-80
HD40L4812 2.7-6.0 4.45 fOSC=0.9
HD404814 4k 4.0-6.0 0.95 fOSC=4.2
HD40L4814 2.7-6.0 4.45 fOSC=0.9
HD404816 6k 4.0-6.0 0.95 fOSC=4.2
HD40L4816 2.7-6.0 4.45 fOSC=0.9
HD404818 8k 4.0-6.0 0.95 fOSC=4.2
HD40L4818 2.7-6.0 4.45 fOSC=0.9
ZTAT HD4074818 8k 4.0-5.5 0.95 fOSC=4.2
HD407L4818 3.0-5.5 4.45 fOSC=0.9
HD404829R Mask
ROM HD404828R 8k 1876 2.7-6.0 1 fOSC=4.2 4 1 44 52seg ×
4com 4 – FP-100A,
FP-100B,
TFP-100B
HD4048212R 12k
HD404829R 16k
ZTAT HD4074829 16k 2.7-5.5
HD404849 Mask
ROM HD404848 8k 512 2.7-6.0 0.89 fOSC=4.5 4 1 35 32seg ×
4com 8 – FP-80A,
FP-80B,
TFP-80C
HD4048412 12k 1184
HD404849 16k
ZTAT HD4074849 16k 2.7-5.5
HD404889*Mask
ROM HD404888 8k 1344 1.8-5.5 0.89 fOSC=4.5 4 1 46 32seg ×
4com 6 – FP-80A,
TFP-80C
HD4048812 12k
HD404889 16k
ZTAT HD4074889 16k 2.0-5.5
*: Under development
Introduction of Packages
Hitachi microcomputer devices include various types of packages which meet the requirements of the ever
smaller, thinner, and more versatile electric appliances. When selecting a suitable package for use, please
refer to this introduction for Hitachi microcomputer packages.
1. Package Classification
Pin insertion types, surface mounting types, and multifunction types are applicable for each kind of
mounting method. Also plastic and ceramic packages are offered. Figure 1 shows the package classification
according to the mounting types onto the printed circuit board (PCB) and the package materials.
(Quad Flat J-leaded package)
Lead type
package
Area array
package
Insertion type
Gull wing lead
package
J-lead
package
Surface
mount type
IC package
Two-directionale
type
Four directionale
type
DIP
S-DIP
PGA
SOP
QFP
QFJ (PLCC)
QFN (LCC)
(Quad Flat Non-leaded package)
(Dual In-line Package)
(Shrink DIP)
(Pin grid array)
(Small Outline
Package)
(Quad Flat Package)
Non-lead
package
Four directionale
type
Four directionale
type
(Thin QFP)
TQFP
SSOP
(Shrink SOP)
Figure 1 Package Classification by Material and by Printed Circuit Board Mounting Method
Introduction of Packages
2
2. Type Number and Package Code Indication
The type number of Hitachi’s 4-bit single-chip microcomputers is followed by the package material and
outline specifications, as shown below. The package type used for each chip is identified by code as
follows, illustrated on its data sheet.
When placing an order, please write the package code beside the type number.
Type Number Indication
Package Code Indication
HDXXXXXXS
DP–64SA Additional outline 2
Number of pins
Outline
D:
F:
TF: Materials
P:
C:
G:
Additional outline 1
S:
D:
HMCS400 series
F:
FS:
H:
P:
S:
C:
TF:
FT:
FP:
QFP
QFP
QFP
Plastic DIP
Shrink-type plastic DIP
Ceramic DIP
TQFP
SSOP
SOP
Plastic
Ceramic
Glass-sealed ceramic
Shrink type
Dual lead type
Dual in-line
Flat
Flat with a mounting
height of 1.27 mm or
less
Introduction of Packages
3
3. Package Dimensional Outline
Hitachi’s 4-bit single-chip microcomputer devices employ the package types shown in table 1 according to
the mounting method onto the PCB.
Table 1 Package List
Mounting Method Package Classification Package Material Package code
Insertion type Standard package (DIP) Plastic DP-42
Shrink package (S-DIP) Plastic DP-28S
DP-42S
DP-64S
Ceramic DC-64S
Surface mounting
type Gullwing lead type Dual lead type
(SOP) Plastic FP-28DA
FP-30D
Quad lead type
(QFP) Plastic FP-44A, FP-54,
FP-64A, FP-64B,
FP-80A, FP-80B,
FP-100A, FP-100B
Thin quad lead type
(TQFP) Plastic TFP-80, TFP-80C
TFP-80F, TFP-100B
Introduction of Packages
4
Plastic DIP
Unit: mm
2.54 Min 5.06 Max
0.25 + 0.11
– 0.05
2.54 ± 0.25 0.48 ± 0.10 0° – 15°
15.24
0.51 Min
52.8
53.8 Max
13.4
15.0 Max
1.2
42
121
22
1.3 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight
DP-42
—
SC-512-42D
6.0 g
Dimension including the plating thickness
Base material dimension
DP-42
Introduction of Packages
5
Shrink type plastic DIP
Unit: mm
10.16
0.51 Min
2.54 Min 5.10 Max
0.25
0° – 15°
+ 0.11
– 0.05
0.48 ± 0.10
1.78 ± 0.25
27.1
27.9 Max
1.0
8.8
10.8 Max
28 15
114
2.41 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight
DP-28S
—
SC-548-28B
1.9 g
Dimension including the plating thickness
Base material dimension
DP-28S
Introduction of Packages
6
Unit: mm
0.25+ 0.10
– 0.05
0° – 15°
15.24
37.3
38.6 Max
1.0
14.0
14.6 Max
0.51 Min
5.10 Max
2.54 Min
0.48 ± 0.10
1.78 ± 0.25
42 22
121
1.38 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight
DP-42S
—
SC-551-42
4.8 g
Dimension including the plating thickness
Base material dimension
DP-42S
0.25+ 0.11
– 0.05
0° – 15°
1.78 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.08 Max
19.05
57.6
58.5 Max
1.0
1
33
32
64
17.0
18.6 Max
1.46 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
DP-64S
—
SC-553-64A
8.8 g
Dimension including the plating thickness
Base material dimension
DP-64S
Introduction of Packages
7
Shrink type ceramic DIP
Unit: mm
0.48 ± 0.10 + 0.11
– 0.05
57.30
18.92
0.9
64 33
132
1.78 ± 0.25 0.25
19.05
5.60 Max2.54 Min
0.51 Min
1.50 Max
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
DC-64S
—
SC-553-64A
9.7 g
DC-64S
Dimension including the plating thickness
Base material dimension
Introduction of Packages
8
Small outline package (SOP)
0.17 ± 0.05
3.00 Max
8.40
18.00
18.75 Max
1.27 Max
28 15
114 11.80 ± 0.30
0 – 10°
1.00 ± 0.20
1.70
0.20
0.15
M
0.40 ± 0.08
1.27
0.38 ± 0.06
+ 0.15
– 0.10
0.20
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-28DA
Introduction of Packages
9
Unit: mm
0.10 M
0.10 ± 0.10 2.00 Max
0.32 ± 0.08
0.65 15
30
11.0
11.2 Max
8.0
0.17 ± 0.05
0.5 ± 0.10
10.0 ± 0.2
0 – 8°
16
1.05 Max
1
0.10
1.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-30D
—
—
—
0.30 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-30D
Introduction of Packages
10
Quad flat package (QFP)
Unit: mm
0 – 8°
0.10
0.15 M
17.2 ± 0.3
14
33 23
34
44 111
17.2 ±0.3
0.37 ± 0.08
0.8
3.05 Max
0.17 ± 0.05
1.6
0.8 ± 0.3
2.70
22
12
3.0
0.10+0.15
–0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-44A
—
ED-7404A
1.2 g
0.15 ± 0.04
0.35 ± 0.06
Dimension including the plating thickness
Base material dimension
FP-44A
Introduction of Packages
11
Unit: mm
0.15 M
0 – 10°
25.6 ± 0.4
20
0.35 ± 0.06
1.0
0.17 ± 0.05
3.10 Max
0 Min
19.6 ± 0.4
14
49 33
50
54
1
5
62223
32
1.7 ± 0.3
2.70
2.8
2.0 2.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-54
—
—
1.7 g
0.37 ± 0.08
0.15 ± 0.04
2.0
Dimension including the plating thickness
Base material dimension
FP-54
Introduction of Packages
12
Unit: mm
0.10
0.15 M
17.2 ± 0.3
48 33
49
64 116
32
17
17.2 ±0.3
0.35 ± 0.06
0.8
3.05 Max
14
2.70
0° – 8°
1.6
0.8 ± 0.3
0.17 ± 0.05
0.10+0.15
–0.10
1.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
FP-64A
—
EDR-7311
1.2 g
0.37 ± 0.08
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-64A
Introduction of Packages
13
Unit: mm
0.20 M
0 – 10°
0.37 ± 0.08
0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
51 33
32
19
1
64
52
18.8 ± 0.4
14
0.15
1.0
20
2.70
2.4
1.0 1.0
0.20+0.10
–0.20
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-64B
—
—
1.7 g
0.35 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-64B
Introduction of Packages
14
Unit: mm
60
0° – 8°
0.10
0.12 M
17.2 ± 0.3
41
61
80 120
40
21
17.2 ±0.3
0.32 ±0.08
0.65
3.05 Max
1.6
0.8 ± 0.3
14
2.70
0.17 ± 0.05
0.10+0.15
–0.10
0.83
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
FP-80A
—
EDR-7311
1.2 g
0.30 ±0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-80A
Introduction of Packages
15
Unit: mm
0.15 M
0 – 10°
0.37 ± 0.08
0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
64 41
40
25
24
1
80
65
18.8 ± 0.4
14
0.15
0.8
2.70
2.4
0.20+0.10
–0.20
0.8 1.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
FP-80B
—
—
1.7 g
0.35 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-80B
Introduction of Packages
16
Unit: mm
0.13 M
0° – 10°
0.32 ± 0.08
0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
80 51
50
31
30
1
100
81
18.8 ± 0.4
14
0.15
0.65
2.70
2.4
0.20+0.10
–0.20
0.58 0.83
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
FP-100A
—
—
1.7 g
0.30 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-100A
Introduction of Packages
17
Unit: mm
0.10
16.0 ± 0.3
1.0
0.5 ± 0.2
16.0 ± 0.3
3.05 Max
75 51
50
26
125
76
100
14
0° – 8°
0.5
0.08 M
0.22 ± 0.05
2.70
0.17 ± 0.05
0.12+0.13
–0.12
1.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
FP-100B
—
EDR-7311
1.2 g
0.20 ± 0.04
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
FP-100B
Introduction of Packages
18
Thin quad flat package (TQFP)
Unit: mm
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TFP-80
—
—
0.5 g
0.10
0.13 M
15.6 ± 0.3
0.17 ± 0.05
0.65
15.6 ± 0.3
60 41
80
1
21
40
20
0 – 8 °
14
61
0.32 ± 0.08
0.5 ± 0.1
1.20 Max
0.10 ± 0.10
0.8
1.00
0.83
0.30 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
TFP-80
Introduction of Packages
19
Unit: mm
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
TFP-80C
—
EDR-7311
0.4 g
0.10 M
0.10 0.5 ± 0.1
0° – 8°
1.20 Max
14.0 ± 0.2
0.5
12
14.0 ± 0.2
60 41
120
80
61
21
40
0.17 ± 0.05
1.0
0.22 ± 0.05
0.10 ± 0.10 1.00
1.25
0.20 ± 0.04
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
TFP-80C
Introduction of Packages
20
Unit: mm
0.13 M
16.0 ± 0.2
0.17 ± 0.05
0.65
0.5 ± 0.1
16.0 ± 0.2
60 41
80
1
21
40
20
0 – 8°
14
61
1.0
0.32 ± 0.08
0.10
0.10 ± 0.10
1.20 Max
1.00
0.83
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TFP-80F
—
ED-7404A
0.5 g
0.30 ± 0.06
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
TFP-80F
Introduction of Packages
21
Unit: mm
16.0 ± 0.2
14
0.08
0.10 0.5 ± 0.1
16.0 ± 0.2
0.5
0.10 ± 0.10
1.20 Max
0.17 ± 0.05
0° – 8°
75 51
125
76
100 26
50
M
0.22 ± 0.05
1.0
1.00
1.0
Hitachi Code
JEDEC Code
EIAJ Code
Weight
(reference value)
TFP-100B
—
EDR-7311
0.5 g
0.20 ± 0.04
0.15 ± 0.04
Dimension including the plating thickness
Base material dimension
TFP-100B
Reliability and Quality Assurance
Microcomputer devices are advancing rapidly in terms of functional capabilities and level of integration,
and are being used in an increasingly wide range of applications. At the same time there are demands for
significantly higher quality and reliability. Hitachi has made a commitment to meeting users' requirements
through the establishment of an integrated quality and reliability system, covering all stages from planning
and development through to after-sales service, with the goal of raising the level of technology in design,
manufacturing, and inspection departments.
The following describes Hitachi's semiconductor quality and reliability system, and presents reliability data
for 4-bit single-chip microcomputer devices.
Quality Assurance
1. Views on Quality and Reliability
At Hitachi the basic views on quality are meeting the individual user’s purchase needs and required quality,
and to be at the satisfied quality level as considered for general marketability. The quality required by the
users can be clearly specified by the contract specifications. If not, the quality required is not always
definite. For both cases, efforts are made to assure the reliability so that the delivered semiconductor
devices can perform their ability in actual operating conditions. To realize such quality in the
manufacturing process, the key points should be: to establish a quality control system in the process, and to
enhance morale for quality.
In addition, the quality of the semiconductor devices required by the users is moving toward higher levels
as the performance of electronic systems on the market is also moving higher and is expanding its size and
application fields. To meet this situation, Hitachi bases its performance on the follow:
1. Build in reliability with the design at the new product development stage.
2. Build in quality at the manufacturing process sources.
3. Execute tougher inspections and reliability confirmations of final products.
4. Increase quality levels with field data feedback.
In order to achieve a major improvement in quality, all departments work together with Hitachi's research
laboratories in the pursuit of semiconductor device quality and reliability.
With the views and methods mentioned above, utmost efforts are made to meet the users’ requirements.
Reliability and Quality Assurance
2
2. Reliability Design of Semiconductor Devices
2.1 Reliability Targets
A reliability target is an important factor in manufacturing and sales as well as performance and price. It is
not practical to rate the reliability target with failure rate at certain common test conditions. The reliability
target is determined by taking the corresponding characteristics of the equipment such as design,
manufacture, inner process quality control, screening and test method, etc., into consideration; other
considerations in which the operating conditions of the equipment in which the semiconductor device is
used in, reliability target of the system, derating applied in the design, operating conditions, and
maintenance.
2.2 Reliability Design
To achieve the reliability required based on reliability targets, design standardization, device design
(including process design and structure design), design review, and reliability test are essential.
1. Design standardization
The establishment of design rules and the standardization of parts, materials, and processes are
necessary. As for the design rules, critical items on quality and reliability are always analyzed at the
circuit design, device design, layout design, etc. Therefore, as long as the standardized processes and
materials are used, the reliability failure risk is extremely small even in newly development devices,
except for the case of including special requirements in functions.
2. Device design
It is important in device design to consider the total balance of process design, structure design, and
circuit and layout design. Especially for cases where new processes and new materials are employed,
technical analysis is thoroughly executed prior to device development.
3. Reliability evaluation by test vehicle
A test vehicle is sometimes called a test pattern. This is a useful method for the design and process
reliability evaluation of ICs and LSIs which have complicated functions.
• Purposes of the test vehicle are as follows:
Verification of fundamental failure mode
Analysis of the relationship between failure mode and manufacturing process conditions
Search of failure mechanism analysis
Establishment of QC points in manufacturing
• Effectiveness of evaluation by the test vehicle are as follows:
Common fundamental failure mode and failure mechanism in devices can be evaluated.
Factors dominating failure mode can be categorized, and comparisons can be made with processes
having been experienced in field.
Ability to analyze the relationship between failure causes and manufacturing factors.
Easy to run tests, etc.
Reliability and Quality Assurance
3
2.3 Design Review
Design review is an organized method that confirms the design has satisfied the required performance
including the specifications of the users and design work, and whether or not technical improvements
accumulated in both the test data of major individual fields and field data are effectively built in. In
addition, from the standpoint of enhancing competitive power in products, the major purpose of design
review is to ensure the quality and reliability of the products. At Hitachi, design review is first performed
from the planning stage of new products and design-modified products. The items considered and
determined at design review are as follows:
1. Description of the products based on specified design documents.
2. From the view of individual specialties, execution of subprogram calculations, experiments, and
investigations are carried out accordingly for any ambiguous information found within the design
documents.
3. Determination of the contents of reliability and the methods based on the design document and
drawings.
4. Checking the process ability of the manufacturing line to achieve the design goal.
5. Discussion on the preparation for production.
6. Planning and execution of subprograms: for any design changes proposed by the individual specialists;
and for tests, experiments, and calculations to confirm the design change.
7. Reference of past failure experiences with similar devices, confirmation of prevention methods and
planning and execution of test programs for their confirmation. These analyses and decisions are made
using separate checklists created depending on the devices.
3. Quality Assurance System of Semiconductor Devices
3.1 Activity of Quality Assurance
The general views of overall quality assurance at Hitachi are as follows:
1. Problems in individual processes should be solved during the process. Therefore, at the final product
stage, potential failure factors have already been eliminated.
2. Feedback of information is needed to ensure satisfied levels of process capabilities.
3. The purpose of quality assurance is to assure the required reliability as a result of the above mentioned.
The following are regards to device design, quality approval at mass production, inner process quality
control, product inspection, and reliability tests.
Reliability and Quality Assurance
4
3.2 Quality Approval
To ensure the quality and required reliability quality approval is executed at the trial production stage of the
device design and the mass production stage based on the reliability design described in section 2.
The views on quality approval are as follows:
1. The third party performs the approval objectively from the standpoint of the customers.
2. Past failure experiences and on-field information are fully considered.
3. Approval is necessary for any changes in design and work.
4. Intensive approval is executed on parts, material, and process.
5. Process capabilities and fluctuation factors are analyzed, and control points are setup at the mass
production stage.
Considering the views mentioned above, quality approval is performed as shown in figure 1.
3.3 Quality and Reliability Control at Mass Production
For quality assurance of products in mass production, quality control is executed with essential division of
function in manufacturing department, quality assurance department (major functions), and other related
departments. The total function flow is shown in figure 2, and the main points are described below.
3.3.1 Quality Control of Parts and Material
As the performance and the reliability of semiconductor devices are increasing the importance in quality
control for materials and parts also increases; for example, crystals, lead frames, fine wires for wire
bonding, and packages for IC production, and materials used in the manufacturing process such as mask
patterns and chemicals. Besides quality approval on parts and materials as stated in section 3.2, the
incoming inspection is also significant in the quality control of parts and materials. The incoming
inspection is performed according to its specifications following purchase specifications and drawings, and
the sampling inspection is executed based mainly on MIL-STD-105D.
The other activities of quality assurance are as follows:
1. An outside-vendor technical information meeting
2. Approval on outside vendors, and guidance of outside vendors
3. Physical chemical analysis and testing
The typical checkpoints of parts and materials are shown in table 1.
Reliability and Quality Assurance
5
Step
Target
specifications
Characteristics approval
Quality approval (1)
Quality approval (2)
Mass
production
Contents Purpose
Characteristics of materials
and parts:
Appearance
Dimension
Heat resistance
Mechanical
Electrical
Other
Reliability test:
Life test
Thermal stress
Moisture resistance
Mechanical stress
Other
Reliability test:
Process check same as
quality approval (1)
Confirmation of
characteristics and
reliability of materials
and parts
Electrical characteristics:
Function
Voltage
Current
Temperature
Other
Appearance and dimension
Confirmation of target
specifications mainly on
electrical characteristics
Confirmation of quality
and reliability in design
Design
trial
production
Materials and
parts approval
Design review
Confirmation of quality
and reliability in mass
production
Figure 1 Flowchart of Quality Approval
3.3.2 Inner Process Quality Control
Inner process quality control is a very important function in quality assurance of semiconductor devices.
The following is a description about the control of semifinal products, final products, manufacturing
facilities, measuring equipment, and manufacturing conditions and submaterials. The quality control in the
manufacturing process is shown in figure 3.
1. Quality control of semifinal products and final products
Potential failure factors of semiconductor devices should be removed in the manufacturing process. To
achieve this, check points are setup in each process, and products which have potential failure factors
are not transferred to the next process. Especially for high reliability semiconductor devices, the
manufacturing line is rigidly selected, and the quality control in the manufacturing process is strictly
executed—rigid checks in each process and lot, 100% inspection to remove failure factors caused by
manufacturing fluctuation, and screening methods such as high temperature aging and temperature
cycling. The considerations of inner process quality control are as follows:
Reliability and Quality Assurance
6
Process Quality Control Method
Lot sampling and
confirmation of
quality level
Confirmation of
quality level
Lot sampling and
confirmation of
quality level
Testing and
inspection
Lot sampling
Confirmation of
quality level
Quality information:
Claim
Field experience
General quality
Report
Inspection of materials and
parts for semiconductor
devices
Manufacturing equipment,
environment, submaterials
and worker supervision
In-process quality control
100% inspection
appearance and electrical
characteristics
Sampling inspection on
appearance and electrical
characteristics
Reliability test
Feedback
information
Materials
and parts
Products
Materials and parts
Inspection
of materials and
parts
Manufacturing
Screening
100% inspection
Lot
assurance
test
Receiving
Shipment
Customer
product
inspection
Figure 2 Flowchart of Quality Control in Manufacturing Process
• Condition control of individual equipment and workers, and sampling checks of semifinal products.
• Proposal and execution of work improvements.
• Education of workers
• Maintenance and improvement of yield
• Recognizing quality problems, and executing countermeasures
• Reports on quality
Reliability and Quality Assurance
7
Process Control Point
Purchase of material
water
Frame
Package
Purpose of Control
Surface oxidation
Inspection on surface
oxidation
Photoresist
Inspection on photoresist
PQC level check
Diffusion
Inspection on diffusion
PQC level check
Evaporation
Inspection on evaporation
PQC level check
Wafer inspection
Inspection on chip
electrical characteristics
Chip scribe
Inspection on chip
appearance
PQC lot judgement
Assembling
PQC level check
Inspection after
assembling
PQC lot judgement
Sealing
PQC level check
Final electrical inspection
Failure analysis
Appearance inspection
Sampling inspection on
products
Receiving
Shipment
Wafer
Oxidation
Photoresist
Diffusion
Evaporation
Wafer
Chip
Assembling
Sealing
Marking
Characteristics; appearance
Appearance; thickness of
oxide film
Dimension; appearance
Diffusion depth; sheet
resistance
Gate width
Characteristics of oxide film
Breakdown voltage
Thickness of vapor film;
Scratches; contamination
Thickness; VTH characteristics
Electrical characteristics
Appearance of chip
Appearance after chip
bonding
Appearance after wire
bonding
Pull strength; compression
width; shear strength
Appearance after assembling
Appearance after sealing
Outline; dimension
Marking strength
Analysis of failures; failure
mode; mechanism
Scratches, removal of crystal
Defective wafers
Assurance of resistance
Pinholes; scratches
Dimension level
check of photoresist
Diffusion status
Control of basic parameters
(VTH, etc.); cleanness of surface;
Prior check VIH breakdown voltage
check
Assurance of standard thickness
Crack; prevention quality assurance
of scribe
Quality check of chip bonding
Quality check of wire bonding
Prevention of open and short circuits
Guarantee of appearance and
dimension
Feedback of analysis information
Figure 3 Example of Inner Process Quality Control
Reliability and Quality Assurance
8
2. Quality control of manufacturing facilities and measuring equipment
The equipment for manufacturing semiconductor devices, which are important factors in determining
quality and reliability, have been remarkably developed to produce the necessary high performance
devices along with improvements in production. At Hitachi, the automation of manufacturing
equipment promotes improvements in manufacturing fluctuation, and regulations have been established
for maintaining the proper operation of high performance equipment and performance of required
functions. As for the maintenance inspection for quality control, both daily inspections based on related
specifications and periodical inspections are performed. During inspection, the specified inspection
points are systematically checked off without allowing any exceptions to pass. For the calibration and
control of measuring equipment, maintenance numbers, specifications, and calibration history are
clearly indicated, and calibration interval control carried out. In inspection, standard equipment
approved by public institutions is used, and the inspection points specified in the standards are checked
in sequence to maintain and improve quality.
3. Quality control of manufacturing conditions and submaterials
The quality and reliability of semiconductor devices are highly affected by the manufacturing process.
Therefore, regulating the manufacturing conditions (i.e., temperature, humidity, and dust) and
submaterials (i.e., gas and pure water) used in the manufacturing process are intensively carried out.
Dust control is described in more detail below.
Dust control is essential for realizing a higher degree of integration and higher reliability of the devices.
At Hitachi, the maintenance and improvement of cleanness within the manufacturing site are executed
by paying intensive attention to buildings, facilities, air-conditioning systems, materials delivered-in,
clothes, work, etc., and including periodical inspections on floating dust within room, falling dust, and
floor dirt.
3.3.3 Final Product Inspection and Reliability Assurance
1. Final product inspection
Lot inspection is done by the quality assurance department for products which were judged as 100%
good after testing, which is the final process in the manufacturing department. Although 100% is
expected of the products sampling inspection is executed to prevent any mixture of failed products by
mistake. The inspection is executed not only to confirm that the products meet the users’ requirements,
but to consider the potential factors. Lot inspection is executed based on MIL-STD-105D.
2. Reliability assurance tests
To assure the reliability of semiconductor devices, periodical reliability tests and reliability tests on
individual manufacturing lots required by the user are performed.
Reliability and Quality Assurance
9
Table 1 Quality Control Checkpoints of Material and Parts (Example)
Material/Parts Control Items Checkpoints
Wafer Appearance Damage and contamination on surface
Dimension Flatness
Sheet resistance Resistance
Defect density Number of defects
Crystal axis
Mask Appearance Number of defects
Scratches
Dimension Dimension level
Resistoration
Gradation Uniformity of gradation
Fine wire for wire
bonding Appearance Contamination; scratches; bendings; twists
Dimension
Purity Purity level
Elongation ratio Mechanical strength
Frame Appearance Contamination; scratches
Dimension Dimension level
Processing precision
Plating Bondability; solderability
Mounting characteristics Heat resistance
Ceramic package Appearance Contamination; scratches
Dimension Dimension level
Leak resistance Airtightness
Plating Bondability; solderability
Mounting characteristics Heat resistance
Electrical characteristics
Mechanical strength Mechanical strength
Plastic Composition Characteristics of plastic material
Electrical characteristics
Thermal characteristics
Molding performance Molding performance
Mounting characteristics Mounting characteristics
Reliability and Quality Assurance
10
Customer
Claim
(failures and information)
Sales dept.
Sales engineering dept.
Quality assurance dept.
Design dept.
Manufacturing dept.
Report
Quality assurance dept.
Sales engineering dept.
Reply
Report
Customer
Failure analysis
Countermeasures and
execution of
countermeasures
Follow-up and confirmation
of countermeasure execution
Figure 4 Process Flowchart of Field Failure
Reliability and Quality Assurance
11
4. Reliability Design
Major advances are being made in IC and LSI design and process technologies in the pursuit of higher
reliability. Specific examples are the setting of target characteristics, reliability design for circuits and
devices, process technologies such as crystal processing, epitaxial growth, impurity diffusion, ion
implantation, auto-etching, surface stabilization, electrodes, bonding, and sealing, manufacturing process
control techniques, as well as techniques for inspection, reliability evaluation, failure analysis, and so on.
Higher reliability can only be achieved by raising the overall level of these technologies.
Reliability design and its advantages with regard to processes are discussed below.
4.1 Surface Stabilization Technology
Surface degradation, one of the major failure modes for semiconductor devices, is of two kinds, according
to the degradation parameters and mechanism. In one case, the effects are due to the conductivity of the Si-
SiO2 surface phase, as with PN junction reverse withstand voltage degradation, and changes over time in
the threshold voltage (VTH) and mutual conductance in MOS devices, while in the other case, the effects are
due to surface carrier recombination, as with current amplification factor degradation or low-frequency
noise degradation.
There are considered to be four major causes of surface degradation, as follows (see figure 5):
Crack→inter-layer shorting Coating defect, crack,
pin hole→Al corrosion PSG: P elution→A1 corrosion,
characteristic deterioration
Poly-Si wiring (polysilicon)
SiO2
Surface peeling
1st passivation
Na contaminationPin holes→
penetration by contaminants
Si substrate
2nd passivation
Al wiring
Inter-layer
insulating film Diffusion
layer
Figure 5 Surface Protective Film Divisions and Problems
• Mobile ions (such as Na+) that infiltrate the first passivation film from the manufacturing process or the
sealing material
• The surface charge (Qss) and surface level at the Si-SiO2 boundary
• Pin hole flaws in the passivation film
• A leakage charge on the second passivation film due to an electric field
Reliability and Quality Assurance
12
There may also be a problem with mobile ion contamination at levels not previously a problem due to the
high degree of integration and sophistication of the devices, and cases of extremely localized
contamination, such as passivation flaws, that may result in fatal defects.
To achieve Si surface stabilization, therefore, it is necessary to improve the getter effect with respect to
mobile ions in the first passivation film, create a flawless film with surface stability and precision by means
of a clean process, and have a threshold voltage (VTH) capable of withstanding a leakage charge.
Meanwhile, the second passivation film plays an extremely important role in improving the reliability
(moisture resistance) of the plastic sealing material, and requires the following characteristics.
• The ability to prevent the penetration of moisture and contaminants from outside, and contaminating
ions from the resin material itself
• Passivation film quality capable of withstanding thermal stress in the resin material
• A low flaw density
In this regard, Hitachi is undertaking research and development in the areas of first and second passivation
films and inter-layer insulating film, to improve the reliability of various semiconductor devices. Some of
these improvements are described below.
1. PSG (phospho-silicate glass) for use as first and second passivation and inter-layer insulating film has
been improved to provide better prevention of external contamination (improving the getter effect with
respect to NA+ ions) and moisture resistance (see figure 6).
65°C 95% RH1000hr
Al Corrosion Defect Rate (Relative Values)
Sample
plastic-packaged ICs (Specification A)
(Specification B)
(Specification C)
Second Passivation Flaw Density (Relative Values)
11010
2103104
10
102
103
1
Figure 6 Passivation Flaw Density and Moisture Resistance
2. Clean, flaw-free process:
This is especially important for the first passivation film, and the aim is to develop cleaner processing,
including higher purity of process materials such as the photoresist, cleaning agent, and vapor
deposition Al, cleaner oxidization oven silica tubes, and also a flaw-free process, including improved
vapor deposition methods, higher photomask quality, improved wafer handling methods, and the
prevention of dust in the process.
Reliability and Quality Assurance
13
3. Leakage charge countermeasures:
The design threshold voltage (VTH) is increased by the formation of channel stopper layer using ion
implantation technology, or the use of a thicker passivation film.
4. Process control:
In addition to the BT (bias-temperature) method of process control relating to mobile ions, Hitachi also
carries out [INPURA ??] quantity control using special MOS elements, and automatic film thickness
measurement by optical means during polysilicon film creation.
4.2 Electrode Formation and Assembly Technology
These processes are represented in chip electrode formation, die bonding which fixes the chip in the
package, and wire bonding which connects the chip electrodes to the leads. The technical level of these
processes has a great effect on reliability. The main failure modes that occur in these processes are
summarized below.
• Disconnection or shorting due to electromigration in the Al vapor deposition wiring, or disconnection in
areas with a level difference
• Bonding disconnection, semi-disconnection, or shorting
• Chip cracking
• Increased resistance or disconnection due to a compound between the Au and Al metals
• Bonding wire fatigue and disconnection due to repeated thermal stress
• Increased thermal resistance and chip separation with soft solder die bonding
Hitachi is engaged in appropriate structural design to cope with these causes of defects, and incorporates
reliability into the manufacturing process. As regards bonding, for example, Hitachi was quick to develop
a computer-controlled, fully automatic thermocompression wire bonding system, which is being used on
the production line to ensure stable quality.
Regarding process quality control, in addition to the conventional visual inspection used in pre-sealing
inspection, Hitachi carries out contour control of the fine wiring in the chip, and bonding contour control,
using a scanning electron microscope.
4.3 Plastic Sealing Technology
Semiconductor device sealing methods consist of hermetic sealing using metal, ceramic, or low-melting-
point glass, and plastic sealing using plastic material. Hermetic sealing has a long history, and there are no
particular problems regarding materials or sealing technology. Leak tests have also been established, and
airtightness is guaranteed by conducting major and minor leak tests. Plastic-packaged semiconductor
devices, meanwhile, which came about in the pursuit of lower cost, have come to play a major role in
extending the range of areas in which semiconductors are used, and are now the mainstream type. The
features of plastic-packaged semiconductor devices in terms of reliability are outlined below.
The main failure modes of plastic-packaged semiconductor devices are disconnection due to corrosion of
the aluminum used in electrode wiring, and wire bonding disconnection.
Reliability and Quality Assurance
14
The main cause of the former is moisture that penetrates via the interface between the plastic and the lead
frame, or moisture that permeates the plastic material itself. This moisture penetration is accelerated by
impurity ions extracted from the plastic, voltages between electrode wires, and humidity, corroding the
electrode wiring and, if there is a large amount of penetrating moisture, finally leading to disconnection.
With the latter failure mode, temperature variations result in internal stress because of the different
coefficients of thermal expansion and elastic coefficients of the materials of which the device is composed
(Si chip, bonding wire, lead frame, and plastic). If the weakest point, the pointing wire, cannot withstand
this stress, disconnection will result.
Various improvements have been adopted from a system standpoint which combines improvements that
affect the electrical characteristics of the device with improvements in plastic materials, mold technology,
structural design, and surface stabilization film, in addition to In dealing with the two main failure modes
described above.
Reliability Test Data of Microcomputer
Reliability of Microcomputer Devices
1. Structure
Four-bit single-chip microcomputer devices are available in plastic and ceramic packages. Figure 1 shows
examples of the package structure.
The structure of COMS 4-bit single-chip microcomputer devices varies depending on the manufacturing
process and circuit configuration. There are generally two kinds of gates, Al gates and Si gates. Hitachi
mainly uses devices with an Si gate structure, because the alignment of the gate parts is comparatively
precise and easy to implement, allowing high reliability to be achieved.
Plastic
Lead
Chip
Bonding wire
Lead
Tab
Bonding wire
Chip
Plastic
Plastic DIP Flat Plastic Package
Figure 1 Package Structure
Drain
Source
SiO2
PSG Al Gate
P-Well
P+N+N+P+
(FET2 only)
FET1
FET2
G
G
D
D
S
S
P-channel
EMOS
N-channel
EMOS
Si-Gate CMOS
Figure 2 Chip Structure and Basic Circuit
Reliability Test Data of Microcomputer
2
2. Reliability Data
2.1 HMCS400 Series Reliability Test Result
The reliability test results of HMCS400 Series are shown in table 1 to table 4. The data is classified by
package type, DIP and QFP.
Table 1 Operation Life (Mask ROM): (Condition: VCC = 6.0 V, Ta = 125°C)
Chip Package Samples Component Hours (C.H.) Failures
HD404019R DIP 45 45,000 0
QFP 45 45,000 0
HD404304 DIP 45 45,000 0
HD404439 QFP 45 45,000 0
HD404618 QFP 45 45,000 0
TQFP 45 45,000 0
HD404678 QFP 45 45,000 0
HD404719 QFP 45 45,000 0
HD404729 DIP 45 45,000 0
QFP 45 45,000 0
HD404222 DIP 45 45,000 0
SOP 45 45,000 0
HD404318 DIP 45 45,000 0
QFP 45 45,000 0
HD404328 DIP 45 45,000 0
QFP 45 45,000 0
HD404339 DIP 45 45,000 0
HD404449 QFP 45 45,000 0
TQFP 45 45,000 0
HD404459 QFP 45 45,000 0
HD404629R QFP 45 45,000 0
TQFP 45 45,000 0
HD404818 QFP 45 45,000 0
TQFP 45 45,000 0
HD404829R QFP 45 45,000 0
TQFP 45 45,000 0
Reliability Test Data of Microcomputer
3
Table 2 Moisture Resistance (Mask ROM): High Temperature High Humidity Storage
(Condition: 65°C, 95%RH)
Chip Package 168 Hours 500 Hours 1000 Hours
HD404019R DIP 0/116 0/116 0/116
QFP 0/77 0/77 0/77
HD404304 DIP 0/116 0/116 0/116
HD404618 QFP 0/77 0/77 0/77
TQFP 0/45 0/45 0/45
HD404729 DIP 0/116 0/116 0/116
QFP 0/77 0/77 0/77
HD404222 DIP 0/45 0/45 0/45
SOP 0/45 0/45 0/45
HD404318 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD404328 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD404339 DIP 0/45 0/45 0/45
HD404449 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404459 QFP 0/45 0/45 0/45
HD404629R QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404818 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404829R QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
Reliability Test Data of Microcomputer
4
Table 2 Moisture Resistance (Mask ROM) (cont): Pressure Cooker Test (Condition: 121°C,
202.65 kPa (2 atm))
Chip Package 40 Hours 60 Hours 100 Hours
HD404019R DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404618 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404729 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404222 DIP 0/22 0/22 0/22
SOP 0/22 0/22 0/22
HD404318 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404328 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404339 DIP 0/22 0/22 0/22
HD404449 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404459 QFP 0/22 0/22 0/22
HD404629R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404818 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404829R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
Reliability Test Data of Microcomputer
5
Table 2 Moisture Resistance (Mask ROM) (cont): High Temperature, High Humidity Bias
(Condition: 85°C, 85%RH, VCC = 5.5 V)
Chip Package 168 Hours 500 Hours 1000 Hours
HD404618 QFP 0/22 0/22 0/22
TQFP 0/32 0/32 0/32
HD404729 DIP 0/22 0/22 0/22
HD404019R DIP 0/32 0/32 0/32
QFP 0/32 0/32 0/32
HD404222 DIP 0/32 0/32 0/32
SOP 0/32 0/32 0/32
HD404318 DIP 0/32 0/32 0/32
QFP 0/32 0/32 0/32
HD404328 DIP 0/32 0/32 0/32
QFP 0/32 0/32 0/32
HD404339 DIP 0/32 0/32 0/32
HD404449 QFP 0/32 0/32 0/32
TQFP 0/32 0/32 0/32
HD404459 QFP 0/32 0/32 0/32
HD404629R QFP 0/32 0/32 0/32
TQFP 0/32 0/32 0/32
HD404818 QFP 0/32 0/32 0/32
TQFP 0/32 0/32 0/32
HD404829R QFP 0/32 0/32 0/32
TQFP 0/32 0/32 0/32
Reliability Test Data of Microcomputer
6
Table 3 Temperature Cycling (Mask ROM): (Condition: –55°C to +150°C)
Chip Package 10 Cycles 100 Cycles 200 Cycles
HD404019R DIP 0/135 0/45 0/45
QFP 0/90 0/45 0/45
HD404304 DIP 0/135 0/45 0/45
HD404618 QFP 0/135 0/45 0/45
TQFP 0/45 0/45 0/45
HD404678 QFP 0/90 0/45 0/45
HD404729 DIP 0/215 0/45 0/45
QFP 0/90 0/45 0/45
HD404222 DIP 0/45 0/45 0/45
SOP 0/45 0/45 0/45
HD404318 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD404328 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD404339 DIP 0/45 0/45 0/45
HD404449 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404459 QFP 0/45 0/45 0/45
HD404629R QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404818 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD404829R QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
Reliability Test Data of Microcomputer
7
Table 4 High Temperature, Low Temperature, Storage (Mask ROM): High Temperature
Storage (Condition: +150°C)
Chip Package 168 Hours 500 Hours 1000 Hours
HD404019R DIP 0/22 0/22 0/22
HD404304 DIP 0/22 0/22 0/22
HD404618 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404678 QFP 0/22 0/22 0/22
HD404729 DIP 0/22 0/22 0/22
HD404222 DIP 0/22 0/22 0/22
SOP 0/22 0/22 0/22
HD404318 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404328 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404339 DIP 0/22 0/22 0/22
HD404449 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404459 QFP 0/22 0/22 0/22
HD404629R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404818 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404829R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
Reliability Test Data of Microcomputer
8
Table 4 High Temperature, Low Temperature, Storage (Mask ROM) (cont): Low Temperature
Storage (Condition: –55°C)
Chip Package 168 Hours 500 Hours 1000 Hours
HD404618 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404729 DIP 0/22 0/22 0/22
HD404019R DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404222 DIP 0/22 0/22 0/22
SOP 0/22 0/22 0/22
HD404318 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404328 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD404339 DIP 0/22 0/22 0/22
HD404449 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404459 QFP 0/22 0/22 0/22
HD404629R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404818 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD404829R QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
Reliability Test Data of Microcomputer
9
2.2 4-Bit ZTAT Microcomputer Reliability Test Result
The reliability test results of four-bit ZTAT microcomputer are shown in table 5 to table 10.
Table 5 Operation Life (ZTAT): (Condition: VCC = 5.5 V, Ta = 125°C)
Chip Package Samples Component Hours (C.H.) Failures
HD4074019 DIP 45 45,000 0
QFP 32 32,000 0
HD4074308 DIP 45 45,000 0
HD4074618 QFP 45 45,000 0
TQFP 45 45,000 0
HD4074719 QFP 45 45,000 0
HD4074729 DIP 45 45,000 0
HD4074224 DIP 45 45,000 0
SOP 45 45,000 0
HD4074318 DIP 45 45,000 0
QFP 45 45,000 0
HD4074329 DIP 45 45,000 0
QFP 45 45,000 0
HD4074339 DIP 45 45,000 0
HD4074449 QFP 45 45,000 0
HD4074629 QFP 45 45,000 0
HD4074818 QFP 45 45,000 0
TQFP 45 45,000 0
HD4074829 QFP 45 45,000 0
Reliability Test Data of Microcomputer
10
Table 6 Moisture Resistance (ZTAT): High Temperature, High Humidity Storage
(Condition: 65°C, 95%RH)
Chip Package 168 Hours 500 Hours 1000 Hours
HD4074308 DIP 0/116 0/116 0/116
HD4074618 QFP 0/77 0/77 0/77
TQFP 0/45 0/45 0/45
HD4074719 QFP 0/77 0/77 0/77
HD4074729 DIP 0/116 0/116 0/116
QFP 0/77 0/77 0/77
HD4074224 DIP 0/45 0/45 0/45
SOP 0/45 0/45 0/45
HD4074318 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD4074329 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD4074339 DIP 0/45 0/45 0/45
HD4074449 QFP 0/45 0/45 0/45
HD4074629 QFP 0/45 0/45 0/45
HD4074818 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD4074829 QFP 0/45 0/45 0/45
Reliability Test Data of Microcomputer
11
Table 6 Moisture Resistance (ZTAT) (cont): Pressure Cooker Test (Condition: 121°C, 202.65
kPa (2 atm))
Chip Package 40 Hours 60 Hours 100 Hours
HD4074019 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074308 DIP 0/22 0/22 0/22
HD4074618 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD4074719 QFP 0/22 0/22 0/22
HD4074729 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074224 DIP 0/22 0/22 0/22
SOP 0/22 0/22 0/22
HD4074318 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074329 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074339 DIP 0/22 0/22 0/22
HD4074449 QFP 0/22 0/22 0/22
HD4074629 QFP 0/22 0/22 0/22
HD4074818 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD4074829 QFP 0/22 0/22 0/22
Reliability Test Data of Microcomputer
12
Table 7 Temperature Cycling (ZTAT): (Condition: –55°C to +150°C)
Chip Package 10 Cycles 100 Cycles 200 Cycles
HD4074019 DIP 0/115 0/45 0/45
QFP 0/90 0/45 0/45
HD4074308 DIP 0/135 0/45 0/45
HD4074618 QFP 0/90 0/45 0/45
TQFP 0/45 0/45 0/45
HD4074719 QFP 0/90 0/45 0/45
HD4074729 DIP 0/135 0/45 0/45
QFP 0/45 0/45 0/45
HD4074224 DIP 0/45 0/45 0/45
SOP 0/45 0/45 0/45
HD4074318 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD4074329 DIP 0/45 0/45 0/45
QFP 0/45 0/45 0/45
HD4074339 DIP 0/45 0/45 0/45
HD4074449 QFP 0/45 0/45 0/45
HD4074629 QFP 0/45 0/45 0/45
HD4074818 QFP 0/45 0/45 0/45
TQFP 0/45 0/45 0/45
HD4074829 QFP 0/45 0/45 0/45
Reliability Test Data of Microcomputer
13
Table 8 High Temperature, Low Temperature, Storage (ZTAT): High Temperature Storage
(Condition: +150°C)
Chip Package 48 Hours 168 Hours 500 Hours 1000 Hours
HD4074308 DIP 0/160 0/22 0/22 0/22
HD4074408 DIP (ceramic) 0/255 0/104 0/104 0/104
DIP 0/260 0/44 0/44 0/44
QFP 0/103 0/32 0/32 0/32
HD4074618 QFP 0/160 0/22 0/22 0/22
TQFP 0/100 0/22 0/22 0/22
HD4074719 QFP 0/140 0/22 0/22 0/22
HD4074729 DIP 0/240 0/22 0/22 0/22
HD4074224 DIP 0/100 0/22 0/22 0/22
SOP 0/100 0/22 0/22 0/22
HD4074318 DIP 0/100 0/22 0/22 0/22
QFP 0/100 0/22 0/22 0/22
HD4074329 DIP 0/100 0/22 0/22 0/22
QFP 0/100 0/22 0/22 0/22
HD4074339 DIP 0/100 0/22 0/22 0/22
HD4074449 QFP 0/100 0/22 0/22 0/22
HD4074629 QFP 0/100 0/22 0/22 0/22
HD4074818 QFP 0/100 0/22 0/22 0/22
TQFP 0/100 0/22 0/22 0/22
HD4074829 QFP 0/100 0/22 0/22 0/22
Reliability Test Data of Microcomputer
14
Table 8 High Temperature, Low Temperature, Storage (ZTAT) (cont): Low Temperature
Storage (Condition: –55°C)
Chip Package 168 Hours 500 Hours 1000 Hours
HD4074019 DIP 0/22 0/22 0/22
HD4074308 DIP 0/22 0/22 0/22
HD4074618 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD4074719 QFP 0/22 0/22 0/22
HD4074729 DIP 0/22 0/22 0/22
HD4074224 DIP 0/22 0/22 0/22
SOP 0/22 0/22 0/22
HD4074318 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074329 DIP 0/22 0/22 0/22
QFP 0/22 0/22 0/22
HD4074339 DIP 0/22 0/22 0/22
HD4074449 QFP 0/22 0/22 0/22
HD4074629 QFP 0/22 0/22 0/22
HD4074818 QFP 0/22 0/22 0/22
TQFP 0/22 0/22 0/22
HD4074829 QFP 0/22 0/22 0/22
Reliability Test Data of Microcomputer
15
Table 9 Mechanical and Environment Test Results
DIP QFP TQFP SOP
Test Test Conditions Samples Failures Samples Failures Samples Failures Samples Failures
Thermal
shock 0°C to 100°C 10 cycles 210 0 150 0 22 0 22 0
Soldering
heat 260°C, 10 sec 246 0 Refer table 11
Solderability 230°C, 5 sec, rosin flux 132 0 88 0 22 0 22 0
Salt water
spray 35°C, NaCl 5%,
24 hours
110 0 66 0 22 0 22 0
Drop test 75 cm, maple board
3 times
44 0 40 0 22 0 22 0
Lead
integrity Stretching
500 g, 10 sec (DIP)
250 g, 10 sec
(QFP, TQFP, SOP)
60 0 40 0 22 0 22 0
Bending
250 g, 90°, 3 times (DIP)
250 g, 90°, 1 time
(QFP, TQFP, SOP)
160 0 22 0 22 0 22 0
Reliability Test Data of Microcomputer
16
Table 10 Soldering Heat Resistance Infrared Reflow (Conditions: 235 °C, 10 Seconds) and Solder
Dip (Conditions: 260°C, 10 Seconds)
Chip Package Pre Conditions Hours Samples Failures
HD404019R QFP 85°C, 85%RH 24 hours 22 0
HD404439 QFP 85°C, 85%RH 48 hours 22 0
HD404618 QFP 85°C, 85%RH 48 hours 22 0
TQFP 85°C, 85%RH 48 hours 22 0
HD404729 QFP 85°C, 85%RH 48 hours 22 0
HD404222 SOP 85°C, 85%RH 96 hours 22 0
HD404449 QFP 85°C, 85%RH 48 hours 22 0
TQFP 85°C, 85%RH 48 hours 22 0
HD404629 QFP 85°C, 85%RH 48 hours 22 0
TQFP 85°C, 85%RH 48 hours 22 0
HD4074618 QFP 85°C, 85%RH 48 hours 22 0
TQFP 85°C, 85%RH 24 hours 22 0
HD4074224 SOP 85°C, 85%RH 24 hours 22 0
HD4074449 QFP 85°C, 85%RH 24 hours 22 0
TQFP 85°C, 85%RH 24 hours 22 0
HD4074629 QFP 85°C, 85%RH 24 hours 22 0
TQFP 85°C, 85%RH 24 hours 22 0
3. Precaution
3.1 Storage
The following lists preferable measures for storing semiconductor devices to prevent the possibility of
breakage and the deterioration of its electrical characteristics, solderability, and appearance.
1. Store at an ambient temperature of 5° to 30°C with a relative humidity of 40% to 60%.
2. Store in an environment of clean air, free from dust and active gases.
3. Store the devices within containers which do not induce static electricity.
4. Keep the devices free of any physical loads.
5. If the devices are to be stored for a long period of time, store the devices of which the leads have not yet
been bent. The bent leads of these devices will corrode at the areas of bending during its storage.
6. If the device is not in a sealed container, store it in a cool, dry, dark, and ductless area. Assemble the
devices within 5 days after they have been unpacked. Storing devices in nitrogen gas is desirable. Using
dry nitrogen gas with a dew point at –30°C or lower allows the devices to be stored for up to 20 days.
Unpacked devices must not be stored for more than 3 months.
Reliability Test Data of Microcomputer
17
Be particularly careful when surface mount packages are soldered by a process that heats the entire
packages, because the packages may crack due to absorption of moisture.
Care must be taken to not allow condensation to occur during storage due to rapid temperature changes.
3.2 Transportation
As with storage methods, general precautions for other electronic component parts are applicable for the
transportation of semiconductors, mounted semiconductor units, and other similar systems. In addition, the
following considerations must also be given:
1. Use containers or jigs which will not induce static electricity as the result of vibration during
transportation. It is preferable to use an electrically conductive container or aluminium foil.
2. In order to prevent the devices from being damaged by static-electricity-induced clothes, workers
should be properly grounded with a resistor while handling the devices. A resistor of about 1 MΩ must
be provided for the worker to protect the devices from electric shock. Figure 3 illustrates measured data
concerning static electricity on a human body.
3. When transporting the printed circuit boards of the mounted semiconductor devices, preventive
measures against static electricity must be taken; for example, voltage buildup is prevented by shorting
the terminal circuits. When a conveyor belt is used, prevent the conveyor belt from being electrically
charged by applying some surface conduction.
4. When transporting semiconductor devices or printed circuit boards, mechanical vibration and shock
must be minimizied.
Electric charges on the body and clothing varies greatly depending
on the type of clothing, footwear, build, ambient temperature and
humidity, and so on. Some actual examples are given below.
Actual Examples of Body Charges
Conditions Max. Voltage Ambient Conditions
(1)
(2)
(3)
(4)
a Shirt, 100% cotton
b Shirt, PVC synthetic fiber
a Shirt, PVC synthetic fiber
b Shirt, 100% cotton
a Bare skin
b Shirt, 100% cotton
a Bare skin
b Shirt, PVC synthetic fiber
+ 4,900V
– 13,000V
– 3,500V
+ 7,200V
– 410V
+ 980V
+ 3,200V
+ 7,000V
Ambient
temperature: 20°C
Relative
humidity: 40%
a, b: Clothing
c, d: Metal tub
a
cbbd
Method of Measuring Body Charge
Insulating material Steel sheet
Static capacitance between steel sheet and metal tub: 50 pF
Insulation resistance: 1.5 x 1012 Ω
Article a is put on over the bare skin, and article b over this.
During this operation, the subject is grounded.
The ground wire is removed, then article b is taken off and
thrown into tub b. In these examples, the potential at this
point is measured.
The "bare skin" case, a, in (3) and (4) in the table refers to
the case where one article of clothing is worn and friction
occurs directly between the body and the clothing.
Figure 3 Examples of Body Charge Measurements
Reliability Test Data of Microcomputer
18
3.3 Handling during Measurement
Avoid static electricity, noise, and surge voltages when measuring semiconductor devices. During
transportation or storage, damage to devices can be prevented by shorting their terminal circuits to equalize
their electrical potential. However, when the devices are to be measured or mounted, these shorted
terminals are left open to introduce the possibility of accidentally being touched by someone or by
measuring equipment, work benches, soldering irons, conveyor belts, etc. The devices will fail if they come
in contact with something which leaks current or carries a static charge. Be careful not to allow curve
tracers, synchroscopes, pulse generator, dc stabilizing power supply units, etc., to leak current from their
terminals or housings to the devices.
While the devices are being tested, take special care to not apply a surge voltage from the tester, to attach a
clamping circuit to the tester, and to not allow any abnormal voltages through bad contacts from the current
source.
During measurement, avoid miswirings and short circuits. When inspecting a printed circuit board, make
sure that no soldering bridges or foreign matter exist before turning on the power switch.
Since these precautions depend upon the types of semiconductor devices, contact Hitachi for further details.
3.4 Special handling precautions
1. Be sure to observe the absolute maximum ratings and to use a device under derated conditions, if
possible.
2. Be sure to minimize any thermal stress as well as humidity stress.
3. Do not apply excessive force between the leads and the chip housing when forming leads.
4. Be sure to avoid applying static electricity while handling, transporting or storing a device. Ensure
complete grounding.
5. Avoid introducing surge from a tester to a chip during measurement.
6. No specification should be exceeded by applying a surge voltage/current or static electricity to a chip,
even after system assembly is completed.
7. Take countermeasures, such as fail-safe provisions, according to the application when designing a
microcomputer system.
8. Be sure to carry out system debugging using a parts-mounted test.
9. Refer to any application notes described in the respective data sheets when using a microcomputer
device with on-chip EPROM.
10.Placing a device of the plastic package type in a high electric field may cause surface leakage due to
charging, resulting in incorrect operation. Avoid using a device where there is a high electric field. Be
sure to cover the package surface with a conductive shield plate if a device is used in a high electric
field.
11.Contact our technical engineers beforehand when using a device under special operating conditions.
Reliability Test Data of Microcomputer
19
Table 11 No.1 Solderability Defects in Storage
Type of defect Description Remedy Classification
Solderability
defects during
storage
A cardboard magazine and black
rubber were used for storing devices,
causing the color of the leads to
change as well as defective
solderability.
The surface of the lead formed sulfides
due to sulfurous compounds in the
magazine used for storage.
Be sure to use a storage
case and magazine for
storing devices which do
not react with lead
materials. Especially,
avoid any sulfurous
compounds.
Other (storage)
Table 12 No.2 Static Discharge Breakdown during Transportation and Storage
Type of defect Description Remedy Classification
Static discharge
breakdown during
transportation and
storage
During the production process of
a device, a normal device
became defective after board
assembly before being mounted.
Devices were stacked, and the
device was destroyed by the
application of the charge
accumulated on a capacitor
facing the device.
(1) Be sure to insert insulation
between the device boards
before transportation.
(2) Discharge capacitors
before transportation.
(3) Separate the device
boards.
Other (storage,
transportation)
Table 13 No.3 Static Discharge Breakdown during Measurement
Type of defect Description Remedy Classification
Static discharge
breakdown during
measurement
During automatic device
measurement, a static electrical
charge accumulated on the
plastic guide rails while sliding
the devices. This charge was
discharged by the measuring
head, destroying the input circuit
of the device.
This failure occurred when the
humidity was low; it did not
occur at high humidity.
(1) The plastic rails were
replaced with metallic rails,
which would not cause
static electricity.
(2) The guide rails were
grounded.
Other
(measurement)
Reliability Test Data of Microcomputer
20
Table 14 No.4 Breakdown during Measurement
Type of defect Description Remedy Classification
Breakdown during
measurement (1) While measuring output
voltage VOL from the bus
driver, applying a constant
input current, IOL, (100 to 300
mA) destroyed a device.
(2) While measuring the
withstand voltage (for ICs
with a strength of 70 V or
more), applying a current (1
mA) generated a similar
failure.
(3) While measuring the
withstand voltage, noise was
superimposed on the
constant-current source.
This caused current to enter
the negative range, which
also destroyed the device.
(1) Use voltage application
instead of current
application.
(2) Apply a voltage equivalent
to the withstand voltage for
current measurement.
Other
(measurement)
3.5 Application Notes for the Surface-Mount Packages
1. Temperature distribution on the package
The infrared reflow method is most generally used for surface mounting. Since the package is made of
black epoxy resin, the area directly exposed to infrared radiation is most likely to absorb heat, which
will increase the temperature locally compared to other areas, if no countermeasures are taken. In the
example shown in figure 4, the temperature of the area exposed to infrared radiation is 20 to 30 °C
higher than the soldered leads, and 40 to 50 °C higher than the bottom surface of the package.
Performing solder mounting under such conditions may cause cracks in the package.
Reliability Test Data of Microcomputer
21
Temperature (°C)
60s
100
150
200
250
300
30s
Time (sec)
T1
T1
T2
T2
T3
T3
(Epoxy resin) Infrared
(Thermocouple)
(Solder)
Figure 4 Typical Temperature Profile when Mounting Solder with Infrared Heating
2. Humidity absorption of the package
Humidity absorption by the epoxy resin used for a plastic package is difficult to avoid in a high-
humidity environment. A large amount of absorbed water rapidly vaporizes during the solder mounting
process. This could cause detachment at the surface between the resin and the lead frame. In the worst
case, it may cause the package to crack. Therefore, devices, especially of the thin-package type, should
be stored in a dry box.
To remove any water absorbed during transportation, storage or handling, we recommend baking at 125
°C for 16 to 24 hours before performing the solder mounting process.
3. Temperature increase and refrigeration
The solder dip method is one of the solder mounting procedures used for electronic parts. The heat-
transfer coefficient with this method is of an order greater than with the reflow method, causing a larger
thermal shock to plastic products. As this may cause package cracking and decreased humidity
resistance, use of this method is limited to certain products.
Note that rapid temperature increases and refrigeration should also be avoided even if the reflow
method is used. Be sure to set an appropriate condition at a target of 4 °C/sec or less.
4. Contamination around the package
A rosin-type flux is recommended for use in soldering. A chlorine-type flux is likely to remain on the
package, which can reduce the reliability of the product. Avoid using flux of this type.
If any flux, including rosin-type flux, remains on the package, leads can become corroded. Therefore,
thorough cleaning and removal are required. Note that some detergents may erase marks printed on the
package if in contact with the package for a long period of time.
Reliability Test Data of Microcomputer
22
General precautions have been outlined above. Note that the reflow conditions may vary with the shape
of the package and printed-circuit board, the type of reflow and equipment. For reference, Figure 5
shows reflow conditions using a QFP infrared reflow chamber. The numbers in this figure refer to the
temperatures at the package resin. Be sure to limit the temperature at the lead section to a maximum of
260 °C for no longer than 10 seconds. Also ensure that the temperature difference between the surface
and reverse side of the resin is 10 °C or less.
Although the infrared reflow method is most typically used, the vapor-phase reflow method is also used.
Figure 6 shows the recommended reflow conditions when using a vapor-phase reflow chamber.
Whether the solder dip method can be used depends on the product type; contact our sales engineers for
details.
Figure 7 shows the recommended conditions for the solder dip method.
For small and thin packages of the surface-mount type, refer to the separate manuals for the mounting
procedure. Contact our sales engineers for details.
10 sec. (max.)
140 to 160 °C
235 °C (max.)
Temperature
Approx.
60 sec.
1 to 5 °C/sec.
1 to 4 °C/sec.
Time
Figure 5 Recommended Infrared Reflow Conditions
30 sec. (max.)
140 to 160 °C
215 °C
Temperature
Approx.
60 sec.
1 to 5 °C/sec.
Time
Figure 6 Recommended Vapor-Phase Reflow Conditions
Reliability Test Data of Microcomputer
23
Time
Baking (1 to 3 min.) Dipping
(2 to 4 sec.)
Tmax = 260 °C
Cooling
Solder melting point
Natural air cooling or forced air cooling
Surface temperature
of the substrate
80 to 150 °C
Figure 7 Recommended Solder Dip Conditions
Programmable ROM (ZTAT)
Microcomputer
ZTATTM Microcomputer with Built-in Programmable ROM
1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM
(1) Precautions for writing to programmable ROM built in ZTATTM microcomputer
In the ZTATTM microcomputer with built-in plastic mold one-time programmable ROM, incomplete
electrical connection between the PROM writer and socket adapter causes writing errors and, makes the
computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points:
(a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with
each other (neither opened nor shorted), before starting the writing process.
(b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no
foreign substance on the contact pin of the socket adapter, which may cause improper electrical
connection.
(c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical
connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it
again.
(d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to
improper electrical connection, carry out the writing process again according to above steps (a), (b), and
(c).
(e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing.
(f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e).
(g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM
writer, socket adapter, etc. for defects.
(h) If any problem is noticed in the written program or in the program after being left at a high temperature,
consult our technical staff.
(2) Precautions when new PROM writer, socket adapter or IC is used
When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing
may become impossible because the noise, overshoot, timing or other electrical characteristics may be
inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points
before starting the writing process.
(a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer,
power source current capacity of VPP, and current consumption at the time of writing to IC are provided
with sufficient margin.
(b) To prevent breakdown of the IC, check that the power source voltage between GND-VCC and GND-
VPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter
are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n
Programmable ROM (ZTAT) Microcomputer
2
connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs,
recheck the power source damping resistance of capacity.
(c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the
socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting
terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power
sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low
inductance.
(d) For stable writing and reading operation, insert the IC into the socket adapter and check the input
waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent
ICs have increased in speed, caution should be exercised against the noise to the power source or
address due to crosstalk from the output data terminal. To avoid these problems, inserting a low
inductance capacitor between the GND and power source or inserting a damping resistance to the output
data terminal is effective.
(e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming
all ICs inserted into the socket adapter.
(f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check
performed to prevent erroneous writing due to improper electrical connection of the power source, etc.,
rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases
due to erroneous writing because of improper connection. Be sure to check the electrical connection
between the PROM writer and socket adapter and IC.
(g) If any abnormality is noticed while checking a written program, consult our technical staff.
2. Programming of Built-in programmable ROM
The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM.
For details on the procedure for setting up PROM mode, see the PROM mode schematic for the individual
product actually being used.
Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256.
Using a socket adapter for specific use of each product, programming is possible with a general-purpose
PROM writer.
Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the
general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits
to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to
write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address
($0000-$7FFF). An example of PROM memory map is shown in figure 1.
Programmable ROM (ZTAT) Microcomputer
3
Notes:
1. When programming with a PROM writer, set up each ROM size to the address given in table 2. If it is
programmed erroneously to an address given in table 2 or later, check of writing of PROM may become
impossible. Particularly, caution should be exercised in the case of a plastic package since
reprogramming is impossible with it. Set the data in unused addresses to $FF.
2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the
product may break down due to overcurrent. Be sure to check that they are properly set to the writer
before starting the writing process.
3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product
employs a VPP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will
result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258
specifications.
Table 1 Selection of Mode (Example of HD404829R Series)
Mode CE OE VPP O0 – O7
Write “Low” “High” VPP Data input
Verify “High” “Low” VPP Data output
Prohibition of programming “High” “High” VPP High impedance
Table 2 PROM Writer Program Address (Example of HD404829R Series)
ROM size Address
8k $0000 – $3FFF
12k $0000 – $5FFF
16k $0000 – $7FFF
Writing/verification
Programming of the built-in program ROM employs a high speed programming method. With this method,
high speed writing is effected without voltage stress to the device or without damaging the reliability of the
written data.
A basic programming flow chart is shown in figure 1 and a timing chart in figure 2.
For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATTM
Microcomputer's Built-in Programmable ROM and precautions for its Applications."
Programmable ROM (ZTAT) Microcomputer
4
$0000
Vector address
Zero-page subroutine
(64 words)
Pattern
(4,096 words)
Program
(16,384 words)
$0001
$001F
$0080
$007F
$2000
$1FFF
$0020
$7FFF
Bit 4 Bit 8
Bit 3 Bit 7
Bit 2 Bit 6
Bit 1 Bit 5
Bit 0
Bit 9
1
11
11
1
Upper three bits are not to be used
(fill them with 111)
Upper 5 bits
Lower 5 bits $0000
$000F
$0010
$003F
$0040
$3FFF
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to RESET, STOPC routine)
JMPL instruction
(jump to INT
0
routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B, INT
2
routine)
JMPL instruction
(jump to INT
1
routine)
JMPL instruction
(jump to timer C, INT
3
routine)
JMPL instruction
(jump to timer D, INT
4
routine)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
JMPL instruction
(jump to A/D, serial routine)
$0FFF
$1000
Figure 1 Memory Map in PROM Mode (Example of HD404829R Series)
Programmable ROM (ZTAT) Microcomputer
5
Start
Verification OK?
Set write/verify modes
VCC = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3V
Address = 0
n = 0
n + 1 n
→
Program t =1 ms ± 5%
PW
Program t = 3n ms
OPW
Last address?
n < 25?
Go
Yes
No
Address + 1 Address
→
Yes
Set read mode
V = 5.0 ± 0.5 V, V = V ± 0.6 V
CC PP CC
Read
all addresses
End
Reject No
Yes
No
Figure 2 Flowchart of High-Speed Programming
Programmable ROM (ZTAT) Microcomputer
6
Programming Electrical Characteristics
DC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0V, T a = 25°C ± 5°C, unless
otherwise specified)
Item Symbol Pin(s) Min Typ Max Unit Test Condition
Input high
voltage level VIH O0 to O7, A0 to A14,
OE, CE 2.2 — VCC + 0.3 V
Input low
voltage level VIL O0 to O7, A0 to A14,
OE, CE –0.3 — 0.8 V
Output high
voltage level VOH O0 to O72.4 — — V IOH = –200 µA
Output low
voltage level VOL O0 to O7— — 0.4 V IOL = 1.6 mA
Input leakage
current IILO0 to O7, A0 to A14,
OE, CE ——2 µAV
in = 5.25 V/0.5 V
VCC current ICC — — 30 mA
VPP current IPP — — 40 mA
AC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, T a = 25°C ± 5°C, unless otherwise
specified)
Item Symbol Min Typ Max Unit Test Condition
Address setup time tAS 2——µs See figure 3
OE setup time tOES 2——µs
Data setup time tDS 2——µs
Address hold time tAH 0——µs
Data hold time tDH 2——µs
Data output disable time tDF — — 130 ns
VPP setup time tVPS 2——µs
Program pulse width tPW 0.95 1.0 1.05 ms
CE pulse width during
overprogramming tOPW 2.85 — 78.75 ms
VCC setup time tVCS 2——µs
Data output delay time tOE 0 — 500 ns
Programmable ROM (ZTAT) Microcomputer
7
Address
Data Data in Stable Data out Valid
VPP VPP
VCC GND
VCC
VCC
CE
OE
tAS
tDS
tVPS
tVCS
tDH
tPW
tOPW
tOES tOE
tAH
tDF
Write Verify
Input pulse level: 0.8 V to 2.2 V
Input rise/fall time: 20 ns
Input timing reference levels: 1.0 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
≤
Figure 3 PROM Write/Verify Timing
Programmable ROM (ZTAT) Microcomputer
8
Notes on PROM Programming
Principles of Programming/Erasure: A memory cell in a ZTATTM
microcomputer is the same as an
EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot
electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an
SiO2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the
corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 1).
The charge in a memory cell may decrease with time. This decrease is usually due to one of the following
causes:
• Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure
principle.
• Heat excites trapped electrons, allowing them to escape.
• High voltages between the control gate and drain may erase electrons.
If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However,
electron erasure does not often occur because defective devices are detected and removed at the testing
stage.
Control gate
Floating gate
Drain
SiO2
Source
NN
++
Control gate
Floating gate
Drain
SiO2
Source
NN
++
Erasure (1)Write (0)
Figure 1 Cross-Sections of a PROM Cell
PROM Programming: PROM memory cells must be programmed under specific voltage and timing
conditions. The higher the programming voltage VPP and the longer the programming pulse tPW is applied,
the more electrons are injected into the floating gates. However, if VPP exceeds specifications, the pn
junctions may be permanently damaged. Pay particular attention to overshooting in the PROM
programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may
reduce breakdown voltages.
The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter.
Therefore, note the following points:
• Check that the socket adapter is firmly mounted on the PROM programmer.
• Do not touch the socket adapter or the LSI
during the programming. Touching them may affect the quality of the contacts, which will cause
programming errors.
Programmable ROM (ZTAT) Microcomputer
9
PROM Reliability after Programming: In general, semiconductor devices retain their reliability,
provided that some initial defects can be excluded. These initial defects can be detected and rejected by
screening. Baking devices under high-temperature conditions is one method of screening that can rapidly
eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure
section.)
ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a
screening method during the wafer fabrication process, but Hitachi recommends that each device be
exposed to 150°C at one atmosphere for at least 48 hours after it is programmed, to ensure its best
performance. The recommended screening procedure is shown in figure 2.
Note: If programming errors occur continuously during PROM programming, suspend programming and
check for problems in the PROM programmer or socket adapter. If programming verification
indicates errors in programming or after high-temperature exposure, please inform Hitachi.
Note: Exposure time is measured from when the temperature in the heater reaches 150°C.
Programming, verification
Exposure to high temperature, without power
150°C ± 10°C, 48 h +8 h
0 h– *
*
Program read check
V = 4.5 V or 5.5 V
CC
Figure 2 Recommended Screening Procedure
Normal programming rate: The normal programming rate is guaranteed to be 95% or higher.
2. Handling window-package product
Glass erase window: Rubbing the glass erase window with a plastic object or attaching any electrically
charged material to it may generate static electricity on the window surface, resulting in faulty chip
operation.
In this case, apply ultraviolet light to the window for a short time to neutralize the electrical charge, then
return to the normal condition. This procedure, however, also reduces the charge accumulated on the
floating gate at the same time; thus, a re-programming operation is recommended.
Since the basic cause of the problem is the electrical charge on the window, the remedy is to avoid any
charge. The following countermeasures are similar to those against static discharge breakdown for general
ICs:
• Ground the human body when handling the product. Do not use gloves which can cause static
electricity.
Programmable ROM (ZTAT) Microcomputer
10
• Do not rub the glass window with a plastic object which is likely to generate static electricity.
• Take care when using a refrigerant spray, since some products may include a few undesirable ions.
• Use an ultraviolet shielding label (especially one containing conductive material), since it effectively
equalizes the surface charge.
Handling after programming the EPROM: Since a small amount of ultraviolet light is emitted by a
fluorescent lamp or sunlight, exposing a chip to such light for a long time may cause memory information
to invert. In addition, the device may malfunction if exposed to strong light due to the effect of a
photoelectric current. It is therefore advisable to attach a light-proof label (e.g. ultraviolet shielding label)
to cover the glass erase window before using the device.
Special labels for this purpose are commercially available. In general, any label that contains metal can
effectively absorb ultraviolet light.
The following should be considered when selecting a shielding label.
1. Adhesive property (mechanical strength)
Re-attaching the same label or using a label with attached dust should be avoided since it reduces
adhesive strength. Since static electricity may be generated when detaching a label, it is recommended
that erasure using ultraviolet light and re-programming be performed after detaching any label (when
replacing a label, use a method such as attaching the new label over the old one, for instance).
2. Allowable temperature range
Take care concerning the shielding-label requirements for the allowable temperature range as well as
the ambient temperature used. The use of a label under conditions exceeding the allowable temperature
range may harden the adhesive, which can cause the label to peel off easily. This also causes the
adhesive to stick to the glass window, and to remain on the glass window after detaching the label.
3. Moisture-proof property
Take care concerning the shielding-label requirements for the allowable humidity range as well as the
ambient humidity.
It is very difficult to find a shielding label which can be used in any ambient conditions allowed for all
currently released MCU models. Therefore, an appropriate shielding label should be selected according to
the application.
Program Development Procedure and
Support Systems
1. General Description
Hitachi provides cross assemblers and emulators as a support environment for user
program development. User developed programs can then be downloaded into ZTAT™
memory and the microcomputer can be installed in the user system, either for sample
production or for mass production. Hitachi also supports ROM mask programming and
the delivery of mask ROM microcomputers with user software in ROM as ICs.
Figure 1 shows the typical design procedure.
Procedure Description
(1) When a user constructs a system using an HMCS400 Series microcomputer, before
designing the rogram, the user first designs the system and allocates I/O pins and
RAM to the required functions according to the system design.
(2)To implement the required functions, the user then designs the algorithms using
flowcharts. Then the user codes the program in HMCS400 assembler language based
on those flowcharts.
(3)The software coded according to the flowcharts is then written to a floppy disk,
completing the creation of the program.
(4)The source program is assembled and linked on a host computer to create a load
module. At this time the user also checks for and corrects errors in the program.
(5)Hardware simulation is used to verify program operation. Hitachi provides a wide
range of hardware emulators for this purpose.
(6)The program is then delivered to Hitachi either as an EPROM or as a ZTAT™
microcomputer. The user also submits two forms, the Single-Chip Microcomputer
Request Specifications form and the Mask Option List form.
(7)Hitachi creates a mask program from the ROM and the mask options, fabricates ICs,
and presents sample ICs to the user. The user evaluates the samples, and mass
production starts when the user has verified that the ICs are programmed correctly.
Program Development Procedure and Support Systems
2
Mask
Test
production
EPROM
EPROM
(1)
(2)
(6)
(7)
(3)
(4)
(5)
Artwork
Sample
OK?
Yes
No Yes
No
Yes
No
Mass production
Sample
evaluation
Source
program
Load module
program
Assemble/linkAssemble list
OK?
Mass production
OK?
Start
Hardware
simulation
Flowchart
Allocation of
RAM and I/O
M/T
Masked ROM
ZTAT
Editor
Cross assembler system
Emulator,
EPROM microcomputer,
PROM microcomputer
Pattern
generator
tape
EPROM or ZTATTM
Figure 1 Program Design Procedure
2. Emulation
The Hitachi emulators for 4-bit single-chip microcomputers provide powerful support for
both the hardware and software aspects of system development. The emulation system
consists of a combination of an emulator unit (the HS400EUA02H), one or more of a
wide range of target probes, the E400 emulator itself (the HS400EPI01H), and user
system interface cables.
Program Development Procedure and Support Systems
3
2.1 Emulator unit
Features
The HS400EUA02H has the following features:
• A wide range of emulation commands for efficient development.
• Support for a wide range of target chips by exchanging the target probe and the user
system interface cables.
• Is provided in its own case and, since it operates on 100 VAC line power, does not
require a separate power supply.
• Small footprint (92 × 353 mm) that does not require much bench space.
Functions
The HS400EUA02H provides the following functions:
• Executes user programs in real time.
• Sets breakpoints
Combination breakpoints: Up to four breakpoints can be set based on arbitrary
values of the program counter, address/data bus, data memory content, external
probe signals, pass count, and other aspects.
PC breakpoint: The entire memory area can be specified according to the program
counter.
• Displays trace results without stopping program execution using trace stop mode.
• Real-time trace: Records and displays up to 2000 steps of bus information and external
signals before and after a breakpoint. Also displays data memory R/W signals, data,
the stack level, and other information.
• Symbolic debugging: Supports debugging using symbolic information for breaking,
tracing, and other operations.
• Execution time measurement: Measure program execution time in microseconds for
run times of up to one hour.
• Line assembler: Allows the contents of memory to be modified in assembler language.
• Disassembler
• Single-step trace: Traces the user program and displays the contents of MCU registers
and data memory at a specified address after each inspection execution cycle.
• Register display and modification
• Program and data memory display and modification
• Coverage function
• Self-diagnostics function
Program Development Procedure and Support Systems
4
•
Dedicated target probe
Emulator
unit
Dedicated
target probe
User
cable
User
system
Common target probe or E400 Emulator
Emulator
unit
Common
target probe
User
cable
User
system
E400
Emulator
Evaluation
chip-set
Evaluation
chip-set
User
cable
User
system
Host
Host
Host
Evaluation chip-set
E400 Emulator Structure of HMCS400 Series Emulator Set
Program Development Procedure and Support Systems
5
Table 1 Emulator Commands
Category Command Function
Object program
management L Loads object program and symbol information
V Verifies object program
P Saves object program
Execution G Executes user program
S Traces user program in single steps
Setting break conditions BP Sets, displays, and cancels program counter (PC) break
TR Sets, displays, and cancels combination break conditions
BR1
BR2
BR3
Management of memory
and registers I Displays and modifies program memory contents
ID Dumps program memory contents
IMAP Sets and displays the program memory area
T Transfers object program
C Compares object program
M Displays and modifies data memory contents
MD Dumps data memory contents
MMAP Sets and displays data memory area
DEF Sets address to display data memory contents during the halt of
user program execution
R Displays and modifies register values
IO Displays and modifies I/O port contents
Support of debugging CONT Restarts realtime trace from subcommand wait
Q Displays realtime trace results
HE Displays all emulator commands
A Line assemble
DA Disassemble
O Searches for bit pattern
CO Displays and clears coverage data
F Sets and displays MCU clock mode
TIM Sets and displays MCU timer operation
N Designates transfer rate
SYM Defines, clears, and displays symbols, and selects the attribute of
the symbols to be loaded
Program Development Procedure and Support Systems
6
2.2 General-purpose target probe
While we at Hitachi have provided target probes for each IC product, we have also
released a general-purpose target probe that can support a wide range of ICs when the
evaluation chip and/or the data ROM in a system is exchanged. This product will increase
the efficiency of our customers’ investments. We intend to make all possible efforts to
assure that new products will also be compatible with this general-purpose target probe.
However, there are certain microcomputers that this target probe cannot support due to
the functions provided by those microcomputers.
Emulator structural units
An emulator system consists of four components: the emulator unit, the general-purpose
target probe, the chip set, and the user system interface cables. Alternatively, the E400
emulator, which combines the emulator unit and the general-purpose target probe in a
single unit, can be used.
• Either the HS400EUA02H, which is provided in a case, or the earlier HS400EUA01H
can be used.
• The model number of the general-purpose target probe is HS400ETA01H.
• The chip set consists of the evaluation chip and data ROM, and is selected according
to the microcomputer for which debugging is to be performed.
• The model number has the form HS4xx(x)ERSvrH, where 4xx(x) is the three or four
digit abbreviated product name, and vr indicates the product version number.
• The user system interface cable is selected according to the microcomputer package.
Note that the user system interface cables used with the earlier target probes cannot be
used with the general-purpose target probe.
2.3 E400 emulator
The emulator unit and the general-purpose target probe have been miniaturized and
combined in a single B5-sized unit to support an even wider range of development
environments.
Features
The E400 emulator (HS4000EPI01H) has the following features:
• The same functions previously provide by two products, an emulator unit and a target
probe.
• Support for high-speed operation (Example: 8 MHz with the HD404639R Series)
• Development using a source code debugger.
• Bus monitor mode connection, which allows display of internal RAM data in LEDs in
real time during user program execution. (Function expansion option: under
development)
Program Development Procedure and Support Systems
7
2.4 Source code debugger
HS4000ISIW1SF
Runs under the Windows*1 operating system on IBM PC*2 compatible personal
computers.
• Source level debugging functions:
Source display
Setting and clearing breakpoints in the source code
Display and modification of symbol contents in the source code
• Multiwindow display
Wide range of information reference and manipulation functions
(source, memory, register, trace, break settings, and other information)
• Menu format
Manipulations using menu selection
• Test support functions
Coverage display
Command chain execution
Execution result acquisition
• Help functions
Online help
Guideline messages
Notes: 1. Windows is a registered trademark of Microsoft.
2. IBM PC is a registered trademark of International Business Machines, Inc.
Program Development Procedure and Support Systems
8
3. System Software Development Standards for Single-Chip Microcomputer
Applications
3.1 Basics of application system development
As shown in figure 2, single-chip microcomputer application system development
consists of hardware and software development. In principle, the customer is responsible
for all aspects of system development.
However, if for one of the following reasons,
• Insufficient software development staff,
• Lack of experience in software development, or
• Inadequate debugging tools,
when the customer is considering developing system software for a single-chip
microcomputer application, they feel they are not able to develop the required software,
Hitachi will undertake the development of the required software for a fee.
Single-chip microcomputer
application system development
Hardware
development Software
development
Figure 2 Single-Chip Microcomputer Application System Development
3.2 When requesting application system software development
Table 2 lists the division of labor and responsibilities when Hitachi accepts a request for
single-chip microcomputer application system software development.
Program development request: The customer must prepare in advance the following
documents, which are created as items 1, 2, 3, and 4 in table 2 when a customer requests
software development from Hitachi.
1. System functional description document
2. Peripheral circuit design diagrams
3. Program specifications document (Including general flowcharts.)
4. System development planning documents and production planning documents
Furthermore, we strongly recommend extensive discussions between the customer and
Hitachi in advance concerning details of the software production.
Hitachi cannot accept modifications to the above items once a request for program
development has been accepted. However, in the event of unavoidable changes, contact
Hitachi as quickly as possible.
Program Development Procedure and Support Systems
9
Table 2 Division of Responsibility in Software Development
No. Item Customer Hitachi Notes
1 Production of system functional description
documents
2 Production of peripheral circuit design diagrams
3 Production of a program specifications document Including general
flowcharts
4 Production of system development planning
documents and production planning documents
5 Production of detailed program flowcharts
6 Production of program code listings
7 Assembling and debugging the program
8 Writing the program to EEPROM and installing it
in an evaluation board
9 Production of test units
10 Debugging in the test units
11 Debugging in an actual system
12 Production of mask ROM tapes or EEPROMs
13 Production of a program design document Two copies will be
delivered
14 Program approval One copy returned to
Hitachi after approval
Notes: : Handled by the person in charge at the corresponding company.
: Indicates joint operations.
The numbers in the No. column correspond to the numbers in parentheses in figure 3.
Program Development Procedure and Support Systems
10
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8)
(2)
(9)
(12)
(14)
(13)
(10)
(11)
OK
NG
NG
Check 2
System functional specifications selection
Microcomputer selection
Rough design if peripheral circuits
Program specifications design
(Including general flowcharts)
System production planning
(Production planning document)
Detailed flowchart production
Coding
Detailed peripheral circuit design
Evaluation unit production
Assembly and debugging
Check 1
Start
Debugging in evaluation units
Debugging in actual systems
Mask ROM code production
Program design specifications
document production
Program acceptance
OK
End
[Hardware] [Software]
Items in parentheses refer
to the No. column in table 2.
Figure 3 Software Development Procedure
Program Development Procedure and Support Systems
11
Program development: Hitachi will develop the program according to the program
specifications document provided by the customer. The fee for this development effort
will depend on the size of the program developed. (Consult your Hitachi sales
representative for details of the fee schedule.) The program will be developed so that it
meets the program specifications document, but note that it will not meet any
specifications not explicitly stated in the program specifications document. If the size of
the developed program exceeds the capacity of the on-chip ROM, Hitachi will request,
based on consultations with the customer, the removal of requirements from the program
specifications document.
Program debugging: In program debugging, what is checked is whether or not the
developed program meets the requirements of the program specifications document. The
customer must provide an evaluation unit that includes the required peripheral circuits for
this process. The program will be debugged by connecting the evaluation unit to an
evaluation board provided by Hitachi. A representative from the customer should be
present during this process.
When we have completed this debugging process, we will present the evaluation unit and
the evaluation board to the customer for a final check. If required, the customer should
install the evaluation board in an actual system and test the software in an actual system.
If the result of this check is that the program does not meet the specifications in the
program specifications document, the customer should request corrections from Hitachi.
Completion of program development: After the final checks using the evaluation unit
and the provided evaluation board have been completed, the customer will receive the
following items:
• Program design document (Includes a program acceptance form) ... Two copies
This includes a description of the program, flowcharts, and a program listing.
• Mask ROM paper tape or EEPROM ... One set will be provided.
After you have verified the program and have accepted it, please return one copy of
the program design document (which includes a program acceptance form) to Hitachi.
This completes the program development procedure.
After service: Hitachi makes all possible efforts to develop programs without errors.
However, it is not possible to say either that all program errors will be discovered in the
debugging stage, or that the customer’s final check will have revealed all program errors.
If any errors remain, Hitachi will correct the program. However, the procedures used and
the charges for those corrections shall be determined by a separate agreement between
Hitachi and the customer.
Instruction Set
The MCU has 101 instructions, classified into the following ten groups:
• Immediate instructions
• Register-to-register instructions
• RAM address instructions
• RAM register instructions
• Arithmetic instructions
• Compare instructions
• RAM bit manipulation instructions
• ROM address instructions
• Input/output instructions
• Control instructions
The functions of these instructions are listed in tables 1 to 10, and an opcode map is shown in table 11.
Symbols and Abbreviations
A → B Transfer from A to B
A ↔ B Exchange between A and B
XLogical negation (NOT)
1 High level
0 Low level
NZ Not Zero*
NB No borrow** Status goes high with NZ,
OVF Overflow*NB or OVF.
∩AND
∪OR
⊕Exclusive OR
≠Not equals
≤Less than or equal to
% Denotes binary number
$ Denotes hexadecimal number
i, m, p 1-digit hexadecimal number ($0–$F)
d 3-digit hexadecimal number ($000–$FFF)
n 2-bit binary number
a 6-bit binary number
b 8-bit binary number
u Combination of p (1-digit hexadecimal number) and d (3-digit hexadecimal number)
y, x 1 or 0
Instruction Set
2
Table 1 Immediate Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Load A from Immediate LAI i 100011i
3i
2i
1i
0i → A 1/1
Load B from Immediate LBI i 100000i
3i
2i
1i
0i → B 1/1
Load Memory from
Immediate LMID i, d 0
d9
1
d8
1
d7
0
d6
1
d5
0
d4
i3
d3
i2
d2
i1
d1
i0
d0
i → M 2/2
Load Memory from
Immediate, Increment Y LMIIY i 101001i
3i
2i
1i
0i → M,
Y + 1 → YNZ 1/1
Table 2 Register-to-Register Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Load A from B LAB 0 0 0 1 0 0 1 0 0 0 B → A 1/1
Load B from A LBA 0 0 1 1 0 0 1 0 0 0 A → B 1/1
Load A from W LAW*20
01
00
00
00
00
00
00
00
00
0W → A 2/2*1
Load A from Y LAY 0 0 1 0 1 0 1 1 1 1 Y → A 1/1
Load A from SPX LASPX 0 0 0 1 1 0 1 0 0 0 SPX → A 1/1
Load A from SPY LASPY 0 0 0 1 0 1 1 0 0 0 SPY → A 1/1
Load A from MR LAMR m 1 0 0 1 1 1 m3m2m1m0MR(m) → A 1/1
Exchange MR and A XMRA m 1 0 1 1 1 1 m3m2m1m0MR(m) ↔ A 1/1
Notes: 1. The assembler automatically provides an operand for the second word of the LAW instruction.
2. This instruction is not available for the following:
•HD404222
•HD40L4222
•HD404201
•HD404202
•HD40L4201
•HD40L4202
•HD4074224
Instruction Set
3
Table 3 RAM Address Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Load W from Immediate LWI i*300111100 i
1i
0i → W 1/1
Load X from Immediate LXI i 1 0 0 0 1 0 i3i2i1i0i → X 1/1
Load Y from Immediate LYI i 1 0 0 0 0 1 i3i2i1i0i → Y 1/1
Load W from A LWA*20
01
00
00
00
01
00
00
00
00
0A → W 2/2*1
Load X from A LXA 0 0 1 1 1 0 1 0 0 0 A → X 1/1
Load Y from A LYA 0 0 1 1 0 1 1 0 0 0 A → Y 1/1
Increment Y IY 0 0 0 1 0 1 1 1 0 0 Y + 1 → Y NZ 1/1
Decrement Y DY 0 0 1 1 0 1 1 1 1 1 Y – 1 → Y NB 1/1
Add A to Y AYY 0 0 0 1 0 1 0 1 0 0 Y + A → Y OVF 1/1
Subtract A from Y SYY 0 0 1 1 0 1 0 1 0 0 Y – A → Y NB 1/1
Exchange X and SPX XSPX 0 0 0 0 0 0 0 0 0 1 X ↔SPX 1/1
Exchange Y and SPY XSPY 0 0 0 0 0 0 0 0 1 0 Y ↔SPY 1/1
Exchange X and SPX,
Y and SPY XSPXY 0 0 0 0 0 0 0 0 1 1 X ↔SPX,
Y ↔ SPY 1/1
Notes: 1. The assembler automatically provides an operand for the second word of the LAW instruction.
2. This instruction is not available for the following:
•HD404222
•HD40L4222
•HD404201
•HD404202
•HD40L4201
•HD40L4202
•HD4074224
3. This instruction is not available for the compact microcomputers:
HD404222, HD40L4222, HD4074224, HD404201, HD404202, HD40L4201 and HD40L4202.
Instruction Set
4
Table 4 RAM Register Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Load A from
Memory LAM(XY) 00100100yx M → A,
(X ↔ SPX,
Y ↔ SPY)
1/1
Load A from
Memory LAMD d 0
d9
1
d8
1
d7
0
d6
0
d5
1
d4
0
d3
0
d2
0
d1
0
d0
M → A 2/2
Load B from
Memory LBM(XY) 00010000yx M → B,
(X ↔ SPX,
Y ↔ SPY)
1/1
Load Memory
from A LMA(XY) 00100101yx A → M,
(X ↔ SPX,
Y ↔ SPY)
1/1
Load Memory
from A LMAD d 0
d9
1
d8
1
d7
0
d6
0
d5
1
d4
0
d3
1
d2
0
d1
0
d0
A → M 2/2
Load Memory
from A, Increment Y LMAIY(X) 000101000x A → M,
Y + 1 → Y
(X ↔ SPX)
NZ 1/1
Load Memory
from A, Decrement Y LMADY(X) 001101000x A → M,
Y – 1 → Y
(X ↔ SPX)
NB 1/1
Exchange Memory
and A XMA(XY) 00100000yx M ↔ A,
(X ↔ SPX,
Y ↔ SPY)
1/1
Exchange Memory
and A XMAD d 0
d9
1
d8
1
d7
0
d6
0
d5
0
d4
0
d3
0
d2
0
d1
0
d0
M ↔ A 2/2
Exchange Memory
and B XMB(XY) 00110000yx M ↔ B,
(X ↔ SPX,
Y ↔ SPY)
1/1
Note: (XY) and (X) have the following meanings:
Each instruction with (XY) has four mnemonics, each with different object codes. For example,
different values of X and Y of the opcode of the LAM(XY) instruction are given below.
Mnemonic y x Function
LAM 0 0 None
LAMX 0 1 X ↔ SPX
LAMY 1 0 Y ↔ SPY
LAMXY 1 1 X ↔ SPX, Y ↔ SPY
Each instruction with (X) has two mnemonics, each with different object codes. For example,
different values of X of the opcode of the LMAIY(X) instruction are given below.
Mnemonic X Function
LMAIY 0 None
LMAIYX 1 X ↔ SPX
Instruction Set
5
Table 5 Arithmetic Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Add Immediate to A AI i 1 0 1 000i
3i
2i
1i
0A + i → A OVF 1/1
Increment B IB 0 0 0 1001100 B + 1 → B NZ 1/1
Decrement B DB 0 0 1 1001111 B – 1 → B NB 1/1
Decimal Adjust for
Addition DAA 0010100110 1/1
Decimal Adjust for
Subtraction DAS 0010101010 1/1
Negate A NEGA 0 0 0 1100000 A + 1 → A 1/1
Complement B COMB 0 1 0 1000000 B → B 1/1
Rotate Right A with
Carry ROTR 0 0 1 0100000 1/1
Rotate Left A with
Carry ROTL 0 0 1 0100001 1/1
Set Carry SEC 0 0 1 1101111 1 → CA 1/1
Reset Carry REC 0 0 1 1101100 0 → CA 1/1
Test Carry TC 0 0 0 1101111 CA 1/1
Add A to Memory AM 0 0 0 0001000 M + A → A OVF 1/1
Add A to Memory AMD d 0
d9
1
d8
0
d7
0
d6
0
d5
0
d4
1
d3
0
d2
0
d1
0
d0
M + A → A OVF 2/2
Add A to Memory
with Carry AMC 0000011000 M + A +
CA → A
OVF → CA
OVF 1/1
Add A to Memory with
Carry AMCD d 0
d9
1
d8
0
d7
0
d6
0
d5
1
d4
1
d3
0
d2
0
d1
0
d0
M + A +
CA → A
OVF → CA
OVF 2/2
Subtract A from
Memory with Carry SMC 0010011000 M – A –
CA → A
NB → CA
NB 1/1
Subtract A from
Memory with Carry SMCD d 0
d9
1
d8
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
0
d1
0
d0
M – A –
CA → A
NB → CA
NB 2/2
OR A and B OR 0 1 0 1000100 A ∪ B → A 1/1
AND Memory with A ANM 0 0 1 0011100 A ∩ M → A NZ 1/1
AND Memory with A ANMD d 0
d9
1
d8
1
d7
0
d6
0
d5
1
d4
1
d3
1
d2
0
d1
0
d0
A ∩ M → A NZ 2/2
OR Memory with A ORM 0 0 0 0001100 A ∪ M → A NZ 1/1
OR Memory with A ORMD d 0
d9
1
d8
0
d7
0
d6
0
d5
0
d4
1
d3
1
d2
0
d1
0
d0
A ∪ M → A NZ 2/2
Instruction Set
6
Operation Mnemonic Operation Code Function Status Words/
Cycles
EOR Memory with A EORM 0 0 0 0 011100 A ⊕ M →
ANZ 1/1
EOR Memory with A EORMD d 0
d9
1
d8
0
d7
0
d6
0
d5
1
d4
1
d3
1
d2
0
d1
0
d0
A ⊕ M →
ANZ 2/2
Note ∩: Logical AND
∪: Logical OR
⊕: Exclusive OR
Table 6 Compare Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Immediate Not Equal
to Memory INEM i 0 0 0 010i
3i
2i
1i
0i ≠ M NZ 1/1
Immediate Not Equal
to Memory INEMD i,d 0
d9
1
d8
0
d7
0
d6
1
d5
0
d4
I3
d3
I2
d2
I1
d1
I0
d0
i ≠ M NZ 2/2
A Not Equal to
Memory ANEM 0 0 0 0000100 A ≠ M NZ 1/1
A Not Equal to
Memory ANEMD d 0
d9
1
d8
0
d7
0
d6
0
d5
0
d4
0
d3
1
d2
0
d1
0
d0
A ≠ M NZ 2/2
B Not Equal to
Memory BNEM 0 0 0 1000100 B ≠ M NZ 1/1
Y Not Equal to
Immediate YNEI i 0 0 0 111i
3i
2i
1i
0Y ≠ i NZ 1/1
Immediate Less than
or Equal to Memory ILEM i 0 0 0 011i
3i
2i
1i
0i ≤ M NB 1/1
Immediate Less than
or Equal to Memory ILEMD i,d 0
d9
1
d8
0
d7
0
d6
1
d5
1
d4
i3
d3
i2
d2
i1
d1
i0
d0
i ≤ M NB 2/2
A Less than or Equal
to Memory ALEM 0 0 0 0010100 A ≤ M NB 1/1
A Less than or Equal
to Memory ALEMD d 0
d9
1
d8
0
d7
0
d6
0
d5
1
d4
0
d3
1
d2
0
d1
0
d0
A ≤ M NB 2/2
B Less than or Equal
to Memory BLEM 0 0 1 1000100 B ≤ M NB 1/1
A Less than or Equal
to Immediate ALEI i 1 0 1 011i
3i
2i
1i
0A ≤ i NB 1/1
Instruction Set
7
Table 7 RAM Bit Manipulation Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Set Memory Bit SEM n 0 0 1 00001n
1n
01 → M(n) 1/1
Set Memory Bit SEMD n,d 0
d9
1
d8
1
d7
0
d6
0
d5
0
d4
0
d3
1
d2
n1
d1
n0
d0
1 → M(n) 2/2
Reset Memory Bit REM n 0 0 1 00010n
1n
00 → M(n) 1/1
Reset Memory Bit REMD n,d 0
d9
1
d8
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
n1
d1
n0
d0
0 → M(n) 2/2
Test Memory Bit TM n 0 0 1 00011n
1n
0M(n) 1/1
Test Memory Bit TMD n,d 0
d9
1
d8
1
d7
0
d6
0
d5
0
d4
1
d3
1
d2
n1
d1
n0
d0
M(n) 2/2
Table 8 ROM Address Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Branch on Status 1 BR b 1 1 b7b6b5b4b3b2b1b01 1/1
Long Branch on
Status 1 BRL u 0
d9
1
d8
0
d7
1
d6
1
d5
1
d4
p3
d3
p2
d2
p1
d1
p0
d0
1 2/2
Long Jump
Unconditionally JMPL u 0
d9
1
d8
0
d7
1
d6
0
d5
1
d4
p3
d3
p2
d2
p1
d1
p0
d0
2/2
Subroutine Jump
on Status 1 CAL a 0 1 1 1 a5a4a3a2a1a01 1/2
Long Subroutine
Jump on Status 1 CALL u 0
d9
1
d8
0
d7
1
d6
1
d5
0
d4
p3
d3
p2
d2
p1
d1
p0
d0
1 2/2
Table Branch TBR p 0 0 1 011p
3p
2p
1p
01/1
Return from
Subroutine RTN 0000010000 1/3
Return from Interrupt RTNI 0 0 0 0010001 1 → I/E
CA recovery ST 1/3
Instruction Set
8
Table 9 Input/Output Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
Set Discrete I/O
Latch SED 0011100100 1 → D(Y) 1/1
Set Discrete I/O
Latch Direct SEDD m 1 0 1 110m
3m
2
m
1m
01 → D(m) 1/1
Reset Discrete I/O
Latch RED 0001100100 0 → D(Y) 1/1
Reset Discrete I/O
Latch Direct REDD m 1 0 0 110m
3m
2
m
1m
00 → D(m) 1/1
Test Discrete I/O
Latch TD 0011100000 D(Y) 1/1
Test Discrete I/O
Latch Direct TDD m 1 0 1 010m
3m
2
m
1m
0D(m) 1/1
Load A from R-Port
Register LAR m 1 0 0 101m
3m
2
m
1m
0R(m) → A 1/1
Load B from R-Port
Register LBR m 1 0 0 100m
3m
2
m
1m
0R(m) → B 1/1
Load R-Port Register
from A LRA m 1 0 1 101m
3m
2
m
1m
0A → R(m) 1/1
Load R-Port Register
from B LRB m 1 0 1 100m
3m
2
m
1m
0B → R(m) 1/1
Pattern Generation P p 0 1 1 011p
3p
2p
1p
01/2
Table 10 Control Instructions
Operation Mnemonic Operation Code Function Status Words/
Cycles
No Operation NOP 0 0 0 0000000 1/1
Start Serial STS 0 1 0 1001000 1/1
Stand-by Mode/
Watch Mode SBY 0101001100 1/1
Stop Mode/
Watch Mode STOP 0 1 0 1001101 1/1
Instruction Set
9
Table 11 Opcode Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
R8
R9 0123456789ABCDEF0123456789ABCDEF
1
0
1
1-word/2-cycle
instruction
... 1-word/3-cycle
instruction
... RAM direct address
instruction
(2-word/2-cycle)
... 2-word/2-cycle
instruction
...
L
H
NOP
XSPX XSPY
XSPXY
ANEM
RTN
RTNI
ALEM
LBM(XY)
INEM
ILEM
i(4)
i(4)
AM
AMC
ORM
EORM
LAW
LWA
*
1
*
1
ANEMD
ALEMD
AMD
AMCD
ORMD
EORMD
INEMD
ILEMD
i(4)
i(4)
YNEI i(4)
LMAIY(X)
NEGA
BNEM
AYY
RED
LAB
LASPY
LASPX
IB
IY
TC
COMB
OR
STS
*3
SBY
STOP
JMPL
CALL
BRL
p(4)
p(4)
p(4)
XMAD
LAMD LMAD
SMCD
ANMD
LMID
P
i(4)
p(4)
SEMD n(2) REMD n(2) TMD n(2)
CAL a(6)
BR b(8)
XMA(XY)
LAM(XY)
SEM n(2)
LMA(XY)
REM n(2) TM n(2)
SMC
ANM
ROTR
ROTL
DAA DAS LAY
TBR p(4)
XMB(XY)
LWI i*2(2)
LMADY(X)
TD
BLEM
SYY
SED
LBA
LYA
LXA REC
DB
DY
SEC
LBI
LYI
LXI
LAI
LBR
LAR
REDD
LAMR
AI
LMIIY
TDD
ALEI
LRB
LRA
SEDD
XMRA
i(4)
i(4)
i(4)
i(4)
m(4)
m(4)
m(4)
m(4)
i(4)
i(4)
m(4)
i(4)
m(4)
m(4)
m(4)
m(4)
Notes: 1. This instruction is not available for the following:
•HD404222
•HD40L4222
•HD404201
•HD404202
•HD40L4201
•HD40L4202
•HD4074224
Instruction Set
10
2. This instruction is not available for the compact microcomputers, HD404222, HD40L4222,
HD4074224, HD404201, HD40L4201, HD404202 and HD40L4202.
3. The STS instruction is not available for the HD404201, HD40L4201, HD404202 and HD40L4202.
General Purpose Microcomputer
HD404019R Series
Rev. 5.0
March 1997
Description
The HD404019R series are HMCS400-series CMOS 4-bit single-chip microcomputers. Each device
incorporates a ROM, RAM, I/O, serial interface, and two timer/counters, and contains high-voltage I/O
pins including high-current output pins to directly drive fluorescent displays.
The HD404019R series includes four chips. The HD404019R and HD40L4019R are Mask ROM versions.
The HD4074019 and HD407L4019 are PROM versions. The HD40L4019R and HD407L4019 are low-
voltage operation versions.
Features
• 16,384-word × 10-bit ROM
Mask ROM: HD404019R, HD40L4019R
PROM: HD4074019, HD407L4019
• 992-digit × 4-bit RAM
• 58 I/O pins, including 26 high-voltage I/O pins (40 V max.)
• Two timer/counters
8-bit free-running timer
8-bit auto-reload timer/counter
• Clock synchronous 8-bit serial interface
• Five interrupt sources
Two by external sources
Two by timer/counters
One by serial interface
• Subroutine stack, up to 16 levels including interrupts
• Minimum instruction execution time: 0.89 µs
• Low-power dissipation modes
Standby: Stops instruction execution while allowing clock oscillation and interrupt functions to
operate
Stop: Stops instruction execution and clock oscillation while retaining RAM data
HD404019R Series
2
• On-chip oscillator
Crystal or ceramic oscillator
External clock
• Packages
64-pin shrink type plastic DIP
64-pin flat plastic package
64-pin shrink type ceramic DIP with window
Ordering Information
Type Product Name Model Name Package
Mask ROM HD404019R HD404019RS DP-64S
HD404019RH FP-64A
HD404019RFS FP-64B
HD40L4019R HD40L4019RS DP-64S
HD40L4019RH FP-64A
ZTATHD4074019 HD4074019S DP-64S
HD4074019H FP-64A
HD4074019FS FP-64B
HD4074019C DC-64S
HD407L4019 HD407L4019S DP-64S
HD407L4019H FP-64A
ZTAT: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd.
HD404019R Series
3
Differences between ZTAT and Mask ROM Version
ZTATMask ROM Version
Item HD4074019 HD407L4019 HD404019R HD40L4019R
Power supply
voltage (V) 4.5 to 5.5 V 3.0 to 5.5 V 3.5 to 6.0 V 2.7 to 6.0 V
Instruction cycle
time (tcyc)0.89 to 20 µs 1.12 to 20 µs 0.89 to 10 µs 1.12 to 10 µs
ROM (word) 16,384 × 10-bit 16,384 × 10-bit 16,384 × 10-bit 16,384 × 10-bit
RAM 992 × 4-bit 992 × 4-bit 992 × 4-bit 992 × 4-bit
I/O pin circuit*1Standard pins NMOS open drain NMOS open
drain Each pin can be without pull-up
MOS (NMOS open drain), with
pull-up MOS, or CMOS
High voltage
pins PMOS open drain PMOS open
drain Each pin can be without pull-down
MOS (PMOS open drain) or with
pull-down MOS
Oscillator
stabilization*2Crystal Available Available Available Available
Ceramic Available Available Available Available
Package DP-64S Available Available Available Available
FP-64A Available Available Available Available
FP-64B Available — Available —
DC-64S Available — — —
—: Not available
Notes: 1. See table 17.
2. See table 20.
HD404019R Series
4
Pin Arrangement
D
3
D
2
D
1
D
0
GND
OSC
2
OSC
1
TEST
RESET
R9
3
R9
2
R9
1
R9
0
R8
3
R8
2
R8
1
R8
0
R7
3
R7
2
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
RA
0
RA
1
/V
disp
R3
0
R3
1
R3
2
/INT
0
R3
3
/INT
1
R5
0
R5
1
R5
2
R5
3
R6
0
R6
1
R6
2
R6
3
V
CC
R4
0
/SCK
R4
1
/SI
R4
2
/SO
R4
3
R7
0
R7
1
R0
0
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
11
D
12
D
13
D
14
D
15
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
RA
0
RA
1
/V
disp
R3
0
R3
1
R3
2
/INT
0
R3
3
/INT
1
R5
0
R5
1
R5
2
R5
3
R6
0
R6
1
R6
2
R6
3
V
CC
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
GND
OSC
2
OSC
1
TEST
RESET
R9
3
R9
2
R9
1
R9
0
R8
3
R8
2
R8
1
R8
0
R7
3
R7
2
R7
1
R7
0
R4
3
R4
2
/SO
R4
1
/SI
R4
0
/SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
20
21
22
23
24
25
26
27
28
29
30
31
32
D
2
D
1
D
0
GND
OSC
2
OSC
1
TEST
RESET
R9
3
R9
2
R9
1
R9
0
R8
3
R8
2
R8
1
R8
0
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
RA
0
RA
1
/V
disp
R3
0
R3
1
R3
2
/INT
0
R3
3
/INT
1
R5
0
R0
2
R0
1
R0
0
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
R5
1
R5
2
R5
3
R6
0
R6
1
R6
2
R6
3
V
CC
R4
0
/SCK
R4
1
/SI
R4
2
/SO
R4
3
R7
0
R7
1
R7
2
R7
3
DP-64S
DC-64S
FP-64B
FP-64A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Top view
HD404019R Series
5
Block Diagram
System control
Instruction
decoder
SP
External interrupt
Timer
B
Timer
A
Serial
inter-
face
Interrupt control
992 × 4-bit RAM
BACA
ST
ALU
Y
SPYSPX
XW
RA
R9
R8
R7
R6
R5
R4 R3 R2 R1 R0 D port
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30
R31
R32/INT0
R33/INT1
R40/SCK
R41/SI
R42/SO
R43
GND
VCC
OSC2
OSC1
TEST
RESET
R32/INT0
R33/INT1
R44/SO
R41/SI
R40/SCK
RA1/Vdisp
RA0
R93
R92
R91
R90
R83
R82
R81
R80
R73
R72
R71
R70
R63
R62
R61
R60
R53
R52
R51
R50
16,384 × 10-bit
ROM
PC
indicates high-
voltage I/O pins
HD404019R Series
6
Pin Functions
Power Supply
VCC: Apply the power supply voltage to this pin.
GND: Connect to ground.
Vdisp: Power supply pin (multiplexed with RA1) for high-voltage I/O pins with a maximum voltage of 40 V
(VCC – 40 V). For details, see the Input/Output section.
TEST: For test purposes only. Connect it to VCC.
RESET: Resets the MCU. For details, see the Reset section.
Oscillators
OSC1, OSC2: OSC1 and OSC2 can be connected to a crystal resonator, ceramic resonator or an external
oscillator circuit. For details, see the Internal Oscillator Circuit section.
Ports
D0 to D15 (D Port): An input/output port addressed by bits. These 16 pins are all input/output pins. D0 to D3
are standard pins and D4 to D15 are high-voltage pins. The circuit type for each pin can be selected using a
mask option. For details, see the Input/Output section.
R0 to RA1 (R Ports): R0 to R9 are 4-bit I/O ports. Only RA is a 2-bit port. R9 and RA are input ports, and
R0 to R8 are I/O ports. R0, R1, R2, and RA are high-voltage ports, and R3 to R9 are standard ports. Each
pin has a mask option which selects its circuit type. The pins R32, R3 3, R40, R4 1, and R4 2 are multiplexed
with INT0, INT1, SCK, SI, and SO, respectively. For details, see the Input/Output section.
Interrupts
INT0, INT1: External interrupts for the MCU. INT1 can be used as an external event input pin for timer B.
INT0 and INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section.
Serial Interface
SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO)
are used for serial interface. SCK, SI, and SO are multiplexed with R40, R41, and R42, respectively. For
details, see the Serial Interface section.
HD404019R Series
7
Memory Map
ROM Memory Map
The MCU contains a 16,384-word × 10-bit ROM (mask ROM or PROM). It is described in the following
paragraphs and by the ROM memory map in figure 1.
Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL
instructions to branch to the starting address of the initialization program and of the interrupt programs.
After reset or an interrupt routine is processed, the program is executed from the vector address.
Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for
subroutines. The CAL instruction branches to subroutines.
Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P
instruction can refer to the ROM data as a pattern.
Program Area ($0000 to $3FFF): Locations from $0000 to $3FFF can be used for program code.
0
15
16
63
64
4095
4096
16383
$0000
$0FFF
$1000
$3FFF
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to reset routine)
JMPL instruction
(jump to INT0 routine)
JMPL instruction
(jump to INT1 routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to serial routine)
Vector address
Zero-page subroutine
(64 words)
Pattern
(4096 words)
Program
(16,384 words)
$000F
$0010
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
$003F
$0040
Figure 1 ROM Memory Map
HD404019R Series
8
RAM Memory Map
The MCU also contains a 992-digit × 4-bit RAM as the data and stack area. In addition to these areas,
interrupt control bits and special function registers are also mapped on the RAM memory space. The RAM
memory map (figure 2) is described in the following paragraphs.
Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.
Special Function Registers Area ($004 to $00B): The special function registers are the mode or data
registers for the external interrupt, the serial interface, and the timer/counters. These registers are classified
into three types: write-only, read-only, and read/write as shown in figure 2. These registers cannot be
accessed by RAM bit manipulation instructions.
Data Area ($020 to $3BF): The 16 digits, $020 through $02F, of the data area are called memory registers
(MR) and are accessible by the LAMR and XMRA instructions (figure 4).
Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL
instruction, CALL instruction) or interrupts are processed. This area can be used as a 16-level nesting stack
in which one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by
the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This
area, when not used as a stack, is available as a data area.
HD404019R Series
9
RAM-mapped registers
Memory registers (MR)
Data
(928 digits)
Stack
(64 digits)
Interrupt control bits area
Port mode register
Serial mode register
Serial data register lower
Serial data register upper
Timer mode register A
Timer mode register B
(PMR)
(SMR)
(SRL)
(SRU)
(TMA)
(TMB)
(TCBL/TLRL)
(TCBU/TLRU)
W
W
R/W
R/W
W
W
R/W
R/W
Not used
Timer B*
*: Two registers are mapped on the same address.
Timer counter B lower
(TCBL) Timer load register B
lower (TLRL)
RW
Timer counter B upper
(TCBU) Timer load register B
upper (TLRU)
RW
R:
W:
R/W:
10
11
$00A
$00B
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$01F
0
31
32
47
48
959
960
1023
$000
$3BF
$3C0
$3FF
0
1
2
3
4
5
6
7
8
9
10
11
12
31
$01F
$020
$02F
$030
Read only
Write only
Read/write
Figure 2 RAM Memory Map
HD404019R Series
10
Bit 3 Bit 2 Bit 1 Bit 0
0
1
2
3
$000
$001
$002
$003
IM0
(IM of INT0)
IMTA
(IM of timer A)
Not used
Not used
IF0
(IF of INT0)
IFTA
(IF of timer A)
Not used
Not used
RSP
(Reset SP bit)
IM1
(IM of INT1)
IMTB
(IM of timer B)
IMS
(IM of serial)
IE
(Interrupt enable flag)
IF1
(IF of INT1)
IFTB
(IF of timer B)
IFS
(IF of serial)
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Note: Each bit of the interrupt control bit area is set by the SEM/SEMD instruction, reset by the
REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other
instructions. Furthermore the interrupt request flag is not affected by the SEM/SEMD
instruction. The value of the status flag becomes invalid when the unusable bits are tested.
Figure 3 Interrupt Control Bits Area Configuration
Memory registers
MR (0)
MR (1)
MR (2)
MR (3)
MR (4)
MR (5)
MR (6)
MR (7)
MR (8)
MR (9)
MR (10)
MR (11)
MR (12)
MR (13)
MR (14)
MR (15)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
960
1023
$3C0
$3FF
Bit 3 Bit 2 Bit 1 Bit 0
ST PC11
PC10 PC9 PC8 PC7
CA PC6 PC5 PC4
PC3 PC2 PC1 PC0
1020
1021
1022
1023
$3FC
$3FD
$3FE
$3FF
PC13 PC12
PC13 to PC0: Program counter
ST: Status flag
CA: Carr
y
fla
g
Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position
HD404019R Series
11
Functional Description
Registers and Flags
The MCU has nine registers and two flags for the CPU operations (figure 5).
CA Carry flag
ST Status flag
PC Program counter
013
Stack pointer
0
111 59 SP
SPY SPY register
03
SPX SPX register
03
Y Y register
03
X X register
03
B B register
03
A Accumulator
03
W W register
01
1
0
0
Figure 5 Registers and Flags
Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the
arithmetic logic unit (ALU), and transfer data to/from memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): The 2-bit W register, and the 4-bit X and Y registers
indirectly address RAM. The Y register is also used for D-port addressing.
SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY assist the X and Y registers,
respectively.
Carry Flag (CA): The carry flag (CA) stores the overflow from the ALU generated by an arithmetic
operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions.
HD404019R Series
12
During an interrupt, a carry is pushed onto the stack. It is restored by the RTNI instruction, but not by the
RTN instruction.
Status Flag (ST): The status flag (ST) holds the ALU overflow, ALU non-zero, and the results of a bit test
instruction for the arithmetic or compare instructions. It is a branch condition of the BR, BRL, CAL, or
CALL instruction. The value for the status flag remains unchanged until the next arithmetic, compare, or
bit test instruction is executed. The status becomes a 1 after the BR, BRL, CAL, or CALL instruction is
either executed or skipped. During an interrupt, the status is pushed onto the stack. It is restored back from
the stack by the RTNI instruction, but not by the RTN instruction.
Program Counter (PC): The program counter is a 14-bit binary counter which controls the sequence in
which the instructions stored in ROM are executed.
Stack Pointer (SP): The stack pointer (SP) points to the address of the next stack area (up to 16 levels).
The stack pointer is initialized to RAM address $3FF. It is decremented by 4 when data is pushed onto the
stack, and incremented by 4 when data is restored from it. The stack can only be used up to 16 levels deep
because the high-order four bits of the stack pointer are fixed at 1111.
The stack pointer is initialized to $3FF by either MCU reset or by the RSP bit reset from the REM/REMD
instruction.
HD404019R Series
13
Interrupts
Five interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A
and B), and serial port (serial). For each source, an interrupt request flag (IF) interrupt mask (IM), and
interrupt vector addresses control and maintain the interrupt request. The interrupt enable flag (IE) also
controls interrupt operations.
Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped on $000 through
$003 of the RAM space. They are accessible by RAM bit manipulation instructions. (The interrupt request
flag (IF) cannot be set by software.) The interrupt enable flag (IE) and IF are cleared to 0, and the interrupt
mask (IM) is set to 1 by MCU reset.
Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector
addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source.
An interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be
activated and vector addresses will be generated from the priority PLA corresponding to the interrupt
source.
Table 1 Vector Addresses and Interrupt Priority
Reset/Interrupt Priority Vector Addresses
RESET — $0000
INT01 $0002
INT12 $0004
Timer A 3 $0006
Timer B 4 $0008
Serial 5 $000C
Table 2 Interrupt Conditions
Interrupt Source
Interrupt Control Bit INT0INT1Timer A Timer B Serial
IE 11111
IF0 · IM0 10000
IF1 · IM1 *1000
IFTA · IMTA **100
IFTB · IMTB ***10
IFS · IMS ****1
Note: *Indicates don’t care
HD404019R Series
14
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is re-executed after jumping to the vector address.
At each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF which caused the interrupt must be reset by software in the interrupt program.
$000,0
IE
$000,2
IF0
$000,3
IM0
$001,0
IF1
$001,1
IM1
$001,2
IFTA
$001,3
IMTA
$002,0
IFTB
$002,1
IMTB
$003,0
IFS
$003,1
IMS
Note: $m, n is RAM address $m, bit number n.
Vector
address
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector address
Priority control
logic
Figure 6 Interrupt Control Circuit Block Diagram
HD404019R Series
15
Instruction cycles
123456
Instruction
execution*
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note: *The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Stacking
Figure 7 Interrupt Processing Sequence
HD404019R Series
16
Yes
No
(serial interrupt)
Yes
No
Yes
PC ← $0002
PC ← $0004
PC ← $0006
PC ← $0008
IE ← 0
INT
0
interrupt?
Timer A
interrupt?
No
Accept interrupt
Power on
IE = 1?
PC ← (PC) + 1
Execute instruction
Interrupt
request?
Yes
No
Yes
No
RESET = 1?
Reset MCU
Yes
No
Yes
PC ← $000C
Timer B
interrupt?
No
INT
1
interrupt?
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
Figure 8 Interrupt Processing Flowchart
HD404019R Series
17
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests as
shown in table 3. It is reset by an interrupt and set by the RTNI instruction.
Table 3 Interrupt Enable Flag
IE Interrupt Enable/Disable
0 Disabled
1 Enabled
External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by
the port mode register (PMR: $004). Setting bit 3 and bit 2 of PMR causes the R33/INT1 and R32/INT0 pins
to be used as INT1 and INT0, respectively.
The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs. (Refer
to table 4.)
The INT1 input can be used as a clock signal input to timer B in which timer B counts up at each falling
edge of the INT1 input. When INT1 is used as the timer B external event input, the external interrupt mask
(IM1) has to be set so that the interrupt request by INT1 will not be accepted. (Refer to table 5.)
Table 4 External Interrupt Request Flags
IF0, IF1 Interrupt Request
0No
1 Yes
Table 5 External Interrupt Masks
IM0, IM1 Interrupt Request
0 Enabled
1 Disabled (masked)
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs, respectively.
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the
external interrupt requests.
Port Mode Register (PMR: $004): The port mode register is a 4-bit write-only register which controls the
R32/INT0 pin, R33/INT1 pin, R41/SI pin, and R42/SO pin as shown in table 6. The port mode register will be
initialized to $0 by MCU reset. These pins are therefore initially used as ports.
HD404019R Series
18
Table 6 Port Mode Register
PMR3 R33/INT1 Pin
0 Used as R33 port input/output pin
1 Used as INT1 input pin
PMR2 R32/INT0 Pin
0 Used as R32 port input/output pin
1 Used as INT0 input pin
PMR1 R41/SI Pin
0 Used as R41 port input/output pin
1 Used as SI input pin
PMR0 R42/SO Pin
0 Used as R42 port input/output pin
1 Used as SO output pin
HD404019R Series
19
Serial Interface
The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register, the
serial mode register, the octal counter, and the multiplexer as illustrated in figure 9. Pin R40/SCK and the
transmit clock signal are controlled by the serial mode register. The contents of the serial data register can
be written into or read out by software. The data in the serial data register can be shifted synchronously
with the transmit clock signal.
The STS instruction initiates serial interface operations and resets the octal counter to $0. The counter starts
to count at the falling edge of the transmit clock ( SCK) signal and increments by one at the rising edge of
SCK. When the octal counter is reset to $0 after eight transmit clock signals, or a transmit/receive operation
is discontinued, the serial interrupt request flag will be set.
System
clock Prescaler (11 bits)
Serial MPX ÷2 MPX
SMR (4 bits)
Serial mode register
R40/SCK
port
SCK
OC (3 bits)
Octal counter IFS
SROF
Serial
interface
interrupt
request flag
Internal bus line (S1)
÷
÷
÷
÷
÷
÷
SR (8 bits)
Serial data register
4
2
344
SCK
SCK
2
8
32
128
512
2048
4
PMR (4 bits)
Port mode register
R41/SI
port
SI SO
R42/SO
port
44
Internal bus line (S2)
Internal bus-line (S2)
Figure 9 Serial Interface Block Diagram
Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R4 0/SCK pin,
prescaler divide ratio, and transmit clock source as shown in table 7.
The write signal to the serial mode register controls the operating state of the serial interface.
The write signal to the serial mode register stops the serial data register and octal counter from accepting
the transmit clock, and it also resets the octal counter to $0 simultaneously. Therefore, when the serial
interface is in the transfer state, the write signal causes the serial mode register to cease the data transmit
and to set the serial interrupt request flag.
HD404019R Series
20
The contents of the serial mode register will be changed on the second instruction cycle after the serial
mode register has been written to. Therefore, the STS instruction must be executed after the data in the
serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU
reset.
Table 7 Serial Mode Register
SMR3 R40/SCK
0 Used as R40 port input/output pin
1 Used as SCK input/output pin
Transmit Clock
SMR2 SMR1 SMR0 R40/SCK Port Clock Source Prescaler Divide
Ratio System Clock
Divide Ratio
000SCK output Prescaler ÷ 2048 ÷ 4096
1SCK output Prescaler ÷ 512 ÷ 1024
10 SCK output Prescaler ÷ 128 ÷ 256
1SCK output Prescaler ÷ 32 ÷ 64
100SCK output Prescaler ÷ 8 ÷ 16
1SCK output Prescaler ÷ 2 ÷ 4
10 SCK output System clock — ÷ 1
1SCK input External clock — —
Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a low-
order digit (SRL: $006) and a high-order digit (SRU: $007).
The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the
falling edge of the transmit clock signal. At the same time, external data is input from the SI pin to the
serial data register, MSB first, synchronously with the rising edge of the transmit clock. Figure 10 shows
the I/O timing chart of the transmit clock signal and the data.
The read/write operations of the serial data register should be performed after the completion of data
transmit/receive. Otherwise the data may not be guaranteed.
LSB MSB
12345678
Transmit clock
Serial output data
Serial input data
latch timing
Figure 10 Serial Interface I/O Timing
HD404019R Series
21
Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag will be set when the
octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the
octal counter. Refer to table 8.
Table 8 Serial Interrupt Request Flag
IFS Interrupt Request
0No
1 Yes
Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request. Refer to
table 9.
Table 9 Serial Interrupt Mask
IMS Interrupt Request
0 Enabled
1 Disabled (masked)
Selection and Change of the Operation Mode: Table 10 shows the serial interface operation modes
which are determined by a combination of the value in the port mode register and in the serial mode
register.
Initialize the serial interface by a write signal to the serial mode register when the operation mode has
changed.
Table 10 Serial Interface Operation Mode
SMR3 PMR1 PMR2 Serial Interface Operating Mode
1 0 0 Clock continuous output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode
Operating State of Serial Interface: The serial interface has three operating states: the STS waiting state,
transmit clock wait state, and transfer state, as shown in figure 11.
The STS waiting state is the initialization state of the serial interface. The serial interface enters this state in
one of two ways: either by the operation mode changing through a change in the data in the port mode
register, or by data being written into the serial mode register. In this state, the serial interface does not
operate even if the transmit clock is applied. If the STS instruction is executed, the serial interface shifts to
the transmit clock wait state.
HD404019R Series
22
In the transmit clock wait state the falling edge of the first transmit clock causes the serial interface to shift
to the transfer state. The octal counter then counts up and the serial data register shifts simultaneously. As
an exception, if the clock continuous output mode is selected, the serial interface stays in the transmit clock
wait state while the transmit clock outputs continuously.
The octal counter becomes 000 again after 8 transmit clocks or the execution of the STS instruction, so the
serial interface returns to the transmit clock wait state and the serial interrupt request flag is set
simultaneously.
When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the
STS instruction, and stops after 8 clocks.
Transmit clock wait state
(octal counter = 000)
Transmit clock
8 transmit clocks,
STS instruction
(IFS ← 1)
STS waiting state
octal counter = 000
transmit clock disable Change PMR
Write to
SMR
(IFS ← 1)
STS
instruction
Change PMR
Write to SMR
*
*
*
Change PMR means the operation mode changes as shown below.
Clock
continuous
output mode
• Transmit mode
• Receive mode
• Transmit/receive mode
Transfer state
(octal counter 000)≠
Note:
Figure 11 Serial Interface Operation State
Transmit Clock Error Detection Example: The serial interface functions abnormally when the transmit
clock is disturbed by external noise. Transmit clock errors can be detected by the procedure shown in figure
12.
If more than 8 transmit clocks occur in the transfer state, the state of the serial interface shifts as follows:
transfer state, transmit clock wait state, and transfer state. The serial interrupt flag should be reset before
entering into the STS state by writing data to SMR. This procedure sets the IFS again.
HD404019R Series
23
Transmit/receive
(IFS ← 1)
Interrupt
disable
IFS ← 0
Write to SMR
IFS = 1?
Normal end
Transmit clock
error processing
Yes
No
Figure 12 Transmit Clock Error Detection Example
HD404019R Series
24
Timers
The MCU contains a prescaler and two timer/counters (timers A and B). See figure 13. The prescaler is an
11-bit binary counter, timer A an 8-bit free-running timer, and timer B is an 8-bit auto-reload timer/event
counter.
Timer mode register B
INT1TBOF
CPTA TAOF
4
Interrupt
request flag
of timer B
Interrupt
request flag
of timer A
Timer mode register A
4
44
3
3
CPTB
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
Internal bus line (S1)
TMB (4 bits)
Timer B MPX
Prescaler (11 bits)
Timer A MPX
TL (4 bits)
Timer latch register
TCB (8 bits)
Timer counter B
TLR (8 bits)
Timer load register B
Internal bus line (S2)
System
clock
IFTA
IFTB
TCA (8 bits)
Timer counter A
TMA (3 bits)
Figure 13 Timer/Counter Block Diagram
Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $0000 by
MCU reset, and it starts to count up with the system clock signal as soon as RESET input goes to logic 0.
The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals
to timer A, timer B, and the serial interface. The prescaler divide ratio is selected by timer mode register A
(TMA), timer mode register B (TMB), or the serial mode register (SMR).
Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input
signal. When the next clock signal is applied after timer A becomes $FF, it generates an overflow and
becomes $00. This overflow causes the timer A interrupt request flag (IFTA: $001, bit 2) to go to 1. This
timer can function as an interval timer periodically generating overflow output at every 256th clock signal
input.
The clock input signals to timer A are selected by timer mode register A (TMA: $008).
Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock
source, and the prescaler divide ratio of timer B. When the external event input is used as an input clock
signal to timer B, select R33/INT1 as INT1 and set the external interrupt mask (IM1) to prevent an external
interrupt request from occurring.
HD404019R Series
25
Timer B is initialized according to the data written into timer load register B by software. Timer B counts
up at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will
generate an overflow output. In this case, if the autoreload function is selected, timer B is initialized
according to the value of timer load register B. If it is not selected, timer B goes to $00. The timer B
interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output.
Timer Mode Register A (TMA: $008): Timer mode register A is a 3-bit write-only register. The TMA
controls the prescaler divide ratio of timer A clock input as shown in table 11. Timer mode register A is
initialized to $0 by MCU reset.
Table 11 Timer Mode Register A
TMA2 TMA1 TMA0 Prescaler Divide Ratio
000÷ 2048
1÷ 1024
10÷ 512
1÷ 128
100÷ 32
1÷ 8
10÷ 4
1÷ 2
Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which
selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as
shown in table 12. Timer mode register B is initialized to $0 by MCU reset.
The operation mode of timer B changes at the second instruction cycle after timer mode register B is
written to. Timer B should be initialized by writing data into timer load register B after the contents of
TMB are changed. The configuration and function of timer mode register B is shown in figure 14.
Table 12 Timer Mode Register B
TMB3 Auto-Reload Function
0No
1 Yes
HD404019R Series
26
TMB2 TMB1 TMB0 Prescaler Divide Ratio, Clock Input Source
000÷ 2048
1÷ 512
10÷ 128
1÷ 32
100÷ 8
1÷ 4
10÷ 2
1INT1 (external event input)
Transmit clock selection
R40/SCK pin mode selection
SMR3
SMR: $005
SMR2 SMR1 SMR0
R42/SO pin mode selection
R41/SI pin mode selection
R32/INT0 pin mode selection
R33/INT1 pin mode selection
PMR3
PMR: $004
PMR2 PMR1 PMR0
Timer B input clock selection
Auto-reload function selection
TMB3
TMB: $009
TMB2 TMB1 TMB0
TMA: $008
TMA2 TMA1 TMA0
Timer A input clock selection
Figure 14 Mode Register Configuration and Function
Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit write-
only timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL:
$00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B). (Refer to figure 2.)
Timer counter B can be initialized by writing data into timer load register B. Write the low-order digit first,
and then the high-order digit. The timer counter is initialized when the high-order digit is written. The timer
load register is initialized to $00 by the MCU reset.
HD404019R Series
27
The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order
digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when
the high-order digit is read.
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 13).
Table 13 Timer A Interrupt Request Flag
IFTA Interrupt Request
0No
1 Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request
from being generated by the timer A interrupt request flag (table 14).
Table 14 Timer A Interrupt Mask
IMTA Interrupt Request
0 Enabled
1 Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B (table 15).
Table 15 Timer B Interrupt Request Flag
IFTB Interrupt Request
0No
1 Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request
from being generated by the timer B interrupt request flag (table 16).
Table 16 Timer B Interrupt Mask
IMTB Interrupt Request
0 Enabled
1 Disabled (masked)
HD404019R Series
28
Input/Output
The MCU has 58 I/O pins, 32 standard and 26 high voltage. One of three circuit types can be selected by
the mask option for each standard pin: CMOS, with pull-up MOS, and without pull-up MOS (NMOS open
drain); and one of two circuit types can be selected for each high-voltage pin: with pull-down MOS and
without pull-down MOS (PMOS open drain). Since the pull-down MOS is connected to the internal Vdisp
line, the RA1/Vdisp pin must be selected as V disp via the mask option when the option with pull-down MOS is
selected for at least one high-voltage pin. See table 17 for I/O pin circuit types.
When every input/output pin is used as an input pin, the mask option and output data must be selected in
the manner specified in table 18.
Output Circuit Operation of With Pull-Up MOS Standard Pins: In the standard pin option with pull-up
MOS, the circuit shown in figure 15 is used to shorten the rise time of the output.
When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this
instruction. This pulse will switch the PMOS (B) on and shorten the rise time. The write pulse keeps the
PMOS in the on state for one-eighth of the instruction cycle time. While the write pulse is 0, a high output
level is maintained by the pull-up MOS (C).
When the HLT signal becomes 0 in the stop mode, MOS (A), (B), and (C) turn off.
D Port: I/O port D has 16 discrete I/O pins, each of which can be addressed independently. It can be
set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD
instructions. See tables 17 and 18 for the classification of standard pin, high-voltage pin, and the I/O pin
circuit types.
R Ports: The eleven R ports are composed of 36 I/O pins and 6 input-only pins. Data is input through the
LAR and LBR instructions and output through the LRA and LRB instructions. The MCU will not be
affected by writing into the input-only and/or non-existing ports, while invalid data will be read when the
output-only and/or non-existing ports are read.
The R32, R33, R40, R41, and R42 pins are multiplexed with the INT0, INT1, SC K, SI, and SO pins,
respectively. See tables 17 and 18 for the classification of standard pins, high-voltage pins and selectable
circuit types of these I/O pins.
Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction because of noise. The I/O
pins should be fixed as follows to prevent malfunction.
High-voltage pins: Select without pull-down MOS (PMOS open drain) via the mask option and connect to
VCC on the printed circuit board.
Standard pins: Select without pull-up MOS (NMOS open drain) via the mask option and connect to GND
on the printed circuit board.
R40/SCK and R42/SO should be used as R40 and R42 by the serial mode register and port mode register,
respectively.
HD404019R Series
29
Table 17 I/O Pin Circuit Types
Standard Pins
Without Pull-Up MOS
(NMOS Open Drain) (A) With Pull-Up MOS (B) CMOS (C) Applicable
Pins
I/O
common
pins
Output
data
HLT
HLT Input
data
Output
data
HLT
VCC
Input
data
HLT
VCC Write
pulse
Output
data
HLT
VCC
Input
data
HLT
D0–D3,
R30–R33,
R40–R43,
R50–R53,
R60–R63,
R70–R73,
R80–R83
Input pins
HLT Input
data
HLT Input
data
HLT
V
CC
—R9
0
–R93
High Voltage Pins
Without Pull-Down MOS
(PMOS Open Drain) (D) With Pull-Up MOS (E) Applicable
Pins
I/O
common
pins
VCC
HLT
HLT
Output
data
Input
data
VCC
HLT
HLT
Output
data
Input
data
VCC
Vdisp
D4–D15,
R00–R03,
R10–R13,
R20–R23
Input pins
HLT Input
data
HLT Input
data
VCC
Vdisp
RA0
Input pins HLT Input
data —RA
1
HD404019R Series
30
Standard Pins
Without Pull-Up MOS
(NMOS Open Drain) or CMOS (A or C) With Pull-Up MOS (B) Applicable
Pins
I/O
common
pins
Internal SC
K
VCC
SCK
HLT + mode select
HLT
Internal SCK
VCC
SCK
VCC HLT +
mode select
HLT
SCK*
(output mode)
Output
pins
SO
VCC
HLT VCC
VCC
SO
HLT
SO
Input pins Input
data
HLT
Input
data
HLT
INT0, INT1
SI, SCK
(input mode)
Notes: In the stop mode, HLT is 0, HLT is 1 and I/O pins are in high impedance.
*If the MCU is interrupted by the serial interface in the external clock input mode, the SCK terminal
becomes input only.
Table 18 Data Input from Common Input/Output Pins
I/O Pin Circuit Type Input Possible Input Pin State
Standard pins CMOS No —
Without pull-up MOS (NMOS open drain) Yes 1
With pull-up MOS Yes 1
High voltage pins Without pull-down MOS (PMOS open drain) Yes 0
With pull-down MOS Yes 0
HD404019R Series
31
MOS Buffer
A
B
C
On-Resistance Value
Approximately 250 Ω
Approximately 1 kΩ
Approximately 30 kΩ to 160 kΩ (VCC = 5 V)
Write pulse
(output
instruction)
HLT
Data
PMOS (B)
NMOS (A)
Pull-up MOS (C)
1 instruction cycle
Output instruction execution
Write pulse
VCC VCC
Figure 15 Output Circuit Operation of With Pull-Up MOS Standard Pins
HD404019R Series
32
Reset
Pulling the RESET pin high resets the MCU. At power-on or when cancelling the stop mode, the reset must
satisfy tRC for the oscillator to stabilize. In all other cases, at least two instruction cycles are required for the
MCU to be reset.
Table 19 shows the components initialized by MCU reset, and the status of each.
Table 19 Initial Values After MCU Reset
Item Initial Value by
MCU Reset Contents
Program counter (PC) $0000 Execute program from the top of
ROM address
Status flag (ST) 1 Enable branching with conditional
branch instructions
Stack pointer (SP) $3FF Stack level is 0
I/O pins, output
register Standard
pins (A) Without pull-up
MOS 1 Enable to input
(B) With pull-up
MOS 1 Enable to input
(C) CMOS 1 —
High-voltage
pins (D) Without pull-
down MOS 0 Enable to input
(E) With pull- down
MOS 0 Enable to input
Interrupt flags Interrupt enable flag (IE) 0 Inhibit all interrupts
Interrupt request flag (IF) 0 No interrupt request
Interrupt mask (IM) 1 Mask interrupt request
Mode registers Port mode register (PMR) 0000 See Port Mode Register section
Serial mode register (SMR) 0000 See Serial Mode Register section
Timer mode register A (TMA) 000 See Timer Mode Register A section
Timer mode register B (TMB) 0000 See Timer Mode Register B section
Timer/counters Prescaler $000 —
Timer counter A (TCA) $00 —
Timer counter B (TCB) $00 —
Timer load register (TLR) $00 —
Octal counter 000 —
HD404019R Series
33
Item After MCU Reset to Recover from
Stop Mode After MCU Reset to Recover from
Other Modes
Carry flag (CA) The contents of the items before
MCU reset are not retained. It is
necessary to initialize them by
software.
The contents of the items before
MCU reset are not retained. It is
necessary to initialize them by
software.
Accumulator (A)
B register (B)
W register (W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SR)
RAM The contents of RAM before MCU
reset (just before STOP instruction)
are retained
Same as above for RAM
Internal Oscillator Circuit
Figure 16 outlines the internal oscillator circuit. A crystal oscillator or ceramic oscillator can be selected as
the oscillator type. Refer to table 20 to select the oscillator type. In addition, see figure 17 for the layout of
the crystal or ceramic oscillator.
OSC
2
1/4
divider
circuit
Timing
generator
circuit
OSC
1
Oscillator System
clock
Figure 16 Internal Oscillator Circuit
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
D0
GND
OSC2
OSC1
TEST
RESET
Figure 17 Layout of Crystal or Ceramic Oscillator
HD404019R Series
34
Table 20 Examples of Oscillator Circuits
Circuit Configuration Circuit Constants
External clock
operation
(OSC1, OSC2)OSC1
Open OSC2
Oscillator
Ceramic oscillator
(OSC1, OSC2)OSC1
C1
C2OSC2
Rf
GND
Ceramic
oscillator
Ceramic oscillator
CSA4.00MG (Murata)
Rf: 1 MΩ ±20%
C1: 30 pF ±20%
C2: 30 pF ±20%
Crystal oscillator
(OSC1, OSC2)
AT-cut parallel
resonance crystal
C0
LC1RSOSC2
OSC1
OSC1
C1
C2OSC2
Rf
GND
Crystal
Rf: 1 MΩ ±20%
C1: 10 pF to 22 pF ±20%
C2: 10 pF to 22 pF ±20%
Crystal: Equivalent circuit shown
at bottom left
Co: 7 pF max.
Rs: 100 Ω max.
f: 1.0 MHz to 4.5 MHz
Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator
manufacturer. The circuit parameters are affected by the crystal, ceramic resonator, and the
floating capacitance when designing the board.
When using the resonator, consult with the crystal or ceramic oscillator manufacturer to
determine the circuit parameters.
2. Wiring among OSC1, OSC2, and other elements should be as short as possible, and avoid
crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator.
Refer to figure 17.
HD404019R Series
35
Operating Modes
The MCU has two low-power dissipation modes, standby mode and stop mode (table 21). Figure 18 is a
mode transition diagram for these modes.
Standby Mode: Executing the SBY instruction puts the MCU into standby mode. In standby mode, the
oscillator circuit is active, and the interrupts, timer/counters, and serial interface remain working. On the
other hand, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and
I/O pins retain the states they were in just before the MCU went into standby mode.
Table 21 Low-Power Dissipation Modes
Condition Standby Mode Stop Mode
Instruction SBY instruction STOP instruction
Oscillator circuit Active Stopped
Instruction execution Stopped Stopped
Registers, flags Retained Reset*1
Interrupt function Active Stopped
RAM Retained Retained
Input/output pins Retained*2High impedance
Timer/counters, serial interface Active Stopped
Cancellation method RESET input, interrupt request RESET input
Notes: 1. The MCU recovers from the stop mode by RESET input. Refer to table 19 for the contents of
flags and registers.
2. When I/O circuits are active, an I/O current may flow in the standby mode, depending on the
state of the I/O pins. This is an additional current added to the standby mode current dissipation.
Standby
mode Stop
mode
Active
mode
Reset
SBY
instruction
RESET = 1
Interrupt
request
RESET = 1 RESET = 0
RESET = 1
STOP
instruction
Figure 18 MCU Operating Mode Transition
HD404019R Series
36
Standby mode may be cancelled by inputting RESET or by asserting an interrupt request. In the former
case the MCU is reset. In the later case, the MCU becomes active and executes the next instruction
following the SBY instruction. If the interrupt enable flag is 1 when an interrupt request is asserted, the
interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution
continues.
Figure 19 shows the flowchart of the standby mode.
Standby
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
RESET
= 1? No
Yes
Restart
processor clocks
Reset MCU Execute
instruction Accept
interrupt
Restart
processor clocks
Yes
Yes
Yes
No
No Yes
Yes
No
No Yes
Yes
No
No Yes
Yes No
No
IF0 = 1?
IM0 = 0?
IF1 = 1?
IM1 = 0?
IFTA = 1?
IMTA = 0?
IFTB = 1?
IE = 1?
No
IFS = 1?
IMS = 0?
Yes
Yes
No
No
IMTB = 0?
Execute next
instruction
(active mode)
Figure 19 MCU Operating Flowchart in Standby Mode
HD404019R Series
37
Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit
and every function of the MCU stop.
The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 20, reset input
must be applied for at least tRC for oscillation to be stabilized. (Refer to the AC Characteristics table.) After
the stop mode is cancelled, RAM retains the state it was in just before the MCU went into stop mode, but
the accumulator, B register, W register, X/SPX registers, Y/SPY registers, carry flag, and serial data
register will not retain their contents.
Oscillator
Internal clock
RESET
Stop mode
STOP instruction
execution tres ≥ tRC (stabilization time)
tres
Figure 20 Timing of Stop Mode Cancellation
HD404019R Series
38
PROM Mode Pin Description
Table 22 describes the pin functions in PROM mode.
Table 22 PROM Mode Signals
Pin Number MCU Mode PROM Mode
DC-64S,
DP-64S FP-64B FP-64A Symbol I/O Symbol I/O
1 5957D
11 I/O VCC
2 6058D
12 I/O
3 6159D
13 I/O
4 6260D
14 I/O
5 6361D
15 I/O
6 6462P0
0I/O A1I
7 1 63 R01I/O A2I
8 2 64 R02I/O A3I
931R0
3I/O A4I
1042R1
0I/O A5I
1153R1
1I/O A6I
1264R1
2I/O A7I
1375R1
3I/O A8I
1486R2
0I/O A0I
15 9 7 R21 I/O A10 I
16 10 8 R22I/O A11 I
17 11 9 R23I/O A12 I
18 12 10 RA0IV
CC
19 13 11 RA1/Vdisp I
20 14 12 R30I/O A13 I
21 15 13 R31I/O A14 I
22 16 14 R32/INT0I/O
23 17 15 R33/INT1I/O
24 18 16 R50I/O
25 19 17 R51I/O
26 20 18 R52I/O
27 21 19 R53I/O
28 22 20 R60I/O
29 23 21 R61I/O
HD404019R Series
39
Pin Number MCU Mode PROM Mode
DC-64S,
DP-64S FP-64B FP-64A Symbol I/O Symbol I/O
30 24 22 R62I/O
31 25 23 R63I/O
32 26 24 VCC VCC
33 27 25 R40/SCK I/O O4I/O
34 28 26 R41/SI I/O O5I/O
35 29 27 R42/SO I/O O6I/O
36 30 28 R43I/O O7I/O
37 31 29 R70I/O CE I
38 32 30 R71I/O OE I
39 33 31 R72I/O
40 34 32 R73I/O O4I/O
41 35 33 R80I/O O3I/O
42 36 34 R81I/O O2I/O
43 37 35 R82I/O O1I/O
44 38 36 R83I/O O0I/O
45 39 37 R90IV
PP
46 40 38 R91IA
9I
47 41 39 R92IM0I
48 42 40 R93IM1I
49 43 41 RESET I RESET I
50 44 42 TEST ITEST I
51 45 43 OSC1I
52 46 44 OSC2
53 47 45 GND GND
54 48 46 D0I/O O0I/O
55 49 47 D1I/O O1I/O
56 50 48 D2I/O O2I/O
57 51 49 D3I/O O3I/O
58 52 50 D4I/O
59 53 51 D5I/O
HD404019R Series
40
Pin Number MCU Mode PROM Mode
DC-64S,
DP-64S FP-64B FP-64A Symbol I/O Symbol I/O
60 54 52 D6I/O
61 55 53 D7I/O
62 56 54 D8I/O
63 57 55 D9I/O
64 58 56 D10 I/O VCC
Notes: 1. I/O: Input/output pins
I: Input pins
O: Output pins
2. Connect each pair of O4, O3, O2, O1, and O0. Hitachi supplies the socket adapter on which these
pairs are internally connected.
HD404019R Series
41
Programmable ROM Operation
The on-chip PROM of HD4074019 and HD407L4019 are programmed in PROM mode. The PROM mode
is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 21. In PROM mode, the MCU
does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM
programmer and a 64-to-28-pin socket adapter. Table 24 lists the recommended PROM programmers and
socket adapters.
Since the instruction of the HMCS400 series consists of 10 bits, the HMCS400-series microcom puter
incorporates a conversion circuit used as a general-purpose PROM programmer. By this circuit, an
instruction is read or programmed using 2 addresses, the low-order 5 bits and the high-order 5 bits. For
example, if 8 kwords of an on-chip PROM are programmed by a general purpose PROM programmer, 16
kbytes of addresses ($0000 to $3FFF) should be specified.
Programming and Verification
The HD4074019 and HD407L4019 can be programmed at high-speed without causing voltage stress or
affecting data reliability.
Table 23 shows how programming and verification modes are selected.
Erasing
PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits become 1s.
The erasing specifications are as follows: ultraviolet (UV) light with wavelength 2537 Å with a minimum
irradiation of 15 W sec/cm2. These conditions are satisfied by exposing the LSI to a 12,000-µW/cm2 UV
source for 15 to 20 minutes at a distance of 1 inch.
Precautions
1. Addresses $0000 to $7FFF should be specified if the PROM is programmed by a PROM programmer.
Note that the plastic package type cannot be erased and reprogrammed.
(Only ceramic window packages can be erased and reprogrammed.)
2. Make sure that the PROM programmer, socket adapter, and LSI match properly. Using the wrong
programmer for the socket adapter may cause an overvoltage and damage the LSI. Make sure that the
LSI is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed to the programmer.
3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the
HD4074019 and HD407L4019, the LSI may be permanently damaged. 12.5 V is the voltage for VPP of
Intel’s 27256.
HD404019R Series
42
Table 23 PROM Modes Selection
Pin
Mode CE OE VPP O0 to O7
Programming Low High VPP Data input
Verify High Low VPP Data output
Programming inhibited High High VPP High impedance
Table 24 Recommended PROM Programmers and Socket Adapters
PROM Programmer*Socket Adapter
Maker Type Name Package Type Type Name Maker
DATA I/O 280 DP-64S HS409ESS11H Hitachi
201 DC-64S
29B + UniPak2B FP-64B HS409ESF01H
S22 FP-64A HS409ESH01H
AVAL DATA Corp. PKW-1000 DP-64S HS409ESS21H Hitachi
PKW-1100 DC-64S
PKW-1600 FP-64B HS409ESF01H
PKW-3100 FP-64A HS409ESH01H
Note: *Since the address pins of the HD4074019 and HD407L4019 are high voltage pins, errors may
occur in device insertion tests if a PROM programmer other than those listed above is used.
HD404019R Series
43
Data
O0 to O7
Address
A0 to A14
CE
OE
CE
OE
O0 to O7
A0 to A14
VCC
RESET
TEST
M0
M1
VCC
VPP
R90/VPP
GND
VCC
Figure 21 PROM Mode Function Diagram
HD404019R Series
44
Addressing Modes
RAM Addressing Modes
As shown in figure 22, the MCU has three RAM addressing modes: register indirect addressing, direct
addressing, and memory register addressing.
X register Y register
W
13
X
2
X
1
X
0
Y
3
Y
2
Y
1
Y
0
AP
7
AP
56
AP
3
AP
4
AP
1
AP
2
AP
0
AP RAM address
Register Indirect Addressing
Instruction 1st word
Opcode
Instruction 2nd word
d
9
d
8
d
7
d
6
d
5
d
4
d
3
d
2
d
1
d
0
AP
7
AP
56
AP
3
AP
4
AP
1
AP
2
AP
0
AP RAM address
Direct Addressing
Instruction
Opcode m
3
m
2
m
1
m
0
0010
AP
7
AP
56
AP
3
AP
4
AP
1
AP
2
AP
0
AP RAM address
Memory Register Addressing
AP
8
AP
9
X W
0
W register
AP
8
AP
9
AP
8
AP
9
00
Figure 22 RAM Addressing Modes
Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits) are
used as the RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits)
following the opcode used as the RAM address.
Memory Register Addressing Mode: The memory registers (16 digits from $020 to $02F) are accessed
by executing the LAMR and XMRA instructions.
HD404019R Series
45
ROM Addressing Modes and the P Instruction
The MCU has four kinds of ROM addressing modes as shown in figure 23.
000000
Instruction 2nd wordInstruction 1st word
[JMPL]
[BRL]
[CALL]
Opcode p3p2p1p0d9d8d7d6d5d4d3d2d1d0
11PC10
9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Direct Addressing
Instruction
b7b6b5b4b3b2b1b0
Opcode[BR]
PC11PC10
9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Current Page Addressing
Instruction
a5a4a3a2a1a0
Opcode[CAL]
PC11PC10 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PC
Zero Page Addressing
Instruction
B register Accumulator
A3A2A1A0
B3B2B1B0
p3p2p1p0
Opcode[TBR]
PC11PC10
9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Table Data Addressing
PC
13
PC 12
PC
13
PC 12
PC
13
PC 12
PC
00
PC13 PC12
00
Program counter
Figure 23 ROM Addressing Modes
HD404019R Series
46
Direct Addressing Mode: The program can branch to any address in ROM memory space by executing
the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC13 to PC0)
with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. By executing
the BR instruction, the program can branch to an address on the current page. This instruction replaces the
low-order eight bits of the program counter (PC7 to PC0) with 8-bit immediate data.
When the BR instruction is on a page boundary (256n + 255) (figure 24), executing it transfers the PC
contents to the next page, due to the hardware architecture. Consequently, the program branches to the next
page when the BR instruction is used on a page boundary. The HMCS400-series cross macroassembler has
an automatic paging facility for ROM pages.
Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page
subroutine area, which is located at $0000 to $003F. When the CAL instruction is executed, 6 bits of
immediate data are placed in the low-order six bits of the program counter (PC5 to PC0) and 0s are placed in
the high-order eight bits (PC13 to PC6).
Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address
determined by the contents of the 4-bit immediate data, accumulator, and B register.
P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure
25). When bit 8 in the referred ROM data is 1, 8 bits of ROM data are written into the accumulator and B
register. When bit 9 is 1, 8 bits of ROM data are written into the R1 and R2 port output registers. When
both bits 8 and 9 are 1, ROM data are written into the accumulator and B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
HD404019R Series
47
BR AAA
AAA NOP
BR AAA
BR BBB
BBB NOP
256(n – 1) + 255
256n
256n + 254
256n + 255
256(n + 1)
Figure 24 BR Instruction Branch Destination on a Page Boundary
HD404019R Series
48
Instruction
p3p2p1p0
Opcode[P] B register Accumulator
A1A0
A2
A3
B1B0
B2
B3
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
Referred ROM address
RO03456789 RORORORORORORORORO 12
ROM data
A0
A1
A2
A3
B0
B1
B2
B3
Accumulator, B register
RO03456789 RORORORORORORORORO 12
ROM data
If RO = 1
8
R10
R11
R12
R13
R20
R21
R22
R23
Output registers R1, R2 If RO = 1
9
Address Designation
Pattern
RA12
RA13
00
Figure 25 P Instruction
HD404019R Series
49
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +14 V 10
Pin voltage VT–0.3 to VCC + 0.3 V 1
VCC – 45 to VCC + 0.3 V 2
Total permissible input current ∑Io50 mA 3
Maximum input current Io15 mA 5, 6
Maximum output current –Io4 mA 6, 7
6 mA 7, 8
30 mA 7, 9
Total permissible output current –∑Io150 mA 4
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
should be under the conditions of the electrical characteristics. If these conditions are exceeded, it
may cause a malfunction or affect the reliability of the LSI.
All voltages are with respect to GND.
1. Standard pins.
2. High voltage pins.
3. Total permissible input current is the total sum of input currents which flow in from all I/O pins to
GND simultaneously.
4. Total permissible output current is the total sum of the output currents which flow out from VCC to
all I/O pins simultaneously.
5. Maximum input current is the maximum amount of input current from each I/O pin to GND.
6. D0 to D3 and R3 to R8.
7. Maximum output current is the maximum amount of output current from VCC to each I/O pin.
8. R0 to R2.
9. D4 to D15.
10.Applied to HD4074019 and HD407L4019.
HD404019R Series
50
Electrical Characteristics
DC Characteristics
(HD404019R: VCC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Conditions Note
Input high
voltage VIH RESET,
SCK,
INT0, INT1
0.8 VCC —V
CC + 0.3 V HD404019R, HD4074019
0.9 VCC —V
CC + 0.3 V HD40L4019R
0.8 VCC —V
CC + 0.3 V HD407L4019: VCC = 4.5 V to 5.5 V
0.9 VCC —V
CC + 0.3 V HD407L4019
SI 0.7 VCC —V
CC + 0.3 V HD404019R, HD4074019
0.8 VCC —V
CC + 0.3 V HD40L4019R
0.7 VCC —V
CC + 0.3 V HD407L4019: VCC = 4.5 V to 5.5 V
0.9 VCC —V
CC + 0.3 V HD407L4019
OSC1VCC –0.5 — VCC + 0.3 V HD404019R, HD4074019,
HD407L4019
VCC –0.3 — VCC + 0.3 V HD40L4019R
Input low
voltage VIL RESET,
SCK,
INT0, INT1
–0.3 — 0.2 VCC V HD404019R, HD4074019
–0.3 — 0.1 VCC V HD40L4019R
–0.3 — 0.2 VCC V HD407L4019: VCC = 4.5 V to 5.5 V
–0.3 — 0.1 VCC V HD407L4019
SI –0.3 — 0.3 VCC V HD404019R, HD4074019
–0.3 — 0.2 VCC V HD40L4019R
–0.3 — 0.3 VCC V HD407L4019: VCC = 4.5 V to 5.5 V
–0.3 — 0.1 VCC V HD407L4019
Input low
voltage VIL OSC1–0.3 — 0.5 V HD404019R, HD4074019,
HD407L4019
–0.3 — 0.3 V HD40L4019R
Output high
voltage VOH SCK, SO VCC –1.0 — — V –IOH = 1.0 mA
VCC –0.5 — — V –IOH = 0.5 mA
HD404019R Series
51
Item Symbol Pin Min Typ Max Unit Test Conditions Notes
Output low
voltage VOL SCK, SO — — 0.4 V IOL = 1.6 mA
Input/output
leakage current | IIL | RESET,
SCK, INT0,
INT1, SI,
SO, OSC1
——1 µAV
in = 0 V to VCC 1
Current
dissipation in
active mode
ICC VCC — — 8.0 mA HD404019R, HD4074019:
VCC = 5 V, fOSC = 4 MHz, divide by 4 2, 5
— — 8.0 mA HD40L4019R, HD407L4019:
VCC = 5 V, fOSC = 4 MHz, divide by 4 2, 5
— — 3.0 mA HD40L4019R, HD407L4019:
VCC = 3 V,
fOSC = 3.58 MHz, divide by 4
2, 5
Current
dissipation in
standby mode
ISBY VCC — — 2.0 mA VCC = 5 V, fOSC = 4 MHz, divide by 4 3, 5
Current
dissipation in
stop mode
ISTOP VCC ——10µA HD404019R, HD40L4019R:
Vin (TEST, R90) = VCC – 0.3 V to VCC,
Vin (RESET) = 0 V to 0.3 V
4
——10µA HD4074019, HD407L4019:
Vin (TEST, R90) = VCC – 0.3 V to VCC,
Vin (RESET) = 0 V to 0.3 V
Stop mode
retaining
voltage
VSTOP VCC 2 ——V
Notes: 1. Excluding pull-up MOS current and output buffer current (HD404019R, HD40L4019R) Excluding
output buffer current (HD4074019, HD407L4019)
2. The MCU is in the reset state. Input/output current does not flow.
• MCU in reset state, operation mode
• RESET, TEST: VCC
• D0 to D3, R3 to R9: VCC
• D4 to D15, R0 to R2, RA0, RA1: Vdisp
3. The timer/counter operates with the fastest clock. Input/output current does not flow.
• MCU in standby mode
• Input/output in reset state
• Serial interface: stop
• RESET: GND
• TEST: VCC
• D0 to D3, R3 to R9: VCC
• D4 to D15, R0 to R2, RA0, RA1: Vdisp
4. Excluding pull-down MOS current.
5. When fOSC = x MHz, estimate the current dissipation as follows:
maximum value at x MHz = x/4 × (maximum value at 4 MHz)
HD404019R Series
52
Input/Output Characteristics for Standard Pins
(HD404019R: VCC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Conditions Note
Input high
voltage VIH D0 to D3,
R3 to R9 0.7 VCC —V
CC + 0.3 V HD404019R, HD4074019
0.8 VCC —V
CC + 0.3 V HD40L4019R
0.7 VCC —V
CC + 0.3 V HD407L4019:
VCC = 4.5 V to 5.5 V
0.8 VCC —V
CC + 0.3 V HD407L4019
Input low
voltage VIL D0 to D3,
R3 to R9 –0.3 — 0.3 VCC V HD404019R, HD4074019
–0.3 — 0.2 VCC V HD40L4019R
–0.3 — 0.3 VCC V HD407L4019:
VCC = 4.5 V to 5.5 V
–0.3 — 0.2 VCC V HD407L4019
Output high
voltage VOH D0 to D3,
R3 to R8 VCC – 1.0 — — V HD404019R, HD40L4019R:
–IOH = 1.0 mA 1
VCC – 0.5 — — V HD404019R, HD40L4019R:
–IOH = 0.5 mA 1
Output low
voltage VOL D0 to D3,
R3 to R8 — — 0.4 V IOL = 1.6 mA
Input/output
leakage
current
| IIL |D
0
to D3,
R3 to R9 ——1 µA HD404019R, HD40L4019R:
Vin = 0 V to VCC
2
D0 to D3,
R3 to R8,
R91 to R93
——1 µA HD4074019, HD407L4019:
Vin = 0 V to VCC
3
R90——20µA
Pull-up
MOS
current
–IPU D0 to D3,
R3 to R9 30 — 150 µA HD404019R, HD40L4019R:
VCC = 5 V, Vin = 0 V 4
Notes: 1. Applied to I/O pins selected as CMOS output by mask option.
2. Excluding pull-up MOS current and output buffer current.
3. Excluding output buffer current.
4. Applied to I/O pins selected as with pull-up MOS by mask option.
HD404019R Series
53
Input/Output Characteristics for High Voltage Pins
(HD404019R: VCC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Conditions Note
Input high
voltage VIH D4 to D15,
R0 to R2,
RA0, RA1
0.7 VCC —V
CC + 0.3 V HD404019R, HD4074019
0.8 VCC —V
CC + 0.3 V HD40L4019R:
VCC = 3.5 V to 6.0 V
0.7 VCC —V
CC + 0.3 V HD407L4019:
VCC = 4.5 V to 5.5 V
0.8 VCC —V
CC + 0.3 V HD407L4019
Input low
voltage VIL D4 to D15,
R0 to R2,
RA0, RA1
VCC – 40 — 0.3 VCC V HD404019R, HD4074019
VCC – 40 — 0.2 VCC V HD40L4019R:
VCC = 3.5 V to 6.0 V
VCC – 40 — 0.3 VCC V HD407L4019:
VCC = 4.5 V to 5.5 V
VCC – 40 — 0.2 VCC V HD407L4019
Output high
voltage VOH D4 to D15 VCC – 3.0 — — V HD404019R, HD40L4019R:
–IOH = 15 mA,
VCC = 5 V ± 20%
VCC – 2.0 — — V HD404019R, HD40L4019R:
–IOH = 10 mA,
VCC = 5 V ± 20%
VCC – 1.0 — — V HD404019R, HD40L4019R:
–IOH = 4 mA
VCC – 3.0 — — V HD4074019: –IOH = 15 mA
VCC – 2.0 — — V HD4074019: –IOH = 10 mA
VCC – 1.0 — — V HD4074019: –IOH = 4 mA
VCC – 3.0 — — V HD407L4019: –IOH = 15 mA,
VCC = 4.5 V to 5.5 V
VCC – 2.0 — — V HD407L4019: –IOH = 10 mA
VCC – 1.0 — — V HD407L4019: –IOH = 4 mA
HD404019R Series
54
Item Symbol Pin Min Typ Max Unit Test Conditions Note
Output high
voltage VOH R0 to R2 VCC – 3.0 — — V HD404019R, HD40L4019R:
–IOH = 3 mA, VCC = 5 V ± 20%
VCC – 2.0 — — V HD404019R, HD40L4019R:
–IOH = 2 mA, VCC = 5 V ± 20%
VCC – 1.0 — — V HD404019R, HD40L4019R:
–IOH = 0.8 mA
VCC – 3.0 — — V HD4074019: –IOH = 3 mA
VCC – 2.0 — — V HD4074019: –IOH = 2 mA
VCC – 1.0 — — V HD4074019: –IOH = 0.8 mA
VCC – 3.0 — — V HD407L4019: –IOH = 3 mA,
VCC = 4.5 V to 5.5 V
VCC – 2.0 — — V HD407L4019: –IOH = 2 mA
VCC – 1.0 — — V HD407L4019: –IOH = 0.8 mA
Output low
voltage VOL D4 to D15,
R0 to R2 ——V
CC – 37 V HD404019R, HD40L4019R:
Vdisp = VCC – 40 V 1
——V
CC – 37 V HD404019R, HD40L4019R:
150 kΩ at VCC – 40 V 2
——V
CC – 37 V HD4074019, HD407L4019:
150 kΩ at VCC – 40 V
Input/output
leakage
current
| IIL |D
4
to D15,
R0 to R2,
RA0, RA1
——20µA HD404019R, HD40L4019R:
Vin = VCC – 40 V to VCC
3
——20µA HD4074019, HD407L4019:
Vin = VCC – 40 V to VCC
4
Pull-down
MOS
current
IPD D4 to D15,
R0 to R2,
RA0, RA1
125 — 900 µA HD404019R, HD40L4019R:
Vdisp = VCC – 35 V, Vin = VCC
1
Notes: 1. Applied to I/O pins selected as with pull-up MOS by mask option.
2. Applied to I/O pins selected as with pull-up MOS (PMOS open drain) by mask option.
3. Excluding pull-down MOS current and output buffer current.
4. Excluding output buffer current.
HD404019R Series
55
AC Characteristics
(HD404019R: VCC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Conditions Note
Oscillation
frequency fOSC OSC1,
OSC2
0.4 4 4.5 MHz HD404019R: divide by 4
0.4 4 4.5 MHz HD40L4019R:
VCC = 3.5 V to 6.0 V, divide by 4
0.4 — 3.58 MHz HD40L4019R: divide by 4
0.2 4 4.5 MHz HD4074019: divide by 4
0.2 4 4.5 MHz HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4
0.2 — 3.58 MHz HD407L4019
Instruction
cycle time tcyc 0.89 1 20 µs HD404019R
0.89 1 10 µs HD40L4019R:
VCC = 3.5 V to 6.0 V
1.12 — 10 µs HD40L4019R
0.89 1 20 µs HD4074019: divide by 4
0.89 1 20 µs HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4
1.12 — 20 µs HD407L4019
Oscillation
stabilization
time
tRC OSC1,
OSC2
— — 20 ms HD404019R, HD4074019 1
— — 20 ms HD40L4019R:
VCC = 3.5 V to 6.0 V 1
— — 40 ms HD40L4019R 1
— — 20 ms HD407L4019:
VCC = 4.5 V to 5.5 V 1
— — 40 ms HD407L4019 1
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable
voltage (HD404019R/HD40L4019R: 3.5 V, HD4074019: 4.5 V, HD407L4019: 3.0 V (3.5 V when
VCC = 3.5 V to 6.0 V)) at power-on until when the oscillator stabilizes, or after RESET goes high
by MCU reset to quit stop mode. At power-on or when recovering from stop mode, apply the
RESET input for more than tRC to meet the necessary time for oscillator stabilization. When using
a crystal or ceramic oscillator, consult with the crystal oscillator manufacturer since the oscillator
stabilization time depends on the circuit constants and stray capacitance. (See figure 26.)
HD404019R Series
56
Item Symbol Pin Min Typ Max Unit Test Conditions Note
External clock
high width tCPH OSC192 — — ns HD404019R, HD4074019: divide
by 4 1
92 — — ns HD40L4019R:
VCC = 3.5 V to 6.0 V, divide by 4 1
120 — — ns HD40L4019R: divide by 4 1
92 — — ns HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4 1
115 — — ns HD407L4019 1
External clock
low width tCPL OSC192 — — ns HD404019R, HD4074019:
divide by 4 1
92 — — ns HD40L4019R:
VCC = 3.5 V to 6.0 V, divide by 4 1
120 — — ns HD40L4019R: divide by 4 1
92 — — ns HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4 1
115 — — ns HD407L4019 1
External clock
rise time tCPr OSC1— — 20 ns 1
External clock
fall time tCPf OSC1— — 20 ns 1
INT0 high width tIH INT02——t
cyc 2
INT0 low width tIL INT02——t
cyc 2
INT1 high width tIH INT12——t
cyc 2
INT1 low width tIL INT12——t
cyc 2
RESET high
width tRSTH RESET 2 — — tcyc 3
Input
capacitance Cin All pins — — 30 pF HD404019R, HD40L4019R:
f = 1 MHz, Vin = 0 V
All pins
except R90
— — 30 pF HD4074019, HD407L4019:
f = 1 MHz, Vin = 0 V
R90— — 180 pF
RESET fall
time tRSTf — — 20 ms 3
Notes: 1. See figure 26.
2. See figure 27.
3. See figure 28.
HD404019R Series
57
Serial Interface Timing Characteristics
(HD404019R: VCC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
unless otherwise specified)
Item Symbol Pin Min Typ Max Unit Test Conditions Notes
Transmit clock
cycle time tScyc SCK output 1 — — tcyc Load shown in figure 30 1, 2
Transmit clock
high widths tSCKH SCK output 0.4 — — tcyc 1, 2
Transmit clock
low widths tSCKL SCK output 0.4 — — tcyc 1, 2
Transmit clock
rise time tSCKr SCK output — — 40 ns HD404019R, HD4074019,
HD407L4019 1, 2
— — 40 ns HD40L4019R:
VCC = 3.5 V to 6.0 V 1, 2
— — 200 ns HD40L4019R 1, 2
Transmit clock
fall time tSCKf SCK output — — 40 ns HD404019R, HD4074019,
HD407L4019 1, 2
— — 40 ns HD40L4019R:
VCC = 3.5 V to 6.0 V 1, 2
— — 200 ns HD40L4019R 1, 2
Transmit clock
cycle time tScyc SCK input 1 — — tcyc 1
Transmit clock
high width tSCKH SCK input 0.4 — — tcyc 1
Transmit clock
low width tSCKL SCK input 0.4 — — tcyc 1
Transmit clock
completion
detect time
tSCKHD SCK input 1 — — tcyc 3
Transmit clock
rise time tSCKr SCK input — — 40 ns 1
Transmit clock
fall time tSCKf SCK input — — 40 ns 1
Notes: 1. See figure 29.
2. See figure 30.
3. Transmit clock completion detect time is the high level period after 8 pulses of transmit clock are
input. The serial interrupt request flag is not set when the next transmit clock is input before the
transmit clock completion detect time has passed.
HD404019R Series
58
Item Symbol Pin Min Typ Max Unit Test Conditions Notes
Serial output
data delay time tDSO SO — — 300 ns HD404019R 1, 2
— — 300 ns HD40L4019R:
VCC = 3.5 V to 6.0 V 1, 2
— — 500 ns HD40L4019R 1, 2
— — 200 ns HD4074019 1, 2
— — 200 ns HD407L4019:
VCC = 4.5 V to 5.5 V 1, 2
— — 400 ns HD407L4019 1, 2
Serial input
data setup time tSSI SI 100 — — ns HD404019R 1
100 — — ns HD40L4019R:
VCC = 3.5 V to 6.0 V 1
Serial input
data setup time tSSI SI 300 — — ns HD40L4019R 1
200 — — ns HD4074019, HD407L4019 1
Serial input
data hold time tHSI SI 200 — — ns HD404019R 1
200 — — ns HD40L4019R:
VCC = 3.5 V to 6.0 V 1
400 — — ns HD40L4019R 1
100 — — ns HD4074019 1
100 — — ns HD407L4019:
VCC = 4.5 V to 5.5 V 1
200 — — ns HD407L4019 1
Notes: 1. See figure 29.
2. See figure 30.
HD404019R Series
59
1/fCP
VCC – 0.5
0.5 tCPH
tCPr tCPf
tCPL
1/fCP
VCC – 0.3
0.3 tCPH
tCPr tCPf
tCPL
HD404019R
HD4074019
HD407L4019
HD40L4019R
Figure 26 Oscillator Timing
0.8 VCC
INT0,INT10.2 VCC
0.9 VCC
INT0,INT10.1 VCC
tIH tIL
tIH tIL
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
Figure 27 Interrupt Timing
0.8 VCC
RESET 0.2 VCC
tRSTf
tRSTH
0.9 VCC
RESET 0.1 VCC
tRSTf
tRSTH
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
Figure 28 Reset Timing
HD404019R Series
60
VCC – 2.0 V (0.8 VCC)*
0.8 V (0.2 VCC)*
VCC – 2.0 V
0.8 V
SCK
SO
SI 0.7 VCC
0.3 VCC
tScyc
tSCKH
tSCKf tSCKL
tDSO
tSCKHD
tSSI tHSI
tSCKr
VCC – 2.0 V (0.9 VCC)*
0.8 V (0.1 VCC)*
VCC – 2.0 V
0.8 V
SCK
SO
SI 0.7 VCC
0.3 VCC
tScyc
tSCKH
tSCKf tSCKL
tDSO
tSCKHD
tSSI tHSI
tSCKr
Note: *VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output.
0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock input.
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
Note: *VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output.
0.8 VCC and 0.2 VCC are the threshold voltages for transmit clock input.
Figure 29 Timing of Serial Interface
VCC
R
12 kΩ
C
30 pF
Test
point 1S2074 H
or equivalent
RL = 2.6 kΩ
Figure 30 Timing Load Circuit
HD404019R Series
61
HD404019R Option List
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
R0
R1
R2
I/O option
Pin I/O ABCDE
Standard
pins
R3
R4
R5
R6
R7
R8
R9
RA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I/O option
Pin I/O ABCDE
High voltage pinsHigh voltage pins
R30
R31
R32
R33
R40
R41
R42
R43
R50
R51
R52
R53
R60
R61
R62
R63
R70
R71
R72
R73
R80
R81
R82
R83
R90
R91
R92
R93
RA0
RA1
Standard pins
High
voltage
pins
Please mark on RA1/Vdisp
Note: I/O options masked by are not available.
5 V operation: HD404019R
Low-voltage operation: HD40L4019R
Date of order
Customer
Dept.
Name
ROM code name
LSI type number
(Hitachi's entry)
1. I/O option
Please check off the appropriate applications and enter
the necessary information.
A: Without pull-up MOS (NMOS open drain)
B: With pull-up MOS
C: CMOS (not be used as input)
D: Without pull-down MOS (PMOS open drain)
E: With pull-down MOS
HD404019R Series
62
HD404019R Option List
5. System oscillator (OSC1 and OSC2)
Ceramic oscillator
Crystal oscillator
External clock
Note: If even one high-voltage pin is selected with
I/O option E, pin RA1/Vdisp must be selected
to function as Vdisp.
4. ROM code media
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are
programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
6. Stop mode
Used
Not used
2. RA1/Vdisp
RA1: Without pull-down MOS (D)
Vdisp
3. Divider (DIV)
Divide by 4
Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTATTM version).
7. Package
DP-64S
FP-64A
FP-64B
HD404019R DP-64S
FP-64A
HD40L4019R
HD404054 Series/HD404094 Series
Rev. 5.0
March 1997
Description
The HD404054 Series and HD404094 Series are HMCS400-series microcomputers designed to increase
program productivity with large-capacity memory. Each microcomputer has three timers, one serial
interface, comparator, input capture circuit.
The HD404054 Series includes three chips: the HD404052 with 2-kword ROM; the HD404054 with 4-
kword ROM; and the HD4074054 with 4-kword PROM (ZTAT version). Also, the HD404094 Series
includes three chips: the HD404092 with 2-kword ROM; the HD404094 with 4-kword ROM; and the
HD4074094 with 4-kword PROM (ZTAT version).
The HD4074054 and HD4074094 are PROM version (ZTAT microcomputers). Program can be written
to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth
the process from debugging to mass production. (The ZTATversion is 27256-compatible.)
Features
• The differences between HD404054 Series and HD404094 Series
HD404054 Series HD404094 Series
I/O pins 10 large-current output pins: Six 15-mA sinks
and four 10-mA sources • 6 largecurrent output pins: Two 15-mA
sinks and four 10-mA sources
• 4 intermediate voltage output pins
• 27 I/O pins and 8 dedicated input pins
• Three timer/counters
• Eight-bit input capture circuit
• Two timer outputs (including two PWM outputs)
• One event counter inputs (including one double-edge function)
• One clock-synchronous 8-bit serial interface
• Comparator (2 channels)
• Built-in oscillators
Main clock: Ceramic or crystal oscillator (an external clock is also possible)
HD404054 Series/HD404094 Series
2
• Six interrupt sources
Two by external sources
Four by internal sources
• Subroutine stack up to 16 levels, including interrupts
• Two low-power dissipation modes
Standby mode
Stop mode
• One external input for transition from stop mode to active mode
• Instruction cycle time: 1 µs (fOSC = 4 MHz at 1/4 division ratio)
1/4, or 1/32 division ratio can be selected by hardware
• Two operating modes
MCU mode
MCU/PROM mode (HD4074054, HD4074094)
Ordering Information
Product Name
Type HD404054 Series HD404094 Series ROM (words) RAM (digit) Package
Mask ROM HD404052H HD404092H 2,048 512 FP-44A
HD404052S HD404092S DP-42S
HD40A4052H FP-44A
HD40A4052S DP-42S
HD404054H HD404094H 4,096 FP-44A
HD404054S HD404094S DP-42S
HD40A4054H FP-44A
HD40A4054S DP-42S
ZTATHD4074054H HD4074094H 4,096 FP-44A
HD4074054S HD4074094S DP-42S
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd.
HD404054 Series/HD404094 Series
3
Pin Arrangement
RD /COMP
RD /COMP
RD
RD
RC
RE /VCref
TEST
OSC
OSC
RESET
GND
D
D
D
D
D
D
D
D
D
D
0 0
1 1
2
3
0
0
1
2
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DP-42S
CC
3 1
2 1
1 1
0
3
2
1
0
3
2
1
0
3
2
1
0
0 1
13 0
12
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
FP-44A
RE0/VCref
TEST
OSC1
OSC2
RESET
GND
D
D
D
D
D
R4 /EVND
R3
R3 /TOD
R3 /TOC
R3
R2
R2
R2
R2
R1
R1
0
3
2
1
0
3
2
1
0
3
2
5
6
7
8
9
12
13 0
0
1
NC
RC0
3
2
1 1
0 0
CC
Top view
3 1
2 1
1 1
10
0
1
2
3
4
V
SEL
R4 /SO
R4 /SI
R4 /SCK
R4 /EVND
R3
R3 /TOD
R3 /TOC
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0 /INT
D /INT
D /STOPC
RD
RD
RD /COMP
RD /COMP
V
SEL
R4 /SO
R4 /SI
R4 /SCK
D
D
D
D
D
D /STOPC
D /INT
R0 /INT
R1
R1
NC
HD404054 Series/HD404094 Series
4
Pin Description
Pin Number
Item Symbol DP-42S FP-44A I/O Function
Power supply VCC 42 38 Applies power voltage
GND 11 6 Connected to ground
Test TEST 7 2 I Used for factory testing only: Connect this pin to VCC
Reset RESET 10 5 I Resets the MCU
Oscillator OSC183I
OSC294O
Port D0–D912–21 7–16 I/O*Input/output pins addressed by individual bits; pins
D0–D3 are high-current source pins that can each
supply up to 10 mA.
The HD404054 Series: pins D4–D9are high-current
sink pins that can each supply up to 15mA.
The HD404094 Series: D4–D7 are intermediate
voltage (12 V) NMOS open-drain pins, and D8, D9 are
high-current sink pins that can each supply up to 15
mA.
D12,D13 22, 23 17, 18 I Input pins addressable by individual bits
R00–R4324–40 19–36 I/O Input/output pins addressable in 4-bit units
RD0–RD3,
RC0, RE0
1–6 39–43,1 I Input pins addressable in 4-bit units
Interrupt INT0, INT123, 24 18, 19 I Input pins for external interrupts
Stop clear STOPC 22 17 I Input pin for transition from stop mode to active mode
Serial SCK138 34 I/O Serial clock input/output pin
SI139 35 I Serial receive data input pin
SO140 36 O Serial transmit data output pin
Timer TOC, TOD 34, 35 30, 31 O Timer output pins
EVND 37 33 I Event count input pins
Comparator COMP0,
COMP1
1, 2 39, 40 I Analog input pins for voltage comparator
VCref 6 1 Reference voltage pin for inputting the threshold
voltage of the analog input pin.
Division rate SEL 41 37 I Input pin for selecting system clock division rate after
RESET input or after stop mode cancellation.
1/4 division rate: Connect it to VCC
1/32 division rate: Connect it to GND
Note: *D4–D7 of the HD404094 Series are output pins.
HD404054 Series/HD404094 Series
5
Block Diagram
RESET
TEST
STOPC
OSC
OSC
SEL
V
GND
System control
RAM
(512 4bit)
×
W (2bit)
X (4bit)
SPX (4bit)
Y (4bit)
SPY (4bit)
ST
(1bit) CA
(1bit)
A (4bit)
B (4bit)
SP (10bit)
Instruction
decoder PC (14bit)
ROM
(4,096 10bit)
(2,048 10bit)
×
×
Internal address bus
Internal data bus
External
interrupt
Timer
A
Timer
C
Timer
D
Serial
1
Compa-
rator
D portR0 portR1 portR2 portR3 portR4 portRD port
RC port
: Data bus
: Signal line
ALU
High
current
source
pins
High
current
sink pins
Intermediate
voltage NMOS
open-drain
output pins*
CPU
D
D
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
8
9
12
13
R0
0
R1
R1
R1
R1
0
1
2
3
R2
R2
R2
R2
0
1
2
3
R3
R3
R3
R3
0
1
2
3
R4
R4
R4
R4
0
1
2
3
RD
RD
RD
RD
0
1
2
3
RC
0
0
1
TOC
EVND
TOD
INT
INT
1
1
1
SI
SO
SCK
0
1
VC
ref
COMP
COMP
1
2
CC
Internal data bus
RE port
RE
0
Note: Only HD404094 Series*
HD404054 Series/HD404094 Series
6
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$07FF (HD404052, HD40A4052, HD404092), $0000–$0FFF (HD404054,
HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding.
0
15
16
63
64
2047
0
$000F
$07FF
$003F
$0040
Vector address
Zero-page subroutine
(64 words)
Program & Pattern
2048 words
(HD404052, HD40A4052,
HD404092)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
$0000 $0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
0
1
JMPL instruction
(Jump to RESET, STOPC routine)
JMPL instruction
(Jump to INT routine)
JMPL instruction
(Jump to timer A routine)
JMPL instruction
(Jump to timer D, routine)
JMPL instruction
(Jump to INT routine)
JMPL instruction
(Jump to serial 1 routine)
JMPL instruction
(Jump to timer C, routine)
Not used
$0010
4096 words
(HD404054, HD40A4054,
HD4074054,HD404094,
HD4074094)
4095 $0FFF
Figure 1 ROM Memory Map
RAM Memory Map
The MCU contains a 512-digit × 4-bit RAM area consisting of a memory register area, a data area, and a
stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.
HD404054 Series/HD404094 Series
7
0$000 $000
64
80
576
960
1023
$040
$050
4
5
6
7
0
3
12
13
14
15
8
9
11
16
17
32
35
18
19
20
63
$003
$004
$005
$006
$007
$008
$009
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$020
$023
$032
$033
$034
$035
$03F
$00E
$00F
W
W
R/W
W
W
W
W
W
W
W
W
W
W
W
R
R
W
R/W
R/W
R/W
$3C0
$240
RAM-mapped registers
Memory registers (MR)
Data (432 digits)
Stack (64 digits)
Interrupt control bits area
Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A
Miscellaneous register
Timer mode register C1
Timer C
Timer mode register D2
Register flag area
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port D to D DCR
Port D to D DCR
Port D and D DCR
03
47
89
14
15 Timer read register C lower
Timer read register C upper Timer write register C lower
Timer write register C upper
$090
R:
W:
R/W:
Read only
Write only
Read/Write
$011
$012
W
W
R
R
17
18 Timer read register D lower
Timer read register D upper Timer write register D lower
Timer write register D upper
144
W
Timer mode register D1 R/W
R/W
Timer D
Timer mode register C2
21 $015
22 $016
R
Compare data register23 $017
36 $024
37 $025
38 $026
39 $027
40 $028
41 $029
42 $02A
43 $02B
24
25
31
$018
$019
$01F
$3FF Compare enable register W
W
W
44
45
46
47
Port mode register B
Port mode register C
Detection edge select register 2
Serial mode register 1B
Port R4 DCR W
W
W
$02C
$02D
$02E
$02F
$031
$030
53
48
49
50
51
52
Two registers are mapped
on the same area.
R/W
R/W
(PMRA)
(SM1A)
(SR1L)
(SR1U)
(TMA)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
(TMC2)
(TMD2)
(CDR)
(CER)
(PMRB)
(PMRC)
(SM1B)
(ESR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(TRCL)
(TRCU)
(TRDL)
(TRDU)
(TWCL)
(TWCU)
(TWDL)
(TWDU)
Not used
Not used
Not used
Not used
Not used
Not used Not used
Not used
Not used
Not used
Figure 2 RAM Memory Map
HD404054 Series/HD404094 Series
8
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$018, $024–$034)
This area is used as mode registers and data registers for external interrupts, serial interface 1,
timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits
can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($090–$23F): 432 digits from $090 to $23F.
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
HD404054 Series/HD404094 Series
9
0
1
2
3
Bit 3 Bit 2 Bit 1 Bit 0
IMTA
(IM of timer A) IFTA
(IF of timer A) IM1
(IM of INT1)IF1
(IF of INT1)
IMTC
(IM of timer C) IFTC
(IF of timer C)
IMS1
(IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D) IFTD
(IF of timer D)
$000
$001
$002
$003
Interrupt control bits area
IM0
(IM of INT0)IF0
(IF of INT0)RSP
(Reset SP bit) IE
(Interrupt
enable flag)
32
33 ICSF
(Input capture
status flag)
$020
$021
Register flag area
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
RAME
(RAM enable
flag) Not used
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Bit 3 Bit 2 Bit 1 Bit 0
Not usedNot used
Not used Not used
Not used
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IF
ICSF
ICEF
RAME
RSP
WDON
Not used
SEM/SEMD REM/REMD TM/TMD
Allowed Allowed Allowed
Not executed Allowed Allowed
Not executed Allowed Inhibited
Allowed Not executed Inhibited
Not executed Not executed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
If the TM or TDM instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
HD404054 Series/HD404094 Series
10
$000
$003
PMRA $004
SM1A $005
SR1L $006
SR1U $007
TMA $008
MIS $00C
TMC1 $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
TMD1 $010
TRDL/TWDL $011
TRDU/TWDU $012
$013
TMC2 $014
TMD2 $015
$016
CDR $017
CER $018
$020
$023
PMRB $024
PMRC $025
$026
ESR2 $027
SM1B $028
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
$03F
Bit 3 Bit 2 Bit 1
Interrupt control bits area : Not used
R4
2
/SI
1
R4
3
/SO
1
Serial transmit clock speed selection 1
Serial data register 1 (lower digit)
Serial data register 1 (upper digit)
Clock source selection (timer A)
2
SO
1
PMOS control
1 Clock source selection (timer C)
Timer C register (lower digit)
Timer C register (upper digit)
1 Clock source selection (timer D)
Timer D register (lower digit)
Timer D register (upper digit)
Timer-C output mode selection
Timer-D output mode selection
3
Result of each analog input comparison
Register flag area
R4
0
/EVND
EVND detection edge selection 6 7
Port D
3
DCR
Port D
7
DCR Port D
2
DCR
Port D
6
DCR Port D
1
DCR
Port D
5
DCR
Port D
9
DCR
Port D
0
DCR
Port D
4
DCR
Port D
8
DCR
Port R1
3
DCR
Port R2
3
DCR
Port R3
3
DCR
Port R4
3
DCR
Port R1
2
DCR
Port R2
2
DCR
Port R3
2
DCR
Port R4
2
DCR
Port R1
1
DCR
Port R2
1
DCR
Port R3
1
DCR
Port R4
1
DCR
Port R0
0
DCR
Port R1
0
DCR
Port R2
0
DCR
Port R3
0
DCR
Port R4
0
DCR
D
12
/STOPCD
13
/INT
0
R0
0
/INT
1
R4
1
/SCK
1
Bit 0
4 5
1. Auto-reload on/off
2. Pull-up MOS control
3. Input capture selection
4. Comparator switch
5. Port/comparator selection
6. SO
1
output level control in idle states
7. Serial clock source selection 1
Notes:
**
*
*
**
*
*
Figure 5 Special Function Register Area
HD404054 Series/HD404094 Series
11
Memory registers
64
65
66
67
68
69
70
71
73
74
75
76
77
78
79
72
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
960 $3C0
1023 $3FF
MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
ST
PC
CA
PC
10
3
13
9
6
2
12
8
5
1
11
7
4
0
Bit 3 Bit 2 Bit 1 Bit 0
$3FC
$3FD
$3FE
$3FF
1020
1021
1022
1023
PC –PC :
ST:
CA:
Program counter
Status flag
Carry flag
13
Stack area
0
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
HD404054 Series/HD404094 Series
12
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
30
30
30
30
30
30
0
0
0
13
95
1
(B)
(A)
(W)
(X)
(Y)
(SPX)
(SPY)
(CA)
(ST)
(PC)
(SP)
1111
Accumulator
B register
W register
X register
Y register
SPX register
SPY register
Carry
Status
Program counter
Initial value: 0,
no R/W
Stack pointer
Initial value: $3FF, no R/W
0
0
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: 1, no R/W
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
HD404054 Series/HD404094 Series
13
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction-but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN
instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
HD404054 Series/HD404094 Series
14
Table 1 Initial Values After MCU Reset
Item Abbr. Initial
Value Contents
Program counter (PC) $0000 Indicates program execution point from start
address of ROM area
Status flag (ST) 1 Enables conditional branching
Stack pointer (SP) $3FF Stack level 0
Interrupt Interrupt enable flag (IE) 0 Inhibits all interrupts
flags/mask Interrupt request flag (IF) 0 Indicates there is no interrupt request
Interrupt mask (IM) 1 Prevents (masks) interrupt requests
I/O Port data register (PDR) All bits 1 Enables output at level 1
Data control register (DCD0 –
DCD2) All bits 0 Turns output buffer off (to high impedance)
(DCR0–
DCR4) All bits 0
Port mode register A (PMRA) - - 00 Refer to description of port mode register A
Port mode register B (PMRB) - - - 0 Refer to description of port mode register B
Port mode register C
bits 3, 1, 0 (PMRC3,
PMRC1,
PMRC0)
000 - Refer to description of port mode register C
Detection edge select
register 2 (ESR2) 00 - - Disables edge detection
Timer/ Timer mode register A (TMA) - 000 Refer to description of timer mode register A
counters, Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1
serial Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2
interface Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1
Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2
Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A
Serial mode register 1B (SM1B) - - X0 Refer to description of serial mode register 1B
Prescaler S (PSS) $000 —
Timer counter A (TCA) $00 —
Timer counter C (TCC) $00 —
Timer counter D (TCD) $00 —
Timer write register C (TWCU,
TWCL) $X0 —
Timer write register D (TWDU, $X0 —
Octal counter TWDL) 000 —
Comparator Compare enable register (CER) 0 - 00 Refer to description of voltage comparator
HD404054 Series/HD404094 Series
15
Item Abbr. Initial
Value Contents
Bit register Watchdog timer on flag (WDON) 0 Refer to description of timer C
Input capture status flag (ICSF) 0 Refer to description of timer D
Input capture error flag (ICEF) 0 Refer to description of timer D
Others Miscellaneous register (MIS) 00 - - Refer to description of operating modes, and
oscillator circuit
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist
Item Abbr.
Status After
Cancellation of Stop
Mode by STOPC Input
Status After
Cancellation of Stop
Mode by MCU Reset Status After all Other
Types of Reset
Carry flag (CA) Pre-stop-mode values are not guaranteed;
values must be initialized by program Pre-MCU-reset values
are not guaranteed;
values must be
initialized by program
Accumulator (A)
B register (B)
W register (W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SRL, SRU)
RAM Pre-stop-mode values are retained
RAM enable flag (RAME) 1 0 0
Port mode register 1
bit 2 (PMRC12) Pre-stop-mode values
are retained 00
Interrupts
The MCU has 6 interrupt sources: Two external signals (INT0, INT1), Three timer/counters (timers A, C,
and D), and one serial interface (serial 1).
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
HD404054 Series/HD404094 Series
16
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt Priority Vector Address
RESET, STOPC*— $0000
INT01 $0002
INT12 $0004
Timer A 3 $0006
Not used 4 $0008
Timer C 5 $000A
Timer D 6 $000C
Serial 1 7 $000E
Note: *The STOPC interrupt request is valid only in stop mode.
HD404054 Series/HD404094 Series
17
IE
IFO
IMO
IF1
IM1
IFTA
IMTA
IFTC
IMTC
IFTD
IMTD
$ 000,0
$ 000,2
$ 000,3
$ 001,0
$ 001,1
$ 001,2
$ 001,3
$ 002,2
$ 002,3
$ 003,0
$ 003,1
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
Priority control logic
Vector
address
Note: $m,n is RAM address $m, bit number n.
$ 003,2
$ 003,3
INT0 interrupt
INT1 interrupt
Timer A interrupt
Timer C interrupt
Timer D interrupt
Serial 1 interrupt
IFS1
IMS1
Not used
Figure 8 Interrupt Control Circuit
HD404054 Series/HD404094 Series
18
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit INT0INT1Timer A Timer C Timer D Serial 1
IE 111111
IF0 · IM0 100000
IF1 · IM1 *10000
IFTA · IMTA **1000
IFTC · IMTC ***100
IFTD · IMTD ****10
IFS1 · IMS1 *****1
Note: *Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
123456
Instruction
execution
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note: The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
*
Stacking
*
Figure 9 Interrupt Processing Sequence
HD404054 Series/HD404094 Series
19
Power on
RESET = 0?
Reset MCU
Interrupt
request?
Execute instruction
PC (PC) + 1
←
PC $0002
←
PC $0004
←
PC $0006
←
PC $000A
←
IE = 1?
Accept interrupt
IE 0
Stack (PC)
Stack (CA)
Stack (ST)
←
INT
0
interrupt?
INT
1
interrupt?
Timer-A
interrupt?
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
No
←
←
←
(serial 1 interrupt)
PC $000C
←Timer-D
interrupt?
Yes
No
No
Timer-C
interrupt?
PC $000E
←
Figure 10 Interrupt Processing Flowchart
HD404054 Series/HD404094 Series
20
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE Interrupt Enabled/Disabled
0 Disabled
1 Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input
to INT0 and INT1 as listed in table 5.
Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001)
IF0, IF1 Interrupt Request
0No
1 Yes
External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the
corresponding external interrupt request flags, as listed in table 6.
Table 6 ExternalInterrupt Masks (IM0, 1M1: $000, $001)
IM0, IM1 Interrupt Request
0 Enabled
1 Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA Interrupt Request
0No
1 Yes
HD404054 Series/HD404094 Series
21
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA Interrupt Request
0 Enabled
1 Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 9.
Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC Interrupt Request
0No
1 Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 10.
Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC Interrupt Request
0 Enabled
1 Disabled (masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
11.
Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD Interrupt Request
0No
1 Yes
HD404054 Series/HD404094 Series
22
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 12.
Table 12 Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD Interrupt Request
0 Enabled
1 Disabled (masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13 Serial Interrupt Request Flag (IFS1: $003, Bit 2)
IFS1 Interrupt Request
0No
1 Yes
Serial Interrupt Masks (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14 Serial Interrupt Mask (IMS1: $003, Bit 3)
IMS1 Interrupt Request
0 Enabled
1 Disabled (masked)
HD404054 Series/HD404094 Series
23
Operating Modes
The MCU has Three operating modes as shown in table 15. The operations in each mode are listed in
tables 16 and 17. Transitions between operating modes are shown in figure 11.
Table 15 Operating Modes and Clock Status
Mode Name
Active Standby Stop
Activation method RESET cancellation,
interrupt request,
STOPC cancellation in
stop mode
SBY instruction STOP instruction
Status System oscillator OP OP Stopped
Cancellation method RESET input,
STOP/SBY instruction RESET input, interrupt
request RESET input, STOPC
input in stop mode
Note: OP implies in operation
Table 16 Operations in Low-Power Dissipation Modes
Function Stop Mode Standby Mode
CPU Reset Retained
RAM Retained Retained
Timer A Reset OP
Timer C Reset OP
Timer D Reset OP
Serial interface 1 Reset OP
Comparator Reset Stopped
I/O Reset*Retained
Note: OP implies in operation
*Output pins are at high impedance.
Table 17 I/O Status in Low-Power Dissipation Modes
Output Input
Standby Mode Stop Mode Active Mode
D0–D9Retained High impedance Input enabled
D12, D13, RC0,
RD0–RD3, RE0
— — Input enabled
R0–R4 Retained or output of
peripheral functions High impedance Input enabled
HD404054 Series/HD404094 Series
24
Reset by
RESET input or
by watchdog timer
fOSC:
øCPU:
øPER:
Oscillate
Stop
fcyc
fOSC:
øCPU:
øPER:
Oscillate
fcyc
fcyc
fOSC:
øCPU:
øPER:
Standby mode
(TMA3 = 0)
SBY
Interrupt
fOSC:
fcyc:
Main oscillation
frequency
f /4 or or f /32
(hardware selectable)
OSC
System clock
Clock for other
peripheral functions
Active
mode
øCPU:
ø:
PER
RESET1 RESET2
RAME = 0 RAME = 1
STOPC
STOP
OSC
Stop
Stop
Stop
Stop mode
Figure 11 MCU Status Transitions
Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1
and OSC2.
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 12.
HD404054 Series/HD404094 Series
25
Standby
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
No
Yes No
Yes No
Yes No
Yes
No
Yes
Yes
Restart
processor clocks
Reset MCU Execute
next instruction Accept interrupt
Restart
processor clocks
No Yes
IF = 1,
IM = 0, and
IE = 1?
RESET = 0?
IF0 • IM0 = 1?
IF1 • IM1 = 1?
IFTA • IMTA
= 1?
IFTC •
IMTC = 1?
IFTD •
IMTD
= 1?
No
Yes
IFS1 •
IMS1 = 1?
No
Stop
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
RESET = 0?
STOPC = 0?
RAME = 1 RAME = 0
Yes
Yes
No
No
Execute
next instruction
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. The MCU enters
stop mode if the STOP instruction is executed in active mode.
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
HD404054 Series/HD404094 Series
26
Stop mode
Oscillator
Internal
clock
STOP instruction execution tres ≥tRC (stabilization period)
tres
,
STOP
or RESET
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by RESET. In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequences shown in figures 14 to 16. It is reset by
an asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
HD404054 Series/HD404094 Series
27
Power on
RESET = 0?
RAME = 0
Reset MCU
MCU
operation
cycle
No
Yes
Figure 14 MCU Operating Sequence (Power On)
HD404054 Series/HD404094 Series
28
MCU operation
cycle
IF = 1?
Instruction
execution
SBY/STOP
instruction?
PC Next
location PC Vector
address
Low-power mode
operation cycle
IE 0
Stack (PC),
(CA),
(ST)
IM = 0 and
IE = 1?
←
←←
Yes
No No
Yes
Yes
No
IF:
IM:
IE:
PC:
CA:
ST:
←
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
HD404054 Series/HD404094 Series
29
Low-power mode
operation cycle
IF = 1 and
IM = 0?
Hardware NOP
execution
←
PC Next
Iocation
MCU operation
cycle
Standby mode
IF = 1 and
IM = 0?
Hardware NOP
execution
PC Next
Iocation
←
Instruction
execution
Stop mode
No
Yes
No
Yes
For IF and IM operation, refer to figure 12.
STOPC = 0?
RAME = 1
Reset MCU
No
Yes
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
HD404054 Series/HD404094 Series
30
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 18, a ceramic
oscillator can be connected to OSC 1 and OSC2. The system oscillator can also be operated by an external
clock.
After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be
selected as 1/4 or 1/32 by setting the SEL pin level.
• 1/4 division ratio: Connect SEL to VCC.
• 1/32 division ratio: Connect SEL to GND.
OSC2
OSC1
System
oscillator 1/4 or
1/32
division
circuit*
Timing
generator
circuit
CPU with ROM,
RAM, registers,
flags, and I/O
Peripheral
function
interrupt
fcyc
tcyc
fOSC φCPU
φPER
Note: * 1/4 or 1/32 division ratio can be selected by SEL pin.
Figure 17 Clock Generation Circuit
OSC2
GND
RESET
OSC1
RE0
TEST
GND
Figure 18 Typical Layout of Ceramic Oscillator
HD404054 Series/HD404094 Series
31
Table 18 Oscillator Circuit Examples
Circuit Configuration Circuit Constants
External clock
operation External
oscillator OSC
Open
1
OSC2
Ceramic oscillator
(OSC1, OSC2) OSC
2
C1
2
COSC
1
Rf
Ceramic
oscillator
GND
Ceramic oscillator: CSB400P22 (Murata),
CSB400P (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 220 pF ± 5%
Ceramic oscillator: CSB800J122 (Murata),
CSB800J (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 220 pF ± 5%
Ceramic oscillator: CSA2.00MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Ceramic oscillator: CSA4.00MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Ceramic oscillator: CSA3.58MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of
the board, the user should consult with the ceramic oscillator manufacturer to determine the
circuit parameters.
2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross
other wiring (see figure 18).
HD404054 Series/HD404094 Series
32
Input/Output
The MCU has 27 input/output pins (D0–D9, R00–R43) and 8 input pins (D12, D13, RC0, RD0– RD3, RE 0). The
features are described below. Some input/output pins have different features between the HD404054 Series
and HD404094 Series. The differences between the HD404054 Series and HD404094 Series are listed in
table 19.
• A maximum current of 15 mA is allowed for each of the pins D4 to D9 with a total maximum current of
less than 105 mA. In addition, D0–D3 can each act as a 10-mA maximum current source.
• Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial
interface. For these pins, the peripheral function setting is done prior to the D or R port setting.
Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection
are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R43/SO1 pin can be set to NMOS open-
drain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Pins D0–D3 have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs,
which can be individually turned on or off by software.
I/O buffer configuration is shown in figure 19 programmable I/O circuits are listed in table 20, and I/O pin
circuit types are shown in table 21.
Table 19 The differences between HD404054 Series and HD404094 Series
HD404054 Series HD404094 Series
Large-current source pins (15 mA) D0–D3D0–D3
Large-current sink pins (10 mA) D4–D9D8, D9
Intermediate voltage NMOS open-drain
pins (12 V) D4–D7 (output only)
Pull-down MOS current pins D0–D3D0–D3
Pull-up MOS current pins D4–D9, R0–R4 D8, D9, R0–R4
HD404054 Series/HD404094 Series
33
Table 20-1 Programmable I/O Circuits (with pull-up MOS)
MIS3 (Bit 3 of MIS) 0 1
DCD, DCR 0 1 0 1
PDR 01010101
CMOS buffer PMOS ———On———On
NMOS — — On — — — On —
Pull-up MOS —————On—On
Note: — indicates off status.
Table 20-2 Programmable I/O Circuits (with pull-down MOS)
MIS3 (Bit 3 of MIS) 0 1
DCD, DCR 0 1 0 1
PDR 01010101
CMOS buffer PMOS ———On———On
NMOS — — On — — — On —
Pull-down MOS ————On—On—
Note: — indicates off status.
D4–D9, R port (HD404054 Series)
D8, D9, R port (HD404094 Series)
MIS3
Input control signal
VCC
Pull-up
MOS
DCD, DCR
PDR
Input data
VCC
HLT
Pull-up control signal
Buffer control signal
Output data
Figure 19-1 I/O Buffer Configuration (with pull-up MOS)
HD404054 Series/HD404094 Series
34
D0–D3 port
VCC
DCD, DCR
PDR
Pull-down control signal
Buffer control signal
Output data
MIS3
HLT
Input control signal Input data
Figure 19-2 I/O Buffer Configuration (with pull-down MOS)
HD404054 Series/HD404094 Series
35
Table 21 Circuit Configurations of I/O Pins
Pins
I/O Pin Type Circuit HD404054
Series HD404094
Series
Input/output
pins VCC VCC Pull-up control signal
Buffer control
signal
Output data
Input data
HLT
MIS3
DCD, DCR
PDR
Input control signal
D4–D9,
R0–R4 D8, D9,
R0–R4
VCC
DCD, DCR
PDR
Pull-down control
signal
Buffer control signal
Output data
MIS3
HLT
Input data
Input control signal D0–D3D0–D3
VCC VCC Pull-up control signal
Buffer control
signal
Output data
Input data
HLT
MIS3
DCR
PDR
Input control signal
MIS2
R43R43
Output pins
Output data
HLT
PDR
DCD
—D
4
–D7
HD404054 Series/HD404094 Series
36
Pins
I/O Pin Type Circuit HD404054
Series HD404094
Series
Input pins Input data
Input control signal
D12, D13, RC0
RD0–RD3, RE0
D12, D13, RC0
RD0–RD3, RE0
Peripheral
function
pins
Input/
output pins VCC VCC Pull-up control signal
Output data
Input data
HLT
MIS3
SCK1
SCK1
SCK1SCK1
Output pins VCC VCC Pull-up control signal
PMOS control
signal
Output data
HLT
MIS3
SO1
MIS2
SO1SO1
V
CC
V
CC
Pull-up control signal
Output data
HLT
MIS3
TOC, TOD
TOC, TOD TOC, TOD
Input pins
V
CC
Input data
HLT
MIS3
SI
1
, INT
1
,
EVND
PDR
SI1, INT1,
EVND SI1, INT1,
EVND
Input data INT0,
STOPC
INT0,
STOPC
INT0,
STOPC
Note: The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal
becomes low, and input/output pins enter high-impedance state.
D Port (D0–D13): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D3 are high-
current sources, and D12 and D13 are input-only pins. D4–D9 of the HD404054 Series are high-current sinks.
D4–D7 of the HD404094 Series are middle voltage output-only pins, and D8 and D9 are high-current sink
pins.
Pins D0–D9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D13 are tested by the TD and
TDD instructions.
HD404054 Series/HD404094 Series
37
The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 20).
Pins D12 and D13 are multiplexed with peripheral function pins S T OP C and I NT0, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 22).
R Ports (R0 0–RE0): 17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these
ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output
data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R
ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034) that are mapped to
memory addresses (figure 20).
Pin R00 is are multiplexed with peripheral pin INT1 respectively. The peripheral function modes of these
pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21).
Pins R31–R32 are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function
modes of these pins are selected by bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014),
and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24).
Pin R40 is multiplexed with peripheral pin EVND respectively. The peripheral function modes of these
pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22).
Pins R41–R43 are multiplexed with peripheral pins SCK1, SI1, and SO1, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26.
Ports RD0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively. The
function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018)
(figure 27).
Port RE0 is multiplexed with peripheral function pin VC ref. While functioning as VC ref, do not use this pin
as an R port at the same time, otherwise, the MCU may malfunction.
Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D12 and D13. The on/off status of
all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin—enabling on/off control of that pin alone (table 20 and figure 28).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by
their pull-up MOS transistors or by resistors of about 100 kΩ or pulled down to GND by their pull-down
MOS transistors.
Note: *If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B
register.
HD404054 Series/HD404094 Series
38
Bit
Initial value
Read/Write
Bit name
3
0
W
DCD03–
2
0
W
DCD02–
0
0
W
DCD00–
1
0
W
DCD01–
DCD0, DCD1
Data control register
DCD13 DCD12 DCD10DCD11
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
DCD20
1
0
W
DCD21
DCD2
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
DCR00
1
—
—
Not used
(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034)
DCR0
Bit
Initial value
Read/Write
Bit name
Correspondence between ports and DCD/DCR bits
0
1
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
Off (high-impedance)
On
3
0
W
DCR13–
2
0
W
DCR12–
0
0
W
DCR10–
1
0
W
DCR11–
DCR43 DCR42 DCR40DCR41
DCR1 to DCR4
All Bits CMOS Buffer On/Off Selection
Register Name
D
3
D
7
—
—
R1
3
R2
3
R3
3
R4
3
Bit 3
D
2
D
6
—
—
R1
2
R2
2
R3
2
R4
2
Bit 2
D
1
D
5
D
9
—
R1
1
R2
1
R3
1
R4
1
Bit 1
D
0
D
4
D
8
R0
0
R1
0
R2
0
R3
0
R4
0
Bit 0
Figure 20 Data Control Registers (DCD, DCR)
HD404054 Series/HD404094 Series
39
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
PMRB0
1
—
—
Not used
Port mode register B (PMRB: $024)
PMRB0
0
1
R00/INT1 mode selection
R00
INT1
Figure 21 Port Mode Register B (PMRB)
Bit
Initial value
Read/Write
Bit name
3
0
W
PMRC3
2
0
W
PMRC2*
0
—
—
Not used
1
0
W
PMRC1
Port mode register C (PMRC: $025)
PMRC1
0
1
R40/EVND mode selection
R40
EVND
PMRC2
0
1
D12
STOPC
PMRC3
0
1
D13
D13/INT0 mode selection
INT0
D12/STOPC mode selection
Note: *PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop
mode, PMRC2 is not reset but retains its value.
Figure 22 Port Mode Register C (PMRC)
HD404054 Series/HD404094 Series
40
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
R/W
TMC22
0
0
R/W
TMC20
1
0
R/W
TMC21
Timer mode register C2 (TMC2: $014)
TMC22 TMC20
0
1
0
1
0
1
0
1
TMC21
0
1
0
1
0
1
R31/TOC mode selection
R31
TOC
TOC
TOC
—
TOC
R31 port
Toggle output
0 output
1 output
Inhibited
PWM output
Figure 23 Timer Mode Register C2 (TMC2)
HD404054 Series/HD404094 Series
41
Bit
Initial value
Read/Write
Bit name
3
0
R/W
TMD23
2
0
R/W
TMD22
0
0
R/W
TMD20
1
0
R/W
TMD21
Timer mode register D2 (TMD2: $015)
TMD22 TMD20
0
1
0
1
0
1
0
1
TMD21
0
1
0
1
0
1
R32/TOD mode selection
R32
TOD
TOD
TOD
—
TOD
R32
R32 port
Toggle output
0 output
1 output
Inhibited
PWM output
Input capture (R32 port)
TMD23
0
1×××
×: Don’t care
Figure 24 Timer Mode Register D2 (TMD2)
PMRA0
0
1
R43/SO1 mode selection
R43
SO1
Bit
Initial value
Read/Write
Bit name
2
—
—
Not used
0
0
W
PMRA0
1
0
W
PMRA1
Port mode register A (PMRA: $004)
PMRA1
0
1
R42/SI1 mode selection
R42
SI1
3
—
—
Not used
Figure 25 Port Mode Register A (PMRA)
HD404054 Series/HD404094 Series
42
Bit
Initial value
Read/Write
Bit name
3
0
W
SM1A3
2
0
W
SM1A2
0
0
W
SM1A0
1
0
W
SM1A1
Serial mode register 1A (SM1A: $005)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Output
Output
Output
Output
Output
Input
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
System clock
External clock
÷2048
÷512
÷128
÷32
÷8
÷2
—
—
SM1A2 SM1A0SM1A1 Clock source
SM1A3
0
1
R41/SCK1
mode selection SCK1
R41
SCK1
Prescaler
division
ratio
Figure 26 Serial Mode Register 1A (SM1A)
Bit
Initial value
Read/Write
Bit name
3
0
W
CER3
2
—
—
Not used
0
0
W
CER0
1
0
W
CER1
Compare enable register (CER: $018)
CER1
0
0
1
1
Analog input pin selection
COMP0
COMP1
Not used
Not used
CER3
Digital input mode:
RD /COMP0 and RD /COMP1
operate as an R port.
Digital/Analog selection
Analog input mode:
RD /COMP0 and RD /COMP1
operate as analog input.
0
1
CER0
0
1
0
1
01
01
Figure 27 Compare Enable Register
HD404054 Series/HD404094 Series
43
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
MIS2
CMOS buffer
on/off selection
for pin R43/SO1
Miscellaneous register (MIS: $00C)
0
1
On
Off
MIS3
0
1
Pull-up MOS
on/off selection
Off
On
0
—
—
Not used
1
—
—
Not used
Figure 28 Miscellaneous Register (MIS)
HD404054 Series/HD404094 Series
44
Prescalers
The MCU has the following prescaler S.
The prescaler operating conditions are listed in table 22, and the prescaler output supply is shown in figure
29. The timers A, C, D input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset.
Table 22 Prescaler Operating Conditions
Prescaler Input Clock Reset Condition Stop Conditions
Prescaler S System clock MCU reset MCU reset, stop mode
System
clock Prescaler S
Timer A
Timer C
Timer D
Serial 1
Figure 29 Prescaler Output Supply
HD404054 Series/HD404094 Series
45
Timers
The MCU has three timer/counters (A, C, and D).
• Timer A: Free-running timer
• Timer C: Multifunction timer
• Timer D: Multifunction timer
Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are
listed in table 23. The operating modes are selected by software.
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
The block diagram of timer A is shown in figure 30.
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 31.
HD404054 Series/HD404094 Series
46
Table 23 Timer Functions
Functions Timer A Timer C Timer D
Clock source Prescaler S Available Available Available
External event — — Available
Timer functions Free-running Available Available Available
Event counter — — Available
Reload — Available Available
Watchdog — Available —
Input capture — — Available
Timer outputs Toggle — Available Available
0 output — Available Available
1 output — Available Available
PWM — Available Available
Note: — means not available.
System
clock
Selector
Prescaler S (PSS)
Internal data bus
Timer A interrupt
request flag
(IFTA)
Clock Overflow
Timer
counter A
(TCA)
Timer mode
register A
(TMA)
3
øPER
2
4
8
32
128
512
1024
2048
÷
÷
÷
÷
÷
÷
÷
÷
Figure 30 Block Diagram of Timer A
HD404054 Series/HD404094 Series
47
Bit
Initial value
Read/Write
Bit name
2
0
W
TMA2
0
0
W
TMA0
1
0
W
TMA1
Timer mode register A (TMA: $008)
00
1
0
1
0
1
0
1
0
1
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
Operating mode
Timer A mode
TMA1TMA2 TMA0 Source
prescaler
2048tcyc
1024tcyc
512tcyc
128tcyc
32tcyc
8tcyc
4tcyc
2tcyc
Input clock
frequency
0
1
1
3
—
—
Not used
Note: Timer counter overflow output period (seconds) = input clock period (seconds) 256. ×
Figure 31 Timer Mode Register A (TMA)
HD404054 Series/HD404094 Series
48
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle, 0, 1, and PWM outputs)
The block diagram of timer C is shown in figure 32.
Watchdog on
flag (WDON)
System
reset signal Timer C interrupt
flag (IFTC)
Timer output
control logic Timer read register CU (TRCU)
Timer output
control Timer read
register CL
(TRCL)
Clock Timer counter C
(TCC)
Selector
System
clock Prescaler S (PSS)
Overflow
Internal data bus
Timer write
register CU
(TWCU) Timer write
register CL
(TWCL)
Timer mode
register C1
(TMC1)
Timer mode
register C2
(TMC2)
Free-running
/reload control
Watchdog timer
control logic
TOC
ø
PER
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
3
3
Figure 32 Block Diagram of Timer C
HD404054 Series/HD404094 Series
49
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.
• Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).
Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input
after timer C has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 33.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 33.
0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after
timer C has reached $FF. Note that this function must be used only when the output level is high.
1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer
C has reached $FF. Note that this function must be used only when the output level is low.
HD404054 Series/HD404094 Series
50
T (N + 1)
T 256
T
T (256 – N)
TMC13 = 0
The waveform is always fixed low when N = $FF.
T:
N:
×
×
×
TMC13 = 1
Input clock period to counter (figures 34 and 41)
The value of the timer write register
Notes:
TMD13 = 0
TMD13 = 1
256 clock cycles 256 clock cycles
Free-running timer
Toggle output waveform (timers C, and D)
PWM output waveform (timers C and D)
(256 – N) clock cycles (256 – N) clock cycles
Reload timer
Figure 33 Timer Output Waveform
HD404054 Series/HD404094 Series
51
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.
Timer mode register C1 (TMC1: $00D)
Timer mode register C2 (TMC2: $014)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 34.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Bit
Initial value
Read/Write
Bit name
3
0
W
TMC13
2
0
W
TMC12
0
0
W
TMC10
1
0
W
TMC11
Timer mode register C1 (TMC1: $00D)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048tcyc
1024tcyc
512tcyc
128tcyc
32tcyc
8tcyc
4tcyc
2tcyc
TMC12 TMC10TMC11
TMC13
0
1
Free-running/reload timer selection
Free-running timer
Reload timer
Input clock period
Figure 34 Timer Mode Register C1 (TMC1)
HD404054 Series/HD404094 Series
52
• Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 35. It is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
R/W
TMC22
0
0
R/W
TMC20
1
0
R/W
TMC21
Timer mode register C2 (TMC2: $014)
TMC22
0
TMC21 R31/TOC mode selection
R31
TOC
TOC
TOC
—
TOC
R31 port
Toggle output
0 output
1 output
Inhibited
PWM output
TMC20
0
1
0
1
0
1
0
1
0
1
10
1
Figure 35 Timer Mode Register C2 (TMC2)
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and an upper digit (TWCU) as shown in figures 36 and 37. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.
Timer C is initialized by writing to timer write register C (TWCL: $00E, TWCU: $00F). In this case,
the lower digit (TWCL) must be written to first, but writing only to the lower digit does not change the
timer C value. Timer C is initialized to the value in timer write register C at the same time the upper
digit (TWCU) is written to. When timer write register C is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer C.
Bit
Initial value
Read/Write
Bit name
3
0
W
TWCL3
2
0
W
TWCL2
0
0
W
TWCL0
1
0
W
TWCL1
Timer write register C (lower digit) (TWCL: $00E)
Figure 36 Timer Write Register C Lower Digit (TWCL)
HD404054 Series/HD404094 Series
53
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWCU3
2
Undefined
W
TWCU2
0
Undefined
W
TWCU0
1
Undefined
W
TWCU1
Timer write register C (upper digit) (TWCU: $00F)
Figure 37 Timer Write Register C Upper Digit (TWCU)
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures
38 and 39. The upper digit (TRCU) must be read first. At this time, the count of the timer C upper digit
is obtained, and the count of the timer C lower digit is latched to the lower digit (TRCL). After this, by
reading TRCL, the count of timer C when TRCU is read can be obtained.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCL3
2
Undefined
R
TRCL2
0
Undefined
R
TRCL0
1
Undefined
R
TRCL1
Timer read register C (lower digit) (TRCL: $00E)
Figure 38 Timer Read Register C Lower Digit (TRCL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCU3
2
Undefined
R
TRCU2
0
Undefined
R
TRCU0
1
Undefined
R
TRCU1
Timer read register C (upper digit) (TRCU: $00F)
Figure 39 Timer Read Register C Upper Digit (TRCU)
HD404054 Series/HD404094 Series
54
Timer D
Timer D Functions: Timer D has the following functions.
• Free-running/reload timer
• External event counter
• Timer output operation (toggle, 0, 1, and PWM outputs)
• Input capture timer
The block diagram for each operation mode of timer D is shown in figures 40-1 and 40-2.
Timer D Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).
Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port
mode register C (PMRC: $025).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2tcyc or longer.
Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.
• Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).
Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by
MCU reset.
Toggle output: The operation is basically the same as that of timer-C’s toggle output.
0 output: The operation is basically the same as that of timer-C’s 0 output.
1 output: The operation is basically the same as that of timer-C’s 1 output.
HD404054 Series/HD404094 Series
55
PWM output: The operation is basically the same as that of timer-C’s PWM output.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.
By selecting the input capture operation, pin R32/TOD is set to R32 and timer D is reset to $00.
HD404054 Series/HD404094 Series
56
Timer D interrupt
request flag (IFTD)
Timer output
control logic Timer read
register DU (TRDU)
Timer output
control Timer read
register DL
(TRDL)
Clock Timer counter D
(TCD)
Selector
System
clock Prescaler S (PSS)
Overflow
Internal data bus
Timer write
register DU
(TWDU) Timer write
register DL
(TWDL)
Timer mode
register D1
(TMD1)
Timer mode
register D2
(TMD2)
Free-running/
reload control
TOD
Edge
detection
logic
Edge detection
selection register
2 (ESR2)
Edge detection control
øPER
2
3
3
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
EVND
Figure 40-1 Block Diagram of Timer D (Free-Running/Reload Timer)
HD404054 Series/HD404094 Series
57
Selector
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
3
2
PER
ø
Input capture
status flag (ICSF) Input capture
error flag (ICEF) Timer D interrupt
request flag (IFTD)
Error
control
logic
Edge
detection
logic
Timer read
register DU
(TRDU) Timer read
register DL
(TRDL)
Read signal
Clock Timer counter D
(TCD) Overflow
System
clock
Edge detection control
Prescaler S (PSS)
Input capture
timer control
Timer mode
register D1
(TMD1)
Timer mode
register D2
(TMD2)
Edge detection
selection register
2 (ESR2)
EVND
Internal data bus
Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode)
HD404054 Series/HD404094 Series
58
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.
Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)
• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 41.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
Bit
Initial value
Read/Write
Bit name
3
0
W
TMD13
2
0
W
TMD12
0
0
W
TMD10
1
0
W
TMD11
Timer mode register D1 (TMD1: $010)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048tcyc
512tcyc
128tcyc
32tcyc
8tcyc
4tcyc
2tcyc
TMD12 TMD10
TMD11 Input clock period and
input clock source
R40/EVND (external event input)
TMD13
0
1
Free-running/reload
timer selection
Free-running timer
Reload timer
Figure 41 Timer Mode Register D1 (TMD1)
HD404054 Series/HD404094 Series
59
• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 42. It is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
3
0
R/W
TMD23
2
0
R/W
TMD22
0
0
R/W
TMD20
1
0
R/W
TMD21
Timer mode register D2 (TMD2: $015)
TMD22 TMD20
0
1
0
1
0
1
0
1
TMD21
0
1
0
1
0
1
R32/TOD mode selection
R32
TOD
TOD
TOD
—
TOD
R32
R32 port
Toggle output
0 output
1 output
Inhibited
PWM output
Input capture (R32 port)
TMD23
0
1×××
×: Don’t care
Figure 42 Timer Mode Register D2 (TMD2)
• Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and an upper digit (TWDU) as shown in figures 43 and 44. The operation of timer write
register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F).
Bit
Initial value
Read/Write
Bit name
3
0
W
TWDL3
2
0
W
TWDL2
0
0
W
TWDL0
1
0
W
TWDL1
Timer write register D (lower digit) (TWDL: $011)
Figure 43 Timer Write Register D Lower Digit (TWDL)
HD404054 Series/HD404094 Series
60
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWDU3
2
Undefined
W
TWDU2
0
Undefined
W
TWDU0
1
Undefined
W
TWDU1
Timer write register D (upper digit) (TWDU: $012)
Figure 44 Timer Write Register D Upper Digit (TWDU)
• Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and an upper digit (TRDU) as shown in figures 45 and 46. The operation of timer read register
D is basically the same as that of timer read register C (TRCL: $00E, TRCU: $00F).
When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRDL3
2
Undefined
R
TRDL2
0
Undefined
R
TRDL0
1
Undefined
R
TRDL1
Timer read register D (lower digit) (TRDL: $011)
Figure 45 Timer Read Register D Lower Digit (TRDL)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRDU3
2
Undefined
R
TRDU2
0
Undefined
R
TRDU0
Timer read register D (upper digit) (TRDU: $012)
1
Undefined
R
TRDU1
Figure 46 Timer Read Register D Upper Digit (TRDU)
HD404054 Series/HD404094 Series
61
• Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown
in figure 47. It is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
3
0
W
PMRC3
2
0
W
PMRC2
0
—
—
Not used
1
0
W
PMRC1
PMRC1
0
1
R4
0
/EVND mode selection
R4
0
EVND
Port mode register C (PMRC: $025)
PMRC3
0
1
D
13
/INT
0
mode selection
D
13
INT
0
PMRC2
0
1
D
12
/STOPC mode selection
D
12
STOPC
Figure 47 Port Mode Register C (PMRC)
• Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 48. It is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
3
0
W
ESR23
2
0
W
ESR22
0
—
—
Not used
1
—
—
Not used
Detection edge register 2 (ESR2: $027)
ESR23
0
1
ESR22
0
1
0
1
EVND detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
Note: Both falling and rising edges are detected.
*
*
Figure 48 Detection Edge Select Register 2 (ESR2)
HD404054 Series/HD404094 Series
62
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 24. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 24 PWM Output Following Update of Timer Write Register
PWM Output
Mode Timer Write Register is Updated during
High PWM Output Timer Write Register is Updated during
Low PWM Output
Free running
Timer write
register
updated to
value N Interrupt
request
T × (255 – N) T × (N + 1)
Timer write
register
updated to
value N Interrupt
request
T × (N' + 1)
T × (255 – N) T × (N + 1)
Reload
Timer write
register
updated to
value N Interrupt
request
TT × (255 – N)T
Timer write
register
updated to
value N Interrupt
request
TT × (255 – N)
T
HD404054 Series/HD404094 Series
63
Serial Interface 1
The MCU has one channel of serial interface. The serial interface serially transfers or receives 8-bit data,
and includes the following features.
• Multiple transmit clock sources
External clock
Internal prescaler output clock
System clock
• Output level control in idle states
Serial interface 1
• Serial data register 1 (SR1L: $006, SR1U: $007)
• Serial mode register 1A (SM1A: $005)
• Serial mode register 1B (SM1B: $028)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
• Octal counter (OC)
• Selector
The block diagram of serial interface 1 is shown in figure 49.
HD404054 Series/HD404094 Series
64
Selector
Prescaler S (PSS)
÷2
÷8
÷32
÷128
÷512
÷2048
Selector
I/O control
logic
Idle control
logic
Octal counter
(OC)
Serial interrupt
request flag
(IFS1)
Clock
Serial data
register
(SR1L/U)
Serial mode register
1A (SM1A)
Serial mode register
1B (SM1B)
Transfer
control
SO1
SCK1
SI1
System
clock
Internal data bus
3
øPER
1/2 1/2
Figure 49 Block Diagram of Serial Interface 1
HD404054 Series/HD404094 Series
65
Serial Interface Operation
Selecting and Changing the Operating Mode: Table 25 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial
mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always
initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface
1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for
Serial Interface for details.
Pin Setting: The R41/SCK1 pin is controlled by writing data to serial mode register 1A (SM1A: $005).
Pins R42/SI1 and R4 3/SO1 are controlled by writing data to port mode register A (PMRA: $004). Refer to
the following section Registers for Serial Interface for details.
Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following
section Registers for Serial Interface for details.
Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data
register 1. The serial data is shifted by the transmit clock and is input from or output to an external system.
The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000
by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When
the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal
counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 is set, and
the transfer stops.
When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock
frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A
(SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 26.
Table 25 Serial Interface 1 Operating Modes
SM1A PMRA
Bit 3 Bit 1 Bit 0 Operating Mode
1 0 0 Continuous clock output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode
HD404054 Series/HD404094 Series
66
Table 26 Serial Transmit Clock (prescaler output)
SM1B SM1A
Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Tranamit Clock Frequency
0000÷ 2048 4096tcyc
1÷ 512 1024tcyc
10÷ 128 256tcyc
1÷ 32 64tcyc
100÷ 8 16tcyc
1÷ 24t
cyc
1000÷ 4096 8192tcyc
1÷ 1024 2048tcyc
10÷ 256 512tcyc
1÷ 64 128tcyc
100÷ 16 32tcyc
1÷ 48t
cyc
Operating States: Serial interface 1 has the following operating states; transitions between them are
shown in figure 50.
STS wait state
Transmit clock wait state
Transfer state
Continuous transmit clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface
in transfer state. However, note that if continuous clock output mode is selected in internal clock mode,
the serial interface does not enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
HD404054 Series/HD404094 Series
67
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK1 pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
STS wait state
(Octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter = 000)
MCU reset
00
SM1A write 04 STS instruction
01
Transmit clock
02
8 transmit clocks
03 STS instruction (IFS1 1)
05 ←
SM1A write (IFS1 1)
06 ←
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter = 000) Transfer state
(Octal counter 000)
SM1A write 14 STS instruction
11
Transmit clock
12
15
STS instruction (IFS1 1)
←
8 transmit clocks
13
Internal clock mode
Continuous transmit
clock output state
(PMRA 0, 1 = 0, 0)
SM1A write
18
Transmit clock 17
16
Note: Refer to the Operating States section for the corresponding encircled numbers.
MCU reset10
←
SM1A write (IFS1 1)
≠
Transfer state
(Octal counter 000)
≠
Figure 50 Serial Interface State Transitions
Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output
of serial output pin, SO1 can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B:
$028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the
output level cannot be controlled in transfer state.
HD404054 Series/HD404094 Series
68
,
State
MCU reset
PMRA write
SM1A write
SM1B write
SR1L, SR1U
write
STS instruction
SCK
1
pin (input)
SO
1
pin
IFS1
STS wait state
Transmit clock
wait state
Transfer state
Transmit clock
wait state
STS wait state
Port selection
External clock selection
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
Data write for transmission
Undefined LSB MSB
Flag reset at transfer completion
External clock mode
State
MCU reset
PMRA write
SM1A write
SM1B write
SR1L, SR1U
write
STS instruction
SCK
1
pin (output)
SO
1
pin
IFS1
STS wait state Transfer state
Transmit clock
wait state
STS wait state
Port selection
Internal clock selection
Output level control in
idle states
Data write for transmission
Output level control in
idle states
Undefined LSB MSB
Flag reset at transfer completion
Internal clock mode
Figure 51 Example of Serial Interface 1 Operation Sequence
HD404054 Series/HD404094 Series
69
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 52.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005)
changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the
serial 1 interrupt request flag is set again, and therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register 1A (SM1A: $005) again.
• Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from
transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS
instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set.
To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution
must be programmed to be executed after confirming that the SCK1 pin is at 1, that is, after executing
the input instruction to port R4.
HD404054 Series/HD404094 Series
70
Transfer completion
(IFS1 1)
Interrupts inhibited
IFS1 0
SM1A write
IFS1 = 1 Transmit clock
error processing
Normal
termination
←
←
Yes
No
Transmit clock error detection flowchart
Transmit clock error detection procedures
State
Transmit clock
wait state Transfer state Transfer state
Transmit clock wait state
Noise
Transfer state has been
entered by the transmit clock
error. When SM1A is written,
IFS1 is set.
Flag set because octal
counter reaches 000. Flag reset at
transfer completion.
SM1A
write
12345678
SCK pin
(input)
IFS1
1
Figure 52 Transmit Clock Error Detection
HD404054 Series/HD404094 Series
71
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
• Serial mode register 1A (SM1A: $005)
• Serial mode register 1B (SM1B: $028)
• Serial data register 1 (SR1L: $006, SR1U: $007)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 53).
• R41/SCK1 pin function selection
• Serial interface 1 transmit clock selection
• Serial interface 1 prescaler division ratio selection
• Serial interface 1 initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock
to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to
000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
HD404054 Series/HD404094 Series
72
Bit
Initial value
Read/Write
Bit name
3
0
W
SM1A3
2
0
W
SM1A2
0
0
W
SM1A0
1
0
W
SM1A1
Serial mode register 1A (SM1A: $005)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SM1A2 SM1A0SM1A1
SM1A3
0
1
R41/SCK1
mode selection
R41
SCK1
SCK1
Output
Output
Input
Clock source
Prescaler
System clock
External clock
—
—
Prescaler
division ratio
Refer to
table 26
Figure 53 Serial Mode Register 1A (SM1A)
Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 54).
• Serial interface 1 prescaler division ratio selection
• Serial interface 1 output level control in idle states
Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data
transfer.
By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit
0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is
controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is
written to.
HD404054 Series/HD404094 Series
73
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
0
W
SM1B0
1
Undefined
W
SM1B1
SM1B0
0
1
Serial clock division ratio
Prescaler output divided by 2
Prescaler output divided by 4
Serial mode register 1B (SM1B: $028)
SM1B1
0
1
Output level control in idle states
Low level
High level
Figure 54 Serial Mode Register 1B (SM1B)
Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 55
and 56)
• Serial interface 1 transmission data write and shift
• Serial interface 1 receive data shift and read
Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of
the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 57.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR13
2
Undefined
R/W
SR12
0
Undefined
R/W
SR10
1
Undefined
R/W
SR11
Serial data register 1(lower digit) (SR1L: $006)
Figure 55 Serial Data Register 1 (SR1L)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR17
2
Undefined
R/W
SR16
0
Undefined
R/W
SR14
1
Undefined
R/W
SR15
Serial data register 1(upper digit) (SR1U: $007)
Figure 56 Serial Data Register 1 (SR1U)
HD404054 Series/HD404094 Series
74
LSB MSB
12345678
Transmit clock
Serial output
data
Serial input data
latch timing
Figure 57 Serial Interface Output Timing
Port Mode Register A (PMRA: $004): This register has the following functions (figure 58).
• R42/SI1 pin function selection
• R43/SO1 pin function selection
Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
0
0
W
PMRA0
1
0
W
PMRA1
Port mode register A (PMRA: $004)
PMRA0
0
1
R43/SO1 mode selection
R43
SO1
PMRA1
0
1
R42/SI1 mode selection
R42
SI1
3
—
—
Not used
2
—
—
Not used
Figure 58 Port Mode Register A (PMRA)
HD404054 Series/HD404094 Series
75
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 59).
• R43/SO1 pin PMOS control
Miscellaneous register (MIS: $00C) is a 2-bit write-only register and is reset to $0 by MCU reset.
MIS2
0
1
R43/SO1 PMOS on/off selection
On
Off
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
Miscellaneous register (MIS: $00C)
MIS3
0
1
Pull-up MOS on/off selection
Off
On
1
—
—
Not used
0
—
—
Not used
Figure 59 Miscellaneous Register (MIS)
HD404054 Series/HD404094 Series
76
Comparator
The block diagram of the comparator is shown in figure 60. The comparator compares input voltage with
the reference voltage.
Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison.
When an input voltage at COMP0, COMP1 is higher than the reference voltage, the TM or TMD command
sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to
COMP0 and COMP1. On the other hand, when an input voltage at COMP0, COMP1 is lower, the TM or
TMD command clears the ST to 0.
Selector
+
–
Com-
parator Comparator data
register (CDR)
Comparator enable
register (CER)
Internal data bus
COMP0
VCref
COMP
COMP1
Figure 60 Block Diagram of Comparator
HD404054 Series/HD404094 Series
77
Compare Enable Register (CER: $018): Three-bit write-only register which enables comparator
operation, and selects the reference voltage and the analog input pin (figure 61).
Bit
Initial value
Read/Write
Bit name
3
0
W
CER3
2
—
—
Not used
0
0
W
CER0
1
0
W
CER1
Compare enable register (CER: $018)
CER3
0
Digital/Analog selection
Digital input mode:
RD /COMP
0
, RD /COMP
1
operate as R port
01
1
Analog input mode:
RD /COMP
0
, RD /COMP
1
operate as analog input
CER1
0
1
Analog input pin selection
COMP
0
COMP
1
Not used
Not used
CER0
0
1
0
1
01
Figure 61 Compare Enable Register
Compare Data Register (CDR: $017): Two-bit read-only register which latches the result of the
comparison between the analog input pins and the reference voltage. Bits 0 and 1 corresponds the results
of comparison with COMP0 and COMP1, respectively. This register can be read only by the TM or TMD
command. Only bit CER3 corresponds to the analog input pin which the input pin selection is made
through pins CER0 and CER1. After a compare operation, the data in this register is not retained (figure
62).
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
0
R
CDR0
1
R
CDR1
Compare data register (CDR: $017)
Undefined Undefined
Result of COMP0 comparison
Result of COMP1 comparison
Figure 62 Compare Data Register
Note on Use: During the compare operation pins RD0/COMP0 and RD1/COMP1 operate as analog inputs
and cannot operate as R ports.
The comparator can operate in active mode but is disabled in other modes.
RE0/VCref cannot operate as an R port when the external input voltage is selected as the reference.
HD404054 Series/HD404094 Series
78
Programmable ROM (HD4074054, HD4074094)
The HD4074054 and HD4074094 are ZTAT microcomputers with built-in PROM that can be
programmed in PROM mode.
PROM Mode Pin Description
Pin No. MCU Mode PROM Mode
DP-42S FP-44A Pin Name I/O Pin Name I/O
139RD
0
/COMP0ICE I
240RD
1
/COMP1IOE I
341RD
2I
442RD
3I
543RC
0I
61RE
0
/VCref IM1I
72TEST ITEST I
8 3 OSC1IV
CC
9 4 OSC2O
10 5 RESET IRESET I
11 6 GND I GND
12 7 D0I/O O
13 8 D1I/O O
14 9 D2I/O VCC
15 10 D3I/O VCC
16 11 D4I/O*O4I/O
17 12 D5I/O*O5I/O
18 13 D6I/O*O6I/O
19 14 D7I/O*O7I/O
20 15 D8I/O A13 I
21 16 D9I/O A14 I
22 17 D12
/STOPC IA
9I
23 18 D13
/INT0IV
PP
24 19 R00
/INT1I/O M0I
25 20 R10I/O A5I
26 21 R11I/O A6I
27 23 R12I/O A7I
Note: I/O: Input/output pin, I: Input pin, O: Output pin
* HD404054 Series: I/O, HD404094 Series: O
HD404054 Series/HD404094 Series
79
Pin No. MCU Mode PROM Mode
DP-42S FP-44A Pin Name I/O Pin Name I/O
28 24 R13I/O A8I
29 25 R20I/O A0I
30 26 R21I/O A10 I
31 27 R22I/O A11 I
32 28 R23I/O A12 I
33 29 R30I/O A1I
34 30 R31/TOC I/O A2I
35 31 R32/TOD I/O A3I
36 32 R33I/O A4I
37 33 R40/EVND I/O O0I/O
38 34 R41/SCK1I/O O1I/O
39 35 R42/SI1I/O O2I/O
40 36 R43/SO1I/O O3I/O
41 37 SEL I
42 38 VCC IV
CC
–22NC–
–44NC–
Note: I/O: Input/output pin, I: Input pin, O: Output pin
HD404054 Series/HD404094 Series
80
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and
M1 low, and RESET low as shown in figure 63. In PROM mode, the MCU does not operate, but it can be
programmed in the same way as any other commercial 27256-type EPROM using a standard PROM
programmer and an 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters
of the HD4074054 and HD4074094 are listed in table 27.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that
if, for example, 4-kwords of built-in PROM are to be programmed by a general-purpose PROM
programmer, a 8-kbyte address space ($0000–$7FFF) must be specified.
Address
A0 to A14
Data
O0 to O7
OE
CE
VPP
GND
VCC
VCC
O0 to O7
A0 to A14
OE
CE
VPP
RESET
TEST
M0
M1
VCC
OSC1
D2
D3
HD4074054
HD4074094
Figure 63 PROM Mode Connections
Table 27 Recommended PROM Programmers and Socket Adapters
PROM Programmer Socket Adapter
Manufacturer Model Name Package Model Name Manufacturer
DATA I/O Corp. 121B DP-42S HS4654ESS01H Hitachi
AVAL Corp. PKW-1000 FP-44A HS4654ESH01H Hitachi
HD404054 Series/HD404094 Series
81
Warnings
1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address
$2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased or reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 28.
Table 28 PROM Mode Selection
Pin
Mode CE OE VPP O0–O7
Programming Low High VPP Data input
Verification High Low VPP Data output
Programming inhibited High High VPP High impedance
HD404054 Series/HD404094 Series
82
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 64 and described below.
AP9AP0
W1Y0
W register X register Y register
RAM address
AP9AP0
RAM address
d9d0
2nd word of Instruction
Opcode
1st word of Instruction
AP9AP0
RAM address
m3
Opcode
Instruction
000100
AP8AP7AP AP5AP46 AP3AP2AP1
AP AP AP AP AP AP AP AP
87654321
d
8
d
7
d
6
d
5
d
4
d
3
d
2
d
1
AP8AP7AP6AP5AP4AP3AP2AP1
W0X3X2X1X0Y3Y2Y1
m2m1m0
Direct addressing
Memory register addressing
Register direct addressing
Figure 64 RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.
HD404054 Series/HD404094 Series
83
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 65 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 67. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight high-
order bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-
bit immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 66. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
HD404054 Series/HD404094 Series
84
d
9
d
8
d
7
d
6
d
5
d
4
d
3
d
2
d
1
d
0
2nd word of instruction
Opcode
1st word of instruction
[JMPL]
[BRL]
[CALL]
PC
9
PC
8
PC
7
PC
6
PC
5
PC
4
PC
3
PC
2
PC
1
PC
0
PCPCPCPC
10111213
Program counter
Direct addressing
Zero page addressing
d
5
d
4
d
3
d
2
d
1
d
0
Instruction
[CAL] Opcode
PC
98
PC
76
PC
54
PC
3
PC
1
PC
0
PCPC
10111213
Program counter
00000000
PCPC PC PC PC PC
2
B
1
B
0
A
3
A
2
A
1
A
0
Accumulator
Program counter
Table data addressing
PC
9
PC
8
PC
7
PC
6
PC
5
PC
4
PC
3
PC
2
PC
1
PC
0
PCPCPC
10111213
B
2
B
3
B register
p
3
p
0
[TBR]
Instruction
Opcode
00
p
2
p
1
PC
Opcode b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Instruction
PC
90
PCPCPC
111213
Program counter
Current page addressing
[BR]
PC
10 7
PC
6
PC
5
PC
4
PC
3
PC
2
PC
1
PCPC
8
PC
p
0
p
1
p
2
p
3
Figure 65 ROM Addressing Modes
HD404054 Series/HD404094 Series
85
B1B0A3A2A1A0
Accumulator
Referenced ROM address
Address designation
RA9RA8RA7RA6RA5RA4RA3RA2RA1RA0
RARARA 10111213
B2
B3
B register
00
p3p0
[P]
Instruction
Opcode p2p1
RA
RO9RO0
RO8RO7RO6RO5RO4RO3RO2RO1
BBBBAA A
A
3210 3210
If RO = 1
8
Accumulator, B register
ROM data
Pattern output
RO9
ROM data
If RO = 1
9
Output registers R1, R2 R23R22R21R20R13R12R11R10
RO0
RO8RO7RO6RO5RO4RO3RO2RO1
Figure 66 P Instruction
HD404054 Series/HD404094 Series
86
BR AAA
AAA NOP
256 (n – 1) + 255
256n
BR AAA
BR BBB 256n + 254
256n + 255
256 (n + 1)
BBB NOP
Figure 67 Branching when the Branch Destination is on a Page Boundary
HD404054 Series/HD404094 Series
87
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +14.0 V 1
Pin voltage VT–0.3 to VCC + 0.3 V
–0.3 to +15.0 V 2
Total permissible input current ∑Io80 mA 3
Total permissible output current –∑Io50 mA 4
Maximum input current Io4 mA 5, 6
30 mA 5, 7
Maximum output current –Io4 mA 8, 9
20 mA 8, 10
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to D13 (VPP) of HD4074054 and HD4074094.
2. Applies to D4 to D7 of HD404092, HD404094, and HD4074094.
3. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
4. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
5. The maximum input current is the maximum current flowing from each I/O pin to GND.
6. Applies to D0–D3, and R0–R4.
7. Applies to D4–D9 .
8. The maximum output current is the maximum current flowing out from VCC to each I/O pin.
9. Applies to D4–D9 and R0–R4.
10.Applies to D0–D3.
HD404054 Series/HD404094 Series
88
Electrical Characteristics
DC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V,
Ta = –20 °C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to
+75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless
otherwise specified)
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Input high
voltage VIH RESET, STOPC,
INT0, INT1, SCK1,
SI1, EVND
0.9 VCC —V
CC + 0.3 V
OSC1VCC – 0.3 — VCC + 0.3 V External clock
Input low
voltage VIL RESET, STOPC,
INT0, INT1, SCK1,
SI1, EVND
–0.3 — 0.10 VCC V
OSC1–0.3 — 0.3 V External clock
Output high
voltage VOH SCK1, SO1,
TOC,TOD VCC – 1.0 — — V –IOH = 0.5 mA
Output low
voltage VOL SCK1, SO1,
TOC,TOD — — 0.4 V IOL = 0.4 mA
I/O leakage
current | IIL | RESET, STOPC,
INT0, INT1, SCK1,
SI1, SO1, EVND,
OSC1, TOC, TOD
——1 µAV
in = 0 V to VCC 1
Current
dissipation in
active mode
ICC1 VCC —5—mAV
CC = 5 V,
fOSC = 4 MHz
Digital input mode
2, 4, 7
— 5 10 mA VCC = 5 V,
fOSC = 8 MHz
Digital input mode
3, 4, 7
ICC2 VCC — 0.6 1.8 mA VCC = 3 V,
fOSC = 800 kHz
Digital input mode
2, 4, 7
ICMP1 VCC —9—mAV
CC = 5 V,
fOSC = 4 MHz
Analog comp. mode
2, 4, 7
— 9 15 mA VCC = 5 V,
fOSC = 8 MHz
Analog comp. mode
3, 4, 7
ICMP2 VCC — 3.1 4.3 mA VCC = 3 V,
fOSC = 800 kHz
Analog comp. mode
2, 4, 7
HD404054 Series/HD404094 Series
89
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Current dissipation
in standby mode ISBY1 VCC — 1.2 — mA VCC = 5 V,
fOSC = 4 MHz 2, 6, 7
—36 mAV
CC = 5 V,
fOSC = 8 MHz 3, 6, 7
ISBY2 VCC — 0.2 0.7 mA VCC = 3 V,
fOSC = 800 kHz 2, 6, 7
Current dissipation
in stop mode ISTOP VCC —15 µAV
CC = 3 V 2, 8
—110µAV
CC = 5 V 3, 8
Stop mode
retaining voltage VSTOP VCC — 1.3 — V 9
Comparator input
reference voltage
scope
VCref VCref 0—V
CC – 1.2 V
Notes: 1. Output buffer current is excluded.
2. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094 and HD4074094.
3. Applies to HD40A4052 and HD40A4054.
4. ICC1 and ICC2 are the source currents when no I/O current is flowing while the MCU is in reset
state. Test conditions: MCU: Reset
Pins: RESET at GND (0 V to 0.3V)
TEST at VCC (VCC – 0.3 to VCC)
5. RD0 and RD1 pins are analog input mode when no I/O current is flowing.
Test conditions: MCU: Analog input mode
Pins: RD0/COMP0 at GND (0 V to 0.3 V)
RD1/COMP1 at GND (0 V to 0.3 V)
RE0/VCref at GND (0 V to 0.3 V)
6. ISBY1 and ISBY2 are the source currents when no I/O current is flowing while the MCU timer is
operating. Test conditions: MCU: I/O reset
Serial interface stopped
Standby mode
Pins: RESET at VCC (VCC – 0.3 to VCC)
TEST at VCC (VCC – 0.3 to V CC)
7. The current dissipation is in proportion to fOSC while the MCU is operating or is in standby mode.
The value of the dissipation on current when fOSC = F MHz is given by the following equation:
Maximum value (fOSC = F MHz) = F/4 × maximum value (fOSC = 4 MHz)
8. These are the source currents when no I/O current is flowing.
Test conditions: Pins: RESET at VCC (VCC – 0.3 to VCC)
TEST at VCC (VCC – 0.3 to VCC)
D13* at VCC (VCC – 0.3 to VCC)
Note: * Applies to HD4074054 and HD4074094
9. RAM data retention.
HD404054 Series/HD404094 Series
90
I/O Characteristics for Standard Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to
6.0 V, GND = 0 V, Ta = –20 °C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V,
Ta = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to
+75°C, unless otherwise specified)
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Input high
voltage VIH D12–D13,
R0–RD, RE0
0.7 VCC —V
CC + 0.3 V
Input low
voltage VIL D12–D13,
R0–RD, RE0
–0.3 — 0.3 VCC V
Output high
voltage VOH R0–R4 VCC – 1.0 — — V –IOH = 0.5 mA
Output low
voltage VOL R0–R4 — — 0.4 V IOL = 0.4 mA
I/O leakage
current | IIL |D
12, R0–RD,
RE0
—— 1 µAV
in = 0 V to VCC 1
D13 —— 1 µAV
in = 0 V to VCC 1, 2, 4
—— 1 µAV
in = VCC – 0.3 V to VCC 1, 3
—— 20µAV
in = 0 V to 0.3 V 1, 3
Pull-up MOS
current –IPU R0–R4 — 30 — µAV
CC = 3 V,
Vin = 0 V 2, 3
20 100 500 µAV
CC = 5 V,
Vin = 0 V 4
Input high
voltage VIHA COMP0,
COMP1
—VC
ref+0.0
5— V Analog compare
mode 5
Input low
voltage VILA COMP0,
COMP1
—VC
ref–0.05 — V Analog compare
mode 5
Notes: 1. Output buffer current is excluded.
2. Applies to HD404052, HD404054, HD404092, HD404094.
3. Applies to HD4074054, HD4074094.
4. Applies to HD40A4052, HD40A4054.
5. The analog input reference voltage should be in the range 0 ≤ VCref ≤ VCC–1.2.
HD404054 Series/HD404094 Series
91
I/O Characteristics for High-Current Pins and Intermediate-Voltage Pins (HD404052, HD404054,
HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052,
HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074054, HD4074094: VCC =
2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified)
Pin(s)
Item Symbol HD404054
Series HD404094
Series Min Typ Max Unit Test
Condition Notes
Input high
voltage VIH D0–D9D0–D3,
D8, D9
0.7 VCC —V
CC + 0.3 V
Input low
voltage VIL D0–D9D0–D3,
D8, D9
–0.3 — 0.3 VCC V
Output high
voltage VOH D0–D9D0–D3,
D8, D9
VCC – 1.0 — — V –IOH = 0.5 mA
D0–D3D0–D32.0 — — V –IOH = 10 mA,
VCC = 4.5 V to
6.0 V
2
—D
4
–D711.5 — — V 500 kΩ at 12 V
Output low
voltage VOL D0–D9D0–D9— — 0.4 V IOL = 0.4 mA
D4–D9D4–D9— — 2.0 V IOL = 15 mA,
VCC = 4.5 V to
6.0 V
2
I/O leakage
current | IIL |D
0
–D9D0–D3,
D8, D9
——1 µAV
in = 0 V to VCC 1
—D
4
–D7——20 µAV
in = 0 V to
12 V 1
Pull-down
MOS current IPD D0–D3D0–D3—30— µAV
CC = 3 V,
Vin = 3 V 3
— 20 100 500 µAV
CC = 5 V,
Vin = 5 V 4
Pull-up MOS
current –IPU D4–D9D8, D9—30— µAV
CC = 3 V,
Vin = 0 V 3
— 20 100 500 µAV
CC = 5 V,
Vin = 0 V 4
Notes: 1. Output buffer current is excluded.
2. When using HD4074054, HD4074094, VCC = 4.5 V to 5.5 V.
3. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094.
4. Applies to HD40A4052, HD40A4054.
HD404054 Series/HD404094 Series
92
AC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V,
Ta = –20 °C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to
+75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless
otherwise specified)
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Clock oscillation
frequency fOSC OSC1,
OSC2
0.4 — 4 MHz 1
0.4 — 8.5 MHz 2
Instruction cycle time tcyc —8 —µsf
OSC = 4 MHz, ÷32 1, 4
— 3.76 — µsf
OSC = 8.5 MHz, ÷32 2, 4
—1 —µsf
OSC = 4 MHz, ÷4 1, 3
— 0.47 — µsf
OSC = 8.5 MHz, ÷4 2, 3
Oscillation stabilization
time (ceramic) tRC OSC1,
OSC2
— — 7.5 ms VCC = 2.7 V to 5.5 V:
HD4074054, HD4074094 3, 4
VCC = 2.7 V to 6.0 V:
HD404052, HD404054,
HD404092, HD404094
— — 60 ms VCC = 1.8 V to 2.7 V:
HD404052, HD404054,
HD404092, HD404094
— — 7.5 ms VCC = 4.0 V to 6.0 V:
HD40A4052,HD40A4054 5, 6
External clock high
width tCPH OSC1105 — — ns 1, 7
49 — — ns 2, 7
External clock low width tCPL OSC1105 — — ns 1, 7
49 — — ns 2, 7
External clock rise time tCPr OSC1— — 20 ns 1, 7
— — 10 ns 2, 7
External clock fall time tCPf OSC1— — 20 ns 1, 7
— — 10 ns 2, 7
INT0, INT1, EVND high
width tIH INT0, INT1,
EVND 2——t
cyc 8
INT0, INT1, EVND low
width tIL INT0, INT1,
EVND 2——t
cyc 8
RESET low width tRSTL RESET 2——t
cyc 9
STOPC low width tSTPL STOPC 1——t
RC 10
RESET rise time tRSTr RESET — — 20 ms 9
STOPC rise time tSTPr STOPC — — 20 ms 10
HD404054 Series/HD404094 Series
93
Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes
Input capacitance Cin All pins except
D13 D4–D7
— — 15 pF f = 1 MHz, Vin = 0 V
D4–D7— — 30 pF f = 1 MHz, Vin = 0 V
D13 — — 15 pF f = 1 MHz, Vin = 0 V:
HD404052, HD404054,
HD404092, HD404094,
HD40A4052,HD40A4054
— — 180 pF f = 1 MHz, Vin = 0 V:
HD4074054, HD4074094
Analog comparator
stabilization time tCSTB COMP0,
COMP1
——2t
cyc VCC = 2.7 V to 5.5 V:
HD4074054, HD4074094 9
VCC = 2.7 V to 6.0 V:
HD404052, HD404054,
HD404092, HD404094
——4t
cyc VCC = 4.0 V to 6.0 V:
HD40A4052,HD40A4054 11
— — 20 tcyc VCC = 1.8 V to 2.7 V:
HD404052, HD404054,
HD404092, HD404094
Notes: 1. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094.
2. Applies to HD40A4052, HD40A4054.
3. SEL = 1
4. SEL = 0
5. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC
reaches 2.7 (HD4074054, HD4074094)/1.8 (HD404052, HD404054, HD404092, HD404094) /4.0
(HD40A4052, HD40A4054)V at power-on, or after RESET input goes low or STOPC input goes
low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or
STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a
ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since
it will depend on the circuit constants and stray capacitance.
6. Applies to ceramic oscillator only.
7. Refer to figure 68.
8. Refer to figure 69.
9. Refer to figure 70.
10.Refer to figure 71.
11.Analog comparator stabilization time is the period for the analog comparator to stabilize and for
correct data to be read after entering RD0/COMP0, RD1/COMP1 into analog input mode.
HD404054 Series/HD404094 Series
94
Serial Interface Timing Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V
to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0
V, T a = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to
+75°C, unless otherwise specified)
During Transmit Clock Output
Item Symbol Pin(s) Min Typ Max Unit Test Condition Note
Transmit clock
cycle time tScyc SCK11——t
cyc Load shown in
figure 73 1
Transmit clock
high width tSCKH SCK10.5 — — tScyc Load shown in
figure 73 1
Transmit clock
low width tSCKL SCK10.5 — — tScyc Load shown in
figure 73 1
Transmit clock
rise time tSCKr SCK1— 100 — ns Load shown in
figure 73 1, 2
— — 80 ns 1, 3
Transmit clock
fall time tSCKf SCK1— 100 — ns Load shown in
figure 73 1, 2
— — 80 ns 1, 3
Serial output
data delay time tDSO SO1— — 500 ns Load shown in
figure 73 1, 2
— — 200 ns 1, 3
Serial input data
setup time tSSI SI1300 — — ns 1, 2
150 — — ns 1, 3
Serial input data
hold time tHSI SI1300 — — ns 1, 2
150 — — ns 1, 3
Note: 1. Refer to figure 72.
2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094.
3. Applies to HD40A4052, HD40A4054.
HD404054 Series/HD404094 Series
95
During Transmit Clock Input
Item Symbol Pin(s) Min Typ Max Unit Test Condition Note
Transmit clock
cycle time tScyc SCK11——t
cyc 1
Transmit clock
high width tSCKH SCK10.5 — — tScyc 1
Transmit clock
low width tSCKL SCK10.5 — — tScyc 1
Transmit clock
rise time tSCKr SCK1— 100 — ns 1, 2
— — 80 ns 1, 3
Transmit clock
fall time tSCKf SCK1— 100 — ns 1, 2
— — 80 ns 1, 3
Serial output
data delay time tDSO SO1— — 500 ns Load shown in
figure 73 1, 2
— — 200 ns 1, 3
Serial input data
setup time tSSI SI1300 — — ns 1, 2
150 — — ns 1, 3
Serial input data
hold time tHSI SI1300 — — ns 1, 2
150 — — ns 1, 3
Note: 1. Refer to figure72.
2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094.
3. Applies to HD40A4052, HD40A4054.
HD404054 Series/HD404094 Series
96
tCPr tCPf
VCC – 0.3 V
0.3 V tCPH
tCPL
1/fCP
OSC1
Figure 68 External Clock Timing
tRSTr
tRSTL
0.9 VCC
0.1 VCC
RESET
Figure 69 Interrupt Timing
0.9 VCC
0.1 VCC
INT0, INT1, EVND
tIH tIL
Figure 70 Reset Timing
tSTPr
tSTPL
0.9 VCC
0.1 VCC
STOPC
Figure 71 STOPC Timing
HD404054 Series/HD404094 Series
97
0.9 V
CC
0.1 V
CC
tDSO
tSCKf tSCKL
tSSI tHSI
tScyc
tSCKr
0.4 V
V – VH
CC
V – VH (0.9 V )*
CC
0.4 V (0.1 V )*
SCK
SO
SI
Note: *CC
V – VH and 0.4 V are the threshold voltages for transmit clock output.
VH = 1.0 V : HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094
VH = 2.0 V : HD40A4052, HD40A4054
0.9 V and 0.1 V are the threshold voltages for transmit clock output.
CC
CC tSCKH
1
1
1
CC CC
Figure 72 Serial Interface Timing
RL = 2.6 kΩ
VCC
1S2074 H
or equivalent
R
12 kΩ
Test point
C
30 pF
Figure 73 Timing Load Circuit
HD404054 Series/HD404094 Series
98
Notes On ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions
(HD404054, HD404094 and HD40A4054). A 4-kword data size is required to change ROM data to mask
manufacturing data since the program used is for a 4-kword version.
This limitation apply to the case of using EPROM and the case of using data base.
Fill this area with all 1s
Vector address
Zero-page subroutine
(64 words)
Pattern and program
(2048 words)
Not used
ROM 2 kwords version:
HD404052, HD404092, HD40A4052
Address $0800 to $0FFF
$0000
$000F
$0010
$003F
$0040
$07FF
$0800
$0FFF
HD404054 Series/HD404094 Series
99
HD40(A)4052/HD40(A)4054 Option List
Please check off the appropriate applications and enter the necessary information.
2. ROM code media
Date of order
Customer
Department
Name
ROM code name
LSI number
EPROM:
Ceramic oscillator
Crystal oscillator
External clock
f = MHz
f = MHz
f = MHz
3. Oscillator for OSC1 and OSC2
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
HD404052: 2-kword
HD404054: 4-kword
HD40A4052: 2-kword
HD40A4054: 4-kword
1. ROM size
DP-42S
FP-44A
5. Package
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
Used
Not used
4. Stop mode
//
HD404054 Series/HD404094 Series
100
HD404092/HD404094 Option List
Please check off the appropriate applications and enter the necessary information.
2. ROM code media
Date of order
Customer
Department
Name
ROM code name
LSI number
EPROM:
Ceramic oscillator
Crystal oscillator
External clock
f = MHz
f = MHz
f = MHz
3. Oscillator for OSC1 and OSC2
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
HD404092: 2-kword
HD404094: 4-kword
1. ROM size
DP-42S
FP-44A
5. Package
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
Used
Not used
4. Stop mode
//
H42
××
Family
HD404202 Series/HD404222 Series
Rev. 5.0
March 1997
Description
These MCU’s are CMOS 4-bit single-chip microcomputers with the same architecture as the HMCS400
Series. Each microcomputers incorporate ROM, RAM, I/O, and peripheral functions such as one or two
timer/counters. Also, HD404222 Series has two-channel comparators, and a serial interface.
The HD404202 Series includes four chips: the HD404201 with 1-kword ROM and 5-V operation;
HD40L4201 with 1-kword ROM and low-voltage operation; HD404202 with 2-kword ROM and 5-V
operation; HD40L4202 with 2-kword ROM and low-voltage operation. The HD404222 Series includes
three chips: HD404222 with 2-kword ROM and 5-V operation; HD40L4222 with 2-kword and low-voltage
operation; HD4074224 with 4-kword PROM.
The HD4074224, incorporating PROM, is a ZTAT microcomputer which can dramatically shorten
system development period and smooth the process from debugging to mass production. (The PROM
program specifications are the same as for the 27256.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• The differences between HD404202 Series and HD404222 Series.
HD404202 Series HD404222 Series
RAM (digits) 64 128
Timers 8-bit × 1 8-bit × 2
Serial interface — Clock-synchronous
8-bit × 1
Comparators — 2 channels
• HMCS400 CPU (software-compatible with the HMCS400 Series)
• 1024-word × 10-bit mask ROM (HD404201, HD40L4201)
• 2048-word × 10-bit mask ROM (HD404202, HD40L4202, HD404222, HD40L4222)
• 4096-word × 10-bit PROM (HD4074224)
HD404202 Series/HD404222 Series
2
• 64-digit × 4-bit RAM (HD404201, HD40L4201, HD404202, and HD40L4202)
• 128-digit × 4-bit RAM (HD404222, HD40L4222, and HD4074224)
• 22 I/O pins including 10 high-current pins
• Two timer/counters
8-bit free-running or watchdog timer (watchdog timer is selectable by mask option) (HD404222
Series)
8-bit auto-reloading timer/event counter
• Clock-synchronous 8-bit serial interface (HD404222 Series)
• Two-channel comparators (HD404222 Series)
Two analog input pins
Reference voltage pin
• One external interrupt
• Low-power dissipation modes
Standby mode
Stop mode
• Built-in oscillator
Resistor or ceramic oscillator (an external clock is also possible)
• Minimum instruction cycle time
0.89 µs (fOSC = 4.5 MHz, VCC = 3.5 V– 6.0 V)
3.55 µs (fOSC = 1.125 MHz, VCC = 2.5 V– 6.0 V)
2.0 µs (fOSC = 2.0 MHz, VCC = 2.5 V–6.0 V) for HD40L4222
• Package
28 pin shrink-type plastic DIP (DP-28S)
28-pin SOP (FP-28DA)
30-pin SSOP (FP-30D)
HD404202 Series/HD404222 Series
3
Type of Product
Device ROM Size Options Package
Mask ROM HD404201S
HD40L4201S 1024 Selected by mask option DP-28S
HD404201FP
HD40L4201FP FP-28DA
HD404201FT
HD40L4201FT FP-30D
HD404202S
HD40L4202S 2048 DP-28S
HD404202FP
HD40L4202FP FP-28DA
HD404202FT
HD40L4202FT FP-30D
HD404222S
HD40L4222S DP-28S
HD404222FP
HD40L4222FP FP-28DA
HD404222FT
HD40L4222FT FP-30D
ZTATHD4074224S01 4096 Timer A: Free-running timer
Oscillator: Resistor DP-28S
HD4074224S02 Timer A: Free-running timer
Oscillator: Ceramic oscillator
HD4074224S03 Timer A: Watchdog timer
Oscillator: Resistor
HD4074224S04 Timer A: Watchdog timer
Oscillator: Ceramic oscillator
HD4074224FP01 Timer A: Free-running timer
Oscillator: Resistor FP-28DA
HD4074224FP02 Timer A: Free-running timer
Oscillator: Ceramic oscillator
HD4074224FP03 Timer A: Watchdog timer
Oscillator: Resistor
HD4074224FP04 Timer A: Watchdog timer
Oscillator: Ceramic oscillator
HD4074224FT01 Timer A: Free-running timer
Oscillator: Resistor FP-30D
HD4074224FT02 Timer A: Free-running timer
Oscillator: Ceramic oscillator
HD4074224FT03 Timer A: Watchdog timer
Oscillator: Resistor
HD4074224FT04 Timer A: Watchdog timer
Oscillator: Ceramic oscillator
HD404202 Series/HD404222 Series
4
Differences between Mask ROM and ZTAT Microcomputers
Mask ROM ZTAT
Item HD404201 HD40L4201 HD404202 HD40L4202 HD404222 HD40L4222 HD4074224
Power supply voltage
(VCC)3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 6.0 V 2.5 to 6.0 V 3.5 to 5.5 V,
2.7 to 3.5 V
Instruction cycle time
(tcyc)0.89 to 4.0
µs3.55 to 10.0
µs0.89 to 4.0
µs3.55 to 10.0
µs0.89 to 4.0
µs2.0 to 10.0
µs0.89 to 4.0 µs,
2.0 to 10.0 µs
ROM 1024 × 10-
bit 1024 × 10-
bit 2048 × 10-
bit 2048 × 10-
bit 2048 × 10-
bit 2048 × 10-
bit 4096 × 10-bit
RAM 64 × 4-bit 64 × 4-bit 64 × 4-bit 64 × 4-bit 128 × 4-bit 128 × 4-bit 128 × 4-bit
Watchdog timer/ free
running timer —— ——1 1 1
Serial interface — — — — 1 1 1
Comparator — — — — 2 ch 2 ch 2 ch
I/O pin
circuit
(standard
pins)
Without
pull-up
MOS
(NMOS
open drain)
(option A)
Available Available Available Available Available Available —
With pull-
up MOS
(option B)
Available Available Available Available Available Available Available
CMOS
(option C) Available Available Available Available Available Available —
Clock
generation Ceramic Available Available Available Available Available Available Available
Resistor Available
with
tcyc = 1.33
to 4.0 µs
— Available
with
tcyc = 1.33
to 4.0 µs
— Available
with
tcyc = 1.33
to 4.0 µs
— Available only
under
VCC = 3.5 to 5.5 V
with tcyc = 1.33 to
4.0 µs
External Available Available Available Available Available Available Available
Package DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
DP-28S
FP-28DA
FP-30D
HD404202 Series/HD404222 Series
5
PinArrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
R1
R1
R1
R1
D
D
D
D
D
D /INT
D
D
D
0
1
2
3
0
1
2
3
4
5
6
7
8
R2
R2
R2
R2
D
D
TEST
RESET
OSC
OSC
V
D
D
D
3
2
1
0
13
12
2
1
CC
11
10
9
DP-28S
FP-28DA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
R1
R1
R1
R1
D
D
D
D
D
D /INT
D /SCK
D /SI
D /SO
0
1
2
3
0
1
2
3
4
5
6
7
8
R2
R2
R2
R2
D
D
TEST
RESET
OSC
OSC
V
D /COMP
D /COMP
D /V
3
2
1
0
13
12
2
1
CC
11
10
9ref
DP-28S
FP-28DA
HD404201, HD40L4201, HD404202, HD40L4202
HD404222, HD40L4222, HD4074224
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NC
GND
R1
R1
R1
R1
D
D
D
D
D
D /INT
D
D
D
NC
R2
R2
R2
R2
D
D
TEST
RESET
OSC
OSC
V
D
D
D
FP-30D
0
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NC
GND
R1
R1
R1
R1
D
D
D
D
D
D /INT
D /SCK
D /SI
D /SO
NC
R2
R2
R2
R2
D
D
TEST
RESET
OSC
OSC
V
D /COMP
D /COMP
D /V
FP-30D
0
1
2
3
0
1
2
3
4
5
6
7
8
0
1
2
3
4
6
7
8
5
3
2
1
0
13
12
2
1
CC
11
10
9
3
2
1
0
13
12
2
1
CC
11
10
9ref
1
0
HD404202 Series/HD404222 Series
6
BlockDiagram
Voltage
comparator Serial
interface Timer B/
event
counter
Timer A/
watchdog
timer
External
interrupt
Interrupt control
128 4-bit RAM
×
D /
Comp1
11
D /
Comp0
10
D /
V9
ref D /
SO
8D /
SI7D /
SCK
6D /
INT RESET TEST OSC1OSC2VCC GND
System control 2048 10-bit
4096 10-bit
ROM
×
Program counterB (4)A (4)CAST
ALU
Y (4)X (4)
SPY (4)SPX (4)
R2 R1 D port
R23R22R21R20R13R12R11R10D13 D12 D /
COMP
11 D /
COMP
10 D /
V9
ref D /
SO
8D /
SI
7D /
SCK
6
5
D /
INT
5D4D3D2D1D0
Stack pointer
Instruction
decoder
High-current pins
Timer B/event counter External
interrupt
Interrupt control
64 4-bit RAM
×
D /
INT RESET TEST OSC1OSC2VCC GND
System control
1024 10-bit
2048 10-bit
ROM
×
Program counterB (4)A (4)CAST
ALU
Y (4)X (4)
SPY (4)SPX (4)
R2 R1 D port
R23R22R21R20R13R12R11R10D13 D12 D
11 D
10 D
9D
8D
7D
6
5
D /
INT
5D4D3D2D1D0
Stack pointer
Instruction
decoder
High-current pins
×
×
HD404201, HD40L4201, HD404202, HD40L4202
HD404222, HD40L4222, HD4074224
10
HD404202 Series/HD404222 Series
7
Pin Description
Pin Number
Item Symbol DP-28S
FP-28DA FP-30D I/O Function
Power supply VCC 18 19 Power supply pin
GND 1 2 Ground connection pin
Test TEST 22 23 I Pin used for test purposes only. Connect it to ground.
Reset RESET 21 22 I MCU reset pins
Oscillator OSC1, 19 20 I Pins for the internal oscillator circuit. Connect them to
a resistor or a ceramic oscillator, or connect OSC1 to
an external oscillator circuit. The internal oscillator is
selected by mask option.
OSC220 21 O
Port D0–D13 6–17,
23, 24 7–18,
24, 25 I/O Input/output ports addressable by individual bits. Pins
D12 and D13 can output 15 mA maximum.
R10–R232–5,
25–28 3–6,
26–29 I/O Input/output ports addressable in 4-bit units. These
pins can output 15 mA maximum.
Interrupt INT 11 12 I Input pin for external interrupt. It is also used as an
external event input for timer B. It is multiplexed with
pin D5.
Serial
interface*
SCK 12 13 I/O Serial interface clock input/output pin. It is multiplexed
with pinD6.
SI 13 14 I Serial interface receive data input pin. It is multi-
plexed with pin D7.
SO 14 15 O Serial interface transmit data output pin. It is multi-
plexed with pin D8.
Comparator*Vref 15 16 I Reference voltage pin to input the threshold voltage of
the analog input pins
COMP016 17 I Analog input pins for the voltage comparator
COMP117 18 I
Note: *Only applicable for the HD404222 Series.
HD404202 Series/HD404222 Series
8
Memory Map
ROM Memory Map
The areas in ROM are described below with its memory map shown in figure 1.
Vector Address Area: Locations $0000 through $0009 can be used for JMPL instructions to branch to the
starting address of an initialization program for interrupt programs. After MCU reset or an interrupt is
performed, the program is executed from a vector address.
Zero-Page Subroutine Area: Locations $0000 through $003F can be used for subroutines. The CAL
instruction branches to subroutines within this area.
Pattern Area ($0000 to $03FF: HD404201, HD40L4201; $0000 to $07FF: HD404202, HD40L4202,
HD404222, HD40L4222; $0000 to $0FFF: HD4074224): The P instruction allows reference to ROM data
in this area as a pattern.
Program Area ($0000 to $03FF: HD404201, HD40L4201; $0000 to $07FF: HD404202, HD40L4202,
HD404222, HD40L4222; $0000 to $0FFF: HD4074224)
HD404202 Series/HD404222 Series
9
0
1
2
3
4
5
6
7
8
9
Vector address JMPL instruction
(Jump to reset routine)
JMPL instruction
(Jump to INT routine)
JMPL instruction
(Jump to timer B routine)
Zero-page subroutine
(64 words)
HD404201, HD40L4201
Program/pattern
(1024 words)
9
10
0
63
64
2047
$0009
$000A
$0000
$003F
$0040
$07FF
Not used
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
HD404202, HD40L4202
Program/pattern
(2048 words)
$03FF
$0400
1023
1024
HD404201, HD40L4201, HD404202, HD40L4202
0
1
2
3
4
5
6
7
8
9
Vector address JMPL instruction
(Jump to RESET routine)
JMPL instruction
(Jump to INT routine)
JMPL instruction
(Jump to timer B routine)
JMPL instruction
(Jump to serial routine)
Zero-page subroutine
(64 words)
HD4074224
Program/pattern
(4096 words)
9
10
0
63
64
2047
2048
4095
$0009
$000A
$0000
$003F
$0040
$07FF
$0800
$0FFF
JMPL instruction
(Jump to timer A routine)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
HD404222, HD40L4222
Program/pattern
(2048 words)
HD404222, HD40L4222, HD4074224
Not used
Figure 1 ROM Memory Map
HD404202 Series/HD404222 Series
10
RAM Memory Map
In addition to data and stack areas, interrupt control bits and special function registers are also mapped in
RAM memory. The RAM memory map shown in figure 2 is described below.
Interrupt Control Bits Area ($0000 to $0002): The interrupt control bits area (figure 3) is used for
interrupt control. This area and CMR (location $03) register is accessible only by RAM bit manipulation
instructions. However, the interrupt request flag cannot be set by software. The RSP bit is used only to
reset the stack pointer.
Note that if unusable bits are manipulated, the MCU may malfunction (HD404202 Series: bits 0, 1 of
$001, and $002; HD404222 Series: bits 2, 3 of $002).
Special Function Registers Area ($003 to $00C): The special function registers are the mode or data
registers for external interrupt, the serial interface, the timer/counters, comparator and are also used as data
control registers for I/O ports. These registers are classified into three types: write-only, read-only, and
read/write, as shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions
(except for CMR register).
Note that if the unusable locations are set, the MCU may mulfunction (only applicable for HD404202
Series $003, $005 to $008 and $00C).
Data Area ($020 to $03F: HD404202 Series; $020 to $07F: HD404222 Series): The 16 digits of $020
through $02F are called memory registers (MR) and are also accessible by the LAMR and XMRA
instructions (figure 4).
Stack Area ($0E0 to $0FF): Locations $0E0 through $0FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or
CALL instruction) or interrupt is performed. This area can be used as an 8-level nesting stack in which one
level requires 4 digits. Figure 4 shows the stack area levels. The program counter is restored by the RTN
and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. When this
area is not used as a stack, it becomes available as a data area.
HD404202 Series/HD404222 Series
11
0
2
3
4
5
6
7
8
9
10
11
12
0
47
48
127
128
255
$000
$07F
$080
$0DF
$0E0
$0FF
$000
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
31
32
223
224
RAM mapped registers
(32 digits)
Memory registers (MR)
(16 digits)
Data (80 digits)
Not used
(96 digits)
Stack (32 digits) 31 $01F
Interrupt control bits
Comparator mode register (CMR)
Port mode register (PMR)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B (TMB)
(TCBL)/(TLRL)
(TCBU)/(TLRU)
Timer B
Reference voltage select register (RSR)
Not used
R/W
W
W
R/W
R/W
W
W
R/W
R/W
R/W
R
R
Timer/event counter B lower
(TCBL) Timer load register B
lower (TLRL)
R: Read only
W: Write only
R/W: Read/Write
Two registers are mapped on the same address.
Timer/event counter B upper
(TCBU) Timer load register B
upper (TLRU)
W
W
$00A
$00B
10
11
$01F
$020
$02F
$030
Note:
HD404222, HD40L4222, HD4074224
The status flag becomes invalid when CMR bits are tested by the TM or TMD instructions
(only applicable for HD404222 Series).
0
2
3
4
5
8
9
10
11
12
0
47
48
255
$000
$0DF
$0E0
$0FF
$000
$002
$003
$004
$005
$008
$009
$00A
$00B
$00C
31
32
223
224
RAM mapped registers
(32 digits)
Memory registers (MR)
(16 digits)
Data (16 digits)
Not used
(160 digits)
Stack (32 digits) 31 $01F
Interrupt control bits
Port mode register (PMR)
(TCBL)/(TLRL)
(TCBU)/(TLRU)
Timer B
Not used
W
$01F
$020
$02F
$030
HD404201, HD40L4201, HD404202, HD40L4202
63
64 $03F
$040
Not used
Timer mode register B (TMB) W
R/W
R/W
Not used
*
*
*
Figure 2 RAM Memory Map
HD404202 Series/HD404222 Series
12
0
1
2
Bit 3 Bit 2 Bit 1 Bit 0
IM of external INT
(IMEX) IF of external INT
(IFEX) Reset SP bit
(RSP) Interrupt enable flag
(IE)
IM of timer B
(IMTB) IF of timer B
(IFTB) IM of timer A
(IMTA) IF of timer A
(IFTA)
Not used IM of serial
(IMS) IF of serial
(IFS)
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, reset by
the REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by
Not used
other instructions. Furthermore, the interrupt request flag is not affected by the
SEM/SEMD instruction.
The status flag becomes invalid when the unused bits and RSP bit are tested by
the TM or TMD instruction.
$000
$001
$002
Note:
**
*
*
*Only applicable for the HD404222 Series.
Figure 3 Configuration of Interrupt Control Bits Area
Memory registers Stack area Bit 3 Bit 2 Bit 1 Bit 0
ST PC
11
PC PC PC PC
98710
CA PC PC PC
654
PC PC PC PC
210
3
252
253
254
255
$0FC
$0FD
$0FE
$0FF
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
MR (0)
MR (1)
MR (2)
MR (3)
MR (4)
MR (5)
MR (6)
MR (7)
MR (8)
MR (9)
MR (10)
MR (11)
MR (12)
MR (13)
MR (14)
MR (15)
$0E0
$0FF
224
255
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
PC – PC : Program counter
ST: Status flag
CA: Carry flag
11 0
PC PC
13 12
Note: According to on-chip ROM capacity, following area are ignored.
HD404201, HD40L4201: PC – PC
HD404202, HD40L4202, HD404222, HD40L4222: PC – PC
HD4074224: PC , PC
13 10 13 11
13 12
Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position
HD404202 Series/HD404222 Series
13
Functional Description
Registers and Flags
The MCU has eight registers and two flags for CPU operations (figure 5).
CA Carry flag
ST Status flag
PC Program counter
011
Stack pointer
0
111 47 SP
SPY SPY register
03
SPX SPX register
03
Y Y register
03
X X register
03
B B register
03
A Accumulator
03
Figure 5 Registers and Flags
Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results of the arithmetic
logic unit (ALU), and transfer data to/from memory, I/O, and other registers.
X Register (X), Y Register (Y): The X and Y registers are 4-bit registers used for indirect addressing of
RAM. The Y register is also used for D port addressing.
SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY are used to assist the X and
Y registers, respectively.
Carry Flag (CA): The carry flag stores the overflow from the ALU generated by an arithmetic operation.
It is also affected by the SEC, REC, ROTL, and ROTR instructions.
HD404202 Series/HD404222 Series
14
During an interrupt, the carry flag is pushed onto the stack and is pulled from the stack only by the RTNI
instruction.
Status Flag (ST): The status flag holds the ALU overflow, ALU non-zero, and the results of a bit test
instruction for arithmetic or compare instructions. The status flag is also used as a branch condition for the
BR, BRL, CAL, and CALL instructions. The value of the status flag remains unchanged until the next
arithmetic, compare, or bit test instruction is executed. The status flag becomes a 1 after the BR, BRL,
CAL, or CALL instruction was either executed or not. During an interrupt, the status flag is pushed onto
the stack and can be pulled from the stack only by the RTNI instruction.
Program Counter (PC): The program counter is a 12-bit binary counter which controls the sequence in
which the instructions stored in ROM are executed.
Stack Pointer: The stack pointer (SP) is used to point to the address of the next stack area (up to 8 levels).
The stack pointer is initialized to RAM address $FF. It is decremented by 4 when data is pushed onto the
stack, and incremented by 4 when data is pulled from it. The stack can only be used up to 8 levels deep
because the upper 3 bits of the stack pointer are fixed at 111.
The stack pointer is initialized to $FF by either MCU reset or RSP bit reset by the REM/REMD instruction.
Reset
The MCU is reset by pulling the RESET pin low. At power-on or when cancelling the stop mode, the reset
period must satisfy tRC for the oscillator to stabilize. In other cases, at least two instruction cycles are
required for the MCU to be reset.
Table 1 shows the components initialized by the MCU reset, and the status of each component.
Table 2 shows how registers recover from the stop mode.
Take note that the reset signal is not acknowledged immediately at power-on by the MCU but at the time
the oscillator has stabilized, so during this period the statuses within the MCU and at the I/O pins are not
defined.
HD404202 Series/HD404222 Series
15
Table 1 Initial Values After MCU Reset
Item Initial Value by MCU
Reset (RESET = 0) Contents
Program counter (PC) $0000 Execute program from the top of
ROM address
Status flag (ST) 1 Enable branching with conditional
branch instructions
Stack pointer (SP) $0FF Stack level is 0
I/Opins, output
registers Without pull-up MOS 1 Enable input
With pull-up MOS 1 Enable input
CMOS 1 —
Interrupt flags
and mask Interrupt enable flag (IE) 0 Inhibit all interrupts
Interrupt request flag (IF) 0 No interrupt request
Interrupt mask (IM) 1 Mask interrupt request
Mode registers Port mode register (PMR) 000 See Port Mode Register section
Serial mode register (SMR)*0000 See Serial Mode Register section
Timer mode register A (TMA)*0000 See Timer Mode Register A
section
Timer mode register B (TMB) 0000 See Timer Mode Register B
section
Comparator mode register
(CMR)*00 See Comparator Mode Register
section
Comparator Reference voltage select
register (RSR)*0000 See Reference Voltage Select
Register section
Timer/counters,
serial interface Prescaler $000 —
Timer counter A (TCA)*$00 —
Timer counter B (TCB) $00 —
Timer load register B (TLR) $00 —
Octal counter*000 —
Note: *Only applicable for the HD404222 Series.
HD404202 Series/HD404222 Series
16
Table 2 Initial Values After MCU Reset
Item After MCU Reset to Recover from
Stop Mode After MCU Reset to Recover from
Other Modes
Carry flag (CA) The contents of the items before MCU
reset are not retained and must be
initialized by software.
The contents of the items before MCU
reset are not retained and must be
initialized by software.
Accumulator (A)
B register (B)
X/SPX registers (X/SPX)
Y/SPY registers (Y/SPY)
Serial data
register (SR)*
RAM The contents of RAM before MCU reset
(just before the STOP instruction) are
retained.
The contents of RAM before MCU
reset are not retained and must be
initialized by software.
Note: *Only applicable for the HD404222 Series.
HD404202 Series/HD404222 Series
17
Interrupts
Two interrupt sources are available on the MCU of HD404202 Series. They are an external request (INT)
and timer/counter (timer B). HD404222 Series has four interrupt sources: the two sources stated above,
timer A and serial interface. For each source, an interrupt request flag (IF), interrupt mask (IM), and
interrupt vector addresses are provided to control and maintain the interrupt request. An interrupt enable
flag (IE) is also used to control interrupt operations.
Interrupt Control Bits and Interrupt Operation: The interrupt control bits are mapped on $000 through
$002 of the RAM. These bits are accessible by RAM bit manipulation instructions. The interrupt request
flag (IF) cannot be set by software. At MCU reset initialization, the IE and IF are cleared to 0, and IM is set
to 1.
Figure 6 is a block diagram of the interrupt control circuit. Table 3 shows the interrupt priority and vector
addresses, and table 4 shows the interrupt conditions corresponding to each interrupt source.
An interrupt request is generated when the IF is set to 1 and IM is 0. If the IE is 1 during this period, the
interrupt will be activated and vector addresses will be generated from the priority PLA corresponding to
the interrupt sources.
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart.
If an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. Also in the second cycle and third cycle, the carry flag, status flag, and program counter are
pushed onto the stack. Included in the third cycle is the generation of the vector address.
At each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF which caused the interrupt must be reset by software in the interrupt program.
HD404202 Series/HD404222 Series
18
Sequence control:
Push PC/CA/ST onto stack
Reset IE
Jump to vector address
Priority control PLA
Vector
address
IFEX
$000,2
IMEX
$000,3
IE
$000,0
IFS
$002,0
IMS
$002,1
IFTB
$001,2
IMTB
$001,3
IFTA
$001,0
IMTA
$001,1
Note: indicates only applicable for the HD404222 Series.
INT interrupt
Serial interrupt
Timer B interrupt
Timer A interrupt
Figure 6 Interrupt Control Circuit Block Diagram
Table 3 Vector Addresses and Interrupt Priority
HD404202 Series
Reset/Interrupts Priority Vector Addresses
RESET — $000
INT 1 $002
Timer B 2 $006
HD404222 Series
Reset/Interrupts Priority Vector Addresses
RESET — $000
INT 1 $002
Timer A 2 $004
Timer B 3 $006
Serial 4 $008
HD404202 Series/HD404222 Series
19
Table 4 Interrupt Conditions
HD404202 Series
Interrupt Control Bits INT Timer B
IE 1 1
IFEX · IMEX 10
IFTB · IMTB *1
Note: *indicates don’t care
HD404222 Series
Interrupt Control Bits INT Timer A Timer B Serial
IE 1111
IFEX · IMEX 1000
IFTA · IMTA *100
IFTB · IMTB **10
IFS · IMS ***1
Note: *indicates don’t care
Instruction cycles
123456
Instruction
execution*
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note: *The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Stacking
Figure 7 Interrupt Processing Sequence
HD404202 Series/HD404222 Series
20
Yes
No
(serial interrupt)
Yes
No
Yes
PC $002
←
PC $004
←
PC $006
←
PC $008
←
←
←
←
←
IE 0
Stack (PC)
Stack (CA)
Stack (ST)
INT
interrupt?
Timer-A
interrupt?
Timer-B
interrupt?
No
Accept interrupt
Power on
IE = 1?
PC (PC) + 1
Execute instruction
←
Interrupt
request?
Yes
No
Yes
No
RESET = 0?
Reset MCU
Yes
No
indicates only applicable
for the HD404222 Series.
Figure 8 Interrupt Processing Flowchart
HD404202 Series/HD404222 Series
21
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag (table 5) enables or disables interrupt
requests. It is reset by an interrupt and set by the RTNI instruction.
Table 5 Interrupt Enable Flag
IE Interrupt Enabled/Disabled
0 Disabled
1 Enabled
External Interrupt (INT): The external interrupt request input (INT) can be selected by the port mode
register (PMR: $004). Setting bit 2 of PMR causes the D5/INT pin to be used as INT .
The external interrupt request flag IFEX (table 6) is set at the falling edge of INT input.
The INT input can be used as a clock signal input to timer B, which counts up at each falling edge of the
INT input. When using INT as the timer B external event input, the external interrupt mask IMEX (table 7)
has to be set so that the INT interrupt request will not be accepted.
Table 6 External Interrupt Request Flag
IFEX Interrupt Request
0No
1 Yes
Table 7 External Interrupt Mask
IMEX Interrupt Request
0 Enabled
1 Disabled (masked)
External Interrupt Request Flag (IFEX: $000, Bit 2): The external interrupt request flag is set the falling
edge of the INT input.
External Interrupt Mask (IMEX: $000, Bit 3): The external interrupt mask (table 7) masks the external
interrupt request.
Timer A Interrupt Request Flag (IFTA: $001, Bit 0): The timer A interrupt request flag (table 8) is set
by the timer A overflow output. It can be only used by the HD404222 Series.
HD404202 Series/HD404222 Series
22
Table 8 Timer A Interrupt Request Flag
IFTA Interrupt Request
0No
1 Yes
Timer A Interrupt Mask (IMTA: $001, Bit 1): The timer A interrupt mask (table 9) prevents an interrupt
request from being generated by the timer A interrupt request flag. It can be only used by the HD404222
Series.
Table 9 Timer A Interrupt Mask
IMTA Interrupt Request
0 Enabled
1 Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $001, Bit 2): The timer B interrupt request flag (table 10) is set
by the overflow output of timer B.
Table 10 Timer B Interrupt Request Flag
IFTB Interrupt Request
0No
1 Yes
Timer B Interrupt Mask (IMTB: $001, Bit 3): The timer B interrupt mask (table 11) prevents an
interrupt request from being generated by the timer B interrupt request flag.
Table 11 Timer B Interrupt Mask
IMTB Interrupt Request
0 Enabled
1 Disabled (masked)
Serial Interrupt Request Flag (IFS: $002, Bit 0): The serial interrupt request flag (table 12) will be set
when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by
resetting the octal counter. It can be only used by the HD404222 Series.
HD404202 Series/HD404222 Series
23
Table 12 Serial Interrupt Request Flag
IFS Interrupt Request
0No
1 Yes
Serial Interrupt Mask (IMS: $002, Bit 1): The serial interrupt mask (table 13) masks the interrupt
request. It can be only used by the HD404222 Series.
Table 13 Serial Interrupt Mask
IMS Interrupt Request
0 Enabled
1 Disabled (masked)
Port Mode Register (PMR: $004): The 3-bit write-only port mode register controls the D5/INT, D7/SI,
and D8/SO pins as shown in table 14. The port mode register is initialized to $0 by MCU reset. Therefore
these pins are initially used as ports. Note that if unusable bit 3 is set, the MCU may malfunction.
Table 14 Port Mode Register
PMR2 PMR1 PMR0
PMR: $004
D /SO pin mode selection
D /SI pin mode selection
D /INT pin mode selection
8
7
5
**
PMR2 D5 /INT Pin
0 Used as D5 port input/output pin
1 Used as INT input pin
PMR1*D7 /SI Pin
0 Used as D7 port input/output pin
1 Used as SI input pin
PMR0*D8 /SO Pin
0 Used as D8 port input/output pin
1 Used as SO output pin
Note: *PMR0 and PMR1 can be only used by the HD404222 Series.
HD404202 Series/HD404222 Series
24
Operating Modes
The MCU has two low-power dissipation modes, standby mode and stop mode (table 15). Figure 9 shows
a mode transition diagram of these modes.
Standby Mode: Executing the SBY instruction places the MCU into standby mode. In standby mode,
the oscillator circuit, interrupts, timer/ counters, and serial interface remain active. On the other hand, the
CPU stops since the clock related to the instruction execution stops. Registers, RAM, and I/O pins retain
the states they were in just before the MCU went into standby mode.
Table 15 Low-Power Dissipation Mode Function
Low-Power
Dissipation Mode Instruction Oscillator
Circuit Instruction
Execution Registers,
Flags Interrupt
Function
Standby mode SBY instruction Active Stop Retained Active
Stop mode STOP
instruction Stop Stop Reset*1Stop
Table 15 Low-Power Dissipation Mode Function (cont)
Low-Power
Dissipation Mode RAM Input/ Output
Pins Timer/ Counters,
Serial Interface*3Comparator*3Cancellation
Method
Standby mode Retained Retained*2Active Stop RESET input,
interrupt
request
Stop mode Retained High impedance Stop Stop RESET input
Notes: *1. The MCU recovers from stop mode by RESET input. Refer to table 1 for the contents of the
flags and registers.
*2. If an I/O circuit is active, an I/O current may flow, depending on the state of the I/O pin in standby
mode. This current is in addition to the current dissipation in standby mode.
*3. Serial interface and comparator can be only used by the HD404222 Series.
The Standby mode may be cancelled by enabling RESET or by asserting an interrupt request. In the former
case, the MCU is reset. In the latter case, the MCU becomes active and executes the next instruction
following the SBY instruction. After this instruction is completed and if the interrupt enable flag is 1 when
an interrupt request asserted, the interrupt is executed, while if it is 0, the interrupt request is put on hold
and normal instruction execution continues.
Figure 10 shows the flowchart of the standby mode.
Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator
circuit and all functions of the MCU stop.
The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 11, the RESET
input must be applied for at least tRC for the oscillation to stabilize. (Refer to the AC Characteristics table.)
After stop mode is cancelled, the RAM retains the state it was in just before the MCU went into stop mode,
HD404202 Series/HD404222 Series
25
but the accumulator, B register, X/SPX and Y/SPY registers, carry flag, and serial data register will not
retain their contents. (The serial data resister can be only used by the HD404222 Series.)
Standby
mode Stop
mode
Active
mode
Reset
state
SBY
instruction
RESET = 0
Interrupt
request
RESET = 0 RESET = 1
RESET = 0
STOP
instruction
Figure 9 MCU Operation Mode Transition
HD404202 Series/HD404222 Series
26
Standby
Oscillator: Active
Peripheral clocks:
Active
All other clocks: Stop
RESET
= 0? No
Yes
Restart
processor clocks
Reset MCU Execute
instruction Accept
interrupt
Restart
processor clocks
Yes
Yes
Yes
No
No Yes
Yes
No
No Yes
Yes
No
No Yes
Yes No
No
IFEX = 1?
IMEX = 0?
IFTA = 1?
IMTA = 0?
IFTB = 1?
IMTB = 0?
IFS = 1?
IMS = 0?
IE = 1?
No
Execute
next instruction
indicates only applicable for
the HD404222 Series.
Figure 10 MCU Operating Flowchart in Standby Mode
HD404202 Series/HD404222 Series
27
Stop mode
Oscillator
Internal clock
RESET
STOP instruction
execution t t (stabilization time)
RC
tres
res ≥
Figure 11 Timing of Stop Mode Cancellation
HD404202 Series/HD404222 Series
28
Internal Oscillator Circuit
Figure 12 shows a block diagram of the internal oscillator circuit. Through mask options, either a ceramic
oscillator or resistor can be selected as the oscillator type and connected to OSC 1 and OSC2. See figure 13
for the layout of the ceramic oscillator. For other cases, an external clock operation is available.
OSC
1/4
divider
circuit
Timing
generator
circuit
OSC Oscillator
(selectable
with mask
options)
1
2
System
clock
Figure 12 Internal Oscillator Circuit
Table 16 Examples of Oscillator Circuits
Circuit Configuration Circuit Constants
External clock
operation OSC
Open
1
OSC2
Oscillator
Ceramic
oscillator OSC
2
C1
2
COSC
1
f
R
f
R
Ceramic oscillator: CSA4.00MG (MURATA)
C1=C2: 30pF±20%
Rf:1MΩ±20%
Ceramic oscillator: CSB1000J (MURATA)
C1=C2:220pF±20%
Rf: 1 MΩ ±20%
Resistor OSC
2
OSC
1
Rf
Rf: 20 kΩ ±1%
Notes: The circuit parameters listed above are dependent on the ceramic oscillator and the floating
capacitance when designing the board. In employing the resonator, consult with the ceramic
oscillator manufacturer to determine the circuit parameters.
The wiring between OSC1, OSC2, and the elements should be as short as possible without crossing
over other wires. Refer to the layout of the ceramic oscillator in figure 13.
HD404202 Series/HD404222 Series
29
!"#()*/0
TEST
RESET
OSC2
OSC1
VCC
D11
Figure 13 Layout of the Ceramic Oscillator
HD404202 Series/HD404222 Series
30
Input/Output
The MCU has 22 standard I/O pins. As for the mask ROM version of HD404201, HD40L4201,
HD404202, HD40L4202, HD404222 and HD40L4222, one of three circuit types can be selected by the
mask option for each standard pin: with pull-up MOS or without pull-up MOS (NMOS open drain) or
CMOS.
The I/O pins for the HD4074224 are fixed as with pull-up MOS.
When every input/output pin is used as an input pin, the mask option and output data must be selected as
specified in table 17.
Table 17 Data Input from Common Input/Output Pins
I/O Pin Circuit Type Input Possible Input Pin State
Standard pins CMOS No —
Without pull-up MOS
(NMOS open drain) Yes 1
With pull-up MOS Yes 1
Output Circuit Operation of with Pull-Up MOS Standard Pins: In the standard pin option with pull-up
MOS, the circuit shown in figure 14 is used to shorten the rise time of output.
When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this
instruction. This pulse will switch the PMOS (B) on (in figure 14) and shorten the rise time. The write
pulse keeps PMOS on for two-eighths of the instruction cycle time. While the write pulse is 0, a high
output level is maintained by the pull-up MOS (C).
When the HLT signal becomes 0 in stop mode, MOSs (A), (B), and (C) turn off. When the HLT signal is
1, the pins’ states are maintained.
HD404202 Series/HD404222 Series
31
Pull-up
MOS (C)
M3
PMOS (B)
M2
NMOS (A)
M1
Write pulse
(by output
instruction)
HLT
Data
1 instruction cycle
Output instruction execution
Write pulse
VCC VCC
Figure 14 Output Circuit Operation of Standard Pins with Pull-Up MOS Option
D Port: The D port has 14 discrete I/O pins, each of which can be addressed independently. The D port
can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD
and TDD instructions.
For the HD404222 Series pins D5 to D11 are multiplexed with pins INT, SCK, SI, SO, Vref, COMP0, and
COMP1, respectively. Setting, resetting, or testing non-existing ports results in invalid data. As for the
HD404202 Series only pin D5/INT applies.
R Ports: The R ports are I/O pins that are accessed in 4-bit units. Data is input through the LAR and LBR
instructions and output through the LRA and LRB instructions. Writing into non-existing ports will not
affect the MCU, however, the values read from the non-existing ports cannot be guaranteed.
Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction due to noise. The I/O pins
should be fixed as follows to prevent malfunction.
• Select the option of without pull-up MOS for unused I/O pins and connect them to GND of the printed
circuit board.
• For the HD404222 Series sets D5/INT, D6/SCK, D7/SI, D8/SO, D9/Vref, D10/COMP0, and D11/COMP1 as
D5 to D11, respectively, by software. As for the HD404202 Series only pin D5/INT applies.
HD404202 Series/HD404222 Series
32
Table 18 I/O Pin Circuit Types Standard Pins
I/O Pins Circuit Type
I/O common pins
(D0–D13, R10–R13, R20–R23)Without pull-up MOS
(NMOS open drain) (A) HLT Input data
HLT
Output data
With pull-up MOS (B) HLT
VCC VCC
Input data
Write pulse
HLT
Output data
CMOS (C) HLT
VCC
Input data
HLT
Output data
I/O common pins
(SCK (output mode))*Without pull-up MOS
(NMOS open drain) or
CMOS (A or C) HLT
VCC
SCK
(internal SCK)
(HLT + mode select)
With pull-up MOS (B)
VCC VCC
SCK
(internal SCK)
(HLT +
mode select)
HLT
HD404202 Series/HD404222 Series
33
Table 18 I/O Pin Circuit Types (cont) Standard Pins
I/O Pins Circuit Type
Output pins (SO)*Without pull-up MOS
(NMOS open drain) or
CMOS (A or C) HLT
VCC
SO
With pull-up MOS (B) VCC
HLT
VCC
SO
Input pins (INT, SI*, SCK*
(input mode)) Without pull-up MOS
(NMOS open drain) or
CMOS (A or C)
Input
data
HLT
With pull-up MOS (B) Input data
HLT
Input pins
(COMP0*, COMP1*)Without pull-up MOS
(NMOS open drain) or
CMOS (A or C)
Reference voltage
+
–
CPU input
Analog comparator
With pull-up MOS (B) Reference voltage
+
–
CPU input
Analog comparator
Notes: 1. HD404202 Series: when selecting pin D5 as INT by software, the pull-up MOS will be disabled
even if selecting mask option B (with pull-up MOS).
2. HD404222 and HD40L4222: when selecting pins D5, D6, and D7 as INT, SCK, and SI input,
respectively, by software, the pull-up MOS of each terminal will be disabled even if selecting
mask option B (with pull-up MOS).
HD4074224: pins D5, D6, and D7 are fixed as with pull-up MOS (B). But when selecting these pins
as INT, SCK, and SI input, respectively, by software, the pull-up MOS of each terminal will be
disabled
*Only applicable for the HD404222 Series.
HD404202 Series/HD404222 Series
34
Timers
The MCU of HD404202 Series contains a prescaler and a timer/counter (timer B), where as one prescaler
and two timer/counters (timers A and B) are available on the MCU of HD404222 Series. Figure 15 shows
the block diagram of timer/counters. The prescaler is an 11-bit counter, timer A is an 8-bit free-
running/watchdog timer, and timer B is an 8-bit auto-reload timer/event counter.
Prescaler: The system clock signal is input to the prescaler. At MCU reset, the prescaler is initialized to
$000 and starts dividing the system clock frequency. The prescaler keeps counting up except at MCU reset
and stop mode. The prescaler provides clock signals to timer A, timer B, and the serial interface (Timer A
and the serial interface can be only used by the HD404222 Series). The prescaler divide ratio is selected by
timer mode register A (TMA), timer mode register B (TMB), and serial mode register (SMR) (TMA and
SMR can be only used by the HD404222 Series).
Timer mode register B
Internal bus line (S1)
TMB (4 bit)
Timer B MPX
INT
Prescaler (11 bit)
Timer A MPX
TMA (4 bit)
Internal bus line (S2)
TL (4 bit)
Timer latch register
TCB (8 bit)
Timer/event counter B
TLR (8 bit)
Timer load register
Internal bus line (S2)
System
clock
IFTA
System
reset
IFTB
TBOF
A
B
Mask
option
CPTA
CPTB
TAOF
3
3
4
44
Interrupt
request flag
of timer B
Interrupt
request flag
of timer A
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
÷1024
Mask option
A
BFree-running timer
Watchdog timer
44
Type Function
TCA (8 bit)
Timer/event counter A
Timer mode register A
indicates (timer A)
only applicable for
the HD404222
Series.
Figure 15 Timer/Counters Block Diagram
HD404202 Series/HD404222 Series
35
Timer A Operation (Only Applicable for the HD404222 Series): Timer A’s function is selected via the
mask option.
When timer A is used as a free-running timer, it counts up every input clock signal after timer A has been
initialized to $00 by MCU reset. When the next clock signal is input after timer A counts up to $FF, timer
A is set to $00 again, and generates an overflow output. This sets the timer A interrupt request flag (IFTA:
$001, bit 0) to 1. Therefore, this timer can function as an interval timer periodically generating overflow
output at every 256th clock signal. The clock signals input to timer A are selected by timer mode register
A (TMA: $008).
Note that when timer A is used as a free-running timer, if setting bit 3 of timer mode resister A may cause
the MCU to malfunction.
When timer A is used as a watchdog timer, the input clock is specified as 1/2048 output divided by the
prescaler. The watchdog timer is initialized to $00 at MCU reset, then counts up every input clock signal.
If a clock signal is applied after the timer becomes $FF, an overflow is generated and the MCU is reset.
After reset, the MCU re-executes the program from the beginning. The program must set bit 3 of timer
mode register A to reset timer counter A.
Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock
source, and the prescaler divide ratio for timer B. When the external event input is used as an input clock
signal to timer B, select D5/INT as INT and set the external interrupt mask (IMEX) to prevent an external
interrupt request from occurring.
Timer B is initialized by software according to the data written in timer load register B. Timer B counts up
at every input clock signal. When the next clock signal is input after timer B is set to $FF, timer B will
generate an overflow output. Then, if the auto-reload function is selected, timer B is initialized to the value
of timer load register B. If it is not selected, timer B goes back to $00. The timer B interrupt request flag
(IFTB: $001, bit 2) will hold the overflow output.
Timer Mode Register A (TMA: $008): Four-bit write-only timer mode register A selects the timer
function for timer A and the prescaler divide ratio of timer A’s clock input as shown in table 19. Timer
mode register A is initialized to $0 by MCU reset.
Table 19 Timer Mode Register A
TMA2 TMA1 TMA0 Prescaler Divide Ratio
000÷ 2048
1÷ 1024
10÷ 512
1÷ 128
100÷ 32
1÷ 8
10÷ 4
1÷ 2
HD404202 Series/HD404222 Series
36
Timer Mode Register B (TMB: $009): Four-bit write-only timer mode register B (TMB) selects the auto-
reload function, the prescaler divide ratio, and the source of the clock input signal as shown in table 20.
Timer mode register B is initialized to $0 by MCU reset.
The operation mode of timer B changes at the second instruction cycle after timer mode register B is
written to. Timer B should be initialized by writing data into timer load register B after the contents of
TMB are changed. The configuration and function of timer mode register B is shown in figure 16.
Table 20 Timer Mode Register B
TMB3 Auto-Reload Function
0No
1 Yes
TMB2 TMB1 TMB0 Prescaler Divide Ratio, Clock Input Source
000÷ 2048
1÷ 512
10÷ 128
1÷ 32
100÷ 8
1÷ 4
10÷ 2
1INT (external event input)
TMA3
TMA*: $008
Timer-B input clock selection
Auto-reload function selection
TMA2 TMA1 TMA0 TMB3
TMB: $009
TMB2 TMB1 TMB0
Input clock selection for free-running timer
TCA initialization for watchdog timer
TMA only applicable for the HD404222 Series.
*
Figure 16 Mode Registers Configuration and Function
HD404202 Series/HD404222 Series
37
Timer B Load Register (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of
an 8-bit write-only timer load register and an 8-bit read-only timer/event counter. Each has a low-order
digit (TCBL: $00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B) (figure 2).
The timer/event counter can be initialized by writing data into timer load register B. In this case, write the
low-order digit first, and then the high-order digit. The timer/event counter is initialized when the high-
order digit is written. The timer load register is initialized to $00 by MCU reset.
The counter value of timer B can be obtained by reading timer counter. In this case, read the high-order
digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when
the high-order digit is read.
HD404202 Series/HD404222 Series
38
Serial Interface
Only applicable for the HD404222 Series.
The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register,
serial mode register, octal counter, and multiplexer, as illustrated in figure 17. Pin D6/SCK and the transmit
clock signal are controlled by the serial mode register. The contents of the serial data register can be
written into or read out by software. The data in the serial data register can be shifted synchronously with
the transmit clock signal.
The STS instruction initiates serial interface operations and resets the octal counter to 000. The counter
starts to count at the falling edge of the transmit clock (SCK) signal and increments by one at the rising
edge of the SCK. When the octal counter is reset to 000 after eight transmit clock signals, or when a
transmit/receive operation is discontinued by resetting the octal counter, the serial interrupt request flag will
be set.
System
clock Prescaler (11 bits)
Serial MPX ÷2 MPX
SMR (4 bits)
Serial mode register
D /SCK
port
6
SCK
OC (3 bits)
Octal counter IFS
SROF
Interrupt
request flag
of serial
interface
Internal bus line (S1)
÷
÷
÷
÷
÷
÷
SR (8 bits)
Serial data register
4
2
344
SCK
SCK
2
8
32
128
512
2048
4
PMR (4 bits)
Port mode register
D /SI
port
7
SI SO
D /SO
port
8
44
Internal bus line (S2)
Internal bus line (S2)
Figure 17 Serial Interface Block Diagram
HD404202 Series/HD404222 Series
39
Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the D6/SCK,
prescaler divide ratio, and transmit clock source as shown in table 21.
A write signal sent to the serial mode register controls the operating state of the serial interface.
The write signal to the serial mode register stops the serial data register and octal counter from using the
transmit clock, and it also resets the octal counter to 000 simultaneously. Therefore, when
serial interface
is in the transfer state, the write signal causes the serial mode register to cease the data transfer and to set
the serial interrupt request flag.
The contents of the serial mode register will be changed on the second instruction cycle after writing into
the serial mode register. Therefore, it is necessary to execute the STS instruction after the data in the serial
mode register has been changed completely. The serial mode register will be reset to $0 by MCU reset.
Table 21 Serial Mode Register
SMR3 D6 /SCK
0 Used as D6 port input/output pin
1 Used as SCK input/output pin
Transmit clock selection
D /SCK pin mode selection
SMR3
SMR: $005
SMR2 SMR1 SMR0
6
Transmit Clock
SMR2 SMR1 SMR0 D6 /SCK Port Clock Source Prescaler Divide
Ratio System Clock
Divide Ratio
000SCK output Prescaler ÷ 2048 ÷ 4096
1SCK output Prescaler ÷ 512 ÷ 1024
10SCK output Prescaler ÷ 128 ÷ 256
1SCK output Prescaler ÷ 32 ÷ 64
100SCK output Prescaler ÷ 8 ÷ 16
1SCK output Prescaler ÷ 2 ÷ 4
10SCK output System clock — ÷ 1
1SCK input External clock — —
HD404202 Series/HD404222 Series
40
Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a low-
order digit (SRL: $006) and a high-order digit (SRU: $007).
The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the
falling edge of the transmit clock signal. At the same time, external data will be input from the SI pin to
the serial data register, to LSB first, synchronously with the rising edge of the transmit clock. Figure 18
shows the I/O timing chart for the transmit clock signal and the data.
The read/write operations of the serial data register should be performed after the completion of data
transmission/reception. Otherwise, the data may not be guaranteed.
LSB MSB
12345678
Transmit
clock
Serial
output
data
Serial input
data
latch timing
Figure 18 Serial Interface I/O Timing
Selecting and Changing the Operation Mode: Table 22 shows the serial interface operation modes which
are determined by a combination of the values in the port mode register and in the serial mode register.
Initialize the serial interface by the write signal to the serial mode register when the operation mode is
changed.
Table 22 Serial Interface Operation Mode
SMR3 PMR1 PMR0 Serial Interface Operating Mode
1 0 0 Clock continuous output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode
HD404202 Series/HD404222 Series
41
Operating State of the Serial Interface: The serial interface has three operating states: the STS waiting
state, transmit clock wait state, and transfer state, as shown in figure 19.
The STS waiting state is the initialization of the serial interface. In this state, the serial interface does not
operate even if the transmit clock is applied.
If the STS instruction is executed, the serial interface shifts to the transmit clock wait state. In this state the
falling edge of the first transmit clock causes the serial interface to shift to the transfer state, in which the
octal counter counts up and the serial data register shifts simultaneously. If clock continuous output mode
is selected, however, the serial interface stays in the transmit clock wait state while the transmit clock
outputs continuously.
The octal counter becomes 000 again after 8 transmit clocks or after the execution of the STS instruction,
so that the serial interface is returned to the transmit clock wait state and the serial interrupt request flag is
set simultaneously.
When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the
STS instruction, and stops after 8 clocks.
Transmit clock wait state
(octal counter = 000)
Transmit clock
8 transmit clocks,
STS instruction
(IFS 1)
←
STS waiting state
octal counter = 000
transmit clock disable Change PMR
Write to
SMR
(IFS 1)
←
STS
instruction
Change PMR
Write to SMR
*
*
*
Change PMR means the change of operation mode as follows.
Clock
continuous
output mode
• Transmit mode
• Receive mode
• Transmit/receive mode
Transfer state
(octal counter 000)≠
Figure 19 Serial Interface Operation States
HD404202 Series/HD404222 Series
42
Transmit Clock Error Detection: The serial interface functions abnormally when the transmit clock is
disturbed by external noise. In this case, transmit clock errors can be detected by the procedure shown in
figure 20.
If more than 8 transmit clocks are applied in the transmit clock wait state, the state of the serial interface
shifts in the following sequence: transfer state, transmit clock wait state, and transfer state again. The serial
interrupt flag should be reset before entering into the STS state by writing data to SMR. This procedure
causes the serial interface request flag to be set again.
Transmit/receive
(IFS 1)
←
Interrupt
disable
IFS 0
←
Write to SMR
IFS = 1?
Normal end
Transmit clock
error processing
Yes
No
Figure 20 Transmit Clock Error Detection
HD404202 Series/HD404222 Series
43
Comparator
Only applicable for the HD404222 Series.
The MCU has two-channel comparators that compare input data with the reference voltage.
Figure 21 shows the comparator block diagram. The comparator block consists of two analog comparators,
the comparator mode register (CMR) which selects the comparator operation, the reference voltage select
register (RSR) which selects the reference voltage, a ladder resistance which generates the internal
reference voltage, and peripheral circuits.
For the COMP0 input, either the external reference voltage or the internal reference voltage, which is
generated by dividing VCC with the internal ladder resistance, can be selected as the reference voltage. For
the COMP1 input, only the external reference voltage is used; the internal reference voltage cannot be
selected.
The power consumption increases after the comparator operation is selected by CMR, because direct
current is constantly supplied to assure the analog comparator characteristics. To reduce the power
consumption during comparator use, the comparator operation should not be selected by software except
when analog comparison is required. In this case, a maximum of two instruction cycles are required after
the comparator operation is selected in order for the analog comparator to stabilize and operate correctly.
Therefore, the comparison result should be read at least two instruction cycles after the comparator
operation is selected.
The comparison result is obtained by executing the TD or TDD instruction. When the analog input voltage
is higher than the reference voltage, a 1 is read as input data from the comparator. The comparator
automatically stops operating in standby and stop modes.
HD404202 Series/HD404222 Series
44
MPX
+
–
Analog
comparator
0
+
–
MPX
RSR CMR
Internal bus
42
3
D /Vref
D /COMP
D /COMP
Analog
comparator
1
VCC
0
1
9
10
11
Figure 21 Comparator Block Diagram
Comparator Mode Register (CMR: $003): This 2-bit register selects the D10/COMP0 and D11/COMP1
functions.
CMR is only affected by the bit manipulation instructions (set by the SEM or SEMD instruction and reset
by the REM or REMD instruction). It is initialized to $0 by MCU reset. Therefore, it becomes
input/output mode after MCU reset.
Reference Voltage Select Register (RSR: $00C): This 4-bit read/write register selects the COMP0
reference voltage for the analog comparator from the eight-level internal voltage or the external voltage. It
is initialized to $0 by MCU reset.
Notes for Use: When using the analog comparator, carefully program the data output instruction and data
input into the port next to COMP0 and COMP1 to assure precise and stabilized comparator operation.
HD404202 Series/HD404222 Series
45
CMR1CMR0
CMR: $003
D /COMP mode selection
D /COMP mode selection
10
11
0
1
Bit 1 Bit 0 D10/COMP0D11/COMP1
00D
10 D11
1 COMP0D11
10D
10 COMP1
1 COMP0COMP1
CMR Mode Selection
Figure 22 Comparator Mode Register
RSR: $00C
Internal reference voltage selection
External/internal reference voltage selection
RSR3 RSR2 RSR1 RSR0
Bit 3 Bit 2 Bit 1 Bit 0 Reference Voltage
0 0 0 0 1/11 VCC
1 2/11 VCC
1 0 3/11 VCC
1 4/11 VCC
1 0 0 5/11 VCC
1 6/11 VCC
1 0 7/11 VCC
1 8/11 VCC
1 — — — External Vref (D9/Vref)
— indicates 0 or 1
RSR
Figure 23 Reference Voltage Select Register
HD404202 Series/HD404222 Series
46
Pins for PROM Mode
VPP (Program Voltage): VPP is the input program voltage (12.5V ±0.3V) for programming the PROM.
CE (Chip Enable): CE input enables programming and verification of the internal PROM.
OE (Output Enable): OE is the data output control signal for verification.
A0–A12 (Address Bus): A0–A12 are address input pins for the internal PROM.
O0–O4 (PROM Data Bus): O0–O4 are the data bus pins for the internal PROM.
HD404202 Series/HD404222 Series
47
PROM Mode Pin Description
Pin No. MCU Mode PROM Mode
DP-28S,
FP-28DA FP-30D Symbol I/O Symbol I/O
1 2 GND GND
23R1
0I/O A5I
34R1
1I/O A6I
45R1
2I/O A7I
56R1
3I/O A8I
67D
0I/O A1I
78D
1I/O A2I
89D
2I/O A3I
910D
3I/O A4I
10 11 D4I/O A0I
11 12 D5
/INT I/O O0I/O
12 13 D6
/SCK I/O O1I/O
13 14 D7
/SI I/O O2I/O
14 15 D8
/SO I/O O3I/O
15 16 D9
/Vref I/O O4I/O
16 17 D1 0
/COMP0I/O CE I
17 18 D11/COMP1I/O OE I
18 19 VCC VCC
19 20 OSC1IV
CC
20 21 OSC2O
21 22 RESET I GND
22 23 TEST I VPP
23 24 D12 I/O VCC
24 25 D13 I/O GND
25 26 R20I/O A9I
26 27 R21I/O A10 I
27 28 R22I/O A11 I
28 29 R23I/O A12 I
HD404202 Series/HD404222 Series
48
Programmable ROM Operation
The HD4074224’s on-chip PROM is programmed in PROM mode.
In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a
standard PROM programmer and a 28-to-28-pin socket adapter as shown in figure 24. Table 23 lists the
recommended PROM programmers and socket adapters.
Since an instruction of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputer
incorporates a conversion circuit to enable the use of a general purpose PROM programmer. By this circuit,
an instruction is read or programmed using 2 addresses, lower 5 bits and upper 5 bits. For example, if 4
kwords of on-chip PROM are programmed by a general purpose PROM programmer, 8 kbytes of addresses
($0000–$1FFF) should be specified.
CE, OE
A12–A0
O4–O0
Control signals
Address bus
Data bus
A14
A13
A12–A0
O4–O0
O7
O6
O5
28-to-28-pin socket adapter PROM programmerHD4074224
VCC
GND
VPP
VCC
GND
VPP
A14–A0
O7–O0
Figure 24 Socket Adapter for the HD4074224
HD404202 Series/HD404222 Series
49
Table 23 PROM Programmer and Socket Adapter
PROM Programmer
Maker Type Name
DATA I/O 29B
UNISITE
AVAL Corp. PKW-1100
PKW-3100
Socket Adapter
Package Type Name Maker
DP-28S HS422ESS01H Hitachi
FP-28DA HS422ESP01H Hitachi
FP-30D HS4224ESF01H Hitachi
Programming and Verification
The HD4074224 can be high-speed programmed without causing voltage stress or affecting data reliability.
Table 24 shows how programming and verification modes are selected.
Table 24 PROM Mode Selection
Pin
Mode CE OE VPP O0–O4
Programming Low High VPP Data input
Verification High Low VPP Data output
Programming inhibited High High VPP High impedance
Precautions
1. Addresses $0000 to $1FFF should be specified if the PROM is programmed by a PROM programmer.
Note that the plastic package type devices cannot be erased and reprogrammed.
2. Be careful that the wrong PROM programmer or socket adapter may cause an overvoltage and damage
the LSI. Make sure that the LSI is firmly fixed onto the socket adapter, and that the socket adapter is
firmly fixed in the programmer.
3. The PROM should be programmed with VPP = 12.5V. Other PROMs use 21V. If 21V is applied to the
HD4074224, the LSI may be permanently damaged. 12.5 V is Intel’s 27256 VPP.
HD404202 Series/HD404222 Series
50
Addressing Modes
RAM Addressing Modes
As shown in figure 25, the MCU has three RAM addressing modes: register indirect addressing, direct
addressing, and memory register addressing.
Register Indirect Addressing: The contents (8 bits) of the X and Y registers are used as the RAM
address.
Direct Addressing: A direct addressing instruction consists of two words, the first word contains the
opcode, the second word (10 bits) is used as the RAM address.
Memory Register Addressing: The memory registers (16 digits from $020 to $02F) are accessed by
executing the LAMR and XMRA instructions.
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes as shown in figure 26.
Direct Addressing Mode: The program can branch to any address in ROM memory by executing the
JMPL, BRL, or CALL instruction. These instructions replace the 12 program counter bits (PC11 to PC0)
with 12-bit immediate data.
Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. The program
can branch to an address on the current page by executing the BR instruction. This instruction replaces the
lower eight bits of the program counter (PC7 to PC0) with 8-bit immediate data.
When the BR instruction falls on a page boundry(256n + 255), executing the Br instruction transfers the PC
contents to the next page (figure 27) according to the hardware architecture. Consequently, the program
branches to the next page when the BR instruction is used on a page boundary. The HMCS400 series cross
macroassembler has an automatic paging facility for ROM pages.
Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page
subroutine area, which is located at $0000–$003F. When the CAL instruction is executed, 6-bits of
immediate data are placed in the low-order six bits of the program counter (PC5 to PC0) and 0s are placed in
the high-order six bits (PC11 to PC6).
Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address
determined by the contents of the 4-bit immediate data, accumulator, and B register.
P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure
28). When bit 8 of the ROM data is 1 (RO8 = 1), 8 bits of ROM data are written into the accumulator and
B register. When bit 9 is 1 (RO9 = 1), 8 bits of ROM data are written into the R1 and R2 port output
registers. When both bits 8 and 9 are 1 (RO8 = 1, RO9 = 1), ROM data are written into the accumulator, B
register, and R1 and R2 port output registers at the same time.
The P instruction has no effect on the program counter.
HD404202 Series/HD404222 Series
51
X register Y register
X
3X
2X
1X
0Y
3Y
2Y
1Y
0
AP
7AP
56 AP
3
AP
4AP
1
AP
2AP
0
AP RAM address
Register Indirect Addressing
First word instruction
Opcode
Second word instruction
d9d8d7d6d5d4d3d2d1d0
AP
7AP
56 AP
3
AP
4AP
1
AP
2AP
0
AP RAM address
Direct Addressing
Instruction
Opcode m3m2m1m0
0010
AP
7AP
56 AP
3
AP
4AP
1
AP
2AP
0
AP RAM address
Memory Register Addressing
d and d should be 0.
98
Figure 25 RAM Addressing Modes
HD404202 Series/HD404222 Series
52
000000
Second word instructionFirst word instruction
[JMPL]
[BRL]
[CALL]
Opcode p3p2p1p0d9d8d7d6d5d4d3d2d1d0
PC11PC10 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
P and P should be 0.
32
Direct Addressing
Instruction
b7b6b5b4b3b2b1b0
Opcode[BR]
PC11PC10 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Current Page Addressing
Instruction
a5a4a3a2a1a0
Opcode[CAL]
PC11PC10 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Zero Page Addressing
Instruction
B register Accumulator
A3A2A1A0
B3B2B1B0
p3p2p1p0
Opcode[TBR]
PC11PC10 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PCProgram counter
Table Data Addressing
Figure 26 ROM Addressing Modes
HD404202 Series/HD404222 Series
53
BR AAA
AAA NOP
BR AAA
BR BBB
BBB NOP
256 (n – 1) + 255
256 n
256 n + 254
256 n + 255
256 (n + 1)
Figure 27 BR Instruction Branch Destination on a Page Boundary
Instruction
p3p2p1p0
Opcode[P] B register Accumulator
A1A0
A2
A3
B1B0
B2
B3
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
Referred ROM address
RO03456789 RORORORORORORORORO 12
ROM data
A0
A1
A2
A3
B0
B1
B2
B3
B register and accumulator
RO03456789 RORORORORORORORORO 12
ROM data
If RO = 1
8
R10
R11
R12
R13
R20
R21
R22
R23
Output registers R2 and R1 If RO = 1
9
Address Designation
Pattern
Figure 28 P Instruction
HD404202 Series/HD404222 Series
54
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +14 V 1
Pin voltage VT–0.3 to VCC + 0.3 V
Total permissible input current ∑Io100 mA 2
Total permissible output current –∑Io30 mA 3
Maximum input current Io30 mA 4, 5
4 mA 4, 6
Maximum output current –Io4mA7
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Notes: 1. Applies to HD4074224.
2. The total permissible input current is the total of input currents simultaneously flowing in from all
I/O pins to GND.
3. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
4. The maximum input current is the maximum current flowing from any I/O pins to GND.
5. Applies to D12, D13, R10 to R13, and R20 to R23.
6. Applies to D0 to D11.
7. The maximum output current is the maximum current flowing from VCC to any I/O pins.
Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
All voltages are with respect to GND.
HD404202 Series/HD404222 Series
55
HD404201, HD404202, HD404222 Electrical Characteristics
DC Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Input high voltage VIH RESET,
INT, SCK*
0.9VCC —V
CC + 0.3 V
SI*0.9VCC —V
CC + 0.3 V
OSC1VCC – 0.5 — VCC + 0.3 V
Input low voltage VIL RESET,
INT, SCK*
–0.3 — 0.2VCC V
SI*–0.3 — 0.2VCC V
OSC1–0.3 — 0.5 V
Output high voltage*VOH SCK, SO VCC – 1.0 — — V –IOH = 1.0 mA
Output low voltage*VOL SCK, SO — — 0.4 V IOL = 0.5 mA
Input/output leakage
current |IIL|RESET,
INT, SCK*,
SI*, SO*,
OSC1
——1 µAV
in = 0 V to VCC 1
Current dissipation in
active mode ICC VCC — — 3.5 mA VCC = 5 V,
fOSC = 4 MHz 2, 5
ICMP*VCC — — 5.5 mA VCC = 5 V,
fOSC = 4 MHz
Comparator active
3, 5
Current dissipation in
standby mode ISBY VCC — — 1.7 mA VCC = 5 V,
fOSC = 4 MHz 4, 5
Current dissipation in
stop mode ISTOP VCC ——10µAV
in(RESET) = VCC – 0.3
V to VCC,
Vin(TEST) = 0 V to 0.3
V
Stop mode retaining
voltage VSTOP VCC 2——V
Notes on next page. * Applies to HD404222.
HD404202 Series/HD404222 Series
56
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Input high voltage*VIHA COMP0,
COMP1
VCref + 0.1 — — V
Input low voltage*VILA COMP0,
COMP1
0—VC
ref – 0.1 V
Comparator input
reference voltage
scope*
VCref Vref 0—V
CC – 1.2 V
Deviation of internal
reference voltage*VOFS — –0.1 — 0.1 V VCC = 4.5 V to 6.0 V 6
Notes: 1. Excluding output buffer current and pull-up MOS current.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:MCU: Reset
Pins: RESET at GND, TEST at GND
D0 to D13, R1, R2 at VCC
3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in
operation.
Test conditions:MCU: Comparator active
Pins: RESET at VCC, TEST at GND
D0 to D8, D12, D13, R1, R2 at VCC
D9 to D11 at GND
4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation.
Test conditions:MCU: I/O same as at reset
Standby mode
Pins: RESET at VCC
TEST at GND
D0 to D13, R1, R2 at VCC
5. Power dissipation is in proportion to fOSC while the MCU is operating or is in standby mode. The
value of the dissipation current when fOSC = x MHz is given by the following equation:
Maximum value (fOSC = x MHz) = x/4 × maximum value (fOSC = 4 MHz)
6. The reference voltage is the expected internal VCref voltage selected by the reference voltage
select register (RSR).
Example: when RSR = $1 reference voltage is 2/11 × VCC.
*Applies to HD404222.
HD404202 Series/HD404222 Series
57
Input/Output Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C )
Item Symbol Pin Min Typ Max Unit Test Condition Note
Input high voltage VIH D0–D13,
R1, R2 0.7VCC —V
CC + 0.3 V
Input low voltage VIL D0–D13,
R1, R2 –0.3 — 0.3VCC V
Output high voltage VOH D0–D13,
R1, R2 VCC – 1.0 — — V –IOH = 1.0 mA 1
Output low voltage VOL D0–D13,
R1, R2 — — 0.4 V IOL = 0.5 mA
D12, D13,
R1, R2 ——2 VI
OL = 15 mA,
VCC = 4.5 V to 6.0 V
Input/output leakage
current |IIL|D
0
–D13,
R1, R2 ——1 µAV
in = 0 V to VCC 2
Pull-up MOS current –IPU D0–D13,
R1, R2 40 80 160 µAV
CC = 5 V,
Vin = 0 V 3
Notes: 1. For I/O pins selected as CMOS output by mask option.
2. Excluding output buffer current and pull-up MOS current.
3. Applies to I/O pins selected as with pull-up MOS by mask option.
HD404202 Series/HD404222 Series
58
AC Characteristics (VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Note
Oscillation frequency fOSC OSC1,
OSC2
1 4 4.5 MHz Ceramic oscillator
1 — 3 MHz Resistor oscillator
Rf = 20 kΩ ±1%
Instruction cycle time tcyc — 0.89 1 4 µs Ceramic oscillator
divided by 4
1.33 — 4 µs Resistor oscillator
divided by 4
Oscillator
stabilization time tRC OSC1,
OSC2
— — 20 ms Ceramic oscillator 1
— — 0.5 ms Resistor oscillator
Capacitance
between pins CRF OSC1,
OSC2
——1 pF
External clock high
and low widths tCPH, tCPL OSC192 — — ns 2
External clock rise
time tCPr OSC1——20ns 2
External clock fall
time tCPf OSC1——20ns 2
INT high width tIH INT 2——t
cyc 3
INT low width tIL INT 2——t
cyc 3
RESET low width tRSTL RESET 2——t
cyc 4
RESET rise time tRSTr RESET ——20ms 4
Input capacitance Cin All pins — — 15 pF f = 1 MHz, Vin = 0 V,
Ta = 25°C
Comparator
stabilization time*tCSTB COMP0——2 t
cyc
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable
voltage (3.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At
power-on or stop mode recovery, RESET must be kept low for at least tRC. Since tRC depends on
the ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscillator
manufacturer when designing the reset circuit.
2. Refer to figure 29.
3. Refer to figure 30.
4. Refer to figure 31.
*Applies to HD404222.
HD404202 Series/HD404222 Series
59
Serial Interface Timing Characteristics (HD404222: VCC = 3.5 V to 6.0 V, GND = 0 V, Ta = –20°C to
+75°C )
During Transmit Clock Output
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle
time tScyc SCK 1——t
cyc Load shown in figure 33 1
Transmit clock high
and low widths tSCKH, tSCKL SCK 0.4 — — tScyc Load shown in figure 33 1
Transmit clock rise
and fall times tSCKr, tSCKf SCK — — 100 ns Load shown in figure 33 1
Serial output data
delay time tDSO SO — — 250 ns Load shown in figure 33 1
Serial input data
setup time tSSI SI 300 — — ns 1
Serial input data hold
time tHSI SI 150 — — ns 1
During Transmit Clock Input
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle
time tScycSCK 1——t
cyc 1
Transmit clock high
and low widths tSCKH, tSCKL SCK 0.4 — — tScyc 1
Transmit clock rise
and fall times tSCKr, tSCKf SCK — — 100 ns 1
Serial output data
delay time tDSO SO — — 250 ns Load shown in figure 33 1
Serial input data
setup time tSSI SI 300 — — ns 1
Serial input data hold
time tHSI SI 150 — — ns 1
Note: 1. Refer to figure 32.
HD404202 Series/HD404222 Series
60
HD40L4201, HD40L4202, HD40L4222 Electrical Characteristics
DC Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Input high voltage VIH RESET,
INT, SCK*
0.9VCC —V
CC + 0.3 V
SI*0.9VCC —V
CC + 0.3 V
OSC1VCC – 0.3 — VCC + 0.3 V
Input low voltage VIL RESET,
INT, SCK*
–0.3 — 0.2VCC V
SI*–0.3 — 0.2VCC V
OSC1–0.3 — 0.3 V
Output high voltage*VOH SCK, SO VCC – 0.5 — — V –IOH = 0.5 mA
Output low voltage*VOL SCK, SO — — 0.4 V IOL = 0.5 mA
Input/output leakage
current |IIL|RESET,
INT, SCK*,
SI*, SO*,
OSC1
——1 µAV
in = 0 V to VCC 1
Current dissipation
in active mode ICC VCC ——1 mAV
CC = 3 V,
fOSC = 1 MHz 2, 5
ICMP*VCC — — 1.6 mA VCC = 3 V,
fOSC = 1 MHz
Comparator active
3, 5
Current dissipation
in standby mode ISBY VCC — — 0.5 mA VCC = 3 V,
fOSC = 1 MHz 4, 5
Current dissipation
in stop mode ISTOP VCC ——10µAV
in(RESET) =
VCC – 0.3 V to VCC,
Vin(TEST) = 0 V to 0.3 V
Stop mode retaining
voltage VSTOP VCC 2——V
Input high voltage*VIHA COMP0,
COMP1
VCref + 0.1 — — V
Input low voltage*VILA COMP0,
COMP1
0—VC
ref – 0.1 V
Comparator input
reference voltage
scope*
VCref Vref 0 — VCC – 1.2 V
Deviation of internal
reference voltage*VOFS — –0.1 — 0.1 V VCC = 4.5 V to 5.5 V 6
HD404202 Series/HD404222 Series
61
Notes: 1. Excluding output buffer current and pull-up MOS current.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:MCU: Reset
Pins: RESET at GND, TEST at GND
D0 to D13, R1, R2 at VCC
3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in
operation.
Test conditions:MCU: Comparator active
Pins: RESET at VCC, TEST at GND
D0 to D8, D12, D13, R1, R2 at VCC
D9 to D11 at GND
4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation.
Test conditions:MCU: I/O same as at reset
Standby mode
Pins: RESET at VCC
TEST at GND
D0 to D13, R1, R2 at VCC
5. Power dissipation is in proportion to fOSC while the MCU is operating or is in standby mode. The
value of the dissipation current when fOSC = x MHz is given by the following equation:
Maximum value (fOSC = x MHz) = x/4 × maximum value (fOSC = 1 MHz)
6. The reference voltage is the expected internal VCref voltage selected by the reference voltage
select register (RSR).
Example: when RSR = $1 reference voltage is 2/11 × VCC.
*Applies to HD40L4222.
HD404202 Series/HD404222 Series
62
Input/Output Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C )
Item Symbol Pin Min Typ Max Unit Test Condition Note
Input high voltage VIH D0–D13,
R1, R2 0.7VCC —V
CC + 0.3 V
Input low voltage VIL D0–D13,
R1, R2 –0.3 — 0.3VCC V
Output high voltage VOH D0–D13,
R1, R2 VCC – 0.5 — — V –IOH = 0.5 mA 1
Output low voltage VOL D0–D13,
R1, R2 — — 0.4 V IOL = 0.4 mA
D12, D13,
R1, R2 ——2 VI
OL = 15 mA,
VCC = 4.5 V to 6.0 V
Input/output leakage
current |IIL|D
0
–D13,
R1, R2 ——1 µAV
in = 0 V to VCC 2
Pull-up MOS current –IPU D0–D13,
R1, R2 10 25 60 µAV
CC = 3 V,
Vin = 0 V 3
Notes: 1. For I/O pins selected as CMOS output by mask option.
2. Excluding output buffer current and pull-up MOS current.
3. Applies to I/O pins selected as with pull-up MOS by mask option.
HD404202 Series/HD404222 Series
63
AC Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Note
Oscillation frequency fOSC OSC1,
OSC2
0.4 1 1.125 MHz Ceramic oscillator
Instructioncycle time tcyc — 3.55 4 10 µs Ceramic oscillator
divided by 4
Oscillator stabilization
time tRC OSC1,
OSC2
— — 20 ms Ceramic oscillator 1
External clock high
and low widths tCPH, tCPL OSC1425 — — ns 2
External clock rise
time tCPr OSC1— — 20 ns 2
External clock fall time tCPf OSC1— — 20 ns 2
INT high width tIH INT 2——t
cyc 3
INT low width tIL INT 2——t
cyc 3
RESET low width tRSTL RESET 2——t
cyc 4
RESET rise time tRSTr RESET — — 20 ms 4
Input capacitance Cin All pins — — 15 pF f = 1 MHz,
Vin = 0 V,
Ta = 25°C
Comparator
stabilization time*tCSTB COMP0——2 t
cyc
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable
voltage (2.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At
power-on or stop mode recovery, RESET must be kept low for at least tRC. Since tRC depends on
the ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscillator
manufacturer when designing the reset circuit.
2. Refer to figure 29.
3. Refer to figure 30.
4. Refer to figure 31.
*Applies to HD40L4222.
HD404202 Series/HD404222 Series
64
Serial Interface Timing Characteristics (VCC = 2.5 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C )
During Transmit Clock Output
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle
time tScyc SCK 1——t
cyc Load shown in figure 33 1
Transmit clock high
and low widths tSCKH, tSCKL SCK 0.4 — — tScyc Load shown in figure 33 1
Transmit clock rise
and fall times tSCKr, tSCKf SCK — — 300 ns Load shown in figure 33 1
Serial output data
delay time tDSO SO — — 600 ns Load shown in figure 33 1
Serial input data setup
time tSSI SI 1000 — — ns 1
Serial input data hold
time tHSI SI 500 — — ns 1
During Transmit Clock Input
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle
time tScyc SCK 1——t
cyc 1
Transmit clock high
and low widths tSCKH, tSCKL SCK 0.4 — — tScyc 1
Transmit clock rise
and fall times tSCKr, tSCKf SCK — — 300 ns 1
Serial output data
delay time tDSO SO — — 600 ns Load shown in figure 33 1
Serial input data setup
time tSSI SI 1000 — — ns 1
Serial input data hold
time tHSI SI 500 — — ns 1
Note: 1. Refer to figure 32.
HD404202 Series/HD404222 Series
65
HD4074224 Electrical Characteristics
DC Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Input high voltage VIH RESET,
SCK, INT
0.9VCC —V
CC + 0.3 V
SI 0.7VCC —V
CC + 0.3 V
OSC1VCC – 0.3 — VCC + 0.3 V 2.7 V ≤ VCC < 3.5 V
VCC – 0.5 — VCC + 0.3 V 3.5 V ≤ VCC ≤ 5.5 V
Input low voltage VIL RESET,
SCK, INT
–0.3 — 0.2VCC V
SI –0.3 — 0.3VCC V
OSC1–0.3 — 0.3 V 2.7 V ≤ VCC < 3.5 V
–0.3 — 0.5 V 3.5 V ≤ VCC ≤ 5.5 V
Output high
voltage VOH SCK, SO VCC – 0.5 — — V 2.7 V ≤ VCC < 3.5 V
– IOH = 0.5 mA
VCC – 1.0 — — V 3.5 V ≤ VCC ≤ 5.5 V
– IOH = 1.0 mA
Output low voltage VOL SCK, SO — — 0.4 V IOL = 0.5 mA
Input/output
leakage current |IIL|RESET,
SCK, INT,
SI, SO, OSC1
——1 µAV
in = 0 V to VCC 1
Current dissipation
in active mode ICC VCC — — 4.2 mA VCC = 5 V, fOSC = 4 MHz 2, 5
——1 mAV
CC = 3 V, fOSC = 1 MHz 2, 5
ICMP VCC — — 6.5 mA VCC = 5 V,
fOSC = 4 MHz,
comparator active
3, 5
— — 1.6 mA VCC = 3 V, fOSC = 1 MHz
comparator active 3, 5
Current dissipation
in standby mode ISBY VCC ——2 mAV
CC = 5 V, fOSC = 4 MHz 4, 5
— — 0.5 mA VCC = 3 V, fOSC = 1 MHz 4, 5
Current dissipation
in stop mode ISTOP VCC ——10µAV
in(RESET) = VCC – 0.3 V
to VCC
Vin(TEST) = 0 V to 0.3 V
Stop mode
retaining voltage VSTOP VCC 2——V
Notes on next page.
HD404202 Series/HD404222 Series
66
Item Symbol Pin Min Typ Max Unit Test Condition Notes
Input high voltage VIHA COMP0,
COMP1
VCref + 0.1 — — V
Input low voltage VILA COMP0,
COMP1
0—VC
ref – 0.1 V
Comparator input
reference voltage
scope
VCref Vref 0—V
CC – 1.2 V
Deviation of
internal reference
voltage
VOFS — –0.1 — 0.1 V VCC = 4.5 V to 5.5 V 6
Notes: 1. Excluding output buffer current and pull-up MOS current.
2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:MCU: Reset
Pins: RESET at GND, TEST at GND
D0 to D13, R1, R2 at VCC
3. ICMP is the source current when no I/O current is flowing while the MCU comparator is in
operation.
Test conditions:MCU: Comparator active
Pins: RESET at VCC, TEST at GND
D0 to D8, D12, D13, R1, R2 at VCC
D9 to D11 at GND
4. ISBY is the source current when no I/O current is flowing while the MCU timer is in operation.
Test conditions:MCU: I/O same as at reset
Standby mode
Pins: RESET at VCC, TEST at GND
D0 to D13, R1, R2 at VCC
5. Power dissipation is in proportion to fOSC while the MCU is operating or is in standby mode.
The value of the dissipation current when fOSC = x MHz is given by the following equation:
Maximum value (fOSC = x MHz) = x/4 × maximum value (fOSC = 4 MHz)
6. The reference voltage is the expected internal VCref voltage selected by the reference voltage
select register (RSR).
Example: When RSR = $1, the reference voltage is 2/11 × VCC.
HD404202 Series/HD404222 Series
67
Input/Output Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Note
Input high voltage VIH D0–D13,
R1, R2 0.7VCC —V
CC + 0.3 V
Input low voltage VIL D0–D13,
R1, R2 –0.3 — 0.3VCC V
Output low voltage VOL D0–D13,
R1, R2 — — 0.4 V IOL = 0.5 mA
D12, D13,
R1, R2 ——2 VI
OL = 15 mA,
VCC = 4.5 V to 5.5 V
Input/output
leakage current |IIL|D
0
–D13,
R1, R2 ——1 µAV
in = 0 V to VCC 1
Pull-up MOS
current –IPU D0–D13,
R1, R2 40 80 160 µAV
CC = 5 V,
Vin = 0 V
10 25 60 µAV
CC = 3 V,
Vin = 0 V
Note: 1. Excluding output buffer current and pull-up MOS current.
HD404202 Series/HD404222 Series
68
AC Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C)
Item Symbol Pin Min Typ Max Unit Test Condition Note
Oscillation frequency
(ceramic oscillator) fOSC OSC1,
OSC2
1 4 4.5 MHz VCC = 3.5 V to 5.5 V
0.4 1 1.125 MHz VCC = 2.7 V to 3.5 V
Instruction cycle time
(ceramic oscillator) tcyc — 0.89 1 4 µsV
CC = 3.5 V to 5.5 V
divided by 4
3.55 4 10 µsV
CC = 2.7 V to 3.5 V
divided by 4
Oscillator stabilization
time(ceramic oscillator) tRC OSC1,
OSC2
— — 20 ms 1
Oscillation frequency
(resistor oscillator) fOSC OSC1,
OSC2
1 — 3 MHz VCC = 3.5 V to 5.5 V
Rf = 20 kΩ ± 1%
Instruction cycle time
(resistor oscillator) tcyc — 1.33 — 4 µsV
CC = 3.5 V to 5.5 V
divided by 4
Oscillator stabilization
time(resistor oscillator) tRC OSC1,
OSC2
— — 0.5 ms VCC = 3.5 V to 5.5 V
Capacitance between
pins CRF OSC1,
OSC2
——1 pFV
CC = 3.5 V to 5.5 V
External clockhigh and
low widths tCPH, tCPL OSC192——nsV
CC = 3.5 V to 5.5 V 2
425 — — ns VCC = 2.7 V to 3.5 V 2
External clock rise time tCPr OSC1— — 20 ns 2
External clock fall time tCPf OSC1— — 20 ns 2
INT high width tIH INT 2 ——t
cyc 3
INT low width tIL INT 2 — — tcyc 3
RESET low width tRSTL RESET 2 ——t
cyc 4
RESET rise time tRSTr RESET — — 20 ms 4
Input capacitance Cin TEST — — 180 pF f = 1 MHz, Vin = 0 V, Ta = 25°C
Others — — 15 pF
Comparator tCSTB COMP0——2 t
cyc stabilization time
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable
voltage (3.5 V) at power-on to when the oscillator stabilizes, or after RESET goes low. At power-
on or stop mode release, RESET must be kept low for at least tRC. Since tRC depends on the
ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscillator
manufacturer when designing the reset circuit.
2. Refer to figure 29.
3. Refer to figure 30.
4. Refer to figure 31.
HD404202 Series/HD404222 Series
69
Serial Interface Timing Characteristics (VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C)
During Transmit Clock Output
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle time tScyc SCK 1——t
cyc Load shown in figure 33 1
Transmit clock high and low
widths tSCKH, tSCKL SCK 0.4 — — tScyc Load shown in figure 33 1
Transmit clock rise and fall
times tSCKr, tSCKf SCK — — 100 ns VCC = 3.5 V to 5.5 V,
load shown in figure 33 1
— — 300 ns VCC = 2.7 V to 3.5 V,
load shown in figure 33 1
Serial output data delay
time tDSO SO — — 250 ns VCC = 3.5 V to 5.5 V,
load shown in figure 33 1
— — 600 ns VCC = 2.7 V to 3.5 V,
load shown in figure 33 1
Serial input data setup time tSSI SI 300 — — ns VCC = 3.5 V to 5.5 V 1
1000 — — ns VCC = 2.7 V to 3.5 V 1
Serial input data hold time tHSI SI 150 — — ns VCC = 3.5 V to 5.5 V 1
500 — — ns VCC = 2.7 V to 3.5 V 1
During Transmit Clock Input
Item Symbol Pin Min Typ Max Unit Test Condition Note
Transmit clock cycle time tScyc SCK 1 ——t
cyc 1
Transmit clock high and low
widths tSCKH,
tSCKL
SCK 0.4 — — tScyc 1
Transmit clock rise and fall times tSCKr, tSCKf SCK — — 100 ns VCC = 3.5 V to 5.5 V 1
— — 300 ns VCC = 2.7 V to 3.5 V 1
Serial output data delay time tDSO SO — — 250 ns VCC = 3.5 V to 5.5 V,
load shown in figure 33 1
— — 600 ns VCC = 2.7 V to 3.5 V,
load shown in figure 33 1
Serial input data setup time tSSI SI 300 — — ns VCC = 3.5 V to 5.5 V 1
1000 — — ns VCC = 2.7 V to 3.5 V 1
Serial input data hold time tHSI SI 150 — — ns VCC = 3.5 V to 5.5 V 1
500 — — ns VCC = 2.7 V to 3.5 V 1
Note: 1. Refer to figure 32.
HD404202 Series/HD404222 Series
70
1/fCP tCPL
tCPH
tCPr tCPf
V – 0.5 V
CC 0.5 V
OSC
1/fCP tCPL
tCPH
tCPr tCPf
V – 0.3 V
CC 0.3 V
HD404201, HD404202, HD404222, HD4074224 (3.5 V V 5.5 V)
HD40L4201, HD40L4202, HD40L4222, HD4074224 (2.7 V V 3.5 V)
1
OSC1
≤CC ≤
≤CC ≤
Figure 29 External Clock Timing
tIH tIL
0.9VCC
0.2VCC
INT
Figure 30 Interrupt Timing
tRSTL
tRSTr
0.9VCC
0.2VCC
RESET
Figure 31 RESET Timing
tSCKL
tScyc
tSCKH
tSCKf tSCKr
tDSO
V – 0.5 V
CC
0.4 V
tSSI tHSI
0.7VCC
0.3VCC
V – 0.5 V (0.9V )
CC CC
0.4 V (0.2V )
CC
SCK
SO
SI
V – 0.5 V and 0.4 V are the threshold voltages for transmit clock output.
0.9V and 0.2V are the threshold voltages for transmit clock input.
CC CC CC
*
*
Note:*
Figure 32 Serial Interface Timing
HD404202 Series/HD404222 Series
71
Test
point
CR
R
L
V
D
D
D
D
CC
D:
R :
R :
C:
1S2074
2.6 k
12 k
30 pF
LΩ
Ω
1
1
H
Figure 33 Timing Load Circuit
HD404202 Series/HD404222 Series
72
Electrical Characteristics (Reference data)
R
f
= 20 kΩ
Ta = –20 to 75°
min.
0.0
1.0
2.0
3.0
4.0
3.0 4.0 5.0 6.0 7.0
V
CC
(V)
Resistor oscillator characteristics (1)
Oscillator frequency v.s. V
CC
(R
f
= 20 kΩ)
Oscillation frequency (MHz)
max.
V
CC
= 5.0 V
Ta = –20 to 75°
4
3
2
1
0
Oscillation frequency (MHz)
min.
max.
010 20 30 40 50
R
f
(k )
Resistor oscillator characteristics (2)
Oscillator frequency v.s. R
f
(V
CC
= 5.0 V)
4
3
2
1
0
Oscillation frequency (MHz)
min.
max.
010 20 30 40 50
Resistor oscillator characteristics (3)
Oscillator frequency v.s. R
f
(V
CC
= 3.5 V)
4
3
2
1
0
Oscillation frequency (MHz)
min.
max.
010 20 30 40 50
Resistor oscillator characteristics (4)
Oscillator frequency v.s. R
f
(V
CC
= 6.0 V)
V
CC
= 6.0 V
Ta = –20 to 75°
V
CC
= 3.5 V
Ta = –20 to 75°
Ω
R
f
(k )ΩR
f
(k )Ω
HD404202 Series/HD404222 Series
73
Notes On ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as 2-kword versions
(HD404202, HD40L4202). A 2-kword data size is required to change ROM data to mask manufacturing
data since the program used is for a 2-kword version.
This limitation apply to the case of using EPROM and the case of using data base.
Fill this area with all 1s
Vector address
Zero-page subroutine
(64 words)
Pattern and program
(2048 words)
Not used
ROM 2 kwords version:
HD404201, HD40L4201
Address $0800 to $0FFF
$0000
$0009
$000A
$003F
$0040
$03FF
$0400
$07FF
HD404202 Series/HD404222 Series
74
HD404201/HD40L4201/HD404202/HD40L4202 Option List
Please check off the appropriate applications and enter the necessary information.
1. ROM Size
5-V operation: HD404201
Low-voltage operation: HD40L4201
2. I/O Options
Pin name ABC
I/O option
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input)
4. System Oscillator (OSC1 and OSC2)
External clock
Resistor
Ceramic oscillator
External clock
Ceramic oscillator
HD404201/HD404202 HD40L4201/HD40L4202
3. ROM Code Media
EPROM:
5-V operation: HD404202
Low-voltage operation: HD40L4202
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
Order date
Customer name
Department
Name
ROM code name
LSI type name
5. Stop Mode
Used
Not used
1-kword
2-kword
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin name ABC
I/O option
D11
D12
D13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R10
R11
R12
R13
R20
R21
R22
R23
R1
R2
Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTAT
TM
version).
f = MHz
f = MHz
f = MHz
f = MHz
f = MHz
6. Package
DP-28S
FP-28DA
FP-30D
HD404202 Series/HD404222 Series
75
HD404222/HD40L4222 Option List
Please check off the appropriate applications and enter the necessary information.
5-V operation: HD404222
Low-voltage operation: HD40L4222
Order date
Customer name
Department
Name
ROM code name
LSI type name
5. Timer A
Free-running timer operation
Watchdog timer operation
1. ROM Size
2. I/O Options
Pin name ABC
I/O option
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin name ABC
I/O option
D11
D12
D13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R10
R11
R12
R13
R20
R21
R22
R23
R1
R2
4. System Oscillator (OSC1 and OSC2)
External clock
Resistor
Ceramic oscillator
External clock
Ceramic oscillator
HD404222 HD40L4222
3. ROM Code Media
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
6. Stop Mode
Used
Not used
Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTAT
TM
version).
f = MHz
f = MHz
f = MHz
f = MHz
f = MHz
7. Package
DP-28S
FP-28DA
FP-30D
H43
××
Family
HD404304 Series
Rev. 5.0
March 1997
Description
The HD404304 Series is a CMOS 4-bit single-chip microcomputer basically equivalent to the HMCS400
series, providing high programming productivity, high speed operation, and low power dissipation. It
incorporates ROM, RAM, I/O, A/D converter, two timer/counters, including high voltage I/O pins to drive
fluorescent display tubes directly.
The HD404304 Series includes three chips: the HD404302R with 2 k-word ROM, the HD404304 wit h 4 k-
word ROM and the HD4074308 with 8 k-word PROM. The HD4074308, which includes PROM, is
ZTAT microcomputer that can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The PROM program specifications are the same as for the 27256.)
ZTAT: Zero Turn Around Time ZTAT is a Trademark of Hitachi Ltd.
Features
• 2048-word × 10-bit ROM (mask ROM version, HD404302R)
4096-word × 10-bit ROM (HD404304)
8192-word × 10-bit PROM (ZTAT version)
• 160-digit × 4-bit RAM
• 33 I/O pins, including 25 high-voltage I/O pins (40 V max.)
• Two timer/counters
11-bit prescaler
8-bit timer (free-running timer/watchdog timer)
8-bit timer (auto-reload timer/event counter)
• Five interrupt sources
Two by external sources
Two by timer/counters
One by A/D converter
• 4-channel × 8-bit A/D converter
• Two tone generator outputs
• Subroutine stack, up to 16 levels including interrupts
HD404304 Series
2
• Two low-power dissipation modes
Standby mode
Stop mode
• On-chip oscillator
Crystal or ceramic oscillator
External clock
• Package
42-pin plastic DIP (DP-42)
42-pin ceramic DIP with window (DC-42)*
42-pin plastic shrink DIP (DP-42S)
54-pin flat plastic package (FP-54)
• Instruction cycle time: 2 µs (fOSC = 4 MHz)
Note: * Available as a sample
Ordering Information
Type Product Name Model Name ROM (Words) Package
Mask ROM HD404302R HD404302RP 2,048 DP-42
HD404302RS DP-42S
HD404302RF FP-54
HD404304 HD404304P 4,096 DP-42
HD404304S DP-42S
HD404304F FP-54
ZTATHD4074308 HD4074308P 8,192 DP-42
HD4074308S DP-42S
HD4074308C*DC-42*
HD4074308F FP-54
Note: *Available as a sample
HD404304 Series
3
Pin Arrangement
NC
NC
NC
D4
D3
D2
D1
D0
V
CC
OSC
2
OSC
1
TEST
RESET
AV
SS
NC
NC
NC
NC
NC
NC
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
NC
NC
NC
R0
0
V
disp
/RA
1
TG
1
/D
12
TG
0
/D
11
D
10
D
9
D
8
D
7
D
6
D
5
R3
0
R3
1
R3
2
/INT
0
R3
3
/INT
1
GND
AV
CC
R4
0
/AN
0
R4
1
/AN
1
R4
2
/AN
2
R4
3
/AN
3
FP-54
DP-42
DP-42S
DC-42
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
V
CC
OSC
2
OSC
1
TEST
RESET
AV
SS
R4
3
/AN
3
R4
2
/AN
2
R4
1
/AN
1
R4
0
/AN
0
AV
CC
D
10
TG
0
/D
11
TG
1
/D
12
V
disp
/RA
1
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
R3
0
R3
1
INT
0
/R3
2
INT
1
/R3
3
GND
Top view
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
5
4
3
2
1
54
53
52
51
50
23
24
25
26
27
28
29
30
31
32
HD404304 Series
4
Pin Description
Pin Number
DP-42, DP-42S,DC-42 FP-54 Pin Name I/O
11 D
10 I/O
22 D
11/TG0I/O
33 D
12/TG1I
44 RA
1
/Vdisp I
55 R0
0I/O
69 R0
1I/O
710R0
2I/O
811R0
3I/O
912R1
0I/O
10 13 R11I/O
11 14 R12I/O
12 15 R13I/O
13 16 R20I/O
14 17 R21I/O
15 18 R22I/O
16 19 R23I/O
17 23 R30I/O
18 24 R31I/O
19 25 R32/INT0I/O
20 26 R33/INT1I/O
21 27 GND
22 28 AVCC
23 29 R40/AN0I/O
24 30 R41/AN1I/O
25 31 R42/AN2I/O
26 32 R43/AN3I/O
27 36 AVSS
28 37 RESET I
29 38 TEST I
30 39 OSC1I
31 40 OSC2O
32 41 VCC
33 42 D0I/O
HD404304 Series
5
Pin Number
DP-42, DP-42S, DC-42 FP-54 Pin Name I/O
34 43 D1I/O
35 44 D2I/O
36 45 D3I/O
37 46 D4I/O
38 50 D5I/O
39 51 D6I/O
40 52 D7I/O
41 53 D8I/O
42 54 D9I/O
—6 NC
—7 NC
—8 NC
—20NC
—21NC
—22NC
—33NC
—34NC
—35NC
—47NC
—48NC
—49NC
NC: No connection
HD404304 Series
6
Pin Functions
Power Supply
VCC: Apply power supply voltage to this pin.
GND: Connect to ground.
Vdisp: This pin, multiplexed with RA1, is for the power supply of the high-voltage output pins with a
maximum voltage of VCC – 40 V. For details, see the Input/Output section.
AVCC, AVSS: Power supply pins for the A/D converter.
TEST: Non-user pin. Connect this pin to VCC.
RESET: MCU reset pin. For details, see the Reset section.
Oscillators
OSC1, OSC2: Input/output pins for the internal oscillator circuit. They can be connected to a crystal,
ceramic, or external oscillator circuit. For details, see the Internal Oscillator Circuit section.
Ports
D0 to D 12 (D Port): Input/output port addressed by its bits. These 13 pins are all high-voltage input/output
pins. The circuit type for each pin can be selected using a mask option. For details, see the Input/Output
section.
R00 to R0 3, R10 to R13, R20 to R23, R30 to R33, R4 0 to R43, RA1 (R Ports): R0 to R4 are 4-bit I/O ports.
RA is a 1-bit input-only port. The pins of R0 to R2 and RA1 are high-voltage pins, and the pins of R3 to R4
are standard pins. R32 and R33 are multiplexed with INT0 and INT1, respectively. For details, see the
Input/Output section.
Interrupts
INT0, INT1: External interrupt pins. INT1 can be used as an external event input pin for timer B. INT0 and
INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section.
Tone Generator
TG0, TG1: Tone generator output pins. These pins are high-voltage pins multiplexed with D11 and D12,
respectively.
HD404304 Series
7
A/D Converter
AN0 to AN3 (AN Port): A/D converter input port. AN0 to AN3 are multiplexed with R40 to R43,
respectively. For details, see the A/D Converter section.
Block Diagram
indicates
high voltage
pins.
Timer A/
watchdog
Timer
B
Interrupt control
160 × 4-bit RAM
(ZTAT™ and mask ROM versions)
System control
SP
ALU
2048 × 10-bit (HD404302R)
4096 × 10-bit (HD404304)
8192 × 10-bit (HD4074308)
ROM
ST
D port
CA A B PC
R0R1R2RA
R3
R4
WX Y
SPYSPX
A/D Pulse
gen-
erator
External
interrupt
Instruction
decoder
GND
VCC
OSC2
OSC1
TEST
RESET
R32/INT0
R33/INT1
D11/TG0
D12/TG1
AVSS
AVCC
AN3/R43
AN2/R42
AN1/R41
AN0/R40
INT1/R33
INT0/R32
R31
R30
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11/TG0
D12/TG1
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
RA1/Vdisp
HD404304 Series
8
Memory Map
ROM Memory Map
The ROM is described in the following paragraphs with the ROM memory map in figure 1.
Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL
instructions to branch to the starting address of the initialization program and the interrupt programs. After
a reset or an interrupt, program execution continues from the vector address.
Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for
subroutines. The CAL instruction branches to these subroutines.
Pattern Area ($0000 to $07FF: HD404302R; $0000 to $0FFF: HD404304, HD4074308): Locations
$0000 through $07FF or $0FFF are reserved for ROM data. The P instruction allows reference to ROM
data as a pattern.
Program Area ($0000 to $07FF: HD404302R; $0000 to $0FFF: HD404304; $0000 to $1FFF:
HD4074308): Locations from $0000 to $1FFF can be used for program code.
0
15
16
63
64
2047
2048
4095
4096
8191
8192
16383
$0000
$000F
$0010
$07FF
$0800
$0FFF
$1000
$1FFF
$2000
$3FFF
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to reset routine)
JMPL instruction
(jump to INT0 routine)
JMPL instruction
(jump to INT1 routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to A/D routine)
Vector address
Zero-page subroutine
(64 words)
Program pattern
(2048 words)
For HD404302R
Program pattern
(4096 words)
For HD404304
Program
(8192 words)
For HD4074308
Not used
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
$003F
$0040
Figure 1 ROM Memory Map
HD404304 Series
9
RAM Memory Map
The MCU contains a 160-digit × 4-bit RAM as the data and stack area. In addition to these areas, interrupt
control bits and special function registers are also mapped on the RAM memory space. The RAM memory
map (figure 2) is described in the following paragraphs.
$000
$03F
$040
0
1023
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$01F
$020
$021
$022
$023
$024
$032
$033
$034
$035
$03F
31
32
35
36
50
51
52
53
63
$04F
$050
$09F
$0A0
$3BF
$3C0
$3FF
Interrupt control bits area
Port mode register A
Port mode register B
Timer mode register A
Timer mode register B
A/D mode register
A/D data register lower
A/D data register upper
A/D port select register
Port R3 DCR
Port R4 DCR
(PMRA)
(PMRB)
(TMA)
(TMB)
(TCBL/TLRL)
(TCBU/TLRU)
(AMR)
(ADRL)
(ADRU)
(ADPR)
(DCR3)
(DCR4)
W
W
W
W
R/W
R/W
W
R
R
W
W
W
Not used
Not used
* Timer B
Not used
Special flag bits area
Not used
Not used
RAM-mapped registers
Memory registers (MR)
(16 digits)
Data (80 digits)
Not used
Stack (64 digits)
Notes: * Two registers are mapped on
the same address.
TCBL:
TCBU:
TLRL:
TLRU:
W:
R:
R/W:
Timer counter B lower
Timer counter B upper
Timer load register B lower
Timer load registr B upper
Write only
Read only
Read/Write
Figure 2 RAM Memory Map
HD404304 Series
10
Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.
Bit 3 Bit 2 Bit 1 Bit 0
0
1
2
3
$000
$001
$002
$003
IM0
(IM of INT0)
IMTA
(IM of timer A)
Not used
IF0
(IF of INT0)
IFTA
(IF of timer A)
Not used
RSP
(Reset SP bit)
IM1
(IM of INT1)
IMTB
(IM of timer B)
IE
(Interrupt enable flag)
IF1
(IF of INT1)
IFTB
(IF of timer B)
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Note: Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, reset by the
REM/REMD instruction, and tested by the TM/TMD instruction. Other instructions have no
effect. Furthermore, the interrupt request flag is not affected by the SEM/SEMD instruction.
The contents of the status flag become invalid when unusable bits and the RSP bit are
tested by the TM or TMD instruction.
IMAD
(IM of A/D)
Not used Not used
IFAD
(IF of A/D)
Bit 3 Bit 2 Bit 1 Bit 0
32 $020
$021
$022
$023
Not used
Reserved
WDON
(Watchdog on flag) ADSF
(A/D start flag)
Not used
Note: The WDON flag can be used by the SEM/SEMD instruction, and reset by MCU reset.
ADSF stays high during A/D conversion and becomes low after A/D conversion.
Figure 3 Configuration of Interrupt Control Bits Area
HD404304 Series
11
Special Function Registers Area ($004 to $034): The special function registers are the mode or data
registers for external interrupt, A/D conversion, and the timer/counters, and are the I/O port data control
registers. These registers are classified into three types: write-only, read-only, and read/write as shown in
figure 2. These registers cannot be accessed by RAM bit manipulation instructions. However, WDON
($020) can be accessed only by those bit instructions.
Data Area ($040 to $09F): The 16 digits of $040 through $04F are called memory registers (MR) and are
accessible by the LAMR and XMRA instructions (figure 4).
Memory registers
MR (0)
MR (1)
MR (2)
MR (3)
MR (4)
MR (5)
MR (6)
MR (7)
MR (8)
MR (9)
MR (10)
MR (11)
MR (12)
MR (13)
MR (14)
MR (15)
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
960
1023
$3C0
$3FF
Bit 3 Bit 2 Bit 1 Bit 0
ST PC11
PC10 PC9 PC8 PC7
CA PC6 PC5 PC4
PC3 PC2 PC1 PC0
1020
1021
1022
1023
$3FC
$3FD
$3FE
$3FF
PC13 PC12
PC13 to PC0: Program counter
ST: Status flag
CA: Carry flag
Notes: 1.
2.
3.
Since the HD404302R has a 2-kword ROM, PC11, PC12, and PC13 are not used.
Since the HD404304 has a 4-kword ROM, PC12 and PC13 are not used.
Since the HD4074308 has a 8-kword ROM, PC13 is not used.
Figure 4 Configuration of Memory Registers, Stack Area, amd Stack Position
Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for the stack area to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL and
CALL instructions) and interrupts are processed. This area can be used as a 16-level nesting stack in which
one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by the RTN
and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This area,
when not used as a stack, is available as a data area.
HD404304 Series
12
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. The following paragraphs describe the
registers and flags shown in figure 5 in detail.
CA Carry flag
ST Status flag
PC Program counter
013
Stack pointer
0
111 59 SP
SPY SPY register
03
SPX SPX register
03
Y Y register
03
X X register
03
B B register
03
A Accumulator
03
W W register
01
1
Figure 5 Registers and Flags
Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the
arithmetic logic unit (ALU) as well as the transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): The 2-bit W register and the 4-bit X and Y registers
indirectly address the RAM. The Y register is also used for D-port addressing.
SPX Register (SPX), SPY Register (SPY): The 4-bit SPX and SPY registers are used to assist the X and
Y registers, respectively.
HD404304 Series
13
Carry Flag (CA): The carry flag (CA) indicates an overflow generated from the ALU during arithmetic
operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the
stack during an interrupt, and popped off the stack by the RTNI instruction. This flag is not affected by the
RTN instruction.
Status Flag (ST): The status flag (ST) indicates an ALU overflow and ALU non-zero during arithmetic or
compare instructions, and the result of a bit test instruction. Moreover, the status flag controls branching
caused by the BR, BRL, CAL, or CALL instruction. Whether these instructions are executed or skipped,
the status flag is always set to 1. The state of this flag remains unchanged until the next arithmetic,
compare, bit test, or branch instruction is executed. During an interrupt, ST is pushed onto the stack, and
popped off the stack by the RTNI instruction. This flag is not affected by the RTN instruction.
Program Counter (PC): The program counter is a 14-bit binary counter which holds the address of the
next program instruction to be executed.
Stack Pointer (SP): The stack pointer (SP) is a 10-bit register which indicates the next stack address. This
pointer, which is initialized to $3FF, is decremented by 4 when data is pushed onto the stack, and is
incremented by 4 when data is popped off the stack. The highest four bits are fixed to 1111, which allows
the pointer to indicate up to 16 levels of subroutines. The stack pointer is initialized when the MCU is reset
or the RSP bit ($000, bit 1) is reset by the REM or REMD instruction.
Interrupts
Five interrupt sources are available on the MCU: external requests ( INT0, INT1), timer/counters (timer A,
timer B), and A/D. For each source, the interrupt request flag (IF), interrupt mask (IM), and interrupt vector
addresses are provided to control and maintain the interrupt request. The interrupt enable flag (IE) is also
used to control interrupt operations.
Interrupt Control Bits and Interrupt Service: The interrupt control bits are mapped on $000 through
$003 of the RAM space. They are accessible by RAM bit manipulation instructions. However, the interrupt
request flag (IF) cannot be set by software. The interrupt enable flag (IE) and IF are cleared to 0, and the
interrupt mask (IM) is set to 1 after MCU reset.
Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector
addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source. The interrupt
request is generated when the IF is set to 1 and IM is 0. If the IE is 1 at this time, the interrupt will be
activated and vector addresses will be generated from the priority PLA corresponding to the interrupt
sources.
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is re-executed, after jumping to the vector address.
At each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF which caused the interrupt must be reset by software in the interrupt program.
HD404304 Series
14
Table 1 Vector Addresses and Interrupt Priority
Reset/Interrupt Priority Vector Addresses
RESET — $0000
INT01 $0002
INT12 $0004
Timer A 3 $0006
Timer B 4 $0008
A/D 5 $000A
Table 2 Interrupt Conditions
Interrupt Control Bit INT0INT1Timer A Timer B A/D
IE 11111
IF0 IM0 10000
IF1 IM1 *1000
IFTA IMTA **100
IFTB IMTB ***10
IFAD IMAD ****1
Note: *Don’t care
HD404304 Series
15
$000,0
IE
$000,2
IF0
$000,3
IM0
$001,0
IF1
$001,1
IM1
$001,2
IFTA
$001,3
IMTA
$002,0
IFTB
$002,1
IMTB
$002,2
IFAD
$002,3
IMAD
Note: $m, n is RAM address $m, bit number n.
Vector
address
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector address
Priority control
logic
Figure 6 Interrupt Control Circuit Block Diagram
HD404304 Series
16
Instruction cycles
123456
Instruction
execution*
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note: *The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Stacking
Figure 7 Interrupt Processing Sequence
HD404304 Series
17
Yes
No
(A/D interrupt)
Yes
No
Yes
PC ← $0002
PC ← $0004
PC ← $0006
PC ← $0008
IE ← 0
INT
0
interrupt?
Timer A
interrupt?
No
Accept interrupt
Power on
IE = 1?
PC ← (PC) + 1
Execute instruction
Interrupt
request?
Yes
No
Yes
No
RESET = 1?
Reset MCU
Yes
No
Yes
PC ← $000A
Timer B
interrupt?
No
INT
1
interrupt?
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
Figure 8 Interrupt Processing Flowchart
HD404304 Series
18
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests. It is
reset by an interrupt and set by the RTNI instruction.
External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by
port mode register A (PMRA: $004) (figure 10).
The external interrupt request flags (IF0, IF1) are set at the falling edge of I NT0 and I NT1 inputs,
respectively.
The INT1 input can be used as a clock signal input to time B. Timer B is incremented at each falling edge
of the INT1. When using INT1 as the timer B external event input, the external interrupt mask (IM1) must
be set so that the interrupt request by INT1 will not be accepted. Figure 9 shows the interrupt mode register.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) (figure 9) are set at the falling edge of the INT0 and INT1 inputs, respectively.
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt mask bits (figure
9) mask an interrupt request caused by the external interrupt request flags.
Port Mode Register A (PMRA: $004): Port mode register A is a 4-bit write-only register which controls
the R32/INT0 pin and R33/INT1 pin as shown in figure 10. Port mode register A will be initialized to $0 by
MCU reset.
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag (figure 9) is set
when an overflow occurs in timer A.
Timer A Interrupt Mask (IMTA: 001, Bit 3): The timer A interrupt mask bit (figure 9) masks an
interrupt request caused by the timer A interrupt request flag.
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag (figure 9) is set
when an overflow occurs in timer B.
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask bit (figure 9) masks an
interrupt request caused by the timer B interrupt request flag.
A/D Interrupt Request Flag (IFAD: $002, Bit 2): The A/D interrupt request flag (figure 9) is set when an
A/D conversion is completed.
A/D Interrupt Mask (IMAD: $002, Bit 3): The A/D interrupt mask bit (figure 9) masks an interrupt
request caused by the A/D interrupt request flag.
HD404304 Series
19
Bit 3 Bit 2 Bit 1 Bit 0
RSP
: $000
Interrupt enable flag
INT0 interrupt request flag
INT0 interrupt mask
IE
IF0
IM0
0
1
0
1
0
1
Disabled
Enabled
No interrupt request
Interrupt requested
Interrupt request enabled
Interrupt request masked
Bit 3 Bit 2 Bit 1 Bit 0 : $001
INT1 interrupt request flag
INT1 interrupt mask
Timer A interrupt mask
Timer A interrupt request flag
Bit 3 Bit 2 Bit 1 Bit 0 : $002
Timer B interrupt request flag
Timer B interrupt mask
A/D interrupt mask
A/D interrupt request flag
0
1
0
1
0
1
0
1
Interrupt request
No
Yes
Enabled
Disabled (masked)
No
Yes
Enabled
Disabled (masked)
IF1
IM1
IFTA
IMTA
Interrupt request
No
Yes
Enabled
Disabled (masked)
No
Yes
Enabled
Disabled (masked)
0
1
0
1
0
1
0
1
IFTB
IMTB
IFAD
IMAD
Figure 9 Interrupt Control Bits
Bit 3 Bit 2 Bit 1 Bit 0 Port mode register A (PMRA: $004)
Not used
Bit 2
Bit 3
0
1
0
1
R32 I/O pin
INT0 input pin
R33 I/O pin
INT1 input pin
Figure 10 Port Mode Register A
HD404304 Series
20
Timers
The MCU contains a prescaler and two timer/counters (timers A and B) as shown by the block diagram in
figure 11.
Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $000 by
MCU reset or by setting bit 3 of timer mode register A (TMA: $008) when the watchdog timer on flag
(WDON: $020, bit 1) is 0, after which the prescaler starts to divide the system clock. It continues operation
until MCU reset or stop mode occurs.
The pulse frequency of timer A input clock, timer B input clock, and the tone generator outputs (TG0, TG1)
are selected among prescaler outputs by timer mode register A (TMA: $008), timer mode register B (TMB:
$009), and port mode register B (PMRB: $005), respectively.
After MCU reset, WDON is 0. Thus, when timer A is reset by setting bit 3 of timer mode register A (TMA)
when the watchdog timer is off, the prescaler is also reset, which affects the operation of timer B and the
tone generator outputs (TG0, TG1). Consequently, the program should control these conditions.
Timer A Operation: Timer A is an 8-bit interval timer which can be used also as a watchdog timer. The
prescaler divide ratio of timer A is selected by timer mode register A (TMA: $008).
After timer A is initialized to $00 by MCU reset or setting bit 3 of timer mode register A (TMA: $008), it is
incremented at every clock input signal. Eight different clock signals, divided by the prescaler, can be used
as an input clock. The clock input signals to timer A are selected by timer mode register A. When the next
clock signal is applied after timer A becomes $FF, an overflow is generated and timer A is reset to $00.
This overflow causes the timer A interrupt request flag (IFTA $001, bit 2) to go to 1.
This timer can function as a watchdog timer to detect a runaway program. The MCU is reset when an
overflow output is generated from a timer counter that cannot be controlled due to a runaway program
while the watchdog timer on flag (WDON) is 1.
Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function input clock
source, and the prescaler divide ratio for timer B. When an external event input is used as an input clock
signal to timer B, select R33/INT1 as I NT1 by setting port mode register A (PMRA: $004), and set the
external interrupt mask (IM1) to prevent an external interrupt request from occurring.
Timer B is initialized according to data written into timer load register B by software. Timer B is
incremented at every clock input signal. When the next clock signal is applied to timer B after it is set to
$FF, it will generate an overflow output. In this case, if the auto-reload function is selected, timer B is
initialized according to the value of timer load register B. If it is not selected, timer B is reset to $00. The
timer B interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output.
HD404304 Series
21
WDON
IFTA
Interrupt
request flag
of timer A
Watchdog timer on flag
System
reset
Timer coutner A (8 bits)
System
reset
22
4
4
4
44
8
MPX TG0
TG1
TBOF IFTB
Interrupt
request flag
of timer B
Internal bus line (S1)
TL (4 bits)
Timer latch register
TCB (8 bits)
Timer counter B
TLR (8 bits)
Timer load register B
Internal bus line (S2)
Timer mode
register A
Timer A MPX
Prescaler (11 bits)
System
clock
Timer B MPX
Timer mode
register B
INT1
3
÷1024
÷512
÷256
÷128
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
PMRB
3
Figure 11 Timers A and B Block Diagram
HD404304 Series
22
Timer Mode Register A (TMA: $008): Timer mode register A is a 4-bit write-only register. Bits 0 to 2 of
TMA control the prescaler divide ratio of the timer counter A clock input, as shown in figure 12. Bit 3
resets timer A when set to 1; if WDON = 0, the prescaler is also reset. Bit 3 retains a 1 for only one
instruction cycle.
Timer mode register A can be modified from the second instruction cycle of the write instruction.
Bit 3 Bit 2 Bit 1 Bit 0
Timer mode register A (TMA: $008)
Bit 1 Bit 0
0
1
0
1
Prescaler divide ratio
Bit 2 0
1
0
1
0
1
0
1
0
1
÷2048
÷1024
÷512
÷128
÷32
÷8
÷4
÷2
Special flag bit ($020)
Bit 3
0
0
1
1
Function
WDON
0
1
0
1
Not changed
Timer counter A and prescaler
are reset
Timer counter A is reset
WDON
ADSF
: Not used
: Watchdog on flag
: A/D start fla
g
WDON
ADSF
Figure 12 Timer Mode Register A Configuration
Timer Mode Register B (TMB: $009): Timer mode register B is a 4-bit write-only register which selects
the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in
figure 13. Timer mode register B is initialized to $0 by MCU reset.
The operation mode of timer B can be modified from the second instruction cycle after timer mode register
B is written to. The initialization of timer B by a write to the timer load register should be performed after
the contents of timer mode register B have been appropriately changed.
HD404304 Series
23
Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit write-
only timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL:
$00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B).
Timer counter B can be initialized by writing data into timer load register B. In this case, write the low-
order digit first, and then the high-order digit. The timer counter is initialized when the high-order digit is
written. The timer load register is initialized to $00 by MCU reset.
The counter value of timer B can be obtained by reading time counter B. In this case, read the high-order
digit first, and then the low-order digit. The count value of the low-order digit is latched when the high-
order digit is read.
Bit 3 Bit 2 Bit 1 Bit 0
Timer mode register B (TMB: $009)
Bit 1 Bit 0
0
1
0
1
Prescaler divide ratio
input clock source
Bit 2
0
1
0
1
0
1
0
1
0
1
÷2048
÷512
÷128
÷32
÷8
÷4
÷2
INT1 (external event
input)
Bit 3 0
1No auto-reload function
Auto-reload function provided
Figure 13 Timer Mode Register B Configuration
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag (figure 14) is set
by the overflow output of timer A. When the watchdog timer function is selected, the timer interrupt
request flag is not set since the MCU is reset by an overflow output.
Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask (figure 14) prevents an
interrupt request from being generated by the timer A interrupt request flag.
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag (figure 14) is set
by the overflow output of timer B.
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask (figure 14) prevents an
interrupt request from being generated by the timer B interrupt request flag.
HD404304 Series
24
IMTA IFTA — — : $001
IFTA
IMTA
0
1
0
1
Timer A interrupt request disabled
Timer A interrupt request enabled
Timer A interrupt request accepted
Timer A interrupt request masked
— — IMTB IFTB : $002
IFTB
IMTB
0
1
0
1
Timer B interrupt request disabled
Timer B interrupt request enabled
Timer B interrupt request accepted
Timer B interrupt request masked
—: Other interrupt control bit
Figure 14 Timer Interrupt Control Bits
HD404304 Series
25
A/D Converter
The HD404302R, HD404304, and HD4074308 incorporate a sequential comparison system A/D converter
consisting of a resistor ladder. It can measure four analog inputs with 8-bit resolution. Figure 15 shows the
A/D converter block diagram. The A/D converter consists of the following registers:
• A/D mode register (4 bits)
• A/D start flag (1 bit)
• A/D port select register (4 bits)
• A/D data register (4 bits + 4 bits)
4 2 2
Internal bus
ADSF: $020 ADRL: $00D
ADRU: $00E
A/D data
register (ADR)
IFAD
A/D interrupt
request flag
Counter
Control logic
+
–
COMP
D/A
MPX
AMR: $00CADPR: $00F
A/D start flag
(ADSF)
A/D mode
register (AMR)
A/D port select
register (ADPR)
R40/AN0
R41/AN1
R42/AN2
R43/AN3
AVCC
AVSS
Figure 15 A/D Converter Block Diagram
A/D Mode Register (AMR: $00C): The A/D mode register (figure 16) is a 4-bit write-only register which
selects the A/D conversion speed (bit 0, bit 1) and analog input channel (bit 2, bit 3).
A/D Start Flag (ADSF: $020, Bit 0): A/D conversion is started when a 1 is written to the A/D start flag
(figure 16). After a conversion is completed, the conversion data is set in the A/D data register and the A/D
start flag is cleared simultaneously.
Note that the bit manipulation instruction SEM or SEMD should be used to write data to ADSF. During
A/D conversion, ADSF must not be written to.
HD404304 Series
26
A/D Port Select Register (ADPR: $00F): The A/D port select register (figure 16) is a write-only register
which selects the digital port and analog port.
Bit 3 Bit 2 Bit 1 Bit 0
A/D mode register (AMR: $00C)
Bit 1 Bit 0
0Conversion cycle
0
134
67
Bit 3 Bit 2
0
1
Analog input
0
1
0
1
AN0
AN1
AN2
AN3
Bit 3 Bit 2 Bit 1 Bit 0
Special flag bit ($020)
Not affect
Start
A/D start flag (ADSF)
ADSF
0
1
Start bit
(write) Status information
(test)
A/D idle
A/D converting
WDON (see Timer section)
Not used
Bit 3 Bit 2 Bit 1 Bit 0
A/D port select register (ADPR: $00F)
1
0AN3
R43
AN2
R42
AN1
R41
AN0
R40
Port select
Figure 16 A/D Register Configuration
HD404304 Series
27
A/D Data Register (ADRL: $00D, ADRU: $00E): The A/D data register (figure 17) is a 4-bit/4-bit read-
only register in which the 8-bit conversion result is set after completing A/D conversion. The data is
preserved until the next conversion begins. Data read is not guaranteed during A/D conversion. The A/D
data register is initialized to $80 by the MCU reset.
Precautions on Using the A/D Converter:
• If a digital signal is input to the R40 to R43 or adjacent pins during A/D conversion, conversion accuracy
may be affected.
• Data in the A/D data register is not guaranteed during A/D conversion.
• Port output instructions should not be executed during A/D conversion to allow for a stable A/D
converter operation.
3210
ADRU ($00E)
3210
ADRL ($00D)
MSB
Bit 7
LSB
Bit 0
Conversion
result
Figure 17 A/D Data Register Configuration
HD404304 Series
28
Input/Output
The MCU has 33 I/O pins, 25 being high-voltage pins. The on/off status of the output buffers of the
standard pins (figure 19) is controlled by the combinations of the value of the port register (PDR) and data
control register (DCR).
D Port: The D port is an I/O port which has 13 discrete I/O pins, each of which can be addressed
independently. It can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested
through the TD and TDD instructions. Furthermore, the contents of the status flag become invalid when the
unused ports are tested. D11 and D12 ports are multiplexed with tone generator pins TG0 and TG1,
respectively. The circuit type of the D port is shown in table 3.
R Ports: The R ports are composed of 20 I/O pins and one input-only pin. Data is input through the LAR
and LBR instructions and output through the LRA and LRB instructions. The MCU will not be affected by
writing into the input-only and non-existing ports. The on/off status of the output buffers of the R3 and R4
ports are controlled by the R port data control register (DCR3, DCR4). R32 and R33 are multiplexed with
INT0 and INT1, respectively. R40, R41, R4 2, and R43 pins are multiplexed with AN0, AN1, AN2, and AN3,
respectively. The circuit type of the R port is shown in table 3.
Port Mode Register B (PMRB: $005): Port mode register B is a 4-bit write-only register which controls
the D11/TG0 pin and D12/TG1 pin as shown in figure 18. The port mode register is initialized to $0 by MCU
reset. These pins are therefore initially used a ports.
Unused I/O Pins: If any unused I/O pins are left floating, the LSI may malfunction due to noise. The I/O
pins should be fixed as follows to prevent malfunction.
• If without pull-down MOS (PMOS open drain) is selected for high-voltage pins connect to VCC on the
printed circuit board.
• If without pull-up MOS is selected for standard pins, connect to GND on the printed circuit board.
The contents of PDR and DCR of the corresponding pin should be programmed to remain the same as in
the reset state. The corresponding pin should not be used as a peripheral function I/O pin.
HD404304 Series
29
Bit 3 Bit 2 Bit 1 Bit 0
Port mode register B (PMRB: $005)
Bit 1 Bit 0
0
1
Pulse frequency
(ø = 1.9 µs)
0
1
0
1
0.5 kHz
1.0 kHz
2.0 kHz
4.0 kHz
Bit 2
Bit 3
0
1
0
1
D11 I/O pin
TG0 output pin
D12 I/O pin
TG1 output pin
Prescaler
divide ratio
÷1024
÷512
÷256
÷128
Figure 18 Port Mode Register B Functions
HD404304 Series
30
indicates
an option Input control
CPU input
PDR
DCR
HLT
PMOS (A)
VCC
VCC
Pull-up MOS
NMOS (B)
Mask Option
DCR (data control register)
PDR (port data register)
CMOS
buffer
Pull-up MOS (C)
Notes: 1: On
0: Off
—: Off
With Pull-Up MOS (B) With Pull-Up MOS (C)
0
—
—
On
1
—
—
On
0
—
On
On
1
On
—
On
0
—
—
—
1
—
—
—
0
—
On
—
1
On
—
—
0101
PMOS (A)
NMOS (B)
Figure 19 I/O Buffer Configuration (Standard Pins)
HD404304 Series
31
Table 3 (1) I/O Pin Circuit Types: Standard Pins
Pin Type With Pull-Up MOS (B) Without Pull-Up MOS (C) Pin Name
I/O
common
pins
CPU
input
HLT
DCR
PDR
V
CC
V
CC
Input
control
CPU
input
HLT
DCR
PDR
VCC
Input
control
R30 to R33
CPU
input
HLT
DCR
PDR
V
CC
V
CC
Input
control
Note: Cannot be used as an analog
input pin (AN
0
to AN
3
).
CPU
input
HLT
DCR
PDR
V
CC
Input
control
R40 to R43
Input pins
CPU
input
HLT
Input
control
V
CC
CPU
input
Input
control
INT0, INT1
