128K x 36, 256K x 18 IDT71V3556S/XS 3.3V Synchronous ZBT SRAMs IDT71V3558S/XS 3.3V I/O, Burst Counter IDT71V3556SA/XSA Pipelined Outputs IDT71V3558SA/XSA Features * 128K x 36, 256K x 18 memory configurations * Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) * ZBT Feature - No dead cycles between write and read cycles * Internally synchronized output buffer enable eliminates the need to contro! OE * Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW: - BWa) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (5%), 3.3V I/O Supply (Vppq) Optional- Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) ee @ Sd Description The iDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega- bit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBT, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, beit read or write. The IDT71V3556/58 contain data {/O, address and control signal registers. Output enabieis the onlyasynchronous signal and canbe used todisable the outputs atany given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) thatallow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads orwrites) willbe completed. The data bus will tri-state two cycles after chip is deselected orawriteis initiated. Pin Description Summary 2006 Integrated Device Technology, Inc. Ao-Ai7 Address Inputs Input Synchronous CE1, CE2, CE Chip Enables input Synchronous OE Output Enable Input Asynchronous RW Read/Write Signal Input Synchronous CEN Clock Enable input Synchronous BWi, BV, BWs, BW Individual Byte Write Selects Input Synchronous CLK Clock Input NA ADv/LD Advance burst address / Load new address Input Synchronous CBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input Synchronous TD! Test Data Input Input Synchronous TCK Test Clock Input NWA TDO Test Data Output Output Synchronous TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous VOo-V/O31, YOp1-VOr4 Data Input / Output vo Synchronous Vop, Vora Core Power, VO Power Supply Static Vss Ground Supply Static 281 tbl Of OCTOBER 2006 DSC-5281/09IDT71V3556, [DT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Description continued The IDT71V3556/58 has an on-chip burst counter. In the burst _ externaladdress (ADV/LD = LOW)orincrementthe internal burst counter mode, the IDT71V3556/58 can provide fourcycles of dataforasingle (ADV/LD = HIGH). address presented to the SRAM. The order of the burst sequence is The IDT71V3556/58 SRAMs utilize IDT's latest high-performance defined by the LBO input pin. The LBO pin selects between linearand CMOS process and are packaged in aJEDEC standard 14mmx20mm interleaved burst sequence. The ADV/LD signal is used toloadanew 100-pinthin plastic quad flatpack (TQFP) as well asa 119 ball grid array (BGA) and a 165 fine pitch ball grid array (BGA). Commercial and Industrial Temperature Ranges Pin Definition Symbol Pin Function Vo Active | Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, AvAt7 Address Inpuis NA ADV/CB low, CEN low, and true chip enables. ADV/LD is a synchronous input that is used to load the intemal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip ADV/LD Advance / Load | NA | deselected, any burst in progress is terminated. When ADV/LD is sampled high then the intemal burst counter is advanced for any burst that was in progress. The extemal addresses are ignored when ADV/LD is sampled high. RAW signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write AW Read / Write NA access to the memory array. The dala bus activity for the current cycle takes place two clock cycies later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are CEN Clock Enable I LOW | ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When RW and ADV/LD are sampled low) the appropriate byte write signal (BW:-BW2) must be valid. The byte I LOW | write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device two cycles later BWi-BW4 can all be tied low if always doing write to the entire 36-bit word. Individual Byte Write Enables Synchronous active low chip enable. CE: and CE are used with CE2 to enable the IDT71V3556/58. (CE: or CE, CE2 Chip Enables | LOW | CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBT has a two cycle deselect, ie., the data bus will tri-state two clock cycles alter deselect is initiated. Synchronous active high chip enable. CEz is used with CE: and CE: to enable the chip. CE has inverted CEe Chip Enable HIGH polarity but otherwise identical to CE: and CE. This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with CLK Clock | NA ne respect to the rising edge of CLK. Oo0-V031 Synchronous data input/output (VO) pins. Both the data input path and data output path are registered and Data Input/Output vo NA VOp1-VOp4 triggered by the rising edge of CLK. Burst order selection input. When [BO is high the Interleaved burst sequence is selected. When [BO is low LBO Linear Burst Order LOW the Linear bursi sequence is selected. [BO is a static input and it must not change during device operation. Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the /O pins OE Output Enable ! LOW | are in a high-impedance state. GE does not need fo be actively controlled for read and write cycles. In normal operation, OE can be tied low. TMS Test Mode Select | NWA | Gives Input command for TAP controller. Sampled on rising edge of TDK. This pin has an intemal pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an intemal pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while fest outputs are driven from the falling edge of TCK. This pin has an intemal pullup. TDI Test Data input | NA TCK Test Clock | NA Serial output of registers placed between TD! and TDO. This output is active depending on the state of the TAP TDO Test Data Output 0 NA controller. JTAG Reset Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset TRST : I LOW | occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. if not used TRST can (Optional) be left floating. This pin has an intemal pullup. Only available in BGA package. Synchronous sleep mode input. ZZ HIGH will gate the CLK intemally and power down the IDT71V3556/3558 to ZZ Sleep Mode | HIGH | its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an intemal pulldown, Voo Power Supply NA NA 3.3V core power supply. Vooa Power Supply NA NA | 3.3V VO Supply. Vss Ground NA NA | Ground. NOTE: 5281 i 0 1. All synchronous inputs must meet specified setup and hold times with respect to CLK,Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock TMS TDI TCK Grist IDT71V3556, 1DT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges =" 128Kx36 BIT MEMORY ARRAY dD QP Le! Address da b| Control S 3 DI DO Ly s = dD arm Control Logic Clk 7 Sel D ~2 Output Register 1 Gate y 5281 drw 01a Data I/O [0:31], (GA Verson) - TDO vO P[1:4]IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/O, Burst Counter, and Pipelined Outputs Functional Block Diagram Commercial and Industrial Temperature Ranges LBO 256x18 BIT MEMORY ARRAY Address A [0:17] *m 5 a > =| Address CE1, CE2,CE2 - WP RW DB Q a = Control CEN -> aAbviD >| & DIDO Bwx | = a y = me D OQ all Control Logic Clik A A, Vv Mux Sel D Clock fF Output Register Lm OE Gate y y 5281 drw O1b ey s STAG Data I/O [0:15], TCK (SA Version) TDO VO P[1:2] P| (optionad Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit Vop | Core Supply Voltage 3.135 3.3 3.465 Vv Vooa =| VO Supply Voltage 3,135 3.3 3.465 V Vss | Supply Voltage 0 0 0 V Vie Input High Voltage - Inputs 2.0 Vob +0.3 V Vi | Input High Voltage - 70 2.0 | Vooa+0.39} Vv Vit | Input Low Voltage 0.3 | 0.8 Vv NOTES: vee 1. Vu (min.) = ~1.0V for pulse width less than tcyc/2, once per cycle. 2. Vik (max.) = +6.0V for pulse width less than tcyc/2, once per cycle.IDT71V3556, 1IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage Commercial and Industrial Temperature Ranges Grade Temperature! Vss Vop Vopa Commercial 0C to +70C OV 3.3Vz5% | 3.3V+5% Industrial 40C to +85C OV 3.3V#5% 3.3V45% NOTES: 5281 tbl 0 1. Tais the instant on case temperature. Pin Configuration - 128K x 36 G GEESE ease hwass A ARAARnnAnAgannnnnAd J. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 vOrsf]1 80 L_] VOp2 vOrel_]2 79 LJ O15 vOr7l_]3 78 {_) O14 Vooa] 4 77 Voba vssC]5 76 Vss VOisl]s 75 (1 1/013 VOi9L]7 74] vote VO20f s 73 yOu VOz1C_]9 72 [1 VO10 Vss[_] 10 71 Vss VooeL] 11 70 [_] Vopa vOzel] 12 69 [J 1/09 VO2s] 13 68 [J 1/08 Von fT} 14 67 L_] Vss Vopf_] 15 66 [_] Vop voo] 16 65 LJ Vop Vssl] 17 64 [J] vsgzz9) Vea] 18 63 L_] 07 VOzsEJ 19 62 [_] Os Vooal] 20 61 [] vopa vsslJat 60 L_] ves O26] 22 59 L] Os VO27T J 23 58 LJ) 1/04 VO2s lj 24 57] vos VO29f] 25 56 LJ O02 vss] 26 55 Vss VovaLZ] 27 54 L_] vopa Oso] 28 53 [J vor O31 29 52 [_] 00 VOraL_] 30 si f{"] yori 31 32. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LULU UUUUOOUDUUUUODUUOT eestence + 3 = 92 - B2t22z zoe eegzezezee won Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to Vop as long as the input voltage is = ViH. 2. Pins 83 and 84 are reserved for future 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to Vss as long as the input voltage is < Vit; on the latest die revision this pin supports ZZ (sleep mode).Pin Configuration - 256K x 18 IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with 4 CEA A Le CME ma lice metic) CO ct ~ oN Soa agar iz 2a & ataitattattalittitatalstistiatia {] // 10099 98 87 56 95 84 83 92 91 90 BO 8B 87 86 ES 84 6 2 Bt ne Cj 0 80 F Ato nc Cj2 79 LINC nc EJs 78 LINC Vooe 4 77 FJ Vooa vss CIs 76 LJ vss nc [7Js 75 LINC nc C7 74] yor vos C78 73 L] yor VvOs C9 72] O56 Vss C2] 10 7 EJ) vss Vooe 411 70 [J vooa VO10 []12 69 1] Os vou C13 68 CJ 04 Voots [714 67 I vss Voo [7] 15 66 [] Vool) Voot) 7] 16 65 LJ Vop vss [17 64 [J vse/zz@) vOre Co 8 63 [_] vos vOrs C19 62 |] vO2 Vope C=} 20 st (J vopa vss Jat cof] vss vOrs Co) 22 so vor vors C23 s8 [1] 1/00 vOr2 [J 24 s7 CI Nc Nc (25 56 L] NC ves C28 55 [_] Vss Vooa [J 27 54 (J Vooa NC FJj28 53] nc NG CZ] 29 52] NC nc F7Js0 sifI nc 3132 33 _34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 > S281 drw 02a = -aos hs Btt2z298 ZEses228 Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to Von as long as the input voltage-is > Vin. 2. Pins 83 and 84 are reserved for future 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to Vss as long as the input voltage is < Vit; on the latest die revision this pin supports ZZ (sleep mode). 100 Pin TQFP Capacitance") (Ta = +25 C, f = 1.0MHz) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings Par on . Commercial & : Symbol Rating Industrial Values Unit VterM) Terminal Voltage with 0.5 to +4.6 V Respect to GND Vierm) | Terminal Voltage with -0.5 to Vop Vv Respect to GND Vierm) | Terminal Voltage with 0.5 to Voo +0.5 V Respect to GND Vterm | Terminal Voltage with -0.5 to Vono +0.5 V Respect to GND Commercial 0 to +70 0} TxD Operating Temperature Industrial ~40 to +85 C Operating Temperature TBIAS Temperature 55 to +125 Under Bias Ts1G Storage 55 to +125 C Temperature PT Power Dissipation 2.0 W lout DC Output Current 50 mA NOTES: 5281 it 06 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Vop terminals. only. Vope terminals only. Input terminals only. VO terminals only. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or /O pin cannot exceed Vooa during power supply ramp up. . Tais the instant on" case temperature. 119 BGA Capacitance") (Ta= +25 C, f= 1.0MHz) Symbol Parameter") Conditions | Max. | Unit Symbol Parameter") Conditions | Max. | Unit Cn Input Capacitance Vin = 3dV 5 pF CN Input Capacitance Vin = 3dV 7 pF Cyo _- | VO Capacitance Vout = 3dV 7 pF Cro | VO Capacitance Vout = 3dV 7 pF 5281 thi 07 $281 bl 07a 165 fBGA Capacitance") (Ta = +25 C, f= 1.0MHz) Symbol Parameter") Conditions | Max. | Unit CIN Input Capacitance VIN = 3dV TBD | pF Cvo VO Capacitance Vout = 3dV TBD | pF 5281 thi O7b NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/O, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 119 BGA Commercial and industrial Temperature Ranges 1 2 3 4 5 6 7 Oo 0 Oo [e) oO A} Voda As Aa NC(2) Aa Al6 VoDO Oo Oo Oo O Oo B NC CE2 AS ADV/LD As GEe NC 0 Oo Oo oO Cc NC A? Aa vob At2 Aid NC Oo [eo] fe) oO Oo D VOt6 VOP3 VSS NC vss VOP2 VO15 o o o 5 o E VO17 1/018 vss GE: VSS O13 vO14 Oo Oo 0 oO Fi VbbdaQ VO19 vss OF vss VO1z VoDQ 0 Oo G| 1/020 vO21 BWs O By? Vo voto Hi O22 O23 vss Rav vss vos vos Ji vpba VoD VDD(1) vpp VDD(1) vob VDDQ Oo Oo Oo oO Oo K O24 /O26 Vss CLK vss VO6 VvOr7 0 Oo O 9 Oo L] Woes vOe7 Bw NC Bw VvOs vOs Oo oO oO Oo o Oo M{ vopa oes vss CEN vss yo VvoDa Oo Oo Oo 0 Oo N VO29 O30 vss Ai vss V2 vor 5 Oo fe) 0 Py) ost VOP4 vss Ao vss VOP1 VvOo oO oO Oo le) Oo Oo O R NC AS LBO vop VDD(1) At3 NC oO oO Oo Oo Oo Oo Oo T Ne NC ao an a Ne nc/zz'5) UL_vopa __NC/TMS@)_ NC/TDIS)_NC/TCK NC/TDO) NC/TRST@4) voba 5281 dw 134 Top View Pin Configuration - 256K x 18, 119 BGA 1 2 3 4 5 6 7 al voo OS) 6 4 NGI2 16 O O So oOo 0 O B CE2 AS ADV/LD AQ CE2 NC oO Oo Oo Oo Oo Oo c NC AT A2 VDD A183 Alz7 NC 0 Oo 9 Oo Di Os NC vss NC vss VOP1 NC Oo 8 oO 6 oO Oo E| NC ve vss CE1 vss NC vO7 Oo 0 fe) Qo Oo F] vooa NC vss 6E vss vOs voDa oO Oo oO o Gi oNC Vio BWe NCQ) vss NC VOs Oo Oo Oo oO Hi von NC vss RW vss vO4 NC 0 0 Oo Oo d YPDQ Yop Vvepay YDD VoD) VoD VYPDQ Oo oO oO fe) oO Ki NC vor vss CLK Vss NC vO3 Oo Oo Oo Oo Oo oO L| vor NC vss NC Bw v2 NC [o) Oo OO 0 OQ Oo M| vopa vO14 vss CEN vss NC vpDa Oo oO 0 Oo oO oO N] vow NC vss At vss vot NC oO Oo Oo ce) Oo Oo Oo P} NC yOr2 vss Ao vss NC vOo oO oO Oo Oo oO R} NC AS [TBO VDD Vpp(1) Alz NC Oo o Oo TE ONC Ato Ais NC Ais Ait ncizzi5 0 oO 0 Oo oO QO. oO UL_vop@___NC/TMS@)_ No/TDI) NC/TCK) NC/TDO) NCARSTE4) vopa S28tdrw 138 Top View NOTES: 1. J3, J5, and R5 do not have to be directly connected to Voo as long as the input voltage is > Vix. 2. G4 and A4 are reserved for future 8M and 16M respectively. 3. These pins are NC for the S" version or the JTAG signal listed for the "SA" version. 4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to Voo. 5. Pin T7 does not have to be connected directly to Vss as long as the input voltage is < Vit; on the latest die revision this pin supports ZZ {sleep mode).IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 165 fBGA Commercial and Industrial Temperature Ranges 1 2 3 4 5 6 7 8 i) 10 "1 A NC AT CET BWs BWe CE CEN | ADv/LD NC@ AB NC B NC AG CE2 Bw BWi CLK RW 6E NC@ Ag NC c VOPS NC Voba Vss VSS Vss Vss VSs VDDQ NC Ore D VO17 VO16 Vopa VoD Vss Vss Vss Vob Vppa VO15 VO E VO19 VO18 VoDQ Vob Vss Vss Vss Vpp Vppa VO1s VOi2 F O21 1/020 VpbQ VpD Vss Vss Vss Vpp Vopa vOut VOto G O23 O22 Vppa Vpo Vss Vss Vss Vpp Vona Og VOs H Vop'? Vop! NC VpD Vss Vss Vss Vop NC NC NC/ZZ) J VO25 O24 Vopa Vpo Vss Vss Vss Vpp Vppa yO7 VO6 K O27 /O26 VpDQ Vop Vss Vss Vss Vpp Vppa VOs VO4 L O29 1/028 Vppa Voo Vss Vss Vss Vpb Vope VO3 VO2 M O31 O30 Vppa Ain) Vss Vss Vss Vop Vppa vor VOo N vOp4 NC VpbDQ Vs NC/TRSTE4 NC Vopt Vss Vopa NC VOP1 P NG NCc AS A2 NC/TDI At NC/TDO Ato Als Ai4 NC R LBO NC Aa A3 NC/TMS Ao NC/TCK Att Ai2 Ai5 At6 5281 tbl 25 Pin Configuration - 256K x 18, 165 fBGA 1 2 3 4 5 6 7 8 9 10 11 A NC?) AT CE BWa NC CE CEN ADVILD NC A8 Ato B NC AG CE2 NC BW CLK RW OE NC@ Ag NC@ C NC NG VoDQ vss vss vss Vss Vss VopQ NC VOPt D ie Os VobQ Vbd vss VSs vss Vpo Vopa NC VO7 E NC VO VDDQ VpD vss Vss vss VoD Vppa NC 06 F NC VO10 VpDQ VoD vss vss vss Vpp VpbdQ NC VO5 G NC vot VppQ VbD vss VSS VSS Vpb VoDQ NC VO4 H Voo' Vopt) NC VpD Vss Vss Vss Voo NC NC NC/ZZ J yO12 NC VoDQ Vob Vss vss vss VpD Vpoa VO3 NC K /O13 NC Vppa Vpb Vss Vss Vss Vpp VppQ 02 NC L YOr4 NC Voda VoD Vss vss vss Vop VDDQ vor NC M VOt15 NC Vppa VDD Vss Vss Vss Voo VooQ Oo NC N VOp2 NC VbDQ Vss NC/TRST NC Vpp vss Voda NC NC P NC NC AS A2 NC/TDIS Ai NC/TDO Ait Al4 Ai5 NC R LBO NC! A4 A3 NC/TMS AO NC/TCK Ai2 Ai3 At Al7 NOTES: 5281 tbi 25a H1, H2, and N7 do not have to be directly connected to Vop as long as the input voltage is = Vin. AQ, BQ, B11, At, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively. These pins are NC for the S" version or the JTAG signal listed for the SA version. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to Vop. Pin H11 does not have to be connected directly to Vss as long as the input voltage is < Vil; on the latest die revision this pin supports ZZ (sleep mode). oP OMIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with 4 ee ae OP eer Clee Mates Melt c) Commercial and industrial Temperature Ranges Synchronous Truth Table (1) CEN RW Chip ADV/LD BWx ADDRESS PREVIOUS CYCLE CURRENT CYCLE vo Enable USED (2 cycles later) L L Select L Valid External X LOAD WRITE Dp) L H Select L x External X LOAD READ Q") L X x H Valid internal LOAD WRITE / BURST WRITE bp) BURST WRITE (Advance burst counter)) L X xX H X Internal LOAD READ / BURST READ Qn BURST READ (Advance burst counter)) L Xx Deselect L xX xX X DESELECT or STOP) HiZ L X xX H X X DESELECT / NOOP NOOP HiZ H X X X X X X SUSPEND Previous Value 5281 tb! 06 NOTES: 1. 2. 3. N& L-= Vil, H = Vin, X = Don't Care. When ADVILD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read. or Write) is determined by the status of the RAW signal when the first address is loaded at the beginning of the burst cycle. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the |/ Os remains unchanged. To select the chip requires CEi = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Q - Data read from the device, D - data written to the device. Partial Truth Table for Writes () OPERATION RW Bw BWe Bws) BW!) READ H X Xx Xx Xx WRITE ALL BYTES L L L L L WRITE BYTE 1 (V/O[0:71, YOP1) L L H H H WRITE BYTE 2 (VO[8:15], VOp2)) L H L H H WRITE BYTE 3 (/O[16:23], YOps\(24) L H H L H WRITE BYTE 4 (V/O[24:31], YOp4)2) L H H H L NO WRITE L H H H H NOTES: 8281 tb! 08 1. 2. 3. L= Vu, H = Vin, X = Don't Care. Multiple bytes may be selected during the same cycle. N/A for X18 configuration.1DT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Interleaved Burst Sequence Table (LBO=Vpp) Commercial and Industrial Temperature Ranges Sequence 1 Sequence 2 Sequence 3 Sequence 4 Al AO Al AO Al AO Al AO First Address 0 0 9) 1 1 0 1 1 Second Address 0 1 0 0 1 1 | 0 Third Address { 0 { 1 0 0 0 1 Fourth Address i i 1 0 0 1 0 0 5281 tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=Vss) Sequence 1 Sequence 2 Sequence 3 Sequence 4 Al AO Al AQ Al AO Al AQ First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address" i 1 0 0 9 1 1 0 5281 tol 11 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram ) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 clock PL Lt Lt LF LF LE Le Le ADDRESS A29 A30 A31 A32 A33 A34 A385 A36 A37 CONTROL C29 C30 C31 C32 633 C34 C35 C36 C37 (RW, ADV/LD, BWx) @) DATA pia27 | piazs | p/az9 | paso | pvasi | pvas2 | p/a33 | pasa | p/a3s /O [0:31], /O P[1:4] /Q /Q3 Q3 Q3 5281 drw 03 NOTES: 1. This assumes CEN, CE1, CE2, CE2 are ail true. 2. All Address, Control and Data_in are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock.Device Operation - Showing Mixed Load, Burst, IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Deselect and NOOP Cycles () Cycle Address RW | ADVD | GE OE 0 | Comments n Ao H L L X X Load read n+i X X H X L X X Burst read n+2 Ai H L L L L Qo | Load read n+3 x xX L H L L Qo+t | Deselect or STOP n+4 xX Xx H X L L Qi | NOOP n+5 A2 H L L L X Zz Load read n+6 X X H X L X Z Burst read n47 X X L H L L Qe | Deselect or STOP n+8 A3 L L L L L Qa | Load write n+ X X H X L X Zz Burst write n+10 A4 L L L L X Ds Load write nei X X L H L X Da+1 | Deselect or STOP n+i2 X X H X L xX Da | NOOP n+13 AS L L L L X Zz Load write n4+14 As H L L L X Zz Load read n+15 AT L L L L X Ds | Load write n+16 X X H X L L Qs | Burst write n+i7 As H L L L X D7 | Load read n+18 X X H X L X Dz+1 | Burst read n+19 Ag L L L L L Qs | Load write NOTES: _ _ _ __ _ 1. CE = Lis defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE: = H, CE2 = H or CE? = L. 2. H = High; L = Low; X = Don't Care; Z = High Impedance. Read Operation (1) Cycle Address RW | aDviD | GE | CEN OE vO | Comments n Ao H L L X Xx Address and Control meet setup nd X X xX X xX X | Clock Setup Valid n+2 xX X xX X L Qo | Contents of Address Ao Read Out NOTES: 1. H = High; L = Low; X = Don't Care; Z = High Impedance. _ _. 2, CE = Lis defined as CE1 = L, Ce2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation ( Commercial and Industrial Temperature Ranges Cycle | Address | RW | ADVILD | TH | CEN | BWx | OE VO | Comments n Ao H L L L X X X Address and Control meet setup n+ X X H xX L X X X Clock Setup Valid, Advance Counter n+2 xX X H X L X L Qo | Address Ao Read Out, Inc. Count n+3 xX X H x L X L Qo+1 | Address Ao+1 Read Out, Inc. Count n+4 x x H X L X L Qo+z | Address Ao+2 Read Out, Inc. Count n+5 At H L L L X L Qo+3 | Address Ao+3 Read Out, Load At n+6 xX X H X L xX L Qo | Address Ao Read Out, Inc. Count n+7 X X H Xx L X L Qi | Address Ai Read Out, Inc. Count n+8 A2 H L L L X L Qi+1 | Address Ai+1 Read Out, Load A2 NOTES: 5281 tbl 14 1. H = High; L = Low; X = Don't Care; Z = High Impedance.. _. _ 2. CE =Lis defined as CE: =1, CE2=L and CE2=H. CE =H is defined as CE: = H, CE2 = H or CE2=L. Write Operation Cycle | Address | RAW | ADVLD | CH | CEN | BWx | OF VO | Comments n Ao L L L L L X X Address and Control meet setup nt X x X X L X X Xx Clock Setup Valid ne2 X X X X L X X Do | Write to Address Ao NOTES: 5281 tbl 15 1, H = High; L = Low; X = Don't Care; Z = High Impedance, _ _ 2. CE = Lis defined as CEi = 1, CE2=L and CE2=H. CE =H is defined as CE1 = H, CE2 = H or CE2=L. Burst Write Operation ( Cycle | Address | RW | ADVILD | CE) | CEN | BWx | OE VO | Comments n Ao L L L L L Xx X Address and Control meet setup nti X Xx H xX L L x X Clock Setup Valid, Inc. Count m2 xX X H X L L X Do | Address Ao Write, Inc. Count n+3 X Xx H X L L X Do+t | Address Ao+t Write, Inc. Count n+4 xX X H X L L X Do+z | Address Ao+2 Write, Inc. Count nid Al L L L L L X Do+3 | Address Ao+3 Write, Load Ai n+6 X X H X L L X Do | Address Ao Write, Inc. Count m7 X X H X L L Xx Di | Address At Write, Inc. Count n+8 A2 L L L L L X Dist | Address A1+t Write, Load A2 NOTES: 5281 tbl 16 1. H = High; L = Low; X = Don't Care; ? = Don't Know, Z = High Impedance. _ _ 2. CE = Lis defined as CE1 = 1, CE2=L and CE2=H. CE =H is defined as CEi = H, CE2 = H or CE2 = L.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and industrial Temperature Ranges Read Operation with Clock Enable Used (1) Cycle | Address | RW | ADVLD | CE | CEN | BWx | OE VO | Comments n Ao H L L L X X xX Address and Control meet setup nei xX X X Xx H xX X X Clock n+1 Ignored n+2 At H L L L X X X Clock Valid n+3 X X xX X H X L Qo | Clock Ignored. Data Qo is on the bus. n+4 xX X X X H X L Qo | Clock Ignored. Data Qo is on the bus. n+5 A2 H L L L X L Qo | Address Ao Read out (bus trans.) n+6 A3 H L L L xX L Qt | Address Ai Read out (bus trans.) n+7 AA H L L L X L Qe | Address A2 Read out (bus trans.) NOTES: 5281 tbl 17 1. H = High; L = Low; X = Don't Care; Z = High Impedance. _. _ 2. CE = L is defined as CEi = L, CE2 = L and CE2 =H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation with Clock Enable Used (1) Cycle | Address | RW | ADVLD | CH | CEN | BWx | OE VO | Comments n Ao L L L L L X X Address and Control meet setup. n+1 X Xx xX X H X X X Clock n+1 Ignored. n+2 At L L L L L X xX Clock Valid. n+3 X X X X H x X X Clock Ignored. ne4 X X xX X H X X xX Clock Ignored. m5 A2 L L L L L X Do | Write Data Do n+6 A3 L L L L L X Di | Write Data Ds n+7 Aa L L L L L Xx De | Write Data De NOTES: 5281 tbl 18 1. H = High; L = Low; X = Dont Care; Z = High Impedance. 2. CE = Lis defined as CE = L, CEe = L and CEz=H. CE = H is defined as CE: = H, CE2 = H or CE2 = L.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Read Operation with CHIP Enable Used (1) Commercial and Industrial Temperature Ranges Cycle | Address RW | aDvD | CE | CEN | BWx | OE yo | Comments n X X L H L X Xx ? Deselected. n+] X X L H L X Xx ? Deselected. m2 Ao H L L L x X Zz Address and Control meet setup +3 X X L H L X X Z | Deselected or STOP. n+4 Ai H L L L X L Qo | Address Ao Read out Load At. ned X X L H L xX X Z Deselected or STOP. n+6 x xX L H L X L Qt | Address At Read out. Deselected. nt7 A2 H L L L X x z Address and control meet setup. n+8 X X L H L X xX Z | Deselected or STOP. n+9 X x L H L x L Qe | Address A2 Read out. Deselected. NOTES: 5281 tbl 19 1, H = High, L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance. __ _. 2. CE = Lis defined as CE1 = L, CE2 = L and CE2= H. CE = H is defined as CE1 = H, CE2 = H or CE2=L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Write Operation with Chip Enable Used Cycle Address RW | aDVviD | CE) | CEN | BWx OE 0% | Comments n X X L H L Xx X ? Deselected. n+1 X xX L H L X X ? Deselected. ne2 Ao L L L L L X Z Address and Control meet setup n+3 xX xX L H L Xx X Zz Deselected or STOP. ne4 At L L L L L X Do | Address Do Write in. Load A1. n+5 X X L H L X Xx Zz Deselected or STOP. n+6 X X L H L xX X Di | Address D1 Write in. Deselected. n47 A2 L L L L L Xx Zz Address and control meet setup. n+8 x X L H L X X Z | Deselected or STOP. n+9 X X L H L X X De | Address De Write in. Deselected. NOTES: 5281 ib! 2 1, H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High impedance. _ 2. CE =L is defined as CE1 = L, CE2 = Land CE2= 1H. CE = H is defined as CEt = H, CE2 = H or CEe = L.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs DC Electrical Characteristics Over the Operating wtwe we sep ety vette ee nee a (VDD=3.3V 4+/-5%) tem per Commercial and Industrial Temperature Ranges Symbol Parameter Test Conditions Min. Max. Unit fly Input Leakage Current Vop = Max., Vin = OV to Vop 5 uA fh LBO, JTAG and ZZ input Leakage Current) Vop = Max., Vin = OV to Voo 30 HA {ILo} Output Leakage Current Vout= OV to Vopa, Device Deselected _ 5 HA VoL Output Low Voltage lot = +8mA, Vop = Min. _ 0.4 V VOH Output High Voltage lon = -8mA, Vop = Min. 2.4 _ V 5281 tbl 21 NOTE: 1. The [BO, TMS, TDI, TCK and TRST pins will be intemally pulled to Voo and ZZ will be intemally pulled if they are not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ) (vpn = 3.3V +/-5%) 200MHz 166MHz 133MHz 100MHz Symbol Parameter Test Conditions Com'l Only | Comt | Ind | Com | Ind | Com | ind Unit 0D | Operating Power Device Selected, Outputs Open, 400 350 | 360 | 300 | 310 | 250 | 255 | mA Supply Current ADV/LD = X, Vpp = Max., VIN > VIH or < Vit, f = fmax) Is8t_ | CMOS Standby Device Deselected, Outputs Open, 40 40 45 40 45 40 45 mA Power Supply Current | VoD = Max., VN > VHD or < VLD, f = 924) S82 | Clock Running Power | Device Deselected, Outputs Open, 430 120 | 130 | 110 | 120 | 100 | 110 | ma Supply Current Vpp = Max., VIN > VHD or < Vip, f = fat?) IsB3 | Idle Power Device Selected, Outputs Open, 40 40 45 40 45 40 45 mA Supply Current CEN > Vin, VDD = Max., Vin > VHD or < Vio, f = fax) NOTES: 5281 tbl 22 1. All values are maximum guaranteed values. 2. At f = fMax, inputs are cycling at the maximum frequency of read cycles of t/icyc; f=0 means no input lines are changing. 3. For I/Os Vup = Vopa 0.2V, Vip = 0.2V. For other inputs Veb = Von - 0.2V, Vip = 0.2V. AC Test Loads voog2 AC Test Conditions (Vppa = 3.3V) V0 input Pulse Levels 0 to 3V 6 Input Rise/Fall Times 2ns ~ S281 dew 04 5 Figure 1. AC Test Load Input Timing Reference Levels 1.5V 4 Output Timing Reference Levels 1.5V AC Test Load See Figure 1 AtcD 3 (Typical, ns) 5281 tht 23 2 1 2030 50 80 100 200 Capacitance (pF) 5281 drw 05 Figure 2. Lumped Capacitive Load, Typical DeratingIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs AC Electrical Characteristics (Vpb = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) Commercial and Industrial Temperature Ranges 200MHz) 166MHz 133MHz 100MHz Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit tere Ciock Cycle Time 5 6 75 _ 10 _ ns te) Clock Frequence _ 200 166 133 _ 100 MHz tcH?) Clock High Pulse Width 1.8 1.8 _ 2.2 3.2 ns tcL) Clock Low Pulse Width 1.8 1.8 2.2 3.2 oe ns Output Parameters tc Clock High to Valid Data 3.2 _ 3.5 42 5 ns toc Clock High to Data Change 1 1 _ 1 1 ~ ns ta.z844) Clock High to Output Active 1 1 1 ~ 1 ~ ns tonz.4) Clock High to Data High-Z 1 3 1 3 i 3 j 3.3 ns tOE Output Enable Access Time 3.2 3.5 _ 4.2 _ 5 ns ta Output Enable Low to Data Active 0 _ 0 0 - 0 a ns tonz54) Output Enable High to Data High-Z 3.5 _ 3.5 4.2 5 ns Set Up Times SE Clock Enable Setup Time 1.5 _ 1.5 _ 1.7 _ 2.0 ns tA Address Setup Time 15 _ 1.6 1.7 2.0 _ ns tsp Data In Setup Time 15 _ 1.5 _ 1.7 _ 2.0 _ ns tow Read/Write (R/W) Setup Time 15 _ 15 1.7 2.0 ns tSADV Advance/Load (ADV/LD) Setup Time 15 _ 1.5 _ 1.7 _ 2.0 _ ns isc Chip Enable/Select Setup Time 15 _ 1.5 1.7 2.0 _ ns tsB Byte Write Enable (BWx) Setup Time 15 1.5 1.7 _ 2.0 _ ns Hold Times tHE Clock Enable Hold Time 0.5 _ 0.5 0.5 _ 0.5 _ ns tHA Address Hold Time 0.5 ~ 0.5 _ 0.5 _ 0.5 ns tHD Data In Hold Time 0.5 _ 0.5 _ 0.5 _ 0.5 ns taw Read/Write (R/W) Hold Time 0.5 0.5 = 0.5 0.5 ns tHaDV Advance/Load (ADV/LD) Hold Time 0.5 _ 0.5 _ 0.5 0.5 _ ns THC Chip Enable/Select Hold Time 0.5 ~ 0.5 _ 0.5 0.5 _ ns tHe Byte Write Enable (BWx) Hold Time 0.5 0.5 ~ 0.5 0.5 ns NOTES: 5281 tbl 24 1. iF = I/tcye. 2, Measured as HIGH above 0.6Vopa and LOW below 0.4Vopa. 3. Transition is measured +200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested, 5. To avoid bus contention, the output buffers are designed such that tcHz (device turn-off) is about ins faster than tc.z (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tc.z is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tcuz, which is a Max. parameter (worse case at 70 deg. C, 3.135V). 6. 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(HOI paldwes C@YAQY) Bunsing si wyHs ou) uayMaleo |uop si Y/Y p MOTTA Buydwes Aq wiys eut ojU! papeo] aze jo.jUOO pue sseippe meu UeUyM Spud jing "HOIH 8! 230 WOJOARM SIU} UO MOT ale 239 PUR 19 USYM ajdwiexe Joy sjeubls 299 pue 139 Ou} 0] pepyeAu! jng jeoljuapi aie suosuer Buu 249 -Z "indul 9g] 94} jo 81e}s 94} Aq peuyjap eouenbes Bu} Ul }sing pom INO} ay} 10} BuloUBApe aye LY PUR oY Siig ssolppeE aioyM O}9 ay ssouppe eased ou} jo aouenbes sing Sy} ul eyep jnduj pou oy) sjuasauday (1+zy) G zy Sseuppe jewa)xXe ay} O} jndul js ayy sjuasaiday (zy) q Ly SSBINPe feUE}Xe Ou} O} INdul jsuy ay} Sjuasaide: (Ly) GQ *E *SA.LON SUM i taser foe 20 MUP LeG auyjadig 4 SYN QUOC SING a eM auledig (aia YX \erevJa X era KXXXK KX eave XX (aya Xx (wa X \ (aieys [eau] Oo} 4 (eBpe 400/90 H-7 uauino nn punoie sdeiiising) Gap usr soyeuiuuie yBiy N39) tan a5} M) \ qaota NIV.LVG ssagqqv aVvaav ra Lu jO xD5 WYHS 8} 0] pajuasaid si eyep jenjor ayy 5 810}6q S9}OK9 OM UI SBWUO LOFELUO JU! ayIM a}Aq 9U | "MO" paldues s| jeubls jy vay paye|yul slajoAo aim y sepAo@yM-}sING PUB SIM fe UO plleAaq isn (xg) seubis ay alg enpIAIpU a "HOIH S] 231 WuOJaneM SIy] UO MO] ale 239 pure yO uaym ejdwiexa 105 sjeuBis 739 pue 1349 84} 0} payeAut ing jeoquap! are suonisued Buu 239 2 g 2y ssaippe 0} Gulpuodsexioa WHS oyt Ol} Blep Indul ey) sjueseudei (zy) q ty Sseuppe feUla}xe ey wWOY INdino js1y oy) sjuasaidel (Ky) D 1 3 SALON o G a 80 up 1gzg Fe ~ + Pe] p> PR i ae POY es 4 rg * =i Z {Y g (WO LnOVLvG BS | ae XX who) (Ke i= > f > = a 00} | TO THO dO 5 Oo tt SIUM ig SHIM, ~ aS (sa ) (ha) ea Novia sie eae eo cy ~ yy} GS} aS 30 n _ = a: AG - IMG 2 matte a CO 2 a PO 55 739 13 Fe w~ (249 39 aS se aaa ssauaay a4 2 a4 rar) ra =O a OC We aS Lo x Le ea & fe] he ran OO ayaay 3Om- a sa 3 a qs Na = O os = ray DD to a? a4 's 19 ~~ aa E Min _ -WVHS 94) 0] pajuasaid si eyep jenjoe oy} a10jaq SejoAd OM} UI S@LUOD LONELUOJUI BUM S}Aq Sy MOT palduies sieuBis jy ueyM palenul slap A. op My sep AoeyM-JsINGpUe SMe UO PEAS isn (xg) sfeuBis aM og fenpINIDU| p aye}$ SNOtAeld JOY] Ule}Ol ||IM WHS 2u} Ul Sie}siBau peulaTUT If 28990 Jou pIp UOHISUeI] 40010 H-7 84} 4I SeeAeYoR IM Wed ey WYHS 24) O}U! BupeBodold wo. y90/9 atp Jo UOMSURL 1-7 JEU) YOo\q jim 490}0 Jo eBpe Burs ou} Uo UBiypalduies UaUMNNAD *C 'HOTH S129 WoJaAeM SIU] UO MOT ale 239 puke 19 UeYM edwexe 104 sjeuBis 739 pue 139 ay! 0] payaAu! ing jeonUEpI a1e sUOTSUBN BUNUN 299 Z "Zy sseuppe 0} Bulpuodseico YS 4) 0} Blep Indu ey) sjuasaidel (zy) q Hy sseuppe feUlEXe ay] WOY Indino jsiy ayy sjuasaidal (Ly) E L on oo o c id ia Kd f= Ss 2 S3LON 3 o ja rs = 60 MID 8zG FE In Z10} E Nt = (X _ byio X Kaho (wo x .nowiva ay <a > ao) = tar eg CO] fm 3 +> 7 pt ZHO} E awa NIVLVG rs Sree = ne Sy (oo co S : SEES oes ae SESE oe Waveform of CEN Operation (1:2:3.4) <q DAD] p> od = Es eI 4 a n A pre c i Rod [s} Pal 7) Pd oe) r) - x x ite] ca ey ie] bd A o + _ Cy re) iw 0 P E 2 oS ite] iD ce > _ MB be =) H bo] a. 7 pod [eo] S ay r R= OW 3 = a _ Q = < pod oO pa a J = a S = J % 9 Fd i] rm Po fe - m Le] T3 WHS 8U} 0] payuasaid si eyep jenjoe au} & 910}9q Sa[0A0 OM} Ul S@LUCO LOHJELUIOJUT aUM a1Aq @y | M\O"]pa|dwues si jeubis /y Ueym papel slapAIOPMY sopADoIM-]SING Ue OYIM|[e UO pfeAeqysnus (xag) sjeubis omy org enpiaipuy py & aye }s snoiAesd OU) UIE}: [IM WY HS eu} Ul su9}siBau (eUO}UI e [ly 4nO90 JOU pip UO}SUBI] YOO[9 }]-7 aul Jt SB@ABYeq|IM Ned ay WYHS Ou] O}U! BuNjeBodosd Woy yoo} ay} Jo UON|sUEL 4-7] FEU) 904d [IM 490|0 Jo aBpe Huis: ay) uO YBlypardwes UaYMNAD * FS "HOIH 81290 WOJaAeM SIU] UO MMO Bie 249 pue 139 uoYyM idusexe 104 sjeuBis 239 pue 139 @Ut 0] payaAuT ing jeoluap! ze suolysues Hutu Z 32 -= 4 ely Ssauppe 0} Bulpuodseioo YS 4} 0] Blep indul ety sjuasaida: (ey) q Hy SSaIppe feLUA]xe Oy) LOY Indio ys4Nj au) SJUSsaidar QWw)Oo 4 E S3LON a OL AUP Lezg a E |) +f B _| WO K (evip XXX _ (hyo } inoviva Ke) 4+ < > ~~ OGoF Go} 3 lm tar g ewid NIV.LVG 5 <-> E as} Oo Waveform of CS Operation (1:23.4) iming <= = S 2] = 4 [sq n 2 i od 9 a a Qo x Pa bd i c c} ~ x x ito ie rs o Sr bd x ae] N Sad - Te) wo o Pd ad i - a o Te] te] St ped pal E a Mn Po Fy 2 B 3 o 3 7 & ry 2 a zu = G Po S eI 3 oO ne wo See e rr) g bd * Cs o J 3 2 c cs ing Fg = fst) is TIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/0, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only) Commercial and industrial Temperature Ranges TCK Device Inputs/ TDI/TMS tbc Device Outputs?)/ TDO tURSR tcp TRST) M5281 drw 01 RST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets. automatically. TRST is an optional JTAG reset. JTAG AC Electrical Characteristics(1:2:3:4) Symbol Parameter Min. Max. | Units " . y Scan Register Sizes ticyc JTAG Clock Input Period 100 _ ns UCH JTAG Clock HIGH 40 _ ns Register Name Bit Size uot JTAG Clock Low 40 | | ng | {lsstuction (IR) 4 uA JTAG Clock Rise Tme | | 5 | ns Bypass (BYR) ' UF JTAG Clock Fall Time | 5 | ns JIAG Kdentiication (JIDR) 32 uRST JTAG Reset 50 ns Boundary Scan (BSR) Note (1) Bt tbl 08 URSR JTAG Reset Recovery 50 ns NOTE: al tcp JTAG Data Output _. 90 ns 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative. upc JTAG Data Output Hold 0 ns us JTAG Setup 25 _ ns lH JTAG Hold 25 ns (5281 tbi OF NOTES: 1. Guaranteed by design. 2. AC Test Load (Fig. 1) on external output signals. 3. Refer to AC Test Conditions stated earlier in this document. 4, JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs JTAG Identification Register Definitions (SA Version only) Commercial and Industrial Temperature Ranges Instruction Field Value Description Revision Number (31:28) 0x2 Reserved for version number. IDT Device ID (27:12) 0x208, 0x20A Defines IDT part number 71V3556SA and 71V3558SA, respectively. iDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT. ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register. 1281 tbl C2 Available JTAG Instructions Instruction Description OPCODE Forces contents of the boundary scan cells onto the device outputs"), EXTEST Places the boundary scan register (BSR) between TDI and. TDO. 0000 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs) and outputs to be captured SAMPLE/PRELOAD in the boundary scan cells and shifted serially through TDO. PRELOAD 0001 allows data to be input serially into the boundary scan cells via the TDI. Loads the JTAG ID register (JIDR) with the vendor ID code and places DEVICE ID the register between TDI and TDO. 0010 HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all 001 device output drivers to a High-Z state. RESERVED 0100 RESERVED Several combinations are reserved. Do not use codes other than those 0101 identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, RESERVED VALIDATE and BYPASS instructions. 0110 RESERVED ont CLAMP Uses BYR. Forces contents of the boundary scan cells onto the device 4000 outputs. Places the bypass register (BYR) between TDI and TDO. RESERVED 1001 RESERVED 1010 Same as above. RESERVED 1011 RESERVED 1100 Automatically loaded into the instruction register whenever the TAP VALIDATE controller passes through the CAPTURE-IR state. The lower two bits '01' 1101 are mandated by the IEEE std. 1149.1 specification. RESERVED Same as above. 1110 The BYPASS instruction is used to truncate the boundary scan register BYPASS as a single bit in length. mt 15281 tbl 04 NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST.IDT71V3556, 1IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and industrial Temperature Ranges 100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline EVEN LEAD SIDES ODD LEAD SIDES 7o SE DEAL =] SEATING FANE fem REF onal i Boat 28 z t t os PR PACKAGE CUTLINE a BASE METAL 14.0 X 20.0 X 1.4 mm TOF 1,00/.10 FORM ET URRRE Se ae DETAL PSc- 4045 | 2 SARA SHEED 1 cy 2 i JEDEC VARIATION : LAND_ PATTERN DIMENSIONS i AZ D A y a N NO NE 6 2 bl a @ > BB - b> 1 DENTE DATED &> LIN 4A mm TOP Our 146 X 26.0 X14 FORW PSC- 4045IDT71V3556, 1DT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 119 Ball Grid Array (BGA) Package Diagram Outline 450 WAX BREAK ana nas LN ITIL, = DDALAT BWICH E & 2 SIVENSENS BAAR 708: rt oo 4b COANED og00s5 COO50 Ce] Ooeeocoo coceoco coceaoo Ccooeooo cooog5o COOoD5O eooesoo ad COoooocoe oO ee CTETE? cooCg00 Sime COCOODO, 2D OOooOd GOoOo00 Ooogo00 2COO00O J wmf om Bom} ben a ca oS = = yaooOeCoooa aoo000000 oooo0ogano c saoarae, Behe [rere x ees & egies tothe {ter tp o [or foo | alae & & 8 & Bg BR eta bor = x g Lo "AS" D CORNER Commercial and industrial Temperature Ranges CIMLIZED OR NK MARK, WARK MUST TON MS~O28, lagested Devien Teebuelog Ean. Th Sherer Way Sarin Gee, OR HOE 80 HOT SOALE DRAWIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, RAREST ees acter Um UL UL ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs 165 Fine Pitch Ball Grid Array (fBGA) Package Commercial and Industrial Temperature Ranges Diagram Outline REVISING aN ae PT i DATE f APPROVES BE, Poe Los/An/eo] "a -, 5 G00000COCOO..: D ecooo0doogooo |: > SBCO0O0C0OCOSGOCO fc a So D eo0oo0c ooo oco 8: ds D coocooooooooo & D oocoebpooooco : 3 ecoococooceo os 5 eoooogocoocea |: 5 eococeoooce x D ooocoooococao |: D eoocoogoocco |: . eoooogvecaccao js > tt ococoog000ca oe D FO 9 O00 OO0CO Ik ii GOR A : (168 re i inizpreted Deviee Technalsgy, tne. iets eo-asesin go 20 AOT Sta DRAKE beer fo 2 fl REVISE beef nev | BEECH PRGN TP ASPROWED: a poe | RA HEZARE O9COCOCOCAOO0 |: OOO meomomemonenomonnr oooo0o0o0coo0o0 |: aoocooo0o00o0co 11 ooooo oo0ono G CONFORN TG ASHE Y14.5-~-1994 lo 2 oooocoeooo000o0 FF ocoecOoboooaO 4s 3 of oy 8 4 a 4& Oo0ocoeooooN aooecoaoo0oocaoan0 A ooooooooo0oo A ococoocodooooo |s : ccoo$o Gooo90 8 A ococogaocooo - 5 CoOoeooooOooo 2 {65 Sau} g : A At ea i : 1 (Laser edt] mene eae) 7 2a, WA Tie tab cae: s-se-ter1DT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation () Commercial and Industrial Temperature Ranges Y 1OE Valid OE {OHZ toLz _ DATAouT NOTE: 1. A read operation is assumed to be in progress. Ordering Information IDT _XXXX_ XXX XX XX X xX Device Power Speed Package Process/ Process/ ype Temperature Temperature Range Range | | X Blank PF BG BQ } 200 166 133 100 s SA IDT71V3856 iDT71V3558 5281 drw 11 Commercial (0C to +70C) Industrial (-40C to +85C) Restricted Hazardous Substance Device 100- pin, Plastic Thin Baa) Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (BGA) Clock Frequency in Megahertz Standard Power Standard Power with JTAG interface X Generation Die Step Optional 128Kx36 Pipelined ZBT SRAM with 3.3V 1/0 256Kx18 Pipelined ZBT SRAM, with 3; Sv VO Commercial temperature range only * JTAG (SA Vatsion) is not available with 100-pin TOFP packageIDT71V3556, 1DT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs Datasheet Document History 6/30/99 8/23/99 10/4/99 12/31/99 04/30/00 05/26/00 07/26/00 10/25/00 1/24/02 9/30 /04 10/18/06 Pg.4,5 Pg.6 Pg. 14 Pg. 15 Pg. 22 Pg. 24 Pg. 14 Pg. 15 Pg. 5,6 Pg.6 Pg. 5,6,7 Pg. 21 Pg. 23 Pg. 5-8 Pg. 8 Pg. 23 Pg. 8 Pg. 1-8, 15,22,23,27 Pg.7 Pg. 27 Pg. 1, 26 Updated to new format Added Smart ZBT functionality Added Note 4 and changed Pins 38, 42, and 43 to DNU Changed U2-U6 to DNU Added SmartZBT AC Electrical Characteristics Improved tcp and toe(max) at 166MHz Revised tcHz(min) for f< 133 MHz Revised foxz (max) forf < 133 MHz Improved teu, tc forf< 166 MHz improved setup times for 100-200 MHz Added BGA package diagrams Added Datasheet Document History Revised AC Electrical Characteristics table Revised tcuz to match tcz and tcpc at 133MHz and 100MHz Removed Smartfunctionality Added Industrial Temperature range offerings at the 100 to 166MHz speed grades. insertclarification note to Recommended Operating Temperature and Absolute Max Ratings tables Add BGA capacitance table Add note to TQFP and BGA Pin Configurations; corrected typo in pinout Add 100pinTQFP package Diagram Outline Add new package offering, 13x 15mm 165 {BGA Correct 119BGA Package Diagram Outline Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts Update BQ165 pinout Update BG 119 package diagram outlinedimensions Remove Preliminary status Add note to pin N5 on BQ165, reserved for TAG TRST Added JTAG "SA" version functionality Updated pin configuration forthe 119 BGA-reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18). Adding Restricted hazardous substance device" to ordering information. Added X generation die step to data sheet. IDT CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES: for Tech Support: 800-345-7015 or 408-284-8200 sramhelp @idt.com fax: 408-284-2775 800-345-7015 or. www.idt.com 408/284-4555 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ze + and Zero Bus Turnaroundare trademarksof a Device ss inc. and the architectureis : Micron and Motorola Inc. Commercial and industrial Temperature Ranges