512Kx72 Pipelined NtRAMTM
- 1 - Rev 0.1
December 2001
K7N327245M Preliminary
Document Title
512Kx72-Bit Pipelined NtRAMTM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
Remark
Preliminary
Preliminary
History
1. Initial document.
1. Speed bin merge.
From K7N327249M to K7N327245M
2. AC parameter change.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20
Draft Date
May. 10. 2001
Dec. 31. 2001
512Kx72 Pipelined NtRAMTM
- 2 - Rev 0.1
December 2001
K7N327245M Preliminary
32Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Information
Org. Part Number Mode VDD Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz) PKG Temp
2Mx18 K7M321825M-Q(H/F)C65/75/85 FlowThrough 3.3 6.5/7.5/8.5ns
Q:100TQFP
H:119BGA
F:165FBGA C
(Commercial
Temperature
Range)
K7N321801M-Q(H/F)C25/22/20/16/15/13 Pipelined 3.3 250/225/200/167/150/133MHz
K7N321845M-Q(H/F)C25/22/20/16/15/13 Pipelined 2.5 250/225/200/167/150/133MHz
1Mx36 K7M323625M-Q(H/F)C65/75/85 FlowThrough 3.3 6.5/7.5/8.5ns
K7N323601M-Q(H/F)C25/22/20/16/15/13 Pipelined 3.3 250/225/200/167/150/133MHz
K7N323645M-Q(H/F)C25/22/20/16/15/13 Pipelined 2.5 250/225/200/167/150/133MHz
512Kx72
K7N327245M-HC25/22/20/16/15/13 Pipelined
(Normal Type) 2.5 250/225/200/167/150/133MHz H : 209BGA
K7Z327285M-HC27/25 Pipelined
(Sigma Type) 1.8 275/250MHz
512Kx72 Pipelined NtRAMTM
- 3 - Rev 0.1
December 2001
K7N327245M Preliminary
512Kx72-Bit Pipelined NtRAMTM
The K7N327245M is 37,748,736-bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output enable
and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored
by an edge triggered output register and then released to the out-
put buffers at the next rising edge of clock.
The K7N327245M are implemented with SAMSUNG′s high per-
formance CMOS technology and is available in 209BGA pack-
ages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
• 2.5V ±5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 209BGA(11x19 Ball Grid Array Package).
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
LOGIC BLOCK DIAGRAM
WE
BWx
CLK
CKE
CS1
CS2
CS2
ADV
OE
ZZ
DQa0 ~ DQh7
ADDRESS
ADDRESS
REGISTER
CONTROL
LOGIC
A′0~A′1
72
DQPa ~ DQPh
OUTPUT
BUFFER
REGISTER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
CONTROL
REGISTER
K
A [0:18]
LBO
A2~A18
A0~A1
(x=a ~ h)
512K x 72
MEMORY
ARRAY
FAST ACCESS TIMES
PARAMETER Symbol -25 -22 -20 -16 -15 -13 Unit
Cycle Time tCYC 4.0 4.4 5.0 6.0 6.7 7.5 ns
Clock Access Time tCD 2.6 2.8 3.2 3.5 3.8 4.2 ns
Output Enable Access Time tOE 2.6 2.8 3.2 3.5 3.8 4.2 ns
512Kx72 Pipelined NtRAMTM
- 4 - Rev 0.1
December 2001
K7N327245M Preliminary
209BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
PIN NAME
SYMBOL PIN NAME SYMBOL PIN NAME
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a~h)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
DQPa~Ph
VDDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
K7N327245M(512K x 72)
Notes : 1. ** A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
12345678910 11
ADQg DQg ACS2AADV ACS2ADQb DQb
BDQg DQg BWcBWgNC WE ABWbBWfDQb DQb
CDQg DQg BWhBWdNC CS1NC BWeBWaDQb DQb
DDQg DQg VSS NC NC OE NC NC VSS DQb DQb
EDQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb
FDQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
GDQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf
HDQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
JDQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf
KNC NC CLK NC VSS CKE VSS NC NC NC NC
LDQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa
MDQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa
NDQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa
PDQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa
RDQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe
TDQd DQd VSS NC NC LBO NC NC VSS DQe DQe
UDQd DQd NC ANC(64M) AAANC DQe DQe
VDQd DQd A A A A1** A A A DQe DQe
WDQd DQd TMS TDI A A0** ATDO TCK DQe DQe
512Kx72 Pipelined NtRAMTM
- 5 - Rev 0.1
December 2001
K7N327245M Preliminary
FUNCTION DESCRIPTION
BURST SEQUENCE TABLE (Interleaved Burst, LBO=High)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst, LBO=Low)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
The K7N327245M is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[h:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
512Kx72 Pipelined NtRAMTM
- 6 - Rev 0.1
December 2001
K7N327245M Preliminary
STATE DIAGRAM FOR NtRAMTM
BEGIN
WRITE
BURST
WRITE
BEGIN
READ
WRITE
DS
READ
BURST
READ
DS
WRITE
DS
READ
DS
READ
DS
WRITE
BURST
DESELECT
BURST
READ
BURST
WRITE
READ WRITE
BURST BURST
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
COMMAND ACTION
DS DESELECT
READ BEGIN READ
WRITE BEGIN WRITE
BURST BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
512Kx72 Pipelined NtRAMTM
- 7 - Rev 0.1
December 2001
K7N327245M Preliminary
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS2ADV WE BWxOE CKE CLK ADDRESS ACCESSED OPERATION
HX X LX X X L↑N/A Not Selected
XLXLX X X L↑N/A Not Selected
X X HLX X X L↑N/A Not Selected
XXXHX X X L↑N/A Not Selected Continue
LHL L HXLL↑External Address Begin Burst Read Cycle
XXXHX X LL↑Next Address Continue Burst Read Cycle
LHL L HXHL↑External Address NOP/Dummy Read
XXXHX X HL↑Next Address Dummy Read
LHL L L L XL↑External Address Begin Burst Write Cycle
XXXHXLXL↑Next Address Continue Burst Write Cycle
LHL L L HXL↑N/A NOP/Write Abort
XXXHXHXL↑Next Address Write Abort
X X X X X X X H↑Current Address Ignore Clock
TRUTH TABLES
WRITE TRUTH TABLE(x72)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WE BWaBWbBWcBWdBWeBWf BWgBWhOPERATION
HXXXXXXXX READ
L L HHHHHHH WRITE BYTE a
LHLHHHHHH WRITE BYTE b
LH H LHHHHH WRITE BYTE c
LHHHLH H H H WRITE BYTE d
LHHHHLH H H WRITE BYTE e
LHHHHHLH H WRITE BYTE f
LHHHHHHLHWRITE BYTE g
LHHHHHHHLWRITE BYTE h
LLLLLLLLL WRITE ALL BYTEs
LHHHHHHHH WRITE ABORT/NOP
512Kx72 Pipelined NtRAMTM
- 8 - Rev 0.1
December 2001
K7N327245M Preliminary
ASYNCHRONOUS TRUTH TABLE
OPERATION ZZ OE I/O STATUS
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 3.6 V
Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Power Dissipation PD1.6 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TOPR 0 to 70 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
OPERATING CONDITIONS(0°C ≤ TA ≤ 70°C)
*Note : VDD and VDDQ must be supplied with identical vlotage levels.
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 2.375 2.5 2.625 V
VDDQ 2.375 2.5 2.625 V
Ground VSS 000V
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION MIN MAX UNIT
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT=0V -7pF
512Kx72 Pipelined NtRAMTM
- 9 - Rev 0.1
December 2001
K7N327245M Preliminary
(TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified)
TEST CONDITIONS
PARAMETER VALUE
Input Pulse Level 0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80%) 1.0V/ns
Input and Output Timing Reference Levels VDDQ/2
Output Load See Fig. 1
VSS
VIH
VSS-0.8V
20% tCYC(MIN)
DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C)
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, -2 +2 µA
Operating Current ICC VDD=Max IOUT=0mA
Cycle Time ≥ tCYC Min
-25 -TBD
mA 1,2
-22 -TBD
-20 -TBD
-16 -TBD
-15 -TBD
-13 -TBD
Standby Current
ISB
Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-25 -TBD
mA
-22 -TBD
-20 -TBD
-16 -TBD
-15 -TBD
-13 -TBD
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V) -TBD mA
ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH -TBD mA
Output Low Voltage VOL IOL=1.0mA -0.4 V
Output High Voltage VOH IOH=-1.0mA 2.0 -V
Input Low Voltage VIL -0.3* 0.7 V
Input High Voltage VIH 1.7 VDD+0.3** V3
512Kx72 Pipelined NtRAMTM
- 10 - Rev 0.1
December 2001
K7N327245M Preliminary
(VDD=2.5V ±5%, TA=0 to 70°C)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
1538Ω5pF*
+2.5V
1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=VDDQ/2
30pF*
AC TIMING CHARACTERISTICS
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER SYMBOL -25 -22 -20 -16 -15 -13 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Cycle Time tCYC 4.0 -4.4 -5.0 -6.0 -6.7 -7.5 -ns
Clock Access Time tCD -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 ns
Output Enable to Data Valid tOE -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 ns
Clock High to Output Low-Z tLZC 1.5 -1.5 -1.5 -1.5 -1.5 -1.5 -ns
Output Hold from Clock High tOH 1.5 -1.5 -1.5 -1.5 -1.5 -1.5 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-0-0-0-ns
Output Enable High to Output High-Z tHZOE -2.6 -2.8 -3.0 -3.0 -3.0 -3.5 ns
Clock High to Output High-Z tHZC -2.6 -2.8 -3.0 -3.0 -3.0 -3.5 ns
Clock High Pulse Width tCH 1.7 -2.0 -2.0 -2.2 -2.5 -3.0 -ns
Clock Low Pulse Width tCL 1.7 -2.0 -2.0 -2.2 -2.5 -3.0 -ns
Address Setup to Clock High tAS 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
CKE Setup to Clock High tCES 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
Data Setup to Clock High tDS 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
Write Setup to Clock High (WE, BWX)tWS 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
Address Advance Setup to Clock High tADVS 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
Chip Select Setup to Clock High tCSS 1.2 -1.4 -1.4 -1.5 -1.5 -1.5 -ns
Address Hold from Clock High tAH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
CKE Hold from Clock High tCEH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
Data Hold from Clock High tDH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
Write Hold from Clock High (WE, BWX)tWH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.3 -0.4 -0.4 -0.5 -0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-2-2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-2-2-2-cycle
512Kx72 Pipelined NtRAMTM
- 11 - Rev 0.1
December 2001
K7N327245M Preliminary
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS
Current during SLEEP MODE ZZ ≥ VIH ISB2 10 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SLEEP current tZZI 2cycle
ZZ inactive to exit SLEEP current tRZZI 0
K
tPDS
ZZ setup cycle
tRZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
tZZI
tPUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON′T CARE
ISB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
512Kx72 Pipelined NtRAMTM
- 12 - Rev 0.1
December 2001
K7N327245M Preliminary
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
01 1 1
1
00
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 BYPASS Bypass Register 4
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 BYPASS Bypass Register 4
1 1 1 BYPASS Bypass Register 4
512Kx72 Pipelined NtRAMTM
- 13 - Rev 0.1
December 2001
K7N327245M Preliminary
Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don′t care).
BIT PIN ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
BOUNDARY SCAN EXIT ORDER
ID REGISTER DEFINITION
Part Revision Number
(31:28) Part Configuration
(27:18) Vendor Definition
(17:12) Samsung JEDEC Code
(11: 1) Start Bit(0)
512Kx72 0000 00111 00101 XXXXXX 00001001110 1
SCAN REGISTER DEFINITION
Part Instruction Register Bypass Register ID Register Boundary Scan
512Kx36 3 bits 1 bits 32 bits 123 bits
BIT PIN ID
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
BIT PIN ID
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
TBD
512Kx72 Pipelined NtRAMTM
- 14 - Rev 0.1
December 2001
K7N327245M Preliminary
JTAG DC OPERATING CONDITIONS
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 2.4 2.5 2.6 V
Input High Level VIH 1.7 -VDD+0.3 V
Input Low Level VIL -0.3 -0.7 V
Output High Voltage VOH 2.0 - - V
Output Low Voltage VOL - - 0.4 V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 -ns
TCK High Pulse Width tCHCL 20 -ns
TCK Low Pulse Width tCLCH 20 -ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Time tCHSX 5-ns
Clock Low to Output Valid tCLQV 010 ns
JTAG AC TEST CONDITIONS
Parameter Symbol Min Unit Note
Input High/Low Level VIH/VIL 2.5/0 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level VDDQ/2 V
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
512Kx72 Pipelined NtRAMTM
- 15 - Rev 0.1
December 2001
K7N327245M Preliminary
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tCES tCEH
tAS tAH
A1 A2 A3
tWS tWH
tCSS tCSH
tOE tHZOE
tLZOE
tCD
tOH tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1Q1-1
Don′t Care
Undefined
tCYC
tADVS tADVH
512Kx72 Pipelined NtRAMTM
- 16 - Rev 0.1
December 2001
K7N327245M Preliminary
TIMING WAVEFORM OF WRTE CYCLE
Clock
Address
WRITE
CS
ADV
Data In
tCH tCL
A2 A3
D2-1D1-1 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3
OE
Data Out
tDS tDH
Don′t Care
Undefined
tCYC
CKE
A1
D3-4
tCES tCEH
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Q0-4
tHZOE
Q0-3
512Kx72 Pipelined NtRAMTM
- 17 - Rev 0.1
December 2001
K7N327245M Preliminary
TIMING WAVEFORM OF SINGLE READ/WRITE
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
tDS tDH
Data Out
A2 A4 A5
D2
tOE
tLZOE
Q1
Don′t Care
Undefined
tCYC
CKE
tCES tCEH
A1 A3 A7A6
Q3 Q4 Q7Q6
D5
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
A9
A8
512Kx72 Pipelined NtRAMTM
- 18 - Rev 0.1
December 2001
K7N327245M Preliminary
TIMING WAVEFORM OF CKE OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1 A2 A3 A4 A5
tCES tCEH
Don′t Care
Undefined
tCYC
CKE
tDS tDH
D2
Q4Q1
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCD
tLZC tHZC
Q3
A6
512Kx72 Pipelined NtRAMTM
- 19 - Rev 0.1
December 2001
K7N327245M Preliminary
TIMING WAVEFORM OF CS OPERATION
Clock
Address
WRITE
CS
ADV
OE
Data In
tCH tCL
Data Out
A1 A2 A3 A4 A5
Don′t Care
Undefined
tCYC
CKE
D5
Q4
tCES tCEH
Q1 Q2
tOE
tLZOE
D3
tCD
tLZC
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tHZC
tDH
tDS
512Kx72 Pipelined NtRAMTM
- 20 - Rev 0.1
December 2001
K7N327245M Preliminary
209 Bump BGA PACKAGE DIMENSIONS
14mm x 22mm Body, 1.0mm Bump Pitch, 11x19 Bump Array
209-∅0.06±0.10
1.00(BSC)
12.50
0.50±0.05
0.90
C1.00 C0.70
14.00
22.00
20.50±0.05
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset: 0.10 MAX.
3. PCB to Cavity Offset: 0.10 MAX.
Indicator of
Ball(1A) Location
1.00x10=10.00(BSC)
1.00(BSC)
1.00x18=18.00(BSC)
1.50
2.20 MAX
