Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH(min)/tLZC(min) from 0.8 to 1.5 at -25 tOH(min)/tLZC(min) from 1.0 to 1.5 at -22 tOH(min)/tLZC(min) from 1.0 to 1.5 at -20 May. 10. 2001 Dec. 31. 2001 Preliminary Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M 32Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Information Org. Part Number Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) K7M321825M-Q(H/F)C65/75/85 FlowThrough 3.3 6.5/7.5/8.5ns 2Mx18 K7N321801M-Q(H/F)C25/22/20/16/15/13 Pipelined 3.3 250/225/200/167/150/133MHz K7N321845M-Q(H/F)C25/22/20/16/15/13 Pipelined 2.5 250/225/200/167/150/133MHz K7M323625M-Q(H/F)C65/75/85 FlowThrough 3.3 6.5/7.5/8.5ns 1Mx36 K7N323601M-Q(H/F)C25/22/20/16/15/13 Pipelined 3.3 250/225/200/167/150/133MHz K7N323645M-Q(H/F)C25/22/20/16/15/13 Pipelined 2.5 250/225/200/167/150/133MHz K7N327245M-HC25/22/20/16/15/13 Pipelined 2.5 (Normal Type) 250/225/200/167/150/133MHz K7Z327285M-HC27/25 Pipelined (Sigma Type) -2- Temp Q:100TQFP H:119BGA F:165FBGA C (Commercial Temperature Range) H : 209BGA 512Kx72 1.8 PKG 275/250MHz December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M 512Kx72-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION * 2.5V 5% Power Supply. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no data contention . * A interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 209BGA(11x19 Ball Grid Array Package). FAST ACCESS TIMES PARAMETER Symbol -25 -22 -20 -16 -15 -13 Unit Cycle Time tCYC 4.0 4.4 5.0 6.0 6.7 7.5 ns Clock Access Time tCD 2.6 2.8 3.2 3.5 3.8 4.2 ns Output Enable Access Time tOE 2.6 2.8 3.2 3.5 3.8 4.2 ns The K7N327245M is 37,748,736-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N327245M are implemented with SAMSUNGs high performance CMOS technology and is available in 209BGA packages. Multiple power and ground pins minimize ground bounce. LOGIC BLOCK DIAGRAM LBO A [0:18] CKE CONTROL LOGIC CLK ADDRESS REGISTER A2 ~A18 ADV WE BW x (x=a ~ h) WRITE ADDRESS REGISTER K CONTROL REGISTER CS1 CS2 CS2 BURST ADDRESS COUNTER A0 ~A1 A0 ~A1 512K x 72 MEMORY ARRAY WRITE ADDRESS REGISTER CONTROL LOGIC K DATA-IN REGISTER K DATA-IN REGISTER K OUTPUT REGISTER BUFFER OE ZZ 72 DQa0 ~ DQh7 DQPa ~ DQPh NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung. -3- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M 209BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7N327245M(512K x 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CS2 A ADV A CS 2 A DQb DQb B DQg DQg BWc BWg NC WE A BWb BWf DQb DQb C DQg DQg BWh BWd NC CS1 NC BWe BWa DQb DQb D DQg DQg VSS NC NC OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CKE VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC LBO NC NC VSS DQe DQe U DQd DQd NC A NC(64M) A A A NC DQe DQe V DQd DQd A A A A1** A A A DQe DQe W DQd DQd TMS TDI A A0** A TDO TCK DQe DQe Notes : 1. ** A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs BWx (x=a~h) OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQe DQf DQg DQh DQPa~Ph Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -4- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M FUNCTION DESCRIPTION The K7N327245M is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS 1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[h:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 BQ TABLE LBO PIN A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -5- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M STATE DIAGRAM FOR NtRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD I WR ST BUR TE BURST R W D R EA IT E DS BURST READ BURST WRITE COMMAND DS W RI DESELECT ST RE A DS DS BURST TE BU R D DS WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -6- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS2 CS2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L N/A Not Selected X L X L X X X L N/A Not Selected X X H L X X X L N/A Not Selected X X X H X X X L N/A Not Selected Continue L H L L H X L L External Address Begin Burst Read Cycle X X X H X X L L Next Address Continue Burst Read Cycle L H L L H X H L External Address NOP/Dummy Read X X X H X X H L Next Address Dummy Read L H L L L L X L External Address Begin Burst Write Cycle X X X H X L X L Next Address Continue Burst Write Cycle L H L L L H X L N/A NOP/Write Abort X X X H X H X L Next Address Write Abort X X X X X X X H Current Address Ignore Clock Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by (). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE (x72) WE BWa BWb BWc BWd BWe BWf BWg BWh OPERATION H X X X X X X X X READ L L H H H H H H H WRITE BYTE a L H L H H H H H H WRITE BYTE b L H H L H H H H H WRITE BYTE c L H H H L H H H H WRITE BYTE d L H H H H L H H H WRITE BYTE e L H H H H H L H H WRITE BYTE f L H H H H H H L H WRITE BYTE g L H H H H H H H L WRITE BYTE h L L L L L L L L L WRITE ALL BYTEs L H H H H H H H H WRITE ABORT/NOP Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). -7- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Dont Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on V DD Supply Relative to VSS VDD -0.3 to 3.6 V Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V Power Dissipation Storage Temperature PD 1.6 W TSTG -65 to 150 C Operating Temperature TOPR 0 to 70 C Storage Temperature Range Under Bias TBIAS -10 to 85 C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 2.375 2.5 2.625 V VDDQ 2.375 2.5 2.625 V VSS 0 0 0 V *Note : VDD and VDDQ must be supplied with identical vlotage levels. CAPACITANCE*(TA=25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT CIN VIN=0V - 5 pF COUT VOUT=0V - 7 pF *Note : Sampled not 100% tested. -8- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M DC ELECTRICAL CHARACTERISTICS(VDD=2.5V 5%, TA=0C to +70C) PARAMETER SYMBOL Input Leakage Current(except ZZ) IIL VDD=Max ; V IN=VSS to VDD Output Leakage Current IOL Output Disabled, Operating Current ICC TEST CONDITIONS UNIT -2 +2 A A -2 +2 -25 - TBD -22 - TBD -20 - TBD Cycle Time tCYC Min -16 - TBD -15 - TBD -13 - TBD -25 - TBD ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V Standby Current ISB1 MAX VDD=Max IOUT=0mA Device deselected, IOUT=0mA, ISB MIN mA -22 - TBD -20 - TBD -16 - TBD -15 - TBD -13 - TBD - TBD mA - TBD mA Device deselected, IOUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, I OUT=0mA, ZZVDD-0.2V, NOTES 1,2 mA ISB2 f=Max, All InputsVIL or VIH Output Low Voltage VOL IOL=1.0mA - 0.4 V Output High Voltage VOH IOH=-1.0mA 2.0 - V Input Low Voltage VIL -0.3* 0.7 V Input High Voltage VIH 1.7 VDD+0.3** V 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. V IH=VDDQ+0.3V VIH VSS VSS-0.8V 20% tCYC(MIN) TEST CONDITIONS (TA=0 to 70C, VDD=2.5V 5%, unless otherwise specified) PARAMETER VALUE Input Pulse Level 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80%) 1.0V/ns Input and Output Timing Reference Levels VDDQ/2 Output Load See Fig. 1 -9- December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M Output Load(A) Dout Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +2.5V RL=50 VL=VDDQ/2 30pF* Zo=50 1667 Dout 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=2.5V 5%, TA=0 to 70C) PARAMETER SYMBOL -25 -22 MIN MAX MIN -20 MAX MIN -16 MAX MIN -15 MAX MIN -13 MAX MIN MAX UNIT Cycle Time tCYC 4.0 - 4.4 - 5.0 - 6.0 - 6.7 - 7.5 - ns Clock Access Time tCD - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns Output Enable to Data Valid tOE - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns Clock High to Output Low-Z tLZC 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns Output Hold from Clock High tOH 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns Clock High to Output High-Z tHZC - 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns Clock High Pulse Width tCH 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns Clock Low Pulse Width tCL 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns Address Setup to Clock High tAS 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns CKE Setup to Clock High tCES 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Data Setup to Clock High tDS 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Write Setup to Clock High (WE, BWX) tWS 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Address Hold from Clock High tAH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (WE, BWX) tWH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature tLZC is more than t HZC. The specs as shown do not imply bus contention because t LZC is a Min. parameter that is worst case at totally different test conditions (0C,2.625V) than tHZC, which is a Max. parameter(worst case at 70C,2.375V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 10 - December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t ZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL ZZ VIH Current during SLEEP MODE MIN ISB2 MAX UNITS 10 ZZ active to input ignored tPDS 2 ZZ inactive to input sampled tPUS 2 ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI mA cycle cycle 2 cycle 0 SLEEP MODE WAVEFORM K tPDS ZZ setup cycle t PUS ZZ recovery cycle ZZ tZZI Isupply ISB2 t RZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DONT CARE - 11 - December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to V DD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller Instruction TDO Output Notes 0 0 0 EXTEST Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 BYPASS Bypass Register 4 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 BYPASS Bypass Register 4 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to V SS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 Exit2 DR 1 1 Update DR 0 - 12 - 1 Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 512Kx36 3 bits 1 bits 32 bits 123 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx72 0000 00111 00101 XXXXXX 00001001110 1 BOUNDARY SCAN EXIT ORDER BIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 PIN ID BIT PIN ID BIT PIN ID 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 D B T Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. dont care). - 13 - December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M JTAG DC OPERATING CONDITIONS Symbol Min Typ Max Unit Power Supply Voltage Parameter VDD 2.4 2.5 2.6 V Input High Level VIH 1.7 - VDD+0.3 V Input Low Level VIL -0.3 - 0.7 V Output High Voltage VOH 2.0 - - V Output Low Voltage VOL - - 0.4 V Note NOTE : The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Symbol Min Unit Input High/Low Level VIH/VIL 2.5/0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns VDDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Symbol Min Max Unit TCK Cycle Time Parameter tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX t CLCH TMS TDI PI (SRAM) tCLQV TDO - 14 - December 2001 Rev 0.1 - 15 - Data Out OE ADV CS WRITE Address CKE Clock A1 tADVH tCSH tWH tAH tLZOE tOE Q1-1 A2 tHZOE tCEH Q2-1 tCD tOH tCYC Q2-2 tCL NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tADVS tCSS tWS tAS tCES tCH Q2-3 A3 TIMING WAVEFORM OF READ CYCLE Q2-4 Q3-1 Q3-2 Q3-3 Undefined Dont Care Q3-4 tHZC K7N327245M Preliminary 512Kx72 Pipelined NtRAMTM December 2001 Rev 0.1 - 16 - Data Out Data In OE ADV CS WRITE Address CKE Clock Q0-4 tHZOE D1-1 A2 tCYC tCL D2-1 D2-2 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-3 A1 tCES tCEH tCH D2-3 A3 TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 tDS D3-2 tDH D3-3 Undefined Dont Care D3-4 K7N327245M Preliminary 512Kx72 Pipelined NtRAMTM December 2001 Rev 0.1 - 17 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A2 Q1 A3 tDS D2 tDH Q3 A4 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L A1 tCES tCEH A5 Q4 A6 D5 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q6 tCYC tCL A8 Q7 A9 Undefined Dont Care K7N327245M Preliminary 512Kx72 Pipelined NtRAMTM December 2001 Rev 0.1 - 18 - Data In A1 tCES tCEH tCD tLZC A2 Q1 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Data Out OE ADV CS WRITE Address CKE Clock tDS A4 D2 TIMING WAVEFORM OF CKE OPERATION tDH tCH Q3 tCYC tCL A5 Q4 A6 Undefined Dont Care K7N327245M Preliminary 512Kx72 Pipelined NtRAMTM December 2001 Rev 0.1 - 19 - Data In Data Out OE ADV CS WRITE Address CKE Clock A1 tCEH tOE tLZOE A2 Q1 Q2 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tCES D3 tDS tDH A4 tCD tLZC TIMING WAVEFORM OF CS OPERATION Q4 A5 tCH tCYC tCL D5 Undefined Dont Care K7N327245M Preliminary 512Kx72 Pipelined NtRAMTM December 2001 Rev 0.1 Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M 209 Bump BGA PACKAGE DIMENSIONS 14mm x 22mm Body, 1.0mm Bump Pitch, 11x19 Bump Array 1.00x10=10.00(BSC) 14.00 1.00(BSC) 20.500.05 22.00 C1.00 1.00x18=18.00(BSC) 1.00(BSC) Indicator of Ball(1A) Location C0.70 2.20 MAX 1.50 12.50 0.90 0.500.05 209-0.060.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset: 0.10 MAX. 3. PCB to Cavity Offset: 0.10 MAX. - 20 - December 2001 Rev 0.1