Page 1 of 4
Document No. 70-0226-01 www. pse mi.com ©2007 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
The PE42632 is a HaRP™-enhanced SP6T
RF Switch developed on the UltraCMOS™
process technology. This 50 switch
addresses the specific design needs of the
Quad-Band GSM Handset Antenna Switch
Module Market. On-chip CMOS decode logic
fa cilitates three -pin low voltage CMOS cont rol.
High ESD tolerance of 1500 V at all ports, no
blocking capacitor requirements and on-chip
SAW filter over-voltage protection devices
make this the ultimate in integration and
ruggedness.
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
proc es s , pr ov i ding perf or m a nc e su per i or to
GaAs with th e ec o nom y and in te gr ation of
conventional CMOS.
Product Brief
SP6T UltraCMOS™ 2.70 V Switch
100 – 3000 MH z, 50
Product Description
Figure 1. Functional Diagram
PE42632 Flip Chip
Features
Three pin CMOS logic control with
integral decoder/driver
Low TX insertion loss: 0.55 dB at
900 MH z, 0.60 dB at 190 0 MHz
TX – RX Isolation of 38 dB at 900 MHz,
31 dB at 1900 MHz
Low har m o ni cs : 2fo = -90 dBc and
3fo = -82 dBc
1500 V HBM ESD tol er ance all por ts
41 dBm P1 dB, TX paths
No blocking capacitors required
RoHS compliant lead-f ree solder balls
Figure 2. Die Top View
RX1
RX2
RX3RX4
TX1
TX2
V2
V3
V1
CMOS
Control/
Driver
and ESD
8 7
5
6
11
13
2
14
10 3
9
4
1
12
15
16
TX1
GND
TX2
RX1
V
DD
V1
V2
V3
GND
RX4 RX3 RX2
GND
GND
GND ANT
PE4263 2 Die
Figure 3. Package Type: Flip Chip
Product Brief
PE42632
Page 2 of 4
©2007 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0226-01 UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Table 2. Opera ti ng Ranges Table 3. Absolute Max imum Rati ngs
Part perf or m anc e is not guar anteed under t hes e
conditi ons . Expos ur e to absolut e maximum c onditions
for extended per iods of time may adversely aff ec t
reliability . Stress es in exces s of absolute maxim um
rati ngs m ay c aus e per m anent damage.
Table 1. Electrical Specifications @ +25 °C, VDD = 2.5 - 2.8 V (ZS = ZL = 5 0 )
Parameter Conditions Typical Units
Operational Frequency 100-3000 MHz
Inser t io n Loss 1
ANT - TX - 850 / 900 MHz
ANT - TX - 1800 / 1900 MHz
ANT - RX - 850 / 900 MHz
ANT - RX - 1800 / 1900 MHz
0.55
0.6
0.9
1.15
dB
dB
dB
dB
Isolation
TX - RX - 850 / 900 MHz
TX - RX - 1800 / 1900 MHz
TX - TX - 850 / 900 MHz
TX - TX - 1800 / 1900 MHz
38
31
31
26
dB
dB
dB
dB
Return Loss 850 / 90 0 MHz
1800 / 19 00 MH z 23
22 dB
2nd Harmonic2,3 35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz -90
-89 dBc
3rd Harmonic2,3 35 dBm TX Input - 850 / 900 MHz
33 dBm TX In put - 1800 / 1900 MHz -82
-80 dBc
Switching Time4 50% Control Logic to 90% RF 1 µs
Notes : 1. Ins ertio n los s spec i fied w it h optim al ANT imp edance matchi ng.
2. Measured in Pulsed Wave Mode.
3. Assumes RF inp ut duty cycle of 50% a nd 4620 µs, meas ured per 3G PP TS 45.00 5
4. Pow e r on any por t mus t no t exc e ed + 20 dB m durin g sw itching eve nt.
Note: 5. Assumes RF input period of 4620 µs an d duty cy c le of 5 0%.
Parameter Symbol Min Typ Max Units
Temperature range TOP -40 +85 °C
VDD Supply V ol t age VDD 2.5 2.70 2.8 V
IDD Power Sup ply Current
(VDD = 2. 75 V ) IDD 13 20 µA
TX i nput power5 (VSWR 3:1)
824-915 MHz +35 dBm
TX i nput power5 (VSWR 3:1)
1710-1910 M Hz +33
RX input po wer5 (VSWR =1:1) PIN +20 dBm
Control V ol tage Hi gh VIH 0.7 x
VDD V
Control V ol tage L ow VIL 0.3 x
VDD V
PIN
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any DC input -0.3 VDD+
0.3 V
TST Storage temperature range -65 +150 °C
TOP Operating temperature range -40 +85 °C
PIN (50 )
TX input power (50 )6,7
824-915 MHz +38
dBm
TX input power (50 )6,7
1710-1910 MHz +36
RX input power (50 )7 +23
PIN (:1)
TX input pow er (VSWR = (:1)6,7
824-915 MHz +35
dBm
dBm
TX input pow er (VSWR = (:1)6,7
1710-1910 MHz +33
VESD
ESD Voltage (HBM, MIL_STD
883 Method 30 15 . 7) 1500 V
ESD Voltage (MM, JEDEC,
JESD22-A114-B) 100 V
Notes: 6. Assumes RF input period of 4620 µs and duty cycle of 50%.
7. VDD within operating range specified in Table 2.
Product Brief
PE42632
Page 3 of 4
Document No. 70-0226-01 www. pse mi.com ©2007 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latc h-Up Avoidance
Unlike conv ent ional CMOS d evices, UltraCMO S
devices are immune to latch-up.
Table 5. Truth Table
Table 6. Ordering Information
Table 4. Pin Descriptions Figure 4. Pad Configuration (Top View)
Path V3 V2 V1
ANT - TX1 0 1 1
ANT - TX2 0 0 1
ANT – RX1 1 1 0
ANT – RX2 0 1 0
ANT – RX3 1 0 0
ANT – RX4 0 0 0
8 7
5
6
11
13
2
14
10 3
9
4
1
12
15
16
TX1
GND
TX2
RX1
V
DD
V1
V2
V3
GND
RX4 RX3 RX2
GND
GND
GND ANT
PE4263 2 Die
Pin No. Pin Name Description
1 TX18 RF I/O – TX1
2 GND TX Ground
3 TX28 RF I/O – TX2
4 RX18 RF I/O – RX1
5 RX28 RF I/O – RX2
6 RX38 RF I/O – RX3
7 RX48 RF I/O – RX4
8 GND RX Ground
9 V3 Switch co ntrol input , CMOS logic l evel
10 V2 Switch control input, CMOS logic level
11 V1 Switch control input, CMOS logic level
12 VDD Supply
13 GND DC Ground
14 ANT8 RF Common - Antenna
15 GND DC Ground
16 GND DC Ground
Note: 8. Blocking capa citors needed only when non-zero DC
voltage present
Order Code Description Package Ship pin g Met hod
PE42632DTI PE42632-DIE-D Bumped Wafer on Film Frame Wafer (Gross Die / Wafer Quantity)
PE42632DBI PE42632-DIE-400G Die in Waffle Pac k 400 Dice / Waffle Pack
EK-42632-01 PE42632-DIE-1H Evaluation Kit 1/ box
Product Brief
PE42632
Page 4 of 4
©2007 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0226-01 UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
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San Diego, CA 92121
Tel: 858-731-9400
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Europe
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timent Maine
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Tel: +33-1-4741-9173
Fax : +33-1 -4741 -917 3
For a list of representat ives in your area, please r efer to our W eb site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specificat ions f or product
development. Spec ifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains pr eliminary data. Addit ional data
may be added at a later date. Peregrine reserves the right
to change specifications at any tim e without notice in order
to supply t he best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
cust omers of the intended changes by issu ing a DCN
(Document Change Notice).
The information in this data sheet is believed t o be reliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entir ely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted t o any third party.
Peregrine’s pr oducts are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Per egrine product could
create a situation in which personal injury or death m ight occur.
Peregr ine assumes no liability for damages, including
consequential or incident al dam ages, arising out of the use of
its products in such applications .
The Peregr ine nam e, logo, and UTSi are registered t r ademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
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