MAY 2002
DSC-5294/03
1
©2002 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
Features
◆◆
◆◆
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OE
◆◆
◆◆
◆Single R/WW
WW
W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
◆◆
◆◆
◆Optional Boundary Scan JTAG Interface (IEEE1149.1
complaint)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
A0-A17 Ad d re s s Inp uts Inp ut Sy nc hro no us
CE1, CE2, CE2Chip Enab les Input Synchro nous
OE Outp ut Enab le Inp ut As ync hro no us
R/WRead/Write Signal Input Synchro nous
CEN Clo ck Enab le Input Synchro no us
BW1, BW2, BW3, BW4Indi vid ual B yte Write Se le c ts Input Sy nchro no us
CLK Clock Input N/A
ADV/LD A d v ance b urst ad dress / Lo ad ne w ad d res s Input Synchro no us
LBO Line ar / Interle ave d Burst Order Input Static
TMS Test Mode Select Input Synchronous
TDI Test Data Input Input Synchronous
TCK Test Clock Input N/A
TDO Te s t Data Ou tp ut Outp ut S y nc hro n o us
TRST JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Synchronous
I/O0-I/O31, I/OP1-I/OP4 Da ta Inp u t / Outp u t I/ O S y nc hro n o us
VDD, VDDQ Core Po wer, I/O Po wer Sup p ly Static
VSS Ground Supply Static
5294 tbl 01
IDT71V2546S
IDT71V2548S
IDT71V2546SA
IDT71V2548SA
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546/48 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546/48 has an on-chip burst counter. In the burst mode,
the IDT71V2546/48 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
6.42
2
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A0-A17 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD lo w, CEN lo w, and true chip enab le s.
ADV/LD Ad vanc e / Lo ad I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled
high.
R/WRe ad / Write I N/ A R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the
low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of
clock.
BW1-BW4Individual Byte
Write Enables I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(Whe n R/W and ADV/ LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appropriate byte(s) of data are written into the de vice two cycles later. BW1-BW4 can all be
tied low if always doing write to the entire 36-bit word.
CE1, CE2Chip Enable s I LOW Sy nchro no us active low c hip e nable . CE1 and CE2 are used with CE2 to enable the IDT71V2546/48. ( CE1 or
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZB TTM has a two cycle de select, i.e., the d ata bus will tri-state two clo ck cycles after d eselect is initiated.
CE2Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable th e chip. C E2 has inverted
polarity but otherwise identical to CE1 and CE2.
CLK Clo ck I N/A This is the clo ck inp ut to the IDT71V 2546/ 48. Exce pt fo r OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE Output Enab le I LOW Asynchrono us o utp ut enab le . OE m us t be lo w to re ad d ata fro m the 71V 2546/ 48 . Whe n OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Tes t Data Inp ut I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are d rive n fro m the falling edge of TCK. This pin has an internal pullup.
TDO Te s t Data Outp ut O N/ A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST JTAG Reset
(Optional) ILOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup.
ZZ Sleep Mode I HIGH Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V2546/2548 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Po we r S up ply N/ A N/A 2.5V I/ O Sup p ly.
VSS Ground N/A N/A Ground.
5294 tbl 02
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
Input Register
5294 drw 01a
Clock
Data I/O [0:31],
I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 128Kx36 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
6.42
4
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:17]
Control Logic
Address
Control
DI DO
Input Register
5294 drw 01b
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 256x18 BIT
MEMORY ARRAY
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Supply Voltage
3.135
3.3
3.465
V
V
DDQ
I/O Supply Voltage
2.375
2.5
2.625
V
V
SS
Supp ly Voltage
0
0
0
V
V
IH
Input High Voltage - Inputs
1.7
____
V
DD
+0.3
V
V
IH
Inp u t Hig h Vo l tag e
-
I/O
1.7
____
V
DDQ
+0.3
(2)
V
V
IL
Inp u t Lo w Vo l tage
-0.3
(1) ____
0.7
V
5294 tbl 03
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Pin Configuration 128K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
Top View
100 TQFP
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
5294 drw 02
VDD(1)
I/O15
I/OP3
VDD(1)
I/OP4
A
15
A
16
I/OP1
VDD(1)
I/OP2
VSS/ZZ(3)
,
NC
NC
NC
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rcial 0° C to +70° C 0V 3.3V ± 5% 2. 5V±5%
Ind ustrial -40°C to +85° C 0V 3.3V±5% 2.5V± 5%
5 294 t b l 05
NOTE:
1. TA is the "instant on" case temperature.
6.42
6
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration 256K x 18
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long
as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial &
Industri al Values
Unit
VTERM(2) Te rminal Vo ltage with
Re s p e ct to GND -0.5 to +4.6 V
VTERM(3,6) Te rminal Voltag e with
Re s p e ct to GND -0.5 to VDD V
VTERM(4,6) Te rminal Voltag e with
Re s p e ct to GND -0.5 to VDD +0.5 V
VTERM(5,6) Te rminal Voltag e with
Re s p e ct to GND -0.5 to VDDQ +0.5 V
TA(7)
Commercial
Operating Temperature -0 to +70 oC
Industrial
Operating Temperature -40 to +85 oC
TBIAS Temperature
Under Bias -55 to +125 oC
TSTG Storage
Temperature -55 to +125 oC
PTPo we r Dis sip atio n 2. 0 W
IOUT DC Outp ut Curre nt 50 mA
5 294 t bl 06
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
5294 drw 02a
VDD(1)
NC
NC
VDD(1)
NC
A
16
A
17
NC
VDD(1)
A10
VSS/ZZ(3)
,
NC
NC
NC
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp u t Cap ac itanc e V IN = 3dV 5 pF
CI/O I/ O Cap ac itanc e VOUT = 3dV 7 pF
5294 tbl 07
100 TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap ac itance V IN = 3dV 7 pF
CI/O I/ O Cap ac itanc e VOUT = 3dV 7 pF
5294 t bl 07a
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap ac itanc e V IN = 3dV TBD pF
CI/O I/ O Cap ac itanc e VOUT = 3dV TBD pF
5294 t b l 07 b
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
1234567
AVDDQ A6A4A8A16 VDDQ
BNC CE2A3ADV/LD A9CE2NC
CA7A2VDD A12 A15 NC
DI/O16 I/OP3 VSS NC VSS I/OP2 I/O15
EI/O17 I/O18 VSS VSS I/O13 I/O14
FVDDQ I/O19 VSS OE VSS I/O12 VDDQ
GI/O20 I/O21 BW3BW2I/O11 I/O10
HI/O22 I/O23 VSS R/WVSS I/O9I/O8
JVDDQ VDD VDD VDD VDDQ
KI/O24 I/O26 VSS CLK VSS I/O6I/O7
LI/O25 I/O27 BW4NC BW1I/O4I/O5
MVDDQ I/O28 VSS CEN VSS I/O3VDDQ
NI/O29 I/O30 VSS A1VSS I/O2I/O1
PI/O31 I/OP4 VSS A0VSS I/O0I/OP1
RNC A5LBO VDD A13
TNC NC A10 A11 A14 NC NC/ZZ(5)
UVDDQ NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4) VDDQ
5294 drw 13a
VDD(1)
NC
NC(2)
CE1
NC(2)
VDD(1) VDD(1)
,
NC
1234567
AVDDQ A6A4NC(2) A8A16 VDDQ
BNC CE2 A3ADV/LD A9CE2NC
CA7A2VDD A13 A17 NC
DI/O8NC VSS NC VSS I/O7NC
ENC I/O9VSS VSS NC I/O6
FVDDQ NC VSS OE VSS I/O5VDDQ
GNC I/O10 BW2NC I/O4
HI/O11 NC VSS R/WVSS I/O3NC
JVDDQ VDD VDD VDD VDDQ
KNC I/O12 VSS CLK VSS NC I/O2
LI/O13 NC NC BW1I/O1NC
MVDDQ I/O14 VSS CEN VSS NC VDDQ
NI/O15 NC VSS A1VSS I/O0NC
PNC I/OP2 VSS A0VSS NC I/OP1
RNC A5LBO VDD A12
TNC A10 A15 NC A14 A11 NC/ZZ(5)
UVDDQ NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4) VDDQ
5294 drw 13b
NC
DD(1)
V
VSS
VSS
CE1
NC(2)
VDD(1) VDD(1)
,
NC
Pin Configuration 128K x 36, 119 BGA
Pin Configuration 256K x 18, 119 BGA
Top View
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
8
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
Pin Configuration - 256K x 18, 165 fBGA
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 supports ZZ (sleep mode) on the latest die revision.
1234567891011
ANC
(2)
A7CE1 BW3BW2CE2CEN ADV/LD NC
(2)
A8NC
BNC A
6CE2BW4BW1CLK R/WOE NC
(2)
A9NC
(2)
CI/O
P3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2
DI/O
17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14
EI/O
19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12
FI/O
21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10
GI/O
23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9I/O8
HV
DD
(1)
VDD
(1)
NC VDD VSS VSS VSS VDD NC NC NC/ZZ
(5)
JI/O
25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7I/O6
KI/O
27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5I/O4
LI/O
29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3I/O2
MI/O
31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1I/O0
NI/O
P4 NC VDDQ VSS NC/TRST
(3,4)
NC VDD
(1)
VSS VDDQ NC I/OP1
PNCNC
(2)
A5A2NC/TDI
(3)
A1NC/TDO
(3)
A10 A13 A14 NC
RLBO NC
(2)
A4A3NC/TMS
(3)
A0NC/TCK
(3)
A11 A12 A15 A16
5294 tb l 25
1234567891011
ANC
(2)
A7CE1BW2NC CE2CEN ADV/LD NC
(2)
A8A10
BNC A
6CE2NC BW1CLK R/WOE NC
(2)
A9NC
(2)
CNC NCV
DDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1
DNC I/O
8VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7
ENC I/O
9VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6
FNCI/O
10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5
GNC I/O
11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4
HV
DD
(1)
VDD
(1)
NC VDD VSS VSS VSS VDD NC NC NC/ZZ
(5)
JI/O
12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3NC
KI/O
13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2NC
LI/O
14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1NC
MI/O
15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0NC
NI/O
P2 NC VDDQ VSS NC/TRST
(3,4)
NC VDD
(1)
VSS VDDQ NC NC
PNC NC
(2)
A5A2NC/TDI
(3)
A1NC/TDO
(3)
A11 A14 A15 NC
RLBO NC
(2)
A4A3NC/TMS
(3)
A0NC/TCK
(3)
A12 A13 A16 A17
5294 tb l 25a
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
CEN
R/
W
Chip
(5)
Enable
ADV/
LD BW
x
ADDRESS
USED
PRE VI OUS CYCLE
CURRE NT CYCL E
I/O
(2 cycl es later)
L L Se le ct L Vali d Exte rnal X LOAD WRITE D(7)
L H Se lect L X Exte rnal X LOAD READ Q(7)
L X X H Valid Inte rnal LOAD WRITE /
BURST WRITE BURST WRITE
(Ad vance b urst co unter)(2) D(7)
L X X H X Inte rnal LOAD READ /
BURS T RE AD BURS T RE AD
(Ad vance b urst co unter)(2) Q(7)
L X De se le c t L X X X DES ELECT or STOP (3) HiZ
L X X H X X DE SELE CT / NOOP NOOP HiZ
H X X X X X X SUSPEND(4) Previous Value
5 294 t bl 08
OPERATION
R/
WBW
1
BW
2
BW
3
(3)
BW
4
(3)
READ HXXXX
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/OP1)(2) LLHHH
WRITE BYTE 2 (I/O[8:15], I/OP2)(2) LHLHH
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3) LHHLH
WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3) LHHHL
NO WRITE L HHHH
5 294 t b l 09
6.42
10
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Functional Timing Diagram(1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
n+29
A29
C29
D/Q27
ADDRESS(2)
(A0 - A16)
CONTROL(2)
(R/W,ADV/LD,BWx)
DATA(2)
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5294 drw 03 ,
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000 110 11
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11000110
52 94 t bl 11
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000 110 11
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11100100
5 294 t bl 10
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation(1)
Device Operation - Showint Mixed Load, Burst,
Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle
Address
R/
W
ADV/
LD CE
(1)
CEN BW
x
OE
I/O
Comments
nA
0HL LLXXXLoad read
n+1 X X H X L X X X Burst read
n+2 A1HL LLXLQ
0Lo ad re ad
n+3 X X L H L X L Q0+1 Deselect or STOP
n+4 X X H XLXLQ
1NOOP
n+5 A2HL LLXXZLoad read
n+6 X X H X L X X Z Burst read
n+7 X X L H L X L Q2Deselect or STOP
n+8 A3L L LLLLQ
2+1 Load write
n+9 X X H X L L X Z Burs t write
n+10 A4L L LLLXD
3Lo ad write
n+11 X X L H L X X D3+1 Deselect or STOP
n+12 X X H X L X X D4NOOP
n+13 A5L L LLLXZLoad write
n+14 A6HL LLXXZLoad read
n+15 A7L L LLLXD
5Lo ad write
n+16 X X H X L L L Q6Burst write
n+17 A8HL LLXXD
7Lo ad re ad
n+18 X X H X L X X D7+1 Burs t re ad
n+19 A9L L LLLLQ
8Lo ad write
5 294 t bl 12
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
nA
0H L L L X X X Ad dre ss and Co ntro l mee t s etup
n+1 X X X X L X X X Clo ck Se tup Valid
n+2 X X X XXXLQ
0Contents of Address A0 Re ad Out
5 294 t bl 13
6.42
12
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Write Operation(1)
Burst Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H XLXLQ
0Address A0 Read Out, Inc. Count
n+3 X X H XLXLQ
0+1 Address A0+1 Read Out, Inc. Count
n+4 X X H XLXLQ
0+2 Address A0+2 Read Out, Inc. Count
n+5 A1HL LLXLQ
0+3 Address A0+3 Read Out, Lo ad A1
n+6 X X H XLXLQ
0Address A0 Read Out, Inc. Count
n+7 X X H XLXLQ
1Address A1 Read Out, Inc. Count
n+8 A2HL LLXLQ
1+1 Address A1+1 Read Out, Lo ad A2
5 294 t bl 14
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
nA
0L L L L L X X Ad dre ss and Control me et se tup
n+1 X X X X L X X X Clo ck Se tup Valid
n+2 X X X X L X X D0Write to Address A0
5 294 t bl 15
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. Count
n+2 X X H X L L X D0Address A0 Write , Inc . Co unt
n+3 X X H X L L X D0+1 Address A0+1 Write , Inc . Co unt
n+4 X X H X L L X D0+2 Address A0+2 Write , Inc . Co unt
n+5 A1 L L LLLXD
0+3 Address A0+3 Write , Lo ad A1
n+6 X X H X L L X D0Address A0 Write, Inc. Count
n+7 X X H X L L X D1Address A1 Write, Inc. Count
n+8 A2L L LLLXD
1+1 Address A1+1 Write , Lo ad A2
5 294 t bl 16
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used(1)
Write Operation with Clock Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Ig nore d
n+2 A1H L L L X X X Clock Valid
n+3 X X X X H X L Q0Clock Ignored. Data Q0 is on the bus.
n+4 X X X X H X L Q0Clock Ignored. Data Q0 is on the bus.
n+5 A2HL LLXLQ
0Address A0 Re ad o ut (b us trans .)
n+6 A3HL LLXLQ
1Address A1 Re ad o ut (b us trans .)
n+7 A4HL LLXLQ
2Address A2 Re ad o ut (b us trans .)
5 294 t bl 17
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Cloc k n+1 Ig nore d.
n+2 A1L L LLLXXClock Valid.
n+3 X X X X H X X X Cloc k Ig nore d.
n+4 X X X X H X X X Cloc k Ig nore d.
n+5 A2L L LLLXD
0Write Data D0
n+6 A3L L LLLXD
1Write Data D1
n+7 A4L L LLLXD
2Write Data D2
5 294 t bl 18
6.42
14
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A0H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A1HL LLXLQ
0Address A0 Read out. Lo ad A 1.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q1Address A1 Read out. Deselected.
n+7 A2H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q2Address A2 Read out. Deselected.
5 294 t bl 19
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A0L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A1L L LLLXD
0Address D0 Write in. Load A1.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D1Address D1 Write in. Deselected.
n+7 A2L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D2Address D2 Write in. Deselected.
5 294 t bl 20
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
(VDDQ = 2.5V)
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(1) (VDD = 3.3V±5%)
Figure 1. AC Test Load
AC Test Loads
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
VDDQ/2
50Ω
I/O Z0=50Ω
5294 drw 04 ,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5294 drw 05 ,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
L
I
|
Input Leakage Current
V
DD
= Max., V
IN
= 0V to V
DD
___
5
µA
|I
LI
|
LBO, JTAG and ZZ
Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30
µA
|I
LO
|
Output Leakage Current
V
OUT
= 0V to V
DDQ
, Device Deselected
___
5
µA
V
OL
Output Low Voltage
I
OL
= +6mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -6mA, V
DD
= Min.
2.0
___
V
5294 t bl 2 1
Symbol Parameter Test Conditions
150MHz 133MHz 100MHz Unit
Com'l Only Com'l Ind Com'l Ind
IDD Operating Power
Supply Current Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX
(2)
325 300 310 250 260 mA
ISB1 CMOS Standb y Po wer
Supply Current Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0
(2,3)
40 40 45 40 45 mA
ISB2 Clo c k Running P o we r
Supply Current Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = fMAX
(2.3)
120 110 120 100 110 mA
ISB3 Id le P o we r
Supply Current Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX
(2,3)
40 40 45 40 45 mA
5294 tbl 22
Inp ut P ul s e Le v e l s
Inp ut Ris e /Fall Time s
Inp ut Timi ng Re fere nce Le ve ls
Outp ut Timing Refe rence Leve ls
AC Te st Load
0 to 2.5V
2ns
(VDDQ/2)
(VDDQ/2)
See Figure 1
5 294 t bl 23
6.42
16
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
150MHz 133MHz 100MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cycle Time 6.7 ____ 7.5 ____ 10 ____ ns
tF
(1)
Clock Frequence ____ 150 ____ 133 ____ 100 MHz
tCH
(2)
Clock High Pulse Width 2.0 ____ 2.2 ____ 3.2 ____ ns
tCL
(2)
Clock Low Pulse Width 2.0 ____ 2.2 ____ 3.2 ____ ns
Output Parameters
tCD Clo ck Hig h to Valid Data ____ 3.8 ____ 4.2 ____ 5ns
tCDC Clo ck Hig h to Data Chang e 1.5 ____ 1.5 ____ 1.5 ____ ns
tCLZ
(3,4,5)
Clo ck Hig h to Outp ut Activ e 1.5 ____ 1.5 ____ 1.5 ____ ns
tCHZ
(3,4,5)
Clo ck Hig h to Data Hig h-Z 1. 5 3 1. 5 3 1.5 3.3 ns
tOE Output Enable Access Time ____ 3.8 ____ 4.2 ____ 5ns
tOLZ
(3,4)
O utp ut Enab le Lo w to Data Ac tive 0 ____ 0____ 0____ ns
tOHZ
(3,4)
O utp ut Enab le Hig h to Data Hig h-Z ____ 3.8 ____ 4.2 ____ 5ns
Set Up Times
tSE Clo c k E nable Se tup Time 1. 5 ____ 1.7 ____ 2.0 ____ ns
tSA Address Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns
tSD Data In Se tup Tim e 1. 5 ____ 1.7 ____ 2.0 ____ ns
tSW Re ad /Write (R/W) Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns
tSADV Ad vanc e/Lo ad (ADV/ LD) Se tup Time 1.5 ____ 1.7 ____ 2.0 ____ ns
tSC Chip Enable/Select Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns
tSB By te Write Enable (BWx) Setup Time 1.5 ____ 1.7 ____ 2.0 ____ ns
Hold Ti mes
tHE Clo c k E nable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHD Data In Ho ld Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
tHW Re ad /Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHADV Ad vanc e /Lo ad (ADV/ LD) Hold Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
tHC Chip Enable/Se lect Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
tHB By te Write Enable (BWx) Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
5294 tbl 24
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
ADV/LD
(CENhigh, eliminates
current L-H clock edge)
O2(A2)
t
CD
t
HADV
Pipeline
Read
(Burst Wraps around
to initial state)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1A2
O1(A2)
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Read
Pipeline
Read
BW
1
-BW
4
5294 drw 06
CE
1
,
CE
2
(2)
Q(A
2+3
)Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
,
6.42
18
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of Write Cycles(1,2,3,4,5)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
OE
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(Burst Wraps around
to initial state)
t
HD
t
SD
(CENhigh, eliminates
current L-H clock edge)
(2)
D(
A2+2
)D(
A2+3
)
D(A
1
)D(A
2
)D(A
2
)
5294 drw 07
BW1-BW4
CE1, CE2
D(A
2+1
)
,
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read
t
CHZ
5294 drw 08
Write
t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
OE
Read
Read
,,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles (1,2,3)
6.42
20
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of CEN Operation(1,2,3,4)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
BW1-BW4
OE
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
5294 drw 09
Q(A
1
)
B(A
2
)
CE
1
,CE
2
(2)
,
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATA
OUT
Q(A
1
)
t
CD
t
CLZ
t
CHZ
t
CDC
t
CH
t
CL
t
CYC
t
HC
t
SC
t
SD
t
HD
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5294 drw 10
Q(A
2
)Q(A
4
)
D(A
3
)
BW1-BW4
CE1, CE2
(2)
,
6.42
22
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs(1)/
TDI/TMS
Device Outputs(2)/
TDO
TRST(
3
)
tJCD
tJDC
tJRST
tJS tJH
tJCYC
tJRSR
tJF tJCLtJR tJCH
M5294 drw 01
x
Symbol Parameter Min. Max. Units
tJCYC JTAG Clock Input Pe rio d 100
____
ns
tJCH JTAG Clock HIGH 40
____
ns
tJCL JTAG Clock Low 40
____
ns
tJR JTAG Clock Rise Time
____
5(1) ns
tJF JTAG Clock Fall Time
____
5(1) ns
tJRST JTAG Reset 50
____
ns
tJRSR JTAG Reset Recovery 50
____
ns
tJCD JTAG Data Outp ut
____
20 ns
tJDC JTA G Data Outp ut Ho ld 0
____
ns
tJS JTAG Setup 25
____
ns
tJH JTAG Hold 25
____
ns
I5294 tbl 01
Reg ister Nam e
Bit Size
Instruction (IR) 4
Bypass (BYR) 1
J TAG Id e ntific atio n (J IDR) 32
Boundary Scan (BSR) Note (1)
I5 2 94 tb l 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instructi on Fi eld Value Descri ption
Revis ion Numbe r (31:28) 0x2 Rese rve d fo r ve rsio n numb er.
IDT De vic e ID (27:12) 0x210, 0x 212 De fines IDT part numb er 71V2546SA and 71V2548SA, resp ective ly.
IDT JE DEC ID (11:1) 0x 33 Allo ws u niq ue id e ntifi c atio n of d evic e ve ndo r as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.
I5294 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction Description OPCODE
EXTEST Forces contents of the bound ary scan cells onto the device outputs
(1)
.
Places the boundary scan registe r (BSR) between TDI and TDO. 0000
SAMPLE/PRELOAD
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the bo undary sc an c ells and shifte d s erially thro ugh TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID Lo ads the JTAG ID re giste r (JIDR) with the ve nd or ID c ode and plac es
the register between TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) be tween TDI and TDO. Forces all
device output drivers to a High-Z state. 0011
RESERVED
Se ve ral c omb inatio ns are re se rve d . Do n ot use c od es o ther than tho se
id e ntifie d fo r EXTES T, SAMPLE /P RELOAD, DEV ICE _ID, HIGHZ, CLAMP,
VALIDATE and BYPASS ins tructio ns.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the bypass registe r (BYR) between TDI and TDO. 1000
RESERVED
Same as above.
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149. 1 sp e cific ation. 1101
RESERVED Same as above. 1110
BYPASS The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length. 1111
I5294 tbl 04
Available JTAG Instructions
6.42
24
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
25
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
26
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
27
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATAOUT
tOHZ tOLZ
tOE
Valid
5294 drw 11 ,
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Power
XX
Speed
XX
Package
PF**
BG
BQ
IDT XXXX
150*
133
100 Clock Frequency in Megahertz
5294 drw 12
Device
Type
IDT71V2546
IDT71V2548 128Kx36 Pipelined ZBT SRAM with 2.5V I/O
256Kx18 Pipelined ZBT SRAM with 2.5V I/O
,
X
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
*Available in commercial range only
** JTAG (SA version) is not available with 100-pin TQFP package
XX
S
SA Standard Power
Standard Power with JTAG Interface
6.42
28
IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726, x4033
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created preliminary datasheet from 71V2556 and 71V2558 datasheets. Changed tCDC, t
tCLZ, andtCHZ minimums from 1.0ns to 1.5ns.
03/04/00 Pg. 1,14, Add 150 MHz speed grade offering
15,22
05/02/00 Pg. 5,6 Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings
tables
Pg. 5,6,7 Clarify note onTQFP and BGA pin configurations; corrected typo in pinout
Pg. 6 Add BGA capacitance table
Pg. 21 Add 100 pin TQFP Package Diagram Outline
05/26/00 Add new package offering, 13 x 15mm 165 fBGA
Pg. 23 Correct 119 BGA Package Diagram Outline
07/26/00 Pg. 5-8 Add ZZ, sleep mode refernce note to BG119, PK100 and BQ165 pinouts
Pg. 8 Update BQ165 pinout
Pg. 23 Update BG119 Package Diagram Outline dimensions
10/25/00 Remove Preliminary status from datasheet
Pg. 8 Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST
05/20/02 Pg. 1-8,15,22,23, Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes
27
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
