100200730002 - ERNI COMPONENTS

ICS9UMS9633B

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

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ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Recommended Application: Features/Benefits:

Poulsbo Based Ultra-Mobile PC (UMPC) • Supports Dothan ULV CPUs with 67 to 167

MHz CPU outputs

• Dedicated TEST/SEL and TEST/MODE pins

saves isolation resistors on pins

• CPU STOP# input for power manangment

• Fully integrated Vreg

• Integrated series resistors on differential

outputs

• 1.5V VDD IO operation, 3.3V VDD core and

REF supply pin for REF

• Industrial Temperature (-40 to +85C) version

available

Output Features:

• 3 - CPU low power differential push-pull pairss

• 3 - SRC low power differential push-pull pairs

• 1 - LCD100 SSCD low power differential

push-pull pair

• 1 - DOT96 low power differential push-pull

pair

• 1 - REF, 14.31818MHz, 3.3V SE output

SSOP Pin Configuration

REF 1 48 VDDREF_3.3

GNDREF 2 47 X1

VDDCORE_3.3 3 46 X2

FSC_L 4 45 CLKPWRGD#/PD_3.3

TEST_MODE 5 44 CPU_STOP#

TEST_SEL 6 43 CPUT0_LPR

SCLK 7 42 CPUC0_LPR

SDATA 8 41 VDDIO_1.5

VDDCORE_3.3 9 40 GNDCPU

VDDIO_1.5 10 39 CPUT1_LPR

DOT96C_LPR 11 38 CPUC1_LPR

DOT96T_LPR 12 37 VDDCORE_3.3

GNDDOT 13 36 VDDIO_1.5

GNDLCD 14 35 GNDCPU

LCD100C_LPR 15 34 CPUT2_LPR

LCD100T_LPR 16 33 CPUC2_LPR

VDDIO_1.5 17 32 FSB_L

VDDCORE_3.3 18 31 *CR#2

*CR#0 19 30 SRCT2_LPR

GNDSRC 20 29 SRCC2_LPR

SRCC0_LPR 21 28 GNDSRC

SRCT0_LPR 22 27 SRCT1_LPR

*CR#1 23 26 SRCC1_LPR

VDDCORE_3.3 24 25 VDDIO_1.5

9UMS9633

* indicates inputs with internal pull up of ~10Kohm to 3.3V

48 SSOP Package

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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SSOP Pin Description

PIN # PIN NAME TYPE DESCRIPTION

1 REF OUT 14.318 MHz reference clock.

2 GNDREF PWR Ground pin for the REF outputs.

3 VDDCORE_3.3 PWR 3.3V power for the PLL core

4FSC_L IN Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

5TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode

while in test mode. Refer to Test Clarification Table.

6 TEST_SEL IN

TEST_SEL: latched input to select TEST MODE

1 = All outputs are tri-stated for test

0 = All outputs behave normally.

7 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.

8 SDATA I/O Data pin for SMBus circuitr

, 3.3V tolerant.

9 VDDCORE_3.3 PWR 3.3V power for the PLL core

10 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

11 DOT96C_LPR OUT Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm

resistor to GND needed. No Rs needed.

12 DOT96T_LPR OUT True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor

to GND needed. No Rs needed.

13 GNDDOT PWR Ground pin for DOT clock output

14 GNDLCD PWR Ground pin for LCD clock output

15 LCD100C_LPR OUT Complement clock of low power differential pair for LCD100 SS clock. No 50ohm

resistor to GND needed. No Rs needed.

16 LCD100T_LPR OUT True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to

GND needed. No Rs needed.

17 VDDIO_1.5 PWR Power suppl

for low power differential outputs, nominal 1.5V.

18 VDDCORE_3.3 PWR 3.3V power for the PLL core

19 *CR#0 IN Clock request for SRC0, 0 = enable, 1 = disable

20 GNDSRC PWR Ground pin for the SRC outputs

21 SRCC0_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

22 SRCT0_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

23 *CR#1 IN Clock request for SRC1, 0 = enable, 1 = disable

24 VDDCORE_3.3 PWR 3.3V power for the PLL core

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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SSOP Pin Description (continued)

PIN # PIN NAME TYPE DESCRIPTION

25 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

26 SRCC1_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

27 SRCT1_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

28 GNDSRC PWR Ground pin for the SRC outputs

29 SRCC2_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

30 SRCT2_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

31 *CR#2 IN Clock request for SRC2, 0 = enable, 1 = disable

32 FSB_L IN Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

33 CPUC2_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

34 CPUT2_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

35 GNDCPU PWR Ground pin for the CPU outputs

36 VDDIO_1.5 PWR Power suppl

for low power differential outputs, nominal 1.5V.

37 VDDCORE_3.3 PWR 3.3V power for the PLL core

38 CPUC1_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

39 CPUT1_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

40 GNDCPU PWR Ground pin for the CPU outputs

41 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

42 CPUC0_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

43 CPUT0_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

44 CPU_STOP# IN Stops all CPU clocks, except those set to be free runnin

clocks

45 CLKPWRGD#/PD_3.3 IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active low input. / Asynchronous

active high input pin used to place the device into a power down state.

46 X2 OUT Crystal output, Nominally 14.318MHz

47 X1 IN Crystal input, Nominally 14.318MHz.

48 VDDREF_3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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MLF Pin Configuration

CPUT0_LPR

CPUC0_LPR

VDDIO_1.5

GNDCPU

CPUT1_LPR

CPUC1_LPR

VDDCORE_3.3

VDDIO_1.5

GNDCPU

CPUT2_LPR

CPUC2_LPR

FSB_L

48 47 46 45 44 43 42 41 40 39 38 37

CPU_STOP# 1 36 *CR#2

CLKPWRGD#/PD_3.3 235

SRCT2_LPR

X2 334

SRCC2_LPR

X1 433

GNDSRC

VDDREF_3.3 532

SRCT1_LPR

REF 631

SRCC1_LPR

GNDREF 730

VDDIO_1.5

VDDCORE_3.3 8 29 VDDCORE_3.3

FSC_L 928

*CR#1

TEST_MODE 10 27 SRCT0_LPR

TEST_SEL 11 26 SRCC0_LPR

SCLK_3.3 12 25 GNDSRC

13 14 15 16 17 18 19 20 21 22 23 24

SDATA_3.3

VDDCORE_3.3

VDDIO_1.5

DOT96C_LPR

DOT96T_LPR

GNDDOT

GNDLCD

LCD100C_LPR

LCD100T_LPR

VDDIO_1.5

VDDCORE_3.3

*CR#0

* indicates inputs with internal pull up of ~10Kohm to 3.3V

48-pin MLF, 6x6 mm, 0.4mm pitch

ICS9UMS9633

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

MLF Pin Description

PIN # PIN NAME TYPE DESCRIPTION

1 CPU_STOP# IN Stops all CPU clocks, except those set to be free running clocks

2 CLKPWRGD#/PD_3.3 IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active low input. / Asynchronous

active high input pin used to place the device into a power down state.

3X2 OUTCr

stal output, Nominall

14.318MHz

4 X1 IN Crystal input, Nominally 14.318MHz.

5 VDDREF_3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V

6 REF OUT 14.318 MHz reference clock.

7 GNDREF PWR Ground pin for the REF outputs.

8 VDDCORE_3.3 PWR 3.3V power for the PLL core

9FSC_L IN Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

10 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode

while in test mode. Refer to Test Clarification Table.

11 TEST_SEL IN

TEST_SEL: latched input to select TEST MODE

1 = All outputs are tri-stated for test

0 = All outputs behave normally.

12 SCLK_3.3 IN Clock pin of SMBus circuitr

, 3.3V tolerant.

13 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.

14 VDDCORE_3.3 PWR 3.3V power for the PLL core

15 VDDIO_1.5 PWR Power suppl

for low power differential outputs, nominal 1.5V.

16 DOT96C_LPR OUT Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm

resistor to GND needed. No Rs needed.

17 DOT96T_LPR OUT True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor

to GND needed. No Rs needed.

18 GNDDOT PWR Ground pin for DOT clock output

19 GNDLCD PWR Ground pin for LCD clock output

20 LCD100C_LPR OUT Complement clock of low power differential pair for LCD100 SS clock. No 50ohm

resistor to GND needed. No Rs needed.

21 LCD100T_LPR OUT True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to

GND needed. No Rs needed.

22 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

23 VDDCORE_3.3 PWR 3.3V power for the PLL core

24 *CR#0 IN Clock request for SRC0, 0 = enable, 1 = disable

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

MLF Pin Description (continued)

PIN # PIN NAME TYPE DESCRIPTION

25 GNDSRC PWR Ground pin for the SRC outputs

26 SRCC0_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

27 SRCT0_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

28 *CR#1 IN Clock request for SRC1, 0 = enable, 1 = disable

29 VDDCORE_3.3 PWR 3.3V power for the PLL core

30 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

31 SRCC1_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

32 SRCT1_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

33 GNDSRC PWR Ground pin for the SRC outputs

34 SRCC2_LPR OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm

series resistor. No 50ohm resistor to GND needed.

35 SRCT2_LPR OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

36 *CR#2 IN Clock request for SRC2, 0 = enable, 1 = disable

37 FSB_L IN Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

38 CPUC2_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

39 CPUT2_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

40 GNDCPU PWR Ground pin for the CPU outputs

41 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

42 VDDCORE_3.3 PWR 3.3V power for the PLL core

43 CPUC1_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

44 CPUT1_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

45 GNDCPU PWR Ground pin for the CPU outputs

46 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.

47 CPUC0_LPR OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated

33ohm series resistor. No 50 ohm resistor to GND needed.

48 CPUT0_LPR OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm

series resistor. No 50 ohm resistor to GND needed.

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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Funtional Block Diagram

Power Groups

VDD GND

41, 46 Low power outputs

42 VDDCORE_3.3V

30 Low power outputs

29 VDDCORE_3.3V

22 Low power outputs

23 VDDCORE_3.3V

15 Low power outputs

14 VDDCORE_3.3V

57 Xtal, REF

SRCCLK

LCDCLK

DOT 96Mhz18

Pin Number Description

25, 33

CPUCLK40, 45

CPU(2:0)

SRC(2:0)

LCD

SS-PLL

FSLB

CKPWRGD/PD#

CPU_STOP#

CR#(2:0)

TESTSEL

TESTMODE

Control

Logic

96M

Non-SS

PLL

LCD100_SSC

CPU, SRC

SS-PLL

REF

OSC

DOT96MHz

FSLC

SMBDAT

SMBCLK

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ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes

3.3V Supply Voltage VDDxxx_3.3 Supply Voltage 3.9 V 1,2

1.5V Supply Voltage VDDxxx_1.5 Supply Voltage 2.1 V 1,2

3.3_Input High Voltage VIH3.3 3.3V Inputs VDD_3.3+

0.3V V 1,2,3

Minimum Input Voltage VIL Any Input GND - 0.5 V 1

Storage Temperature Ts - -65 150 °C1,2

Human Body Model 2000 V 1,2

Man Machine Model 200 V 1,2

1Guaranteed by design and characterization, not 100% tested in production.

Input ESD protection ESD prot

2 Operation under these conditions is neither implied, nor guaranteed.

3 Maximum input voltage is not to exceed maximum VDD

Electrical Characteristics - Input/Supply/Common Output Parameters

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes

Ambient Operating Temp Tambient No Airflow 0 70 °C 1

3.3V Supply Voltage VDDxxx_3.3 3.3V +/- 5% 3.135 3.465 V 1

1.5V Supply Voltage VDDxxx_1.5 1.5V +/- 5% 1.425 1.575 V 1

3.3V Input High Voltage VIHSE3.3 Single-ended inputs 2 VDD + 0.3 V 1

3.3V Input Low Voltage VILSE3.3 Single-ended inputs VSS - 0.3 0.8 V 1

Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1

Input Leakage Current IINRES

Inputs with pull or pull down

resistors (CR# pins)

VIN = VDD , VIN = GND

-200 200 uA 1

Output High Voltage VOHSE Single-ended outputs, IOH = -1mA 2.4 V 1

Output Low Voltage VOLSE Single-ended outputs, IOL = 1 mA 0.4 V 1

Low Threshold Input-

High Voltage VIH_FS 3.3 V +/-5% 0.7 1.5 V 1

Low Threshold Input-

Low Voltage VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1

IDD_DEFAULT 3.3V supply, LCDPLL off 55 mA 1

IDD_LCDEN 3.3V supply, LCDPLL enabled 60 mA 1

IDD_IO

1.5V supply, Differential IO current,

all outputs enabled 50 mA 1

IDD_PD3.3 3.3V supply, Power Down Mode 1 mA 1

IDD_PDIO 1.5V IO supply, Power Down Mode 0.1 mA 1

Input Frequency FiVDD = 3.3 V 15 MHz 2

Pin Inductance L

in 7nH1

CIN Logic Inputs 1.5 5 pF 1

COU

Output pin capacitance 6 pF 1

CINX X1 & X2 pins 5 pF 1

Spread Spectrum Modulation

Frequency fSSMOD Triangular Modulation 30 33 kHz 1

Operating Supply Current

Power Down Current

Input Capacitance

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

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ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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AC Electrical Characteristics - Input/Common Parameters

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes

Clk Stabilization TSTAB

From VDD Power-Up or de-

assertion of PD# to 1st clock 1.8 ms 1

Tdrive_SRC TDRSRC

SRC output enable after

PCI_STOP# de-assertion 15 ns 1

Tdrive_PD# TDRPD

Differential output enable after

PD# de-assertion 300 us 1

Tdrive_CPU TDRSRC

CPU output enable after

CPU_STOP# de-assertion 10 ns 1

Tfall_PD# TFALL 5ns1

Trise_PD# TRISE 5ns1

Fall/rise time of PD# and

CPU_STOP# inputs

AC Electrical Characteristics - Low Power Differential Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES

Rising Edge Slew Rate tSLR Differential Measurement 0.5 4 V/ns 1,2

Falling Edge Slew Rate tFLR Differential Measurement 0.5 4 V/ns 1,2

Rise/Fall Time Variation tSLVAR Single-ended Measurement 125 ps 1

Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1

Minimum Output Voltage VLOW Includes undershoot -300 mV 1

Differential Voltage Swing VSWING Differential Measurement 300 mV 1

Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4

Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5

Duty Cycle DCYC Differential Measurement 45 55 % 1

CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 85 ps 1

SRC Jitter - Cycle to Cycle SRCJC2C Differential Measurement 125 ps 1

DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 250 ps 1

CPU[2:0] Skew CPUSKEW10 Differential Measurement 100 ps 1

SRC[2:0] Skew SRCSKEW Differential Measurement 250 ps 1

Electrical Characteristics - REF-14.318MHz

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes

Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2

Clock period T

eriod 14.318MHz output nominal 69.8203 69.8622 ns 2

Absolute min/max period Tabs 14.318MHz output nominal 69.8203 70.86224 ns 2

Output High Voltage VOH IOH = -1 mA 2.4 V 1

Output Low Voltage VOL IOL = 1 mA 0.4 V 1

Output High Current IOH

VOH @MIN = 1.0 V,

VOH@MAX = 3.135 V -33 -33 mA 1

Output Low Current IOL

VOL @MIN = 1.95 V,

VOL @MAX = 0.4 V 30 38 mA 1

Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 4 V/ns 1

Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 4 V/ns 1

Duty Cycle dt1 V

= 1.5 V 45 55 % 1

Jitter tjcyc-cyc VT = 1.5 V 1000 ps 1

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

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ULTRA MOBILE PC/MOBILE INTERNET DEVICE

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Electrical Characteristics - SMBus Interface

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes

SMBus Voltage VDD 2.7 3.3 V 1

Low-level Output Voltage VOLSMB @ IPULLUP 0.4 V 1

Current sinking at

VOLSMB = 0.4 V IPULLUP SMB Data Pin 4 mA 1

SCLK/SDATA

Clock/Data Rise Time TRI2C

(Max VIL - 0.15) to

(Min VIH + 0.15) 1000 ns 1

SCLK/SDATA

Clock/Data Fall Time TFI2C

(Min VIH + 0.15) to

(Max VIL - 0.15) 300 ns 1

Maximum SMBus Operating

Frequency FSMBUS Block Mode 100 kHz 1

Notes on Electrical Characteristics:

1Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through Vswing centered around differential zero

3 Vxabs is defined as the voltage where CLK = CLK#

4 Only applies to the differential rising edge (CLK rising and CLK# falling)

6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz

7 Operation under these conditions is neither implied, nor guaranteed.

9 See PCI Clock-to-Clock Delay Figure

8 Maximum input voltage is not to exceed maximum VDD

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of

CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets

CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate

calculations.

Clock Periods Differential Outputs with Spread Spectrum Enabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+

Absolute

Period

Short-term

Average

Long-Term

Average Period Long-Term

Average

Short-term

Average Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Nominal Maximum Maximum Maximum

SRC 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2

CPU 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2

CPU 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2

CPU 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2

Clock Periods Differential Outputs with Spread Spectrum Disabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+

Absolute

Period

Short-term

Average

Long-Term

Average Period Long-Term

Average

Short-term

Average Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Nominal Maximum Maximum Maximum

SRC 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2

CPU 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2

CPU 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2

CPU 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2

DOT 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2

1Guaranteed by design and characterization, not 100% tested in production.

2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

Measurement Window

Units Notes

Symbol

Definition

Signal Name Signal

Name

Notes

Symbol

Definition

Measurement Window

Units

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Table 1: CPU Frequency Select Table

FSLC1 FSLB1 CPU

MHz

SRC

MHz

DOT

MHz

LCD

MHz

REF

MHz

0 0 133.33

0 1 166.67

1 0 100.00

11Reserved

1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

100.00 96.00 100.00 14.318

Table 2: LCD Spread Select Table (Pin 20/21)

B1b5 B1b4 B1b3 Spread

%Comment

0 0 0 -0.5% LCD100

0 0 1 -1% LCD100

0 1 0 -2% LCD100

0 1 1 -2.5% LCD100

1 0 0 +/- 0.25

LCD100

1 0 1 +/-0.5% LCD100

1 1 0 +/-1% LCD100

1 1 1 +/-1.25% LCD100

Table 3: CPU N-ste

Pro

rammin

CPU

(

MHz

)

PDefault N

(

hex

)

133.33 3 64

166.67 3 7D

100.00 4 64

200.00 2 64

= 4MHz x N/P

Fcpu

= 4MHz x N/P

01Enable Running Running

1X Enable Low/20K Low

00Enable High Low

0X Disable Low/20K Low

00Enable Running Running Running Running

1X X Low/20K Low Low/20K Low

01Enable Low/20K Low Running Running

0X Disable Low/20K Low Low/20K Low

REF Power Management Table

0 Enable Running

1X Low

0Disable Low

SRC, LCD, DOT Power Management Table

CPU Power Management Table

PD CPU_STOP# SMBus Register

OE CPU CPU#

DOT#/LCD#PD CR_x# SMBus Register

OE SRC SRC#

REFPD SMBus Register

DOT/LCD

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

General I2C serial interface information for the ICS9UMS9633B

How to Write:

•Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

WR ACK

ACK

PstoP bit

X Byte

Index Block Write Operation

Slave Address D2(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D3(H)

Index Block Read Operation

Slave Address D2(H)

Beginning Byte = N ACK

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 0 PLL & Divider Enable Register

Bit(s) Pin # Name Description Type 0 1 Default

7 - PLL1 Enable This bit controls whether the PLL driving the CPU

and SRC clocks is enabled or not. RW 0 = Disabled 1 = Enabled 1

6 - PLL2 Enable This bit controls whether the PLL driving the DOT

and clock is enabled or not. RW 0 = Disabled 1 = Enabled 1

5 - PLL3 Enable This bit controls whether the PLL driving the LCD

clock is enabled or not. RW 0 = Disabled 1 = Enabled 1

4- 0

3 - CPU Divider Enable

This bit controls whether the CPU output divider is

enabled or not.

NOTE: This bit should be automatically set to ‘0’ if

bit 7 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

SRC Output Divider

Enable

This bit controls whether the SRC output divider is

enabled or not.

NOTE: This bit should be automatically set to ‘0’ if

bit 7 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

LCD Output Divider

Enable

This bit controls whether the LCD output divider is

enabled or not.

NOTE: This bit should be automatically set to ‘0’ if

bit 5 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

DOT Output Divider

Enable

This bit controls whether the DOT output divider is

enabled or not.

NOTE: This bit should be automatically set to ‘0’ if

bit 6 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

Byte 1 PLL SS Enable/Control Register

Bit(s) Pin # Name Description Type 0 1 Default

7 PLL1 SS Enable

This bit controls whether PLL1 has spread enabled

or not. Spread spectrum for PLL1 is set at -0.5%

down-spread. Note that PLL1 drives the CPU and

SRC clocks.

RW 0 = Disabled 1 = Enabled 1

6 PLL3 SS Enable

This bit controls whether PLL3 has spread enabled

or not. Note that PLL3 drives the SSC clock, and

that the spread spectrum amount is set in bits 3-5.

RW 0 = Disabled 1 = Enabled 1

5 0

4 0

3 0

2 0

1 0

0 0

Reserved

See Table 2: LCD Spread

Select Table

PLL3 FS Select

These 3 bits select the frequency of PLL3 and the

SSC clock when Byte 1 Bit 6 (PLL3 Spread

Spectrum Enable) is set.

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 2 Output Enable Register

Bit(s) Pin # Name Description Type 0 1 Default

7 CPU0 Enable This bit controls whether the CPU[0] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

6 CPU1 Enable This bit controls whether the CPU[1] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

5 CPU2 Enable This bit controls whether the CPU[2] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

4 SRC0 Enable This bit controls whether the SRC[0] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

3 SRC1 Enable This bit controls whether the SRC[1] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

2 SRC2 Enable This bit controls whether the SRC[2] output buffer

is enabled or not. RW 0 = Disabled 1 = Enabled 1

1 DOT Enable This bit controls whether the DOT output buffer is

enabled or not. RW 0 = Disabled 1 = Enabled 1

0 LCD100 Enable This bit controls whether the LCD output buffer is

enabled or not. RW 0 = Disabled 1 = Enabled 1

Byte 3 Output Control Register

Bit(s) Pin # Name Description Type 0 1 Default

7 0

6 0

5 REF Enable This bit controls whether the REF output buffer is

enabled or not. RW 0 = Disabled 1 = Enabled 1

2 CPU0 Stop Enable

This bit controls whether the CPU[0] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[0] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

1 CPU1 Stop Enable

This bit controls whether the CPU[1] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[1] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

0 CPU2 Stop Enable

This bit controls whether the CPU[2] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[2] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

10REF Slew

00 = Slow Edge Rate

01 = Medium Edge Rate

10 = Fast Edge Rate

11 = Reserved

RWThese bits control the edge rate of the REF clock.

Reserved

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 4

PU PLL N Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 1

Bit 6 1

Bit 5 1

Bit 4 1

Bit 3 1

Bit 2 1

Bit 1 1

Bit 0 CPU N Div8 N Divider Prog bit 8 RW 0

Byte 5

PU PLL/N Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 CPU N Div7 RW X

Bit 6 CPU N Div6 RW X

Bit 5 CPU N Div5 RW X

Bit 4 CPU N Div4 RW X

Bit 3 CPU N Div3 RW X

Bit 2 CPU N Div2 RW X

Bit 1 CPU N Div1 RW X

Bit 0 CPU N Div0 RW X

Byte 6 Reserved

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 1

Bit 6 1

Bit 5 1

Bit 4 1

Bit 3 0

Bit 2 0

Bit 1 1

Bit 0 1

Byte 7 Reserved

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

Bit 0 0

Reserved

See Table 3: CPU N-step Programming

Default depends on latched

input frequency.

Default for CPU = 166 is 7Dh.

Default for all other frequencies

is 64h.

Reserved

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 8 Reserved

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

Bit 0 0

Byte 9 LCD100 PLL N Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 LCD100 N Div7 R X

Bit 6 LCD100 N Div6 R X

Bit 5 LCD100 N Div5 R X

Bit 4 LCD100 N Div4 R X

Bit 3 LCD100 N Div3 R X

Bit 2 LCD100 N Div2 R X

Bit 1 LCD100 N Div1 R X

Bit 0 LCD100 N Div0 R X

Byte 10 Status Readback Register

Bit(s) Pin # Name Description Type 0 1 Default

7 37 FSB Frequency Select B R Latch

6 9 FSC Frequency Select C R Latch

5 24 CR0# Readbk Real time CR0# State Indicator R CR0# is Low CR0# is High X

4 28 CR1# Readbk Real time CR1# State Indicator R CR1# is Low CR1# is High X

3 36 CR2# Readbk Real time CR2# State Indicator R CR2# is Low CR2# is High X

2 0

1 0

0 0

Byte 11 Revision ID/Vendor ID Register

Bit(s) Pin # Name Description Type 0 1 Default

7 Rev Code Bit 3 R X

6 Rev Code Bit 2 R X

5 Rev Code Bit 1 R X

4 Rev Code Bit 0 R X

3 Vendor ID bit 3 R 0

2 Vendor ID bit 2 R 0

1 Vendor ID bit 1 R 0

0 Vendor ID bit 0 R 1

Byte 12 Device ID Register

Bit(s) Pin # Name Description Type 0 1 Default

7 DEV_ID3 Device ID MSB R 0

6 DEV_ID2 Device ID 2 R 0

5 DEV_ID1 Device ID 1 R 1

4 DEV_ID0 Device ID LSB R 1

3 0

2 0

1 0

0 0

Reserved

Vendor ID

Reserved

N Divider Programming Byte9 bit(7:0) and Byte8

bit7

See N-step programming

formula

Reserved

See Table 1: CPU Frequency

Select Table

Reserved

Revision ID

(0 for A rev)

Vendor specific

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 13 Reserved Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

Bit 0 0

Byte 14 Reserved Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 0

Bit 0 0

Byte 15 Byte Count Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 BC5 Byte Count 5 RW 0

Bit 4 BC4 Byte Count 4 RW 0

Bit 3 BC3 Byte Count 3 RW 1

Bit 2 BC2 Byte Count 2 RW 1

Bit 1 BC1 Byte Count 1 RW 1

Bit 0 BC0 Byte Count LSB RW 1

Byte 41 N Program Enable Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 0

Bit 3 0

Bit 2 0

Bit 1 CPU N Enable Enables CPU N programming RW Disabled Enabled 0

Bit 0 LCD N Enable Enables LCD N programming RW Disabled Enabled 0

Reserved

Bytes 16:40 are reserved

Reserved

Specifies Number of bytes to

be read back during an SMBus

read.

Default is 0xF.

Reserved

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Test Clarification Table

Comments

TEST_SEL

HW PIN

TEST_MODE

HW PIN OUTPUT

<0.35V X NORMAL

>0.7V <0.35V HI-Z

>0.7V >0.7V REF/N

Power-up w/ TEST_SEL = 1 to enter test mode

Cycle power to disable test mode

TEST_MODE -->low Vth input

TEST_MODE is a real time input

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

MLF Top Mark Information (9UMS9633BKLF)

Line 1. Company name

Line 2. Part Number

Line 3. YYWW = Date Code

Line 3. Country of Origin

Line 4. ####### = Lot Number

48 47 46 45 44 43 42 41 40 39 38 37

136

235

334

433

532

631

730

829

928

10 27

11 26

12 25

13 14 15 16 17 18 19 20 21 22 23 24

ICS

UMS9633BL

YYWW

C of O

#######

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Ordering Information

9UMS9633BKLFT

Example:

Designation for tape and reel packaging

Lead Free, RoHS Compliant

Package Type

K = MLF

Revision Designator

Device Type

XXXX B K LF T

DIMENSIONS

A0.81.0 N 48

A1 0 0.05 ND12

A3 NE12

b 0.18 0.3 D x E BASIC 6.00 x 6.00

e D2 MIN. / MAX. 3.95 / 4.25

E2 MIN. / MAX. 3.95 / 4.25

L MIN. / MAX. 0.30 / 0.50

0.20 Reference

0.40 BASIC

48L

TOLERANCE

THERMALLY ENHANCED, VERY THIN, FINE PITCH

QUAD FLAT / NO LEAD PLASTIC PACKAGE

DIMENSIONS

SYMBOL MIN. MAX. SYMBOL

Top View

Index Area

Sawn

Singulation

Anvil

Singulation

0. 08 C C

Seating Plane

-1)x e

(Ref.)

& N

Even

(Re f.)

Odd

(Typ.)

(Ref.)

If N & N

(N -1)x

Thermal

Base

Chamfer 4x

0.6 x 0.6 max

OPTIONAL

are Even

IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Ordering Information

9UMS9633BFLFT

Example:

Designation for tape and reel packaging

Lead Free, RoHS Compliant

Package Type

F = SSOP

Revision Designator

Device Type

XXXX B F LF T

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291 .299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

a 0°8°0°8°

VARIATIONS

MIN MAX MIN MAX

48 15.75 16.00 .620 .630

10-0034

0.635 BASIC 0.025 BASIC

COMMON DIMENSIONS

In Millimeters In Inches

COMMON DIMENSIONS

Reference Doc.: JEDEC Publication 95, MO-118

300 mil SSOP

SEE VARIATIONS SEE VARIATIONS

D mm. D (inch)

SYMBOL

SEE VARIATIONS SEE VARIATIONS

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE Advance Information

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

408-284-6578

pcclockhelp@idt.com

Corporate Headquarters

Integrated Device Technology , Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

United S t ates

800 345 7015

+408 284 8200 (outside U.S.)

Asia Pacific and Jap an

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria

Singapore 238877

+65 6 887 5505

Europe

IDT Europe, Limited

Prime House

Barnett Wood Lane

Leatherhead, Surrey

United Kingdom KT22 7DE

+44 1372 363 339

Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks

or registered trademarks used to identify products or services of their respective owners.

Printed in USA

Revision History

Rev. Issue Date Description Page #

0.1 12/06/07 Initial Release -

0.2 02/27/08

1. Byte 4 default value changed to FF hex

2. B

te 6 default value chan

ed to F3 hex.

0.3 05/21/08

1. Corrected Reference in Byte 5 to CPU NDIV8. Should refer to

Byte 4, bit 0.

2. Corrected Reference in LCD100 NDIV to only refer to Byte 9

3. Corrected headings in clock period table.

4. Added N-step programming info.

5. Corrected Byte 4 default value

0.4 11/12/08 Removed reference to 1.5V inputs Various

0.5 01/20/09 Updated SMBus b

te 4/5; added CPU N-Step Pro

rammin

table 11,15