Product Folder Order Now Support & Community Tools & Software Technical Documents bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG 1 1 Features * * * * * * * * * 90% High Efficiency Switch Mode 3-A Charger 3.9-V to 6.2-V Single Input USB-Compliant Charger with 6.4-V Over-Voltage Protection - USB Host or Charging Port D+/D- Detection Compatible to USB Battery Charger Spec (BC1.2) - Supports Nonstandard 2-A/1-A Adapters Detection (bq24297) - Input Voltage and Current Limit Supports USB 2.0 and USB 3.0 - Input Current Limit: 100 mA, 150 mA, 500 mA, 900 mA, 1 A, 1.5 A, 2 A, and 3 A USB OTG with Adjustable Output 4.55 V to 5.5 V at 1 A or 1.5 A - Fast OTG Startup (22 ms Typ) - 90% 5-V Boost Mode Efficiency - Accurate 15% Hiccup Mode Over-Current Protection Narrow VDC (NVDC) Power Path Management - Instant System On with No Battery or Deeply Discharged Battery - Ideal Diode Operation in Battery Supplement Mode 1.5-MHz Switching Frequency for Low Profile 1.2mm Inductor I2C Port for Optimal System Performance and Status Reporting Autonomous Battery Charging With or Without Host Management - Battery Charge Enable and Preconditioning - Charge Termination and Recharge High Accuracy - 0.5% Charge Voltage Regulation - 7% Charge Current Regulation - 7.5% Input Current Regulation - 3% Output Voltage Regulation in USB OTG Boost Mode High Integration - Power Path Management - Synchronous Switching MOSFETs - Integrated Current Sensing - Bootstrap Diode - Internal Loop Compensation * * * * * Safety - Battery Temperature Sensing for Charging and Discharging in OTG Mode - Battery Charging Safety Timer - Thermal Regulation and Thermal Shutdown - Input and System Over-Voltage Protection - MOSFET Over-Current Protection Charge Status Outputs for LED or Host Processor Maximum Power Tracking Capability by Input Voltage Regulation 20-A Low Battery Leakage Current and Support Shipping Mode 4.00-mm x 4.00-mm VQFN-24 Package 2 Applications * * * Tablet PC, Smart Phone, Internet Devices Portable Audio Speaker Handheld Computers, PDA, and POS 3 Description The bq24296/bq24297 are highly-integrated switchmode battery charge management and system power path management devices for 1 cell Li-Ion and Lipolymer batteries in a wide range of smart phone and tablet applications. Device Information(1) PART NUMBER bq24296/7 PACKAGE BODY SIZE (NOM) VQFN (24) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Schematic 1mH 5V USB SDP/DCP VBUS 47nF 1mF PMID 8.2mH SYS BTST 4.7mF PGND SDA SCL INT OTG SYS 10mF QON Optional TS D+/PSEL D-/PG Battery BAT CE USB PHY 20mF REGN STAT VREF Host SYSTEM SW ILIM + - bq24296/297 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 1 1 1 2 4 4 5 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings ............................................................ 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 12 Typical Characteristics ............................................ 12 Detailed Description ............................................ 15 9.1 Overview ................................................................. 15 9.2 Functional Block Diagram ....................................... 16 9.3 Feature Description................................................. 17 9.4 Device Functional Modes........................................ 29 9.5 Programming........................................................... 30 9.6 Register Map........................................................... 34 10 Application and Implementation........................ 41 10.1 Application Information.......................................... 41 10.2 Typical Application ................................................ 41 11 Power Supply Recommendations ..................... 46 12 Layout................................................................... 46 12.1 Layout Guidelines ................................................. 46 12.2 Layout Example .................................................... 47 13 Device and Documentation Support ................. 48 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Documentation Support ....................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 48 48 48 48 48 48 48 14 Mechanical, Packaging, and Orderable Information ........................................................... 48 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November 2014) to Revision C Page * Changed CE to CE for bq24297 in Pin Functions.................................................................................................................. 5 * Changed VREF to VREGN in Figure 18 ................................................................................................................................. 25 * Changed 20C to -20C and VREF to VREGN in Figure 19 ................................................................................................. 26 * Changed Equation 1 ............................................................................................................................................................ 26 * Changed Bit 3 RESET from 1 to 0 in Table 12 ................................................................................................................... 37 * Changed Bit 2 RESET from 1 to 0 in Table 12 ................................................................................................................... 37 * Changed 0 to 1 for REG05 Bit 2 Reset in Table 13 ............................................................................................................ 37 * Changed 1 to 0 for REG05 Bit 1 Reset in Table 13 ............................................................................................................ 37 * Changed DPDM_EN to IINDET_EN in Table 15.................................................................................................................. 39 * Changed D+/D- to Input current limit in Table 15 ................................................................................................................ 39 * Added note to Figure 40 ...................................................................................................................................................... 41 * Added note to Figure 41 ...................................................................................................................................................... 42 * Changed last paragraph in Output Capacitor section .......................................................................................................... 43 Changes from Revision A (October 2013) to Revision B Page * Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 * Changed front page schematic............................................................................................................................................... 1 * Changed REG01[4] = 1 to REG01[5] = 1 in OTG description................................................................................................ 5 * Added (10k NTC thermister only) to QON description ........................................................................................................ 6 * Added ESD information to Handling Ratings ........................................................................................................................ 7 * Changed ICHG = 1792 mA in IICHG_REG_ACC test conditions ...................................................................................................... 8 2 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 * Changed falling to rising in VHTF ............................................................................................................................................. 9 * Changed VHTF TYP to 47.2% ................................................................................................................................................. 9 * Changed Input high threshold (OTG) MIN to 1.1 V.............................................................................................................. 10 * Changed Table 3 ................................................................................................................................................................. 20 * Changed Figure 15 .............................................................................................................................................................. 23 * Changed RT1 = 5.25 k ..................................................................................................................................................... 26 * Deleted and LSFET from Voltage and Current Monitoring in Buck Mode description ......................................................... 28 * Deleted HSFET and from Voltage and Current Monitoring in Boost Mode description ....................................................... 29 * Changed text in Over-Current Protection ............................................................................................................................ 29 * Changed REG09[5] to REG09[3] in Battery Over-Voltage Protection (BATOVP) section ................................................... 29 * Changed REG09 Bit 3 description 1 - Battery OVP ........................................................................................................... 40 Changes from Original (September 2013) to Revision A * Page Deleted H from bq24297 PART NUMBER ............................................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 3 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 5 Description (Continued) Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charge time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution. The device supports 3.9-V to 6.2-V USB input sources, including standard USB host port and USB charging port with 6.4-V over-voltage protection. The device is compliant with USB 2.0 and USB 3.0 power specifications with input current and voltage regulation. To set the default input current limit, the bq24296 takes the result from the detection circuit in the system, such as USB PHY device and the bq24297 detects the input source through D+/D- detection following the USB battery charging spec 1.2. In addition, the bq24297 detects non-standard 2A/1-A adapters. The device also supports USB On-the-Go operation by providing fast startup and supplying adjustable voltage 4.55-V to 5.5-V (default 5 V) on the VBUS with an accurate current limit up to 1.5 A. The power path management regulates the system slightly above battery voltage but does not drop below 3.5-V minimum system voltage (programmable). With this feature, the system keeps operating even when the battery is completely depleted or removed. When the input source current or voltage limit is reached, the power path management automatically reduces the charge current to zero and then starts discharges the battery until the system power requirement is met. This supplement mode operation keeps the input source from getting overloaded. The device initiates and completes a charging cycle when host control is not available. It automatically charges the battery in three phases: pre-conditioning, constant current, and constant voltage. In the end, the charger automatically terminates when the charge current is below a preset limit in the constant voltage phase. Later on, when the battery voltage falls below the recharge threshold, the charger automatically starts another charging cycle. The charge device provides various safety features for battery charging and system operation, including negative thermistor monitoring, charging safety timer, and over-voltage/over-current protections. The thermal regulation reduces charge current when the junction temperature exceeds 120C (programmable). The STAT output reports the charging status and any fault conditions. The INT immediately notifies the host when a fault occurs. The bq24296 and bq24297 are available in a 24-pin, 4.00 x 4.00 mm2 thin VQFN package. 6 Device Comparison Table bq24296 bq24297 I C Address 6BH 6BH USB OTG Yes Adjustable 4.5 V to 5.5 V at 1.5 A (max) Yes Adjustable 4.5 V to 5.5 V at 1.5 A (max) USB Detection PSEL D+/D- 2 4 Default Battery Voltage 4.208 V 4.208 V Default Charge Current 2.048 A 2.048 A Default Adapter Current Limit 3A 3A Default Pre-Charge Current / Max PreCharge Current 256 mA / 2.048 A 256 mA / 2.048 A Default Termination Current 256 mA 256 mA Charging Temperature Profile Cold/Hot Cold/Hot Status Output STAT, PG STAT STAT During Fault Blinking at 1 Hz Blinking at 1 Hz Default Safety Timer 12 hr 12 hr Default VINDPM 4.36 V 4.36 V Default Pre-charge Timer 4 hr 4 hr Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 7 Pin Configuration and Functions 24-Pin VQFN RGE Package (Top View) VBUS PMID REGN BTST SW SW VBUS PMID REGN BTST SW SW 24-Pin VQFN RGE Package (Top View) 24 23 22 21 20 19 24 23 22 21 20 19 VBUS 1 18 PGND VBUS 1 18 PGND PSEL 2 17 PGND D+ 2 17 PGND 16 SYS D- 3 16 SYS PG 3 bq24297 bq24296 STAT 15 SYS 14 BAT SCL 5 14 SDA 6 13 BAT SDA 13 BAT 7 8 9 10 11 12 QON 12 TS 11 ILIM 10 CE 9 6 OTG 8 4 INT 7 QON 5 TS SCL ILIM SYS CE 15 OTG 4 INT STAT BAT Pin Functions PIN NUMBER TYPE DESCRIPTION VBUS 1,24 P Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-F ceramic capacitor from VBUS to PGND and place it as close as possible to IC. PSEL PSEL 2 I Power source selection input. High indicates a USB host source and Low indicates an adapter source. - D+ 2 PG - 3 - D- 3 STAT STAT 4 bq24296 bq24297 VBUS I Positive line of the USB data line pair. D+/D- based USB host/charging port detection. The detection Analo includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters. g O Open drain active low power good indicator. Connect to the pull up rail via 10-k resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA. I Negative line of the USB data line pair. D+/D- based USB host/charging port detection. The detection Analo includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters. g O Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10k resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in the charge blinks at 1 Hz. SCL SCL 5 I I2C Interface clock. Connect SCL to the logic rail through a 10-k resistor. SDA SDA 6 I/O I2C Interface data. Connect SDA to the logic rail through a 10-k resistor. INT INT 7 O Open-drain Interrupt Output. Connect the INT to a logic rail via 10k resistor. The INT pin sends active low, 256-s pulse to host to report charger device status and fault. OTG OTG 8 CE CE 9 I Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low. ILIM ILIM 10 I ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) x KILIM. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA. I USB current limit selection pin during buck mode, and active high enable pin during boost mode. Digital For bq24296, when in buck mode with USB host (PSEL = High), when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA. For bq24297, when in buck mode with USB host, when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA. The boost mode is activated when the REG01[5] = 1 and OTG pin is High. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 5 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Pin Functions (continued) PIN NUMBER TYPE DESCRIPTION bq24296 bq24297 TS TS 11 QON QON 12 I BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2-ms high level turns on BATFET to exit shipping mode. It has internal 1-M (Typ) pull down. For backward compatibility, when BATFET enable control function is not used, the pin can be no connect or tied to TS pin (10-k NTC thermister only). (Refer to Shipping Mode for detail description). BAT BAT 13,14 P Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 F closely to the BAT pin. SYS SYS 15,16 I System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. PGND PGND 17,18 P Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. SW SW 19,20 O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-F bootstrap capacitor from SW to BTST. BTST BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047-F bootstrap capacitor from SW to BTST. REGN REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the booststrap diode. Connect a 4.7-F (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin. PMID PMID 23 O Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance, connect a 1-F capacitor on VBUS to PGND, and the recommended 8.2 F or more on PMID to PGND. Thermal Pad Thermal Pad - P Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. I Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program Analo temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost disable when TS pin is out of range. A 103AT-2 thermistor is recommended. g 8 Specifications 8.1 Absolute Maximum Ratings (1) MIN V -2 PMID (converter not switching) -0.3 15 (2) V STAT, PG -0.3 12 V BTST -0.3 12 V -2 7 8 (Peak for 20ns duration) V BAT, SYS (converter not switching) -0.3 6 V SDA, SCL, INT, OTG, ILIM, REGN, TS, QON, CE , D+, D-, PSEL -0.3 7 V BTST TO SW -0.3 7 V PGND to GND -0.3 0.3 V 6 mA SW INT, STAT, PG 15 UNIT (2) VBUS (converter not switching) Voltage (with respect to GND) Output sink current MAX Junction temperature -40 150 C Storage temperature range, Tstg -65 150 C (1) (2) 6 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground pin unless otherwise noted. VBUS is specified up to 16 V for a maximum of 24 hours under no load conditions. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 8.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1000 V Charged device model (CDM), per JEDEC specification JESD22C101 (2) 250 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN MAX UNIT 3.9 6.2 (1) V Input current (VBUS) 3 A ISYS Output current (SYS) 3.5 A VBAT Battery voltage 4.4 V 3 A VIN Input voltage IIN Fast charging current IBAT Discharging current with internal MOSFET TA (1) Operating free-air temperature range -40 5.5 A 85 C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise. 8.4 Thermal Information bq2429x THERMAL METRIC (1) RGE (VQFN) UNIT 24 PIN RJA Junction-to-ambient thermal resistance 32.2 C/W RJC(top) Junction-to-case (top) thermal resistance 29.8 C/W RJB Junction-to-board thermal resistance 9.1 C/W JT Junction-to-top characterization parameter 0.3 C/W JB Junction-to-board characterization parameter 9.1 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 2.2 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 8.5 Electrical Characteristics VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENTS IBAT IVBUS IBOOST Battery discharge current (BAT, SW, SYS) Input supply current (VBUS) Battery discharge current in boost mode VVBUS < VUVLO, VBAT = 4.2 V, leakage between BAT and VBUS 5 High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), -40C - 85C 16 20 A High-Z Mode, or no VBUS, BATFET enabled (REG07[5] = 0), -40C - 85C 32 55 A VVBUS = 5 V, High-Z mode, No battery 15 30 A VVBUS > VUVLO, VVBUS > VBAT, converter not switching 1.5 3 mA A VVBUS > VUVLO, VVBUS > VBAT, converter switching, VBAT = 3.2 V, ISYS = 0 A 4 mA VVBUS > VUVLO, VVBUS > VBAT, converter switching, charge disable, VBAT = 3.8 V, ISYS = 100 A 3.5 mA VBAT = 4.2 V, Boost mode, IVBUS = 0 A, converter switching 3.5 mA VBUS/BAT POWER UP VVBUS_OP VBUS operating voltage 3.9 6.2 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 V 7 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 35 80 120 mV VVBUS rising, VVBUS-VBAT 170 250 350 mV VVBUS rising 6.2 6.4 6.6 VVBUS_UVLOZ VBUS for active I2C, no battery VVBUS rising 3.6 VSLEEP Sleep mode falling threshold VVBUS falling, VVBUS-VBAT VSLEEPZ Sleep mode rising threshold VACOV VBUS over-voltage rising threshold VACOV_HYST VBUS over-voltage falling hysteresis VVBUS falling VBAT_UVLOZ Battery for active I2C, no VBUS VBAT rising VBAT_DPL Battery depletion threshold VBAT falling 2.4 VBAT_DPL_HY Battery depletion rising hysteresis VBAT rising 200 VVBUSMIN Bad adapter detection threshold VVBUS falling 3.8 V IBADSRC Bad adapter detection current source 30 mA V 250 V mV 2.3 V 2.6 V mV POWER PATH MANAGEMENT VSYS_MAX Typical system regulation voltage Isys = 0 A, BATFET (Q4) off, VBAT up to 4.2 V, REG01[3:1] = 101, VSYSMIN = 3.5 V 3.5 VSYS_MIN System voltage outpu REG01[3:1] = 101, VSYSMIN = 3.5 V 3.5 RON(RBFET) Top reverse blocking MOSFET onresistance between VBUS and PMIID RON(HSFET) Internal top switching MOSFET onresistance between PMID and SW RON(LSFET) Internal bottom switching MOSFET onresistance between SW and PGND VFWD 4.35 3.65 V V 28 41 m TJ = -40C - 85C 39 51 TJ = -40C - 125C 39 58 TJ = -40C - 85C 61 82 TJ = -40C - 125C 61 90 BATFET forward voltage in supplement mode BAT discharge current 10mA 30 mV VSYS_BAT SYS/BAT comparator VSYS falling 70 mV VBATGD Battery good comparator rising threshold VBAT rising 3.55 V VBATGD_HYST Battery good comparator falling threshold VBAT falling 100 mV m m BATTERY CHARGER VBAT_REG_ACC IICHG_REG_ACC Charge voltage regulation accuracy VBAT = 4.112 V and 4.208 V Fast charge current regulation accuracy -0.5% 0.5% VBAT = 3.8 V, ICHG = 1024 mA, TJ = 25C -4% 4% VBAT = 3.8 V, ICHG = 1024 mA, TJ = -20C - 125C -7% 7% VBAT = 3.8 V, ICHG = 1792 mA, TJ = -20C - 125C -10% 10% 175 mA ICHG_20pct Charge current with 20% option on VBAT = 3.1 V, ICHG = 104 mA, REG02 = 03 and REG02[0] =1 75 VBATLOWV Battery LOWV falling threshold Fast charge to precharge, REG04[1] = 1 2.6 2.8 2.9 V VBATLOWV_HYST Battery LOWV rising threshold Precharge to fast charge, REG04[1] = 1 (Typical 200-mV hysteresis) 2.8 3.0 3.1 V IPRECHG_ACC Precharge current regulation accuracy VBAT = 2.6 V, ICHG = 256 mA ITYP_TERM_ACC Typical termination current ITERM = 256 mA, ICHG = 2048 mA ITERM_ACC Termination current accuracy ITERM = 256 mA, ICHG = 2048 mA VSHORT Battery short voltage VBAT falling 2.0 V VSHORT_HYST Battery Short Voltage hysteresis VBAT rising 200 mV ISHORT Battery short current VBAT < 2.2 V 100 mA VRECHG Recharge threshold below VBAT_REG VBAT falling, REG04[0] = 0 100 mV tRECHG Recharge deglitch time VBAT falling, REG04[0] = 0 20 TJ = 25C 24 28 TJ = -40C - 125C 24 35 RON_BATFET SYS-BAT MOSFET on-resistance -20% 20% 265 -22.5% mA 22.5% ms m INPUT VOLTAGE/CURRENT REGULATION VINDPM_REG_ACC IUSB_DPM 8 Input voltage regulation accuracy USB Input current regulation limit, VBUS = 5V, current pulled from SW -2% 2% USB100 85 100 mA USB150 125 150 mA USB500 440 500 mA USB900 750 900 mA Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS IADPT_DPM Input current regulation accuracy IADP = 1.5 A, REG00[2:0] = 101 IIN_START Input current limit during system start up VSYS < 2.2 V KILIM IIN = KILIM/RILIM IINDPM = 1.5 A MIN TYP 1.3 MAX 1.5 100 395 435 UNIT A mA 475 A x D+/D- DETECTION (bq24297) VD+_SRC D+ voltage source ID+_SRC D+ connection check current source ID-_SINK D- current sink 0.5 0.7 V 7 14 A 150 A D-, switch open 50 -1 100 1 A D+, switch open -1 1 A ID_LKG Leakage current into D+/D- VD+_LOW D+ low comparator threshold VD-_LOWdatref D- low comparator threshold RD-_DWN D- pulldown for connection check tSDP_DEFAULT Charging timer with 100mA USB host in default mode Vadpt1_lo D+ low comparator threshold for nonstandard adapter Divider-1 As percentage of REGN, 0C - 85C (1) 46.5% 48% 49.5% Vadpt1_hi D+ low comparator threshold for nonstandard adapter divider-1 As percentage of REGN, 0C - 85C (1) 58.5% 60% 61.5% Vadpt2_lo D+ low comparator threshold for nonstandard adapter divider-2 As percentage of REGN, 0C - 85C (1) 15.5% 17% 18.5% Vadpt2_hi D+ low comparator threshold for Nonstandard adapter divider-2 As percentage of REGN, 0C - 85C (1) 28.5% 30% 31.5% Vadpt3_lo D- low comparator threshold for nonstandard adapter divider-3 As percentage of REGN, 0C - 85C (1) 46.5% 48% 49.5% Vadpt3_hi D- high comparator threshold for nonstandard adapter divider-3 As percentage of REGN, 0C - 85C (1) 58.5% 60% 61.5% 0.8 V 250 400 mV 14.25 24.8 k 45 mins BAT OVER-VOLTAGE PROTECTION VBATOVP Battery over-voltage threshold VBAT rising, as percentage of VBAT_REG 104% VBATOVP_HYST Battery over-voltage hysteresis VBAT falling, as percentage of VBAT_REG 2% tBATOVP Battery over-voltage deglitch time to disable charge 1 s THERMAL REGULATION AND THERMAL SHUTDOWN TJunction_REG Junction temperature regulation accuracy REG06[1:0] = 11 120 C TSHUT Thermal shutdown rising temperature Temperature increasing 160 C TSHUT_HYS Thermal shutdown hysteresis 30 C Thermal shutdown rising deglitch Temperature increasing delay 1 ms Thermal shutdown falling deglitch Temperature decreasing delay 1 ms COLD/HOT THERMISTER COMPARATOR VLTF Cold temperature threshold, TS pin voltage rising threshold Charger suspends charge. as percentage to VREGN VLTF_HYS Cold temperature hysteresis, TS pin voltage falling As percentage to VREGN VHTF Hot temperature TS pin voltage rising threshold As percentage to VREGN 46.6% 47.2% 48.8% VTCO Cut-off temperature TS pin voltage falling threshold As percentage to VREGN 44.2% 44.7% 45.2% Deglitch time for temperature out of range detection VTS > VLTF, or VTS < VTCO, or VTS < VHTF Cold temperature threshold, TS pin voltage rising threshold As percentage to VREGN REG02[1] = 0 (Approx. -10C w/ 103AT) VBCOLD0 VBCOLD0_HYS (1) As percentage to VREGN REG02[1] = 0 (Approx. 1C w/ 103AT) 73% 73.5% 74% 0.4% 10 75.5% 76% ms 76.5% 1% REGN LDO is configured in drop-out mode. VBUS is close to REGN when IREGN = 0 mA. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 9 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER VBCOLD1 TEST CONDITIONS Cold temperature threshold 1, TS pin voltage rising threshold As percentage to VREGN REG02[1] = 1 (Approx. -20C w/ 103AT) Hot temperature threshold, TS pin voltage falling threshold Hot temperature threshold 1, TS pin voltage falling threshold 78.5% 79% 79.5% As percentage to VREGN REG06[3:2] = 01 (Approx. 55C w/ 103AT) 35.5% As percentage to VREGN REG06[3:2] = 10 (Approx. 65C w/ 103AT) 32.5% 36.5% 33% 33.5% 3% 29.5% As percentage to VREGN REG06[3:2] = 10 (Approx. 3C w/ 103AT) VBHOT2_HYS 36% 3% As percentage to VREGN REG06[3:2] = 00 (Approx. 3C w/ 103AT) Hot temperature threshold 2, TS pin voltage falling threshold UNIT 1% As percentage to VREGN REG06[3:2] = 00 (Approx. 60C w/ 103AT) VBHOT1_HYS VBHOT2 MAX As percentage to VREGN REG06[3:2] = 01 (Approx. 3C w/ 103AT) VBHOT0_HYS VBHOT1 TYP As percentage to VREGN REG02[1] = 1 (Approx. 1C w/ 103AT) VBCOLD1_HYS VBHOT0 MIN 30% 30.5% 3% CHARGE OVER-CURRENT COMPARATOR IHSFET_OCP HSFET cycle by cycle over-current threshold 5.3 7.5 A IBATFET_OCP System over load threshold 5.5 6.6 A VLSFET_UCP LSFET charge under-current falling threshold 100 mA FSW PWM Switching frequency, and digital clock DMAX Maximum PWM duty cycle VBTST_REFRESH From sync mode to non-sync mode 1300 1500 1700 kHz 97% Bootstrap refresh comparator threshold VBTST-VSW when LSFET refresh pulse is requested, VBUS = 5 V 3.6 V BOOST MODE OPERATION VOTG_REG_ACC OTG output voltage I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) VOTG_REG_ACC OTG output voltage accuracy I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) VOTG_BAT Battery voltage exiting OTG mode BAT falling, REG04[1] = 1 5 -3% V 3% 2.9 V REG01[0] = 0 1 A REG01[0] = 1 1.5 5.8 IOTG OTG mode output current VOTG_OVP OTG over-voltage threshold Rising threshold VOTG_OVP_HYS OTG over-voltage threshold hysteresis Falling threshold IOTG_LSOCP LSFET cycle by cycle current limit IOTG_HSZCP HSFET under current falling threshold IRBFET_OCP RBFET over-current threshold A 6 V 300 mV 100 mA 5 A REG01[0] = 0 1.00 1.15 1.30 REG01[0] = 1 1.50 1.70 1.90 5.5 A REGN LDO VREGN REGN LDO output voltage IREGN REGN LDO current limit VVBUS = 6 V, IREGN = 40 mA 4.8 5 VVBUS = 5 V, IREGN = 20 mA 4.7 4.8 VVBUS = 5 V, VREGN = 3.8 V 50 V V mA LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG) VILO Input low threshold 0.4 VIH Input high threshold (CE, STAT, QON, PSEL, PG) VIH_OTG Input high threshold (OTG) VOUT_LO Output low saturation voltage Sink current = 5 mA IBIAS High level leakage current (OTG, CE, STAT , PSEL, PG) IBIAS High level leakage current (QON) 1.3 V V 1.1 V 0.4 V Pull-up rail 1.8 V 1 A Pull-up rail 3.6 V 8 A I2C INTERFACE (SDA, SCL, INT) VIH 10 Input high threshold level VPULL-UP = 1.8 V, SDA and SCL Submit Documentation Feedback 1.3 V Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = -40C to 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input low threshold level VPULL-UP = 1.8 V, SDA and SCL 0.4 VOL Output low threshold level Sink current = 5 mA 0.4 V V IBIAS High-level leakage current VPULL-UP = 1.8 V, SDA and SCL 1 A fSCL SCL clock frequency 400 kHz DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 11 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 8.6 Timing Requirements MIN TYP MAX UNIT VBUS/BAT POWER UP tBADSRC Bad source detection duration 30 ms BOOST MODE OPERATION tOTG_OCP_OFF OTG mode over-current protection off cycle time 32 ms tOTG_OCP_ON OTG mode over-current protection on cycle time 260 s QON TIMING tQON QON pin high time to turn on BATFET 2 ms DIGITAL CLOCK AND WATCHDOG TIMER tWDT REG05[5:4] = 11 REGN LDO disabled 112 160 REGN LDO enabled 136 160 s Figure 1. I2C-Compatible Interface Timing Diagram 8.7 Typical Characteristics Table 1. Table of Figures FIGURE Charging Efficiency vs Charging Current (DCR = 10 m) Figure 2 System Efficiency vs System Load Current (DCR = 10 m) Figure 3 Boost Mode Efficiency vs VBUS Load Current (DCR = 10 m) Figure 4 SYS Voltage Regulation vs System Load Current Figure 5 Boost Mode VBUS Voltage Regulation (Typical Output = 4.998 V, REG06[7:4] = 0111) vs VBUS Load Current Figure 6 SYS Voltage vs Temperature Figure 7 BAT Voltage vs Temperature Figure 8 Input Current Limit vs Temperature Figure 9 Charge Current vs Package Temperature Figure 10 12 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 95 95 90 85 Efficiency (%) Efficiency (%) 90 80 75 85 80 75 70 VBUS = 5V VBUS = 5V 65 70 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 Charge Current (A) 100 4 95 3.9 90 3.8 85 80 75 60 0 0.5 3 1 3.7 3.6 SYSMIN = 3.5 SYSMIN = 3.2 SYSMIN = 3.7 3.5 3.3 3.2 1.5 0 0.5 1 VBUS Load Current (A) 1.5 2 2.5 3 3.5 System Load Current (A) Figure 4. Boost Mode Efficiency vs VBUS Load Current Figure 5. SYS Voltage Regulation vs System Load Current 3.7 5.1 5 3.65 SYS Voltage (V) BOOST Mode Output Voltage (V) 2.5 3.4 VBAT = 3.2V VBAT = 3.5V VBAT = 3.8V 65 2 Figure 3. System Efficiency vs System Load Current SYS Voltage (V) Efficiency (%) Figure 2. Charge Efficiency vs Charge Current 70 1.5 Load Current (A) 4.9 4.8 4.7 3.55 VBAT = 3.2V VBAT = 3.5V VBAT = 3.8V 4.6 4.5 0 0.5 1 3.6 SYSMIN = 3.5V 3.5 1.5 -50 -25 0 25 50 75 100 125 150 Temperature (oC) VBUS Load Current (A) Typical Output = 4.998 V, REG06[7:4] = 0111 Figure 6. Boost Mode VBUS Voltage Regulation vs VBUS Load Current Figure 7. SYS Voltage vs Temperature Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 13 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 4.4 2.5 Input Current Limit (A) BAT Voltage (V) 4.35 4.3 4.25 4.2 1.5 IIN = 500mA IIN = 1.5A IIN = 2A 1 0.5 VREG = 4.208V 4.15 2 VREG = 4.35V 4.1 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 Temperature (oC) 50 75 100 125 150 Temperature (oC) Figure 8. BAT Voltage vs Temperature 2.5 Figure 9. Input Current Limit vs Temperature TREG = 120C TREG = 80C Charge Current (A) 2 1.5 1 0.5 0 60 80 100 120 140 160 Package Temperature (oC) Figure 10. Charge Current vs Package Temperature 14 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9 Detailed Description 9.1 Overview The bq24296, bq24297 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), lowside switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 15 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 9.2 Functional Block Diagram VBUS PMID RBFET (Q1) VVBUS_UVLOZ UVLO Q1 Gate Control VBATZ+VSLEEP SLEEP REGN REGN LDO EN_HIZ ACOV VACOV BTST FBO VBUS VOTG_OVP VINDPM VBUS_OVP_BOOST I(Q2) IOTG_HSZCP Q2_UCP_BOOST I(Q3) Q3_OCP_BOOST SW IOTG_LSOCP IINDPM BAT IC TJ CONVERTER CONTROL BATOVP HSFET (Q2) REGN 104%xVBAT_REG BAT TREG VBAT_REG LSFET (Q3) ILSFET_UCP UCP Q2_OCP I(Q3) SYS PGND IHSFET_OCP VSYSMIN ICHG_REG I(Q2) EN_HIZ EN_CHARGE EN_BOOST REFRESH VBTST-SW VBTST_REFRESH SYS ICHG VBAT_REG ICHG_REG REF DAC BAD_SRC CONVERTER CONTROL TSHUT STATE MACHINE ILIM D+ (bq24297) D- (bq24297) PSEL(bq24296) USB Host Adapter Detection BAT_GD USB Adapter OTG RECHRG INT I2C Interface SCL 16 SDA BATSHORT Q4 Gate Control BATFET (Q4) IDC BAT IC TJ TSHUT BAT QON VBATGD VBAT_REG - VRECHG BAT ICHG TERMINATION CHARGE ITERM CONTROL SUSPEND STATE VBATLOWV MACHINE BATLOWV BAT STAT PG(bq24296) IBADSRC bq24296/297 BATTERY THERMISTER SENSING TS VSHORT BAT CE Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.3 Feature Description 9.3.1 Device Power Up 9.3.1.1 Power-On-Reset (POR) The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR. 9.3.1.2 Power Up from Battery without DC Source If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. During both boost and charge mode, the device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again. 9.3.1.2.1 BATFET Turn Off The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode. 9.3.1.2.2 Shipping Mode To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage. The BATFET can be turned off by setting REG07[5] (BATFET_DISABLE) bit. In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] = 00) and disable BATFET (REG07[5] = 1) at the same time. Once the BATFET is disabled, one of the following events can turn on BATFET and clear REG07[5] (BATFET_DISABLE) bit. 1. Plug in adapter 2. Write REG07[5] = 0 3. watchdog timer expiration 4. Register reset (REG01[7] = 1) 5. A logic low to high transition on QON pin (refer to Figure 11 for detail timing) Min. 2ms QON BATFET Status Turn on by QON REG07[5]=0 Turn off by i2c command REG07[5]=1 Figure 11. QON Timing 9.3.1.3 Power Up from DC Source When the DC source plugs in, the charger device checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 17 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 9.3.1.3.1 REGN LDO The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS external resistors. The pull-up rail of STAT and PG (bq24296) can be connected to REGN as well. The REGN is enabled when all the conditions are valid. 1. VBUS above VVBUS_UVLOZ 2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode 3. After typical 220-ms delay (100 ms minimum) is complete If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS (15 A typical) from VBUS during HIZ state. The battery powers up the system when the device is in HIZ. 9.3.1.3.2 Input Source Qualification After REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter. 1. VBUS voltage below VACOV (not in VBUS over-voltage) 2. VBUS voltage above VBADSRC (3.8 V typical) when pulling IBADSRC (30 mA typical) (poor source detection) Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin (bq24296) goes low. An INT is asserted to the host. If the device fails the poor source detection, it will repeat the detection every 2 seconds. 9.3.1.3.3 Input Current Limit Detection The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (100 mA/500 mA in USB 2.0, and 150 mA/900 mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 3 A. After the PG is LOW (bq24296) or REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode. The bq24297 follows Battery Charging Specification 1.2 (BC1.2) to detect input source through USB D+/D- lines. The bq24296 sets input current limit through PSEL and OTG pins. After the input current limit detection is done, the detection result is reported in VBUS_STAT registers (REG08[7:6]) and input current limit is updated in IINLIM register (REG00[2:0]). In additon, host can write to REG00[2:0] to change the input current limit. 9.3.1.3.4 D+/D- Detection Sets Input Current Limit (bq24297) The bq24297 contains a D+/D- based input source detection to program the input current limit. The D+/Ddetection has three steps: data contact detect (DCD), primary detection, and non-standard adapter detection. When the charging source passes data contact detect, the device would proceed to run primary detection. Otherwise the charger would proceed to run non-standard adapter detection. 18 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 Feature Description (continued) D+ VDP_SRC VLGC_HI IDP_SRC CHG_DET VDAC_REF IDM_SINK D- RDM_DWN Figure 12. USB D+/D- Detection DCD (Data Contact Detection) uses a current source to detect when the D+/D- pins have made contact during an attach event. The protocol for data contact detect is as follows: * Detect VBUS present and REG08[2] = 1 (power good) * Turn on D+ IDP_SRC and the D- pull-down resistor RDM_DWN for 40 ms * If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec. * Turn off IDP_SRC and disconnect RDM_DWN The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP). The protocol for primary detection is as follows: * Turn on VDP_SRC on D+ and IDM_SINK on D- for 40 ms * If PD is attached to a USB host (SDP), the D- is low. If PD is attached to a charging port (CDP or DCP), the D- is high * Turn off VDP_SRC and IDM_SINK Table 2 shows the input current limit setting after D+/D- detection. Table 2. bq24297 USB D+/D- Detection D+/D- DETECTION OTG INPUT CURRENT LIMIT REG08[7:6] 0.5 sec timer expired in DCD (D+/D- floating) -- Proceed to non-standard adapter detection 00 USB host LOW 100 mA 01 USB host HIGH 500 mA 01 Charging port -- 3A 10 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 19 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com When DCD 0.5 sec timer expires, the non-standard adapter detection is used to distinguish three different divider bias conditions on D+/D- pins. When non-standard adapter is detected, the input current limit (REG0[2:0]) is set based on the table shown below and REG08[7:6] is set to 10 (Adapter port). If non-standard adapter is not detected, REG08[7:6] is set to 00 (Unknown) and the input current limit is set in REG0[2:0] to 500 mA by default. Table 3. bq24297 Non-Standard Adapter Detection NONSTANDARD ADAPTER INPUT CURRENT LIMIT D+ THRESHOLD D- THRESHOLD Divider 1 Vadpt1_lo < VD+ < Vadpt1_hi For VBUS = 5 V, typical range 2.4 V < VD+ < 3.1 V VD- < Vadpt1_lo or VD- > Vadpt1_hi For VBUS = 5 V, typical range VD- < 2.4 V or VD- > 3.1 V 2.0A Divider 2 Vadpt2_lo < VD+ < Vadpt2_hi For VBUS = 5 V, typical range 0.85 V < VD+ < 1.5 V NA 2.0A Divider 3 VD+< Vadpt3_lo or VD+> Vadpt3_hi For VBUS = 5 V, typical range VD+ < 2.4 V or VD+ > 3.1 V Vadpt3_lo < VD- < Vadpt3_hi For VBUS = 5 V, typical range 2.4 V < VD- < 3.1 V 1A After D+/D- detection is completed with an input source already plugged in, the input current limit is not changed unless DPDM_EN (REG07[7]) bit is set to force detection. 9.3.1.3.5 PSEL/OTG Pins Set Input Current Limit The bq24296 has PSEL instead of D+/D-. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. Table 4. bq24296 Input Current Limit Detection PSEL OTG INPUT CURRENT LIMIT REG08[7:6] HIGH LOW 100 mA 01 HIGH HIGH 500 mA 01 LOW -- 3A 10 9.3.1.3.6 HIZ State with 100mA USB Host In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state, the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 A. The system is supplied by the battery. Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state. In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another source plugs in, the charger IC will run detection again, and update the input current limit. 9.3.1.3.7 Force Input Current Limit Detection While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting REG07[7] = 1 or when watchdog timeout. During the forced detection, the input current limit is set to 100 mA. After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on D+/D- (bq24297) or PSEL/OTG (bq24296). 9.3.1.4 Converter Power-Up After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery. The device provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input current limit is forced to 100mA. After the system rises above 2.2 V, the charger device sets the input current limit set by the lower value between register and ILIM pin. 20 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 As a battery charger, the charger deploys a 1.5-MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design. A type III compensation network allows using ceramic capacitors at the output of the converter. An internal sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage. In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS. 9.3.1.5 Boost Mode Operation from Battery The device supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 1-A output requirement. The maximum output current is 1.5 A. The boost operation can be enabled if the following conditions are valid: 1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1]) 2. VBUS less than VBAT + VSLEEP (in sleep mode) 3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10) 4. Thermistor Temperature is within boost mode temperature monitor threshold unless BHOT[1:0] is set to 11 (REG06[1:0]) to disable this monitor function 5. After 30ms delay from boost mode enable In boost mode, the device employs a 1.5-MHz step-up switching regulator. Similar to buck operation, the device switches from PWM operation to PFM operation at light load to improve efficiency. During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5 V and the output current can reach up to 1 A or 1.5 A, selected via I2C (REG01[0]). In addition, the device provides adjustable boost voltage from 4.55 V to 5.5 V by changing BOOSTV bits in REG06[7:4] Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to 1 and an INT is asserted. 9.3.2 Power Path Management The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both. 9.3.2.1 Narrow VDC Architecture The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V). When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. When the battery charging is disabled or terminated, the system is always regulated at 150 mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 21 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 4.5 4.3 Charge Enabled 4.1 SYS (V) Charge Disabled 3.9 3.7 3.5 Minimum System Voltage 3.3 3.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 BAT (V) Figure 13. V(SYS) vs V(BAT) 9.3.2.2 Dynamic Power Management To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit. When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery. During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high. Figure 14 shows the DPM response with 5-V/1.2-A adapter, 3.2-V battery, 2.0-A charge current and 3.4-V minimum system voltage setting. Voltage VBUS 5V SYS 3.6V 3.4V 3.2V 3.18V BAT Current 3A ICHG 2.3A 2.0A ISYS 1.5A 1.0A 0.5A IIN -0.7A DPM DPM Supplement Figure 14. DPM Response 22 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.3.2.3 Supplement Mode When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold. 3.0 CURRENT (A) 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 V(BAT-SYS) (mV) Figure 15. BATFET V-I Curve 9.3.3 Battery Charging Management The device charges 1-cell Li-Ion battery with up to 3-A charge current for high capacity tablet battery. The 24-m BATFET improves charging efficiency and minimizes the voltage drop during discharging. 9.3.3.1 Autonomous Charging Cycle With battery charging enabled at POR (REG01[5:4] = 01), the charger device complete a charging cycle without host involvement. The device default charging parameters are listed in the following table. Table 5. Charging Parameter Default Setting (1) A * * * * * DEFAULT MODE bq24296 / bq24297 Charging voltage 4.208 V Charging current 2.048 A Pre-charge current 256 mA Termination current 256 mA Temperature profile Hot/Cold Safety timer 12 hours (1) See Charging Safety Timer for more information. new charge cycle starts when the following conditions are valid: Converter starts Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low No thermistor fault on TS No safety timer fault BATFET is not forced to turn off (REG07[5]) The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the device automatically starts another charging cycle. After the charge done, either toggle CE pin or REG01[5:4] will initiate a new charging cycle. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 23 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host. The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C. 9.3.3.2 Battery Charging Profile The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current. Table 6. Charging Current Setting VBAT CHARGING CURRENT REG DEFAULT SETTING REG08[5:4] VBAT < VSHORT (Typical 2 V) 100 mA - 01 VSHORT VBAT < VBATLOWV (Typical 2 V VBAT < 3 V) REG03[7:4] 256 mA 01 VBAT VBATLOWV (Typical VBAT 3 V) REG02[7:2] 2048 mA 10 If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate. Regulation Voltage (3.5V - 4.4V) Battery Voltage Fast Charge Current (500mA-3008mA) Charge Current VBAT_LOWV (2.8V/3V) VBAT_SHORT (2V) IPRECHARGE (128mA-2048mA) ITERMINATION (128mA-2048mA) IBATSHORT (100mA) Trickle Charge Pre-charge Fast Charge and Voltage Regulation Safety Timer Expiration Figure 16. Battery Charging Profile 9.3.3.3 Thermistor Qualification The charger device provides a single thermistor input for battery temperature monitor. 9.3.3.3.1 Cold/Hot Temperature Window The device continuously monitors battery temperature by measuring the voltage between the TS pin and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charge or boost is allowed. 24 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range. For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to VBHOTx thresholds unless boost mode temperature is disabled by setting BHOT bits (REG06[3:2]) to 11. When temperature is outside of the temperature thresholds, the boost mode is suspended and REG08[7:6] bits (VBUS_STAT) are set to 00. Once temperature returns within thresholds, the boost mode is recovered. REGN bq24296 bq24297 RT1 TS RT2 RTH 103AT Figure 17. TS Resistor Network When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended. TEMPERATURE RANGE TO INITIATE CHARGE TEMPERATURE RANGE DURING A CHARGE CYCLE VREGN VREGN CHARGE SUSPENDED CHARGE SUSPENDED VLTF VLTF VLTFH VLTFH CHARGE at full C CHARGE at full C VHTF VTCO CHARGE SUSPENDED CHARGE SUSPENDED AGND AGND Figure 18. TS Pin Thermistor Sense Thresholds in Charge Mode Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 25 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Temperature Range to Boost VREGN Boost Disable V BCOLDx (-10C / -20C) Boost Enable V BHOTx (55C / 60C / 65C) Boost Disable AGND Figure 19. TS Pin Thermistor Sense Thresholds in Boost Mode Assuming a 103AT NTC thermistor is used on the battery pack Figure 18, the value RT1 and RT2 can be determined by using the following equation: ae 1 1 o VREGN RTHCOLD RTHHOT c / V V TCO o e LTF RT2 = aeV o aeV o RTHHOT c REGN - 1/ - RTHCOLD c REGN - 1/ e VLTF o e VTCO o VREGN -1 VLTF RT1 = 1 1 + RT2 RTHCOLD (1) Select 0C to 45C range for Li-ion or Li-polymer battery, RTHCOLD = 27.28 k RTHHOT = 4.911 k RT1 = 5.25 k RT2 = 31.23 k 9.3.3.4 Charging Termination The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode. When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7]. 9.3.3.4.1 Termination When REG02[0] = 1 When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4]. 26 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.3.3.5 Charging Safety Timer The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 4 hours when the battery is below batlowv threshold. The user can program fast charge safety timer (default 12 hours) through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart the safety timer after safety timer expires: * Toggle the CE pin HIGH to LOW to HIGH (charge enable) * Write REG01[5:4] from 00 to 01 (charge enable) * Write REG05[3] from 0 to 1 (safety timer enable) During input voltage/current regulation, thermal regulation, or FORCE_20PCT bit (REG02[0]) is set , the safety timer counting at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6]. 9.3.3.5.1 Safety Timer Configuration Change When safety timer value needs to be changed, it is recommended that the timer is disabled first before new configuration is written to REG05[2:1]. The safety timer can be disable by writing 1 to REG05[3]. This ensures the safety timer restart counting after new value is configured. 9.3.3.6 USB Timer When Charging from USB100mA Source The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. 9.3.4 Status Outputs (PG, STAT, and INT) 9.3.4.1 Power Good Indicator (PG) (bq24296) In bq24296, PG goes LOW to indicate a good input source when: 1. VBUS above VBUS_UVLO 2. VBUS above battery (not in sleep) 3. VBUS below VACOV threshold 4. VBUS above VBUS_MIN when IBADSRC current is applied (not a poor source) 9.3.4.2 Charging Status Indicator (STAT) The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows. Table 7. STAT Pin State CHARGING STATE STAT Charging in progress (including recharge) LOW Charging complete HIGH Sleep mode, charge disable HIGH Charge suspend (Input over-voltage, TS fault, timer fault, input or system over-voltage) blinking at 1Hz 9.3.4.3 Interrupt to Host (INT) In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate a 256-s INT pulse. 1. USB/adapter source identified (through PSEL or DPDM detection, and OTG pin) 2. Good input source detected - not in sleep - VBUS below VACOV threshold Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 27 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com - current limit above IBADSRC 3. Input removed or VBUS above VACOV threshold 4. Charge Complete 5. Any FAULT event in REG09 For the first four events, INT pulse is always generated. For the last event, when a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads the fault register. If a prior fault exists, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and the 2nd reads the current fault register status. 9.3.5 Protections 9.3.5.1 Input Current Limit on ILIM For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as: 1V IINMAX = KLIM RILIM (2) The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3 A, and ILIM has a 316- resistor to ground for 1.5 A, the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings. The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation (Refer to Dynamic Power Path Management section). The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 3: V IIN = ILIM IINMAX (3) 1V For example, if ILIM pin sets 2 A, and the ILIM voltage is 0.75 V, the actual input current 1.5 A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1 V. If ILIM pin is short, the input current limit is set by the register. 9.3.5.2 Thermal Regulation and Thermal Shutdown During charge operation, the device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60C to 120C allows the user to optimize the system thermal performance. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high. Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host. 9.3.5.3 Voltage and Current Monitoring in Buck Mode The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode operation. 9.3.5.3.1 Input Over-Voltage (ACOV) The maximum input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host. 28 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.3.5.3.2 System Over-Voltage Protection (SYSOVP) The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to clamp the overshoot. 9.3.5.4 Voltage and Current Monitoring in Boost Mode The charger device closely monitors the VBUS voltage, as well as LSFET current to ensure safe boost mode operation. 9.3.5.4.1 Over-Current Protection The charger device closely monitors the RBFET (Q1) and LSFET (Q3) current to ensure safe boost mode operation. During over-current condition, the device will operate in hiccup mode for protection. While in hiccup mode cycle, the device turns off RBFET for tOTG_OCP_OFF (32 ms typical) and turns on RBFET for tOTG_OCP_ON (260 us typical) in an attempt to restart. If the over-current condition is removed, the boost converter will maintain the RBFET on state and the VBUS OTG output will operate normally. When over-current condition continues to exist, the device will repeat the hiccup cycle until over-current condition is removed. When over-current condition is detected, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is asserted to the host. 9.3.5.4.2 VBUS Over-Voltage Protection When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the VBUS voltage exceeds VOTG_OVP, the device stops switching and the device exits boost mode. During the overvoltage, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is asserted to the host. 9.3.5.5 Battery Protection 9.3.5.5.1 Battery Over-Voltage Protection (BATOVP) The battery over-voltage limit is clamped at VBAT_OVP (4% nominal) above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[3] goes high and an INT is asserted to the host. 9.3.5.5.2 Battery Short Protection If the battery voltage falls below Vshort (2V typical), the device immediately turns off BATFET to disable the battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100-mA current. The device does not turn on BATFET to discharge a battery that is below 2.5 V. 9.3.5.5.3 System Over-Current Protection If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET. 9.4 Device Functional Modes 9.4.1 Host Mode and Default Mode The device is a host controlled device, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or with host in sleep. When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings. The device keeps charging the battery by default with 12-hour fast charging safety timer. At the end of the 12 hours, the charging is stopped and the buck converter continues to operate to supply system load. Any write command to device transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4] = 00. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 29 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Device Functional Modes (continued) When the host changes watchdog timer configuration (REG05[5:4]), it is recommended to first disable watchdog by writing 00 to REG05[5:4] and then change the watchdog to new timer values. This ensures the watchdog timer is restarted after new value is written. POR watchdog timer expired Reset registers I2C interface enabled Host Mode Y I2C Write? Start watchdog timer Host programs registers N Default Mode Reset watchdog timer Reset registers N Y Reset REG01 bit[6]? Y N I2C Write? Y N Watchdog Timer Expired? Figure 20. Watchdog Timer Flow Chart 9.4.1.1 Plug in USB100mA Source with Good Battery When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold (VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement. If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state. If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit. 9.4.1.2 USB Timer When Charging from USB100mA Source The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. 9.5 Programming 9.5.1 Serial Interface The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). 30 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 Programming (continued) Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pullup resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain. 9.5.1.1 Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred. SDA SCL Data line stable; Data valid Change of data allowed Figure 21. Bit Transfer on the I2C Bus 9.5.1.2 START and STOP Conditions All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition. SDA SDA SCL SCL STOP (P) START (S) Figure 22. START and STOP Conditions 9.5.1.3 Byte Format Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 31 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Programming (continued) Acknowledgement signal from receiver Acknowledgement signal from slave MSB SDA SCL S or Sr 2 1 7 8 2 1 9 ACK START or Repeated START 8 9 ACK P or Sr STOP or Repeated START Figure 23. Data Transfer on the I2C Bus 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK) The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. 9.5.1.5 Slave Address and Data Direction Bit After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). SDA SCL S 1-7 8 9 START ADDRESS R/W ACK 8 1-7 9 8 1-7 ACK DATA DATA 9 P ACK STOP Figure 24. Complete Data Transfer 9.5.1.5.1 Single Read and Write 1 7 1 1 8 1 8 1 1 S Slave Address 0 ACK Reg Addr ACK Data Addr ACK P Figure 25. Single Write 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 1 1 Data NCK P Figure 26. Single Read If the register address is not defined, the charger IC send back NACK and go back to the idle state. 32 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 Programming (continued) 9.5.1.5.2 Multi-Read and Multi-Write The charger device supports multi-read and multi-write on REG00 through REG08. 1 7 1 1 8 1 S Slave Address 0 ACK Reg Addr ACK 8 1 8 1 8 1 1 Slave Address ACK Data to Addr+1 ACK Data to Addr+1 ACK P Figure 27. Multi-Write 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 1 Data @ Addr ACK 8 1 Data @ Addr+1 ACK 8 1 1 Data @ Addr+1 ACK P Figure 28. Multi-Read The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write. REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if there is a TS fault but gets recovered immediately, the host still sees TS fault during the first read. In order to get the fault information at present, the host has to read REG09 for the second time. REG09 does not support multi-read and multi-write. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 33 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 9.6 Register Map 9.6.1 I2C Registers Address: 6BH. REG00-07 support Read and Write. REG08-0A are Read only. 9.6.1.1 Input Source Control Register REG00 [reset = 00110xxx, or 3x] Figure 29. Input Source Control Register REG00 Format 7 EN_HIZ R/W 6 VINDPM[3] R/W 5 VINDPM[2] R/W 4 VINDPM[1] R/W 3 VINDPM[0] R/W 2 IINLIM[2] R/W 1 IINLIM[1] R/W 0 IINLIM[0] R/W LEGEND: R/W = Read/Write Table 8. Input Source Control Register REG00 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Bit 7 EN_HIZ R/W 0 0 - Disable, 1 - Enable Default: Disable (0) Offset 3.88 V, Range: 3.88 V - 5.08 V Default: 4.36 V (0110) Input Voltage Limit Bit 6 VINDPM[3] R/W 0 640 mV Bit 5 VINDPM[2] R/W 1 320 mV Bit 4 VINDPM[1] R/W 1 160 mV Bit 3 VINDPM[0] R/W 0 80 mV Input Current Limit (Actual input current limit is the lower of I2C and ILIM) Bit 2 IINLIM[2] R/W x Bit 1 IINLIM[1] R/W x Bit 0 IINLIM[0] R/W x 34 000 - 100 mA, 001 - 150 mA, 010 - 500 mA, 011 - 900 mA, 100 - 1 A, 101 - 1.5 A, 110 - 2 A, 111 - 3A Submit Documentation Feedback bq24296 PSEL = Lo : 3 A (111) PSEL = Hi : 100 mA (000) (OTG pin = Lo) or 500 mA (OTG pin = Hi) bq24297 Default SDP : 100 mA (000) (OTG pin = Lo) or 500 mA (OTG pin = Hi) Default DCP/CDP: 3 A (111) Default Divider 1 and 2 : 2 A (110) Default Divider 3 : 1 A (100) Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.6.1.2 Power-On Configuration Register REG01 [reset = 00011011, or 0x1B] Figure 30. Power-On Configuration Register REG01 Format 7 Register Reset R/W 6 I2C Watchdog Timer Reset R/W 5 4 3 2 1 0 OTG_CONFIG CHG_CONFIG SYS_MIN[2] SYS_MIN[1] SYS_MIN[0] BOOST_LIM R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write Table 9. Power-On Configuration Register REG01 Field Description BIT FIELD Bit 7 Bit 6 TYPE RESET DESCRIPTION NOTE Register Reset R/W 0 0 - Keep current register setting, 1 - Reset to default Default: Keep current register setting (0) Note: Register Reset bit does not reset device to default mode I2C Watchdog Timer Reset R/W 0 0 - Normal ; 1 - Reset Default: Normal (0) Note: Consecutive I2C watchdog timer reset requires minimum 20-s delay Bit 5 OTG_CONFIG R/W 0 0 - OTG Disable; 1 - OTG Enable (1) Default: OTG disable (0) Note: OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG Bit 4 CHG_CONFIG R/W 1 0- Charge Disable; 1- Charge Enable (1) Default: Charge Battery (1) Offset: 3.0 V, Range 3.0 V - 3.7 V Default: 3.5 V (101) Charger Configuration Minimum System Voltage Limit Bit 3 SYS_MIN[2] R/W 1 0.4 V Bit 2 SYS_MIN[1] R/W 0 0.2 V Bit 1 SYS_MIN[0] R/W 1 0.1 V 1 0 - 1 A, 1 - 1.5 A Boost Mode Current Limit Bit 0 (1) BOOST_LIM R/W Default: 1.5 A (1) The CHG_CONFIG and OTG_CONFIG bits cannot be set at the same time. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 35 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 9.6.1.3 Charge Current Control Register REG02 [reset = 01100000, or 60] Figure 31. Charge Current Control Register REG02 Format 7 ICHG[5] R/W 6 ICHG[4] R/W 5 ICHG[3] R/W 4 ICHG[2] R/W 3 ICHG[1] R/W 2 ICHG[0] R/W 1 BCOLD R/W 0 FORCE_20PCT R/W LEGEND: R/W = Read/Write Table 10. Charge Current Control Register REG02 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Offset: 512 mA Range: 512 - 3008 mA (000000 - 100111) Default: 2048 mA (011000) Note: ICHG higher than 3008mA is not supported Fast Charge Current Limit Bit 7 ICHG[5] R/W 0 2048 mA Bit 6 ICHG[4] R/W 1 1024 mA Bit 5 ICHG[3] R/W 1 512 mA Bit 4 ICHG[2] R/W 0 256 mA Bit 3 ICHG[1] R/W 0 128 mA Bit 2 ICHG[0] R/W 0 64 mA Bit 1 BCOLD R/W 0 Set Boost Mode temperature monitor threshold voltage to disable boost mode 0 - Vbcold0 (Typ. 76% of REGN or -10C w/ 103AT thermistor ) 1 - Vbcold1 (Typ. 79% of REGN or -20C w/ 103AT thermistor) Default: Vbcold0 (0) Bit 0 FORCE_20PCT R/W 0 0 - ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as PreCharge Current (REG03[7:4]) programmed 1 - ICHG as 20% Fast Charge Current (REG02[7:2]) and IPRECH as 50% PreCharge Current (REG03[7:4]) programmed Default: ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as Pre-Charge Current (REG03[7:4]) programmed (0) 9.6.1.4 Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11] Figure 32. Pre-Charge/Termination Current Control Register REG03 Format 7 IPRECHG[3] R/W 6 IPRECHG[2] R/W 5 IPRECHG[1] R/W 4 IPRECHG[0] R/W 3 ITERM[3] R/W 2 ITERM[2] R/W 1 ITERM[1] R/W 0 ITERM[0] R/W LEGEND: R/W = Read/Write Table 11. Pre-Charge/Termination Current Control Register REG03 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Offset: 128 mA, Range: 128 mA - 2048 mA Default: 256 mA (0001) Pre-Charge Current Limit Bit 7 IPRECHG[3] R/W 0 1024 mA Bit 6 IPRECHG[2] R/W 0 512 mA Bit 5 IPRECHG[1] R/W 0 256 mA Bit 4 IPRECHG[0] R/W 1 128 mA Termination Current Limit Bit 3 ITERM[3] R/W 0 1024 mA Bit 2 ITERM[2] R/W 0 512 mA Bit 1 ITERM[1] R/W 0 256 mA Bit 0 ITERM[0] R/W 1 128 mA 36 Offset: 128 mA Range: 128 mA - 2048 mA Default: 256 mA (0001) Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.6.1.5 Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2] Figure 33. Charge Voltage Control Register REG04 Format 7 VREG[5] R/W 6 VREG[4] R/W 5 VREG[3] R/W 4 VREG[2] R/W 3 VREG[1] R/W 2 VREG[0] R/W 1 BATLOWV R/W 0 VRECHG R/W LEGEND: R/W = Read/Write Table 12. Charge Voltage Control Register REG04 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Offset: 3.504 V Range: 3.504 V - 4.400 V Default: 4.208 V (101100) Charge Voltage Limit Bit 7 VREG[5] R/W 1 512 mV Bit 6 VREG[4] R/W 0 256 mV Bit 5 VREG[3] R/W 1 128 mV Bit 4 VREG[2] R/W 1 64 mV Bit 3 VREG[1] R/W 0 32 mV Bit 2 VREG[0] R/W 0 16 mV Bit 1 BATLOWV R/W 1 0 - 2.8 V, 1 - 3.0 V Default: 3.0 V (1) (pre-charge to fast charge) Battery Recharge Threshold (below battery regulation voltage) Bit 0 VRECHG R/W 0 0 - 100 mV, 1 - 300 mV Default: 100 mV (0) 9.6.1.6 Charge Termination/Timer Control Register REG05 [reset = 10011010, or 0x9A] Figure 34. Charge Termination/Timer Control Register REG05 Format 7 EN_TERM R/W 6 Reserved R/W 5 4 WATCHDOG[1] WATCHDOG[0] R/W R/W 3 EN_TIMER R/W 2 1 CHG_TIMER[1] CHG_TIMER[0] R/W R/W 0 Reserved R/W LEGEND: R/W = Read/Write Table 13. Charge Termination/Timer Control Register REG05 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Default: Enable termination (1) Charging Termination Enable Bit 7 EN_TERM R/W 1 0 - Disable, 1 - Enable Bit 6 Reserved R/W 0 0 - Reserved 00 - Disable timer, 01 - 40 s, 10 - 80 s, 11 - 160 s Default: 40 s (01) I2C Watchdog Timer Setting Bit 5 WATCHDOG[1] R/W 0 Bit 4 WATCHDOG[0] R/W 1 Charging Safety Timer Enable Bit 3 EN_TIMER R/W 1 0 - Disable, 1 - Enable Default: Enable (1) 00 - 5 hrs, 01 - 8 hrs, 10 - 12 hrs, 11 - 20 hrs Default: 12 hrs (10) (See Charging Safety Timer for details) Fast Charge Timer Setting Bit 2 CHG_TIMER[1] R/W 1 Bit 1 CHG_TIMER[0] R/W 0 Bit 0 Reserved R/W 0 0 - Reserved Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 37 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 9.6.1.7 Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73] Figure 35. Boost Voltage/Thermal Regulation Control Register REG06 Format 7 BOOSTV[3] R/W 6 BOOSTV[2] R/W 5 BOOSTV[1] R/W 4 BOOSTV[0] R/W 3 BHOT[1] R/W 2 BHOT[0] R/W 1 TREG[1] R/W 0 TREG[0] R/W LEGEND: R/W = Read/Write Table 14. Boost Voltage/Thermal Regulation Control Register REG06 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE Bit 7 BOOSTV[3] R/W 0 512 mV Bit 6 BOOSTV[2] R/W 1 256 mV Offset: 4.55 V Range: 4.55 V - 5.51 V Default:4.998 V (0111) Bit 5 BOOSTV[1] R/W 1 128 mV Bit 4 BOOSTV[0] R/W 1 64 mV Bit 3 BHOT[1] R/W 0 Bit 2 BHOT[0] R/W 0 Set Boost Mode temperature monitor threshold voltage to disable boost mode Voltage to disable boost mode 00 - Vbhot1 (33% of REGN or 55C w/ 103AT thermistor) 01 - Vbhot0 (36% of REGN or 60C w/ 103AT thermistor) 10 - Vbhot2 (30% of REGN or 65C w/ 103AT thermistor) 11 - Disable boost mode thermal protection. Default: Vbhot1 (00) Note: For BHOT[1:0] = 11, boost mode operates without temperature monitor and the NTC_FAULT is generated based on Vbhot1 threshold 00 - 60C, 01 - 80C, 10 - 100C, 11 - 120C Default: 120C (11) Thermal Regulation Threshold Bit 1 TREG[1] R/W 1 Bit 0 TREG[0] R/W 1 38 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 9.6.1.8 Misc Operation Control Register REG07 [reset = 01001011, or 4B] Figure 36. Misc Operation Control Register REG07 Format 7 DPDM_EN R/W 6 TMR2X_EN R/W 5 BATFET_Disable R/W 4 Reserved R/W 3 Reserved R/W 2 Reserved R/W 1 INT_MASK[1] R/W 0 INT_MASK[0] R/W LEGEND: R/W = Read/Write Table 15. Misc Operation Control Register REG07 Field Description BIT FIELD TYPE RESET DESCRIPTION NOTE R/W 0 0 - Not in Input current limit detection; 1 - Force Input current limit detection when VBUS power is presence Default: Not in Input current limit detection (0), Back to 0 after detection complete Force DPDM detection Bit 7 IINDET_EN Safety Timer Setting during Input DPM and Thermal Regulation Bit 6 TMR2X_EN R/W 1 0 - Safety timer not slowed by 2X during input DPM or thermal regulation, 1 - Safety timer slowed by 2X during input DPM or thermal regulation Default: Safety timer slowed by 2X (1) Default: Allow BATFET (Q4) turn on(0) Force BATFET Off Bit 5 BATFET_Disable R/W 0 0 - Allow BATFET (Q4) turn on, 1 - Turn off BATFET (Q4) Bit 4 Reserved R/W 0 0 - Reserved Bit 3 Reserved R/W 1 1 - Reserved Bit 2 Reserved R/W 0 0 - Reserved Bit 1 INT_MASK[1] R/W 1 0 - No INT during CHRG_FAULT, 1 - INT on CHRG_FAULT Default: INT on CHRG_FAULT (1) Bit 0 INT_MASK[0] R/W 1 0 - No INT during BAT_FAULT, 1 - INT on BAT_FAULT Default: INT on BAT_FAULT (1) 9.6.1.9 System Status Register REG08 Figure 37. System Status Register REG08 Format 7 6 5 VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] R R R 4 CHRG_STAT[0] R 3 DPM_STAT R 2 PG_STAT R 1 THERM_STAT R 0 VSYS_STAT R LEGEND: R = Read only Table 16. System Status Register REG08 Field Description BIT FIELD TYPE DESCRIPTION Bit 7 VBUS_STAT[1] R Bit 6 VBUS_STAT[0] R 00 - Unknown (no input, or DPDM detection incomplete), 01 - USB host, 10 - Adapter port, 11 - OTG Bit 5 CHRG_STAT[1] R Bit 4 CHRG_STAT[0] R Bit 3 DPM_STAT R 0 - Not DPM, 1 - VINDPM or IINDPM Bit 2 PG_STAT R 0 - Not Power Good, 1 - Power Good Bit 1 THERM_STAT R 0 - Normal, 1 - In Thermal Regulation Bit 0 VSYS_STAT R 0 - Not in VSYSMIN regulation (BAT > VSYSMIN), 1 - In VSYSMIN regulation (BAT < VSYSMIN) 00 - Not Charging, 01 - Pre-charge (<VBATLOWV), 10 - Fast Charging, 11 - Charge Termination Done Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 39 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 9.6.1.10 New Fault Register REG09 Figure 38. New Fault Register REG09 Format 7 WATCHDOG _FAULT R 6 5 4 3 2 1 0 OTG_FAULT CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT Reserved NTC_FAULT[1] NTC_FAULT[0] R R R R R R R LEGEND: R = Read only Table 17. New Fault Register REG09 Field Description (1) (2) (3) BIT FIELD TYPE DESCRIPTION Bit 7 WATCHDOG_FAULT R 0 - Normal, 1- Watchdog timer expiration Bit 6 OTG_FAULT R 0 - Normal, 1 - VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that cannot start boost function) Bit 5 CHRG_FAULT[1] R Bit 4 CHRG_FAULT[0] R 00 - Normal, 01 - Input fault (OVP or bad source), 10 - Thermal shutdown, 11 - Charge Timer Expiration Bit 3 BAT_FAULT R 0 - Normal, 1 - Battery OVP Bit 2 Reserved R Reserved - 0 Bit 1 NTC_FAULT[1] R 0-Normal 1-Cold Note: Cold temperature threshold is different based on device operates in buck or boost mode Bit 0 NTC_FAULT[0] R 0-Normal 1-Hot Note: Hot temperature threshold is different based on device operates in buck or boost mode (1) (2) (3) REG09 only supports single byte I2C read. All register bits in REG09 are latched fault. First time read of REG09 clears the previous fault and second read updates fault register to any fault that still presents. When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] is set to 01 once. 9.6.1.11 Vender / Part / Revision Status Register REG0A Figure 39. Vender / Part / Revision Status Register REG0A Format 7 PN[2] R 6 PN[1] R 5 PN[0] R 4 Reserved R 3 Reserved R 2 Rev[2] R 1 Rev[1] R 0 Rev[0] R LEGEND: R = Read only Table 18. Vender / Part / Revision Status Register REG0A Field Description BIT FIELD TYPE DESCRIPTION Bit 7 PN[2] R Bit 6 PN[1] R 001 (bq24296) 011 (bq24297) Bit 5 PN[0] R Bit 4 Reserved R 0 - Reserved Bit 3 Reserved R 0 - Reserved Bit 2 Rev[2] R 000 Bit 1 Rev[1] R Bit 0 Rev[0] R 40 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The bq24296 and bq24297 evaluation module (EVM) PWR021 is a complete charger module for evaluating the bq24296 and bq24297. The application curves were taken using the bq24296/297 VM-021. Refer to the Related Links section. 10.2 Typical Application bq24296 5V USB SDP/DCP VBUS PMID 1F 1H 10F BOOT REGN 317W (1.5A max) 4.7F ILIM SYS PGND 2.2kW SYS PG STAT VREF 10kW 10F 47nF 8.2F 10kW SYS: 3.5V-4.35V SW BAT 10F 10kW Host PHY SDA SCL INT OTG CE QON PSEL 4.2V Optional REGN 5.25kW TS 31.23kW Power Pad 10kW Charge Enable (0C - 45C) VREF is the pull up voltage of I2C communication interface. Figure 40. bq24296 with PSEL from PHY, Charging from SDP/DCP, and Optional BATFET Enable Interface Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 41 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com Typical Application (continued) bq24297 5V USB SDP/DCP 1 F 1H 10F 47nF 8.2F USB SYS: 3.5V-4.35V SW VBUS PMID 10F BTST REGN D+ 4.7F D- SYS PGND 2.2kW SYS STAT BAT 317W (1.5A max) 10F ILIM VREF QON 10kW 10kW 10kW REGN SDA SCL INT OTG CE Host 4.2V Optional 5.25kW TS 31.23kW 10kW Charge Enable (0C - 45C) Power Pad VREF is the pull up voltage of I2C communication interface. Figure 41. bq24297 with USB D+/D- Detection, USB On-The-Go (OTG) and Optional BATFET Enable Interface 10.2.1 Design Requirements Table 19. Design Requirements DESIGN PARAMATER EXAMPLE VALUE Input voltage range 3.9 V to 6.2 V Input current limit 3000 mA Fast charge current 3000 mA Boost mode output current 1.5 A 10.2.2 Detailed Design Procedure 10.2.2.1 Inductor Selection The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ICHG + (1/ 2 ) IRIPPLE (4) The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L): V D (1 - D) IRIPPLE = IN |s L (5) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20 - 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. 42 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 10.2.2.2 Input Capacitor Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation: ICIN = ICHG D (1 - D) (6) For best performance, VBUS should be decouple to PGND with 1-F capacitance. The remaining input capacitor should be place on PMID. Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25-V rating or higher capacitor is preferred for 15-V input voltage. 22-F capacitance is suggested for typical of 3-A to 4-A charging current. 10.2.2.3 Output Capacitor Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given: I ICOUT = RIPPLE 0.29 IRIPPLE 2 3 (7) The output capacitor voltage ripple can be calculated as follows: o VOUT aec V 1 - OUT / DVO = 2 c VIN / 8LC| s e o (8) At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 15 kHz and 36 kHz. The preferred ceramic capacitor is 6 V or higher rating, X7R or X5R. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 43 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 10.2.3 Application Performance Plots VBUS 5V/div VBUS 5V/div REGN 5V/div REGN 5V/div SYS 2V/div SYS 2V/div IVBUS 100mA/div IBAT 2A/div 100ms/div 100ms/div VBAT = 3.2 V VBAT = 3.2 V Figure 42. bq24296 Power Up with Charge Enabled Figure 43. bq24297 Power Up with Charge Enabled STAT 2V/div VBUS 5V/div CE 2V/div REGN 5V/div SW 5V/div SYS 2V/div IBAT 2A/div IBAT 1A/div 200ms/div 100ms/div VBAT = 3.2 V VBAT = 5 V Figure 44. bq24297 Power Up with Charge Disabled Figure 45. Charge Enable STAT 2V/div CE 5V/div IL 1A/div SW 5V/div SW 2V/div IBAT 1A/div 4ms/div 400ns/div VBUS = 5 V, No Battery, ISYS = 40 mA, Charge Disable Figure 46. Charge Disable 44 Figure 47. PWM Switching in Buck Mode Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 SYS3p5 500mV/div SYS3p7 100mV/div ISYS 2A/div SW 2V/div IL 1A/div IVBUS 2A/div 4ms/div 2ms/div VBUS = 5 V, IIN = 3 A, No Battery, Charge Disable VBUS = 5 V, VBAT = 3.6 V, ICHG = 2.5 A Figure 49. Input Current DPM Response without Battery Figure 48. PFM Switching in Buck Mode SYS3p8 500mV/div ISYS 2A/div SW 2V/div IBAT 2A/div IVBUS 2A/div IL 1A/div 400ns/div 20ms/div VBUS = 5 V, IIN = 1.5 A, VBAT = 3.8 V VBAT = 3.8 V, ILOAD = 1 A Figure 50. Load Transient During Supplement Mode Figure 51. Boost Mode Switching VBUS 200mV/div IBAT 1A/div IVBUS 1A/div 4ms/div VBAT = 3.8 V Figure 52. Boost Mode Load Transient Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 45 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 11 Power Supply Recommendations In order to provide an output voltage on SYS, the bq24296/297 require a power supply between 3.9 V and 6.2 V input with at least 100-mA current rating connected to VBUS; or, a single-cell Li-Ion battery with voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the charger to provide maximum output power to SYS. 12 Layout 12.1 Layout Guidelines The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 53) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane. 2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. 4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using thermal pad as the single ground connection point. Or using a 0 resistor to tie analog ground to power ground. 5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible. 7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 8. The via size and number should be enough for a given current path. See the EVM design for the recommended component placement with trace and via locations. For the VQFN information, refer to SCBA017 and SLUA271. Figure 53. High Frequency Current Path 46 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 bq24296, bq24297 www.ti.com SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 12.2 Layout Example CPMID PGND Top layer L CBUS PGND CREGN CBTST RBTST 2nd layer (PGND) PGND VBUS CSYS PIN1 via VSYS PGND VBAT PGND PGND on Top layer CBAT PGND PGND Figure 54. Layout Example Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 47 bq24296, bq24297 SLUSBP6C - SEPTEMBER 2013 - REVISED DECEMBER 2016 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation bq24296/7 EVM (PWR021) User's Guide (SLUUAQ1) Quad Flatpack No-Lead Logic Packages Application Report (SCBA017) QFN/SON PCB Attachment Application Report (SLUA271) 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 20. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY bq24296 Click here Click here Click here Click here Click here bq24297 Click here Click here Click here Click here Click here 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 48 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: bq24296 bq24297 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) BQ24296RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24296 BQ24296RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24296 BQ24297RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24297 BQ24297RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24297 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ24296RGER VQFN RGE 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24296RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24297RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24297RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24296RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24296RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24297RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24297RGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H PACKAGE OUTLINE VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD A 4.1 3.9 B 4.1 3.9 PIN 1 INDEX AREA 1 MAX C SEATING PLANE 0.05 0.00 0.08 C (0.2) TYP 2X 2.5 12 7 20X 0.5 6 13 25 2X 2.5 SYMM 1 PIN 1 ID (OPTIONAL) 18 24X 0.30 0.18 24 19 SYMM 24X 0.48 0.28 0.1 0.05 C A B C 4219016 / A 08/2017 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) ( 2.7) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) 25 SYMM (3.825) 2X (1.1) TYP 6 13 (R0.05) 12 7 2X(1.1) SYMM LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4219016 / A 08/2017 NOTES: (continued) 4. 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) 4X ( 1.188) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) SYMM (3.825) (0.694) TYP 6 13 (R0.05) TYP METAL TYP 25 7 SYMM 12 (0.694) TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED COVERAGE BY AREA SCALE: 20X 4219016 / A 08/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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