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KH29LV040C
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
3V ONLY EQUAL SECTOR FLASH MEMORY
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Any combination of sectors can be erased with erase
suspend/resume function
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 32-pin PDIP (not support now)
- 32-pin PLCC
- All Pb-free devices are RoHS Compliant
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8 only
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- 8 equal sector of 64K-Byte each
- Byte Programming (9us typical)
- Sector Erase (Sector structure 64K-Byte x8)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase
GENERAL DESCRIPTION
The KH29LV040C is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memor y. The KH29LV040C is
packaged in 32-pin PDIP and 32-pin PLCC. It is de-
signed to be repro g rammed and erased in system or in
standard EPROM programmers.
The standard KH29LV040C of fers access time as fast
as 55ns, allowing o peratio n o f high-speed micro proces-
sors without wait states. To eliminate bus contention,
the KH29LV040C has separate chip enab le (CE#) and
o utput enable (OE#) co ntrols.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and pro gramming. The
KH29LV040C uses a co mmand register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and pro gram cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The KH29LV040C uses a 2.7V~3.6V VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
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PIN CONFIGURATIONS
32 PLCC
32 PDIP
SYMBOL PIN NAME
A0~A18 Address Input
Q0~Q7 Data Input/Output
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
GND Ground Pin
VCC +3.0V single power supply
PIN DESCRIPTION
Sector A18 A17 A16 Address Range
SA0 0 0 0 00000h-0FFFFh
SA1 0 0 1 10000h-1FFFFh
SA2 0 1 0 20000h-2FFFFh
SA3 0 1 1 30000h-3FFFFh
SA4 1 0 0 40000h-4FFFFh
SA5 1 0 1 50000h-5FFFFh
SA6 1 1 0 60000h-6FFFFh
SA7 1 1 1 70000h-7FFFFh
Note:All sectors are 64 Kbytes in size.
SECTOR STRUCTURE
T able 1. KH29L V040C SECT OR ADDRESS T ABLE
KH29LV040
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
Q7
Q6
Q5
Q4
Q3
1
4
5
9
13
14 17 20
21
25
29
32 30 A14
A13
A8
A9
A11
OE#
A10
CE#
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
A12
A15
A16
A18
VCC
WE#
A17
KH29LV040C
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REV. 1.2, DEC. 09, 2005
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTA GE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0-A18
CE#
OE#
WE#
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REV. 1.2, DEC. 09, 2005
AUTOMATIC PROGRAMMING
The KH29LV040C is byte programmable using the Auto-
matic Pro gramming algo rithm. The Auto matic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the KH29LV040C is less than 10 sec-
onds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is acco mplished in
less than 4 seco nd. The Auto matic Erase algo rithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verificatio n of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The KH29LV040C is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
secto r(s) prio r to electrical erase. The timing and v erifi-
catio n of electrical erase are co ntro lled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device .
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The de vice auto matically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to Data# Polling and a status bit
to ggling between consecutive read cycles, pro vide feed-
back to the user as to the status of the programming
operation. Refer to write operation status table 6, for more
information on these status bits.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard micro processo r write timings. The device will auto-
matically pre-program and v erify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry . During write cycles, the co mmand register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
MXIC's Flash technology combines years of EPROM
e xperience to pro duce the highest le v els of quality, reli-
ability, and co st effectiveness. The KH29LV040C electri-
cally erases all bits simultaneously using Fowler-
No rdheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
thro ugh identifier co des o utput on Q7~Q0. This mo de is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1, and A0 as referring
to Table 2. In addition, to access the automatic select
codes in-system, the host can issue the automatic se-
lect command through the command register without
requiring VID , as shown in tab le 3.
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REV. 1.2, DEC. 09, 2005
A18 A15 A8 A5
Description CE# OE# WE# | | A9 | A6 | A1 A0 Q7~Q0
A16 A10 A7 A2
Read Manufacture Code L L H X X VID X L X L L C2H
Silicon ID Device ID L L H X X VI D X L X L H 4F H
01H
Sector Protection L L H SA X VID X L X H L (protected)
Verification 00H
(unprotected)
TABLE 2. KH29LV040C AUTOMATIC SELECT MODE OPERATION
NO TE:SA=Secto r Address, X=Don't Care, L=Lo gic Lo w , H=Logic High
To verify whether or no t secto r being protected, the sec-
tor address must appear on the appropriate highest order
address bit (see T able 1 and T able 2). The rest of address
bits, as shown in table 3, are do n't care. Once all neces-
sary bits have been set as required, the programming
equipment may read the corresponding identifier code on
Q7~Q0.
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REV. 1.2, DEC. 09, 2005
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Manufacture ID 4 555H AAH 2AAH 55H 555H 90H X00H C2H
Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H X01H 4FH
Sector Protect 4 555H AAH 2AAH 55H 555H 90H (SA) 00H
Verify x02H 01H
Program 4 555H AAH 2AAH 55H 555H A0H PA PD
Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30 H
TABLE 3. KH29LV040C COMMAND DEFINITIONS
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.
(Refer to table 2)
DDI = Data of Device identifier : C2H for manufacture code, 4FH for device code.
X = X can be VIL or VIH
RA=Address of memor y location to be read.
RD=Data to be read at location RA.
2. PA = Address of memor y location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
3. For Sector Protect Verify o peration : If read out data is 01H, it means the sector has been pro tected. If read o ut data is 00H, it
means the sector is still not being protected.
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ADDRESS
DESCRIPTION CE # OE# WE# A18 A1 5 A 9 A 8 A 6 A 5 A 1 A 0 Q0~Q7
A16 A10 A7 A2
Read L L H AIN Dout
Write L H L AIN DIN(3)
Reset X X X X High Z
Output Disable L H H X High Z
Standby Vcc±0.3V X X X High Z
Sector Protect L H L SA X X X L X H L X
Chip Unprotect L H L X X X X H X H L X
Sector Protection Verify L L H SA X VID X L X H L CODE(5)
TABLE 4. KH29LV040C BUS OPERATION
NOTES:
1. Manuf acture and de vice codes ma y also be accessed via a co mmand register write sequence. Ref er to Table 3.
2. VID is the Silicon-ID-Read high vo ltage, 11.5V to 12.5V.
3. Refer to Table 3 f o r valid Data-In during a write o peration.
4. X can be VIL or VIH, L=Logic Low=VIL, H=Logic High=VIH.
5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
6. A18~A13=Secto r address fo r secto r pro tect.
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mo de. Table 3 defines the valid register co mmand
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REV. 1.2, DEC. 09, 2005
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
co ntro l and selects the de vice. OE# is the o utput co ntro l
and gates array data to the o utput pins. WE# sho uld remain
at VIH.
The internal state machine is set for reading array data
upon device power-up. This ensures that no spurious
alteration of the memory content occurs during the power
transition. No command is necessary in this mode to
obtain array data. Standard microprocessor read cycles
that asser t valid address on the device address inputs
produce valid data o n the device data o utputs. The device
remains enabled for read access until the command
register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To pro gram data to the device or erase secto rs of memory
, the system must driv e WE# and CE# to VIL, and OE#
to VIH.
An erase o peration can erase one sector, multiple sectors
, or the entire device. T able 1 indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a secto r.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 3 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
STANDBY MODE
When the system is no t reading o r writing to the device,
it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC±0.3V. (Note that this is a
more restricted vo ltage range than VIH.) If CE# is held at
VIH, but not within VCC±0.3V, the device will be in the
standby mode, but the standby current will be greater.
The device requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
fro m the devices are disabled. This will cause the output
pins to be in a high impedance state.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
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REV. 1.2, DEC. 09, 2005
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.
The KH29LV040C co ntains a Silicon-ID-Read operation
to supple traditional PROM pro gr amming metho dology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
4FH for KH29LV040C.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlo c k" write cycles. These are f o llo wed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory fo r an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 6), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE# o r CE# pulse , whiche ver happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)
Manufacture code VIL VIL X 1 0 0 0 0 1 0 C 2H
Device code VIH VIL 0 1 0 0 1 1 1 1 4FH
Sector Protection Verification VIL VIH 0 0 0 0 0 0 0 0 00H (Unprotected)
TABLE 5. EXPANDED SILICON ID CODE
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REV. 1.2, DEC. 09, 2005
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.
RESET COMMAND
Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase
Suspend mode). Once programming begins, however,
the device ignores reset commands until the operation
is complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command must be written to return to reading array
data (also applies to SILICON ID READ during Erase
Suspend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mo de. The system is not
required to provide any control or timing during these
operations.
When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The secto r address is latched on the falling edge of WE#
or CE#, whichever happens later, while the
co mmand(data) is latched o n the rising edge of WE# o r
CE#, whichever happens first. Sector addresses se-
lected are lo aded into internal register o n the sixth f all-
ing edge of WE# o r CE#, whichever happens later . Each
successiv e secto r lo ad cycle started by the f alling edge
of WE# or CE#, whichever happens later must begin
within 50us fro m the rising edge of the preceding WE# o r
CE#, whichever happens first. Otherwise, the loading
perio d ends and internal auto secto r erase cycle starts.
(Monitor Q3 to determine if the sector erase timer win-
dow is still open, see section Q3, Sector Erase Timer.)
Any command other than Sector Erase(30H) or Erase
Suspend(B0H) during the time-out period resets the de-
vice to read mo de .
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Status Q7 Q6 Q5 Q3 Q2
(Note1) (Note2)
Byte Program in Auto Program Algorithm Q 7# Toggle 0 N/A No
Toggle
Auto Erase Algorithm 0 Toggle 0 1 Toggle
Erase Suspend Read 1 No 0 N/A Toggle
(Erase Suspended Sector) Toggle
In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data
(Non-Erase Suspended Sector)
Erase Suspend Program Q7# Toggle 0 N/A N/A
Byte Program in Auto Program Algorithm Q 7# Toggle 1 N/A No
Toggle
Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle
Erase Suspend Program Q7# Toggle 1 N/A N/A
Table 6. Write Operation Status
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appro priate subsectio n fo r further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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REV. 1.2, DEC. 09, 2005
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Secto r Erase o peratio n. When the Erase Suspend co m-
mand is written during a sector erase operation, the de-
vice requires a maximum of 100us to suspend the erase
operations. However , When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the command register will initiate erase suspend
mo de. The state machine will return to read mode auto-
matically after suspend is ready. At this time, state ma-
chine only allows the command register to respond to
the Read Memor y Array, Erase Resume and program
commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing. However ,
a 10ms time delay must be required after the erase re-
sume command, if the system implements an endless
erase suspend/resume loop, or the number of erase sus-
pend/resume is exceeded 1024 times . The erase times
will be expended if the erase behavior always be sus-
pended. (Please refer to MXIC Flash Application Note
for details.)
AUTOMATIC PROGRAM COMMANDS
To initiate A utomatic Program mo de, A three-cycle co m-
mand sequence is required. There are two "unlock" write
cycles. These are fo llowed by writing the Auto matic Pro-
gram command A0H.
Once the Automatic Program command is initiated, the
next WE# pulse causes a transition to an active pro-
gramming o peratio n. Addresses are latched on the fall-
ing edge, and data are internally latched o n the rising
edge o f the WE# o r CE#, whichev er happens first. The
rising edge of WE# or CE#, whichever happens first,
also begins the programming operation. The system is
not required to provide further controls or timings. The
device will auto matically pro vide an adequate internally
generated pro gram pulse and verify margin.
The device provides Q2, Q3, Q5, Q6, Q7 to determine
the status of a write operation. If the program operation
was unsuccessful, the data on Q5 is "1" (see Table 6),
indicating the program operation exceed internal timing
limit. The automatic programming o peration is completed
when the data read on Q6 stops toggling for two con-
secutive read cycles and the data on Q7 and Q6 are
equivalent to data written to these two bits, at which
time the device returns to the Read mode(no program
verify command is required).
WORD/BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 3 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, or Q6. See "Write Operation Status" for information
on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
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REV. 1.2, DEC. 09, 2005
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus o f a write operatio n: Q2, Q3, Q5, Q6 and Q7. Table 6
and the following subsections describe the functions of
these bits. Q7 and Q6 each offer a method for determin-
ing whether a program or erase operation is complete or
in progress. These three bits are discussed first.
Q7: Data# Polling
The Data# P o lling bit, Q7, indicates to the ho st sys-tem
whether an Automatic Algorithm is in progress or com-
pleted, o r whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to pro gramming dur-
ing Erase Suspend. When the Automatic Pro gram algo-
rithm is complete, the device outputs the datum pro-
gr ammed to Q7. The system must provide the pro gram
address to read valid status information on Q7. If a pro-
gram address f alls within a protected secto r, Data# P o ll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.
During the Auto matic Erase algo rithm, Data# Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mo de , Data# P o lling pro duces a "1" o n Q7. This is
analogous to the complement/true datum output de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement," or "0". The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
After an erase command sequence is written, if all sec-
to rs selected fo r erasing are pro tected, Data# Polling o n
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
ab le (OE#) is asserted low.
Q6:Toggle BIT I
To ggle Bit I on Q6 indicates whether an A uto matic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge o f the final WE# o r CE#, whichever
happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
co ntrol the read cycles. When the o peratio n is complete,
Q6 sto ps to ggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
If a program address f alls within a protected secto r, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
Table 6 shows the outputs for Toggle Bit I on Q6.
still "0". Only erase operations can convert a "0" to a
"1".
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Q2:Toggle Bit II
The "To ggle Bit II" on Q2, when used with Q6, indicates
whether a par ticular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge o f the final WE# o r CE#, whichever
happens first, in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , bo th status bits
are required for sectors and mode information. Refer to
Table 6 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a to ggle bit is toggling. Typically , the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
co mpleted the pro gram o r erase o peratio n. The system
can read array data on Q7-Q0 on the following read cycle.
How ever, if after the initial two read cycles , the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must wr ite
the reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perfor m other system tasks. In
this case, the system m ust start at the beginning o f the
algorithm when it returns to determine the status of the
operation.
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data# Polling and Toggle
Bit are the only operating functions of the device under
this co nditio n.
If this time-out condition occurs during sector erase op-
eratio n, it specifies that a particular secto r is bad and it
may no t be reused. However , other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program o r erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-o ut is co mplete. Data# P o lling
and T o ggle Bit are valid after the initial secto r erase co m-
mand sequence.
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REV. 1.2, DEC. 09, 2005
POWER-UP SEQUENCE
The KH29LV040C powers up in the Read o nly mo de. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.
SECTOR PROTECTION
The KH29LV040C f eatures hardware secto r pro tectio n.
This feature will disable both program and erase opera-
tio ns f o r these secto rs pro tected. To activ ate this mo de,
the pro gramming equipment must f o rce VID o n address
pin A9 and OE# (suggest VID = 12V). Programming of
the protectio n circuitry begins o n the f alling edge of the
WE# pulse and is terminated o n the rising edge. Please
refer to sector protect algorithm and waveform.
To verify programming o f the protection circuitry , the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at device output Q0 for a pro tected sector . Other-
wise the device will produce 00H for the unprotected sec-
to r. In this mode, the addresses, except fo r A1, are don't
care. Address locations with A1 = VIL are reser ved to
read manufacturer and device co des.(Read Silico n ID)
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
P erfo rming a read operatio n with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
If Data# P olling or the To ggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is co mpleted as indicated b y Data# Po lling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
DATA PROTECTION
The KH29LV040C is designed to o ffer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorpo-
rates several features to pre vent inadvertent write cycles
resulting fro m VCC power-up and power-down transitio n
or system noise.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND .
16
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KH29LV040C
REV. 1.2, DEC. 09, 2005
CHIP UNPROTECT
The KH29LV040C also features the chip unprotect mo de,
so that all sectors are unprotected after chip unprotect
is completed to incorporate any changes in the code. It
is recommended to protect all sectors before activating
chip unprotect mode.
To activate this mo de, the pro gramming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. Refer to chip unpro tect algorithm and wavefo rm fo r
the chip unprotect algorithm. The unprotected mecha-
nism begins o n the falling edge o f the WE# pulse and is
terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
P erfo rming a read o peration with A1=VIH, it will produce
00H at data o utputs(Q0-Q7) fo r an unpro tected secto r.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
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REV. 1.2, DEC. 09, 2005
ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Vo ltage with Respect to Gro und
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC vo ltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During vo ltage transitio ns, input o r I/O pins may o ver-
sho ot to VCC +2.0 V f or perio ds up to 20 ns.
2. Minimum DC input vo ltage o n pins A9 and OE# is -0.5
V. During voltage transitio ns , A9 and OE# may ov er-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC input voltage on pin A9 is +12.5 V which
ma y oversho ot to 14.0 V f or perio ds up to 20 ns.
3. No mo re than one output ma y be shorted to gro und at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define tho se limits between which the
functio nality o f the de vice is guaranteed.
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Table 7. CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 1 2 pF VIN = 0V
COUT Output Capacitance 12 p F V OUT = 0V
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
Table 8. DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 2.7V to 3.6V
Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current ± 1 uA VIN = VSS to VCC
ILIT A9 Input Leakage Current 3 5 uA VCC=VCC max; A9=12.5V
ILO Output Leakage Current ± 1 uA V OUT = VSS to VCC, VCC=VCC max
ICC1 VCC Active Read Current 7 1 2 mA CE#=VIL, OE#=VIH @5MHz
2 4 mA @1MHz
ICC2 VCC Active write Current 1 5 3 0 mA CE#=VIL, OE#=VIH
ICC3 VCC Standby Current 0.2 5 uA CE#;VCC ± 0.3V
ICC4 VCC Standby Current 0.2 5 uA CE#; VCC ± 0.3V
During Reset
ICC5 Automatic sleep mode 0.2 5 uA VIH=VCC ± 0.3V;VIL=VSS ± 0.3V
VIL Input Low Voltage(Note 1) -0.5 0.8 V
VIH Input High Voltage 0.7xVCC VCC+ 0.3 V
VID Voltage for Auto 11.5 12.5 V VCC=3.3V
Select
VOL Output Low Voltage 0.45 V IOL = 4.0mA, VCC= VCC min
VOH1 Output High Voltage(TTL) 0.85xVCC IOH = -2mA, VCC=VCC min
VOH2 Output High Voltage VCC-0.4 IOH = -100uA, VCC min
(CMOS)
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KH29LV040C
REV. 1.2, DEC. 09, 2005
NOTE:
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
TEST CONDITIONS:
•Input pulse levels: 0V/3.0V.
•Input rise and fall times is equal to or less than 5ns.
•Output load: 1 TTL gate + 100pF (Including scope and
jig), for 29LV040C-90. 1 TTL gate + 30pF (Including
scope and jig) for 29LV040C-70.
•Reference levels for measuring timing: 1.5V.
AC CHARACTERISTICS
Table 9. READ OPERATIONS
29LV040C-70 29LV040C-90
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS
tRC Read Cycle Time (Note 1) 7 0 90 ns
tACC Address to Output Delay 7 0 9 0 ns CE#=OE#=VIL
tCE CE# to Output Delay 7 0 90 ns OE#=VIL
tOE OE# to Output Delay 30 35 ns CE#=VIL
tDF OE# High to Output Float (Note 2) 0 25 0 30 ns CE#=VIL
tOEH Output Enable Read 0 0 ns
Hold Time Toggle and 10 10 ns
Data# Polling
tOH Address to Output hold 0 0 ns CE#=OE#=VIL
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 1. SWITCHING TEST CIRCUITS
Figure 2. SWITCHING TEST WAVEFORMS
TEST POINTS
3.0V
0V
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
OUTPUT
1.5V1.5V
INPUT
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm +3.3V
CL=100pF Including jig capacitance
CL=30pF for KH29LV040-70
21
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 3. READ TIMING WAVEFORMS
Addresses
CE#
OE#
tACC
WE#
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
HIGH Z HIGH Z
D ATA V alid
tOE
tOEH tDF
tCE
tACC
tRC
Outputs
tOH
ADD V alid
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KH29LV040C
REV. 1.2, DEC. 09, 2005
AC CHARACTERISTICS
Table 10. Erase/Program Operations
Parameter Speed Options
Std. Description 70 90 Unit
tW C Write Cycle Time (Note 1) Mi n 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Hold Time Min 4 5 ns
tDS Data Setup Time Min 35 4 5 ns
tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL Read Recovery Time Before Write Min 0 ns
(OE# High to WE# Low)
tCS CE# Setup Time Min 0 ns
tCH CE# Hold Time Min 0 ns
tWP Write Pulse Width Min 3 5 ns
tWPH Write Pulse Width High Min 3 0 ns
tWHWH1 Programming Operation (Note 2) Typ 9 us
tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCC Setup Time (Note 1) Min 5 0 us
tBAL Sector Address Load Time Max 5 0 us
NOTES:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or mo re info rmatio n.
23
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REV. 1.2, DEC. 09, 2005
NOTE:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or mo re info rmatio n.
AC CHARACTERISTICS
Table 11. Alternate CE# Controlled Erase/Program Operations
Parameter Speed Options
Std. Description 70 90 Unit
tWC Write Cycle Time (Note 1) Min 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Ho ld Time Min 4 5 ns
tDS Data Setup Time Min 3 5 4 5 ns
tDH Data Ho ld Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL Read Reco very Time Befo re Write Min 0 ns
tWS WE# Setup Time Min 0 ns
tWH WE# Ho ld Time Min 0 ns
tCP CE# Pulse Width Min 3 5 ns
tCPH CE# Pulse Width High Min 3 0 ns
tWHWH1 Programming Operation(note2) Typ 9 us
tWHWH2 Sector Erase Operatio n (note2) Typ 0.7 sec
24
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REV. 1.2, DEC. 09, 2005
Figure 4. COMMAND WRITE TIMING WAVEFORM
Addresses
CE#
OE#
WE#
DIN
tDS
tAH
Data
tDH
tCS tCH
tCWC
tWPH
tWP
tOES
tAS
VCC 3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADD V alid
25
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REV. 1.2, DEC. 09, 2005
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tio n can be verified by Data# Polling and toggle bit check-
ing after auto matic programming starts. Device o utputs
DA TA# during programming and DAT A# after programming
o n Q7.(Q6 is f o r to ggle bit; see toggle bit, Data# P o lling,
timing waveform)
tWC
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
PA PA
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH1
Read Status Data (last two cycle)Program Command Sequence(last two cycle)
tCS tWPH
tVCS
WE#
Data
VCC
26
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Verify Word Ok ?
YES
Auto Program Completed
Data Poll
from system
Increment
Address
Last Address ?
No
No
27
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REV. 1.2, DEC. 09, 2005
Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM
tWC
tWH
tGHEL
tWHWH1 or 2
tCP
Address
WE#
OE#
CE#
Data Q7
PA
Data# Polling
DOUT
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
tAH
tAS
PA for program
SA for sector erase
555 for chip erase
tDH
tDS
tWS
A0 for program
55 for erase
tCPH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
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REV. 1.2, DEC. 09, 2005
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by Data# P o lling and to ggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, Data# P olling, timing wavefo rm)
Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM
AUTOMATIC CHIP ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh 555h
10h In
Progress Complete
VA VA
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tCS tWPH
tVCS
WE#
Data
VCC
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data Pall from System
Auto Chip Erase Completed
30
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A13 to A18 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by Data# Polling and toggle bit check-
ing after automatic erase starts. De vice outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see to ggle bit, Data# P o lling, timing wa vef o rm)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
Sector
Address n
tAS
tAH
tBAL
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tCS tWPH
tVCS
WE#
Data
VCC
30h
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data Poll from System
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART
Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is
exceeded 1024 times, then the 10ms time delay must be put into consideration.
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Delay 10ms (note)
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
33
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 13. TIMING WAVEFORM FOR SECTOR PROTECT
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
A6
tOESP
tWPP 1
tVLHT
tVLHT
tVLHT
Verify
01H F0H
A18-A12 Sector Address
34
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 14. SECTOR PROTECTION ALGORITHM
START
Set Up Sector Addr
PLSCNT=1
Sector Protection
Complete
Data=01H?
Yes
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
35
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 15. TIMING WAVEFORM FOR CHIP UNPROTECTED
Notes: tWPP1 (Write pulse width for sector protect)=100ns min.
tWPP2 (Write pulse width for sector unprotect)=100ns min.
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
tOESP
tWPP 2
tVLHT
tVLHT
tVLHT
Verify
00H
A6
Sector Address
A17-A12
F0H
36
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 16. CHIP UNPROTECTED ALGORITHM
START
Protect All Sectors
PLSCNT=1
Chip Unprotect
Complete
Data=00H?
Yes
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 50ms
Set OE#=CE#=VIL
A9=VID,A1=1
Set Up First Sector Addr
All sectors have
been verified?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Increment
PLSCNT
No
Read Data from Device
Yes
Yes
No
Increment
Sector Addr
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
37
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 17. DATA# POLLING ALGORITHM
WRITE OPERATION STATUS
Read Q7~Q0
Add.=VA(1)
Read Q7~Q0
Add.=VA
Start
Q7 = Data ?
Q5 = 1 ?
Q7 = Data ?
FAIL Pass
No
No
(2)
No
Yes
Yes
Yes
NOTE : 1.VA=Valid address for programming
2.Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.
38
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 18. TOGGLE BIT ALGORITHM
Read Q7-Q0
Read Q7-Q0
Q5= 1?
Read Q7~Q0 Twice
Program/Erase Operation
Not Complete,Write
Reset Command
Program/Erase
operation Complete
Toggle bit Q6=
Toggle?
Toggle Bit Q6 =
Toggle ? NO
(Note 1)
(Note 1,2)
YES
NO
NO
YES
YES
Note:1.Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".
Start
39
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 19. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS)
NOTES:
1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
2. CE# must be toggled when DATA# polling.
tDF
tCE
tACC
tRC
tCH
tOE
tOEH
tOH
Address
CE#
OE#
WE#
Q7
Q0-Q6
Status Data Status Data
Complement Complement Valid DataTrue
VAVAVA
High Z
High Z
Valid DataTrue
40
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
NOTES:
1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
2. CE# must be toggled when toggle bit toggling.
tDF
tCE
tACC
tRC
tCH
tOE
tOEH
High Z
tOH
Address
CE#
OE#
WE#
Q6/Q2 Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA
Valid Data
41
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 21. Q6 vs Q2 for Erase and Erase Suspend Operations
NOTES:
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
WE#
Enter Embedded
Erasing Erase
Suspend Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read Erase
Erase
Resume
Erase
Complete
Erase
Q6
Q2
42
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KH29LV040C
REV. 1.2, DEC. 09, 2005
Figure 22. ID CODE READ TIMING WAVEFORM
tACC
tCE
tACC
tOE
tOH tOH
tDF
DATA OUT
C2H/00C2H B9H/BAH (Byte)
22B9H/22BAH (Word)
VID
VIH
VIL
ADD
A9
ADD
A2-A8
A10-A17
CE#
OE#
WE#
ADD
A0
DATA OUT
DATA
Q0-Q7
VCC
A1
3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
43
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KH29LV040C
REV. 1.2, DEC. 09, 2005
RECOMMENDED OPERATING CONDITIONS
At Device P ower-Up
AC timing illustrated in Figure A is reco mmended f o r the supply vo ltages and the co ntro l signals at de vice power-up .
If the timing in the figure is igno red, the device ma y no t operate co rrectly.
Figure A. A C Timing at Device P ower-Up
No tes :
1. Sampled, no t 100% tested.
2. This specificatio n is applied f o r no t o nly the device po wer-up but also the no rmal o peratio ns.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 2 0 500000 us/V
tR Input Signal Rise Time 1, 2 2 0 us/V
tF Input Signal F all Time 1 ,2 2 0 us/V
VCC
ADDRESS
CE#
WE#
OE#
DATA
tVR
tACC
tR or tF
tCE
tF
VCC(min)
GND
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH High Z
VOL
WP#/ACC VIH
VIL
Valid
Ouput
Valid
Address
tR or tF
tR
tOE
tF tR
44
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KH29LV040C
REV. 1.2, DEC. 09, 2005
MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
LIMITS
PARAMETER MIN. TYP.(2) MAX.(3) UNITS
Sector Erase Time 0. 7 1 5 sec
Chip Erase Time 4 3 2 sec
Byte Programming Time 9 300 us
Chip Programming Time 4.5 13.5 sec
Erase/Program Cycles 100,000 Cycles
Table 13. LATCH-UP CHARACTERISTICS
Table 12. ERASE AND PROGRAMMING PERFORMANCE (1)
Note: 1.Not 100% Tested, Excludes e xternal system le v el over head.
2.Typical values measured at 25°C, 3V.
3.Maximum values measured at 25°C, 2.7V.
Table 14. DATA RETENTION
Parameter Description Test Conditions Min Unit
150°C 10 Years
Data Retention Time 125°C 20 Years
45
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KH29LV040C
REV. 1.2, DEC. 09, 2005
QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE ( for KH29LV040C)
KH29LV040C is capable of operating in the CFI mode.
This mode all the host system to determine the manu-
facturer of the device such as operating parameters and
co nfiguratio n. Two commands are required in CFI mo de.
Quer y command of CFI mode is placed first, then the
Reset command exits CFI mode. These are described in
Table 15.
TABLE 15-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "QRY" 2 0 1 0 0051
22 11 0052
24 12 0059
Primary vendor command set and control interface ID code 2 6 1 3 0002
28 14 0000
Address for primary algorithm extended query table 2A 1 5 0040
2C 16 0000
Alternate vendor command set and control interface ID code (none) 2E 1 7 0000
30 18 0000
Address for secondary algorithm extended query table (none) 32 19 0000
34 1A 0000
TABLE 15-2. CFI Mode: System Interface Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
VCC supply, minimum (2.7V) 3 6 1B 0027
VCC supply, maximum (3.6V) 3 8 1 C 0036
VPP supply, minimum (none) 3A 1D 0000
VPP supply, maximum (none) 3 C 1 E 0000
Typical timeout for single word/byte write (2N us) 3E 1F 0004
Typical timeout for Minimum size buffer write (2N us) 4 0 2 0 0000
Typical timeout for individual block erase (2N ms) 42 2 1 000A
Typical timeout for full chip erase (2N ms) 4 4 22 0000
Maximum timeout for single word/byte write times (2N X Typ) 46 23 0005
Maximum timeout for buffer write times (2N X Typ) 48 24 0000
Maximum timeout for individual block erase times (2N X Typ) 4 A 25 0004
Maximum timeout for full chip erase times (not supported) 4C 2 6 0000
The single cycle Query co mmand is valid o nly when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Read ID mo de; however , it is ignored
otherwise.
The Reset command exits from the CFI mode to the
Read mo de , o r Erase Suspend mo de , o r read ID mo de.
The co mmand is valid o nly when the device is in the CFI
mode.
46
P/N:PM1220
KH29LV040C
REV. 1.2, DEC. 09, 2005
TABLE 15-3. CFI Mode: Device Geometry Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Device size (2N bytes) 4E 27 0013
Flash device interface code (refer to the CFI publication 100) 5 0 2 8 0000
52 29 0000
Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000
56 2B 0000
Number of erase block regions 5 8 2 C 0001
Erase block region 1 information (refer to the CFI publication 100) 5A 2D 0007
5C 2E 0000
5E 2F 0000
60 30 0001
Erase block region 2 information 6 2 31 0000
64 32 0000
66 33 0000
68 34 0000
Erase block region 3 information 6A 3 5 0000
6C 36 0000
6E 37 0000
70 38 0000
Erase block region 4 information 7 2 39 0000
74 3A 0000
76 3B 0000
78 3C 0000
TABLE 15-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "PRI" 8 0 4 0 0050
82 41 0052
84 42 0049
Major version number, ASCII 8 6 43 0031
Minor version number, ASCII 8 8 44 0030
Address sensitive unlock (0=required, 1= not required) 8A 45 0001
Erase suspend (2= to read and write) 8 C 4 6 0002
Sector protect (N= # of sectors/group) 8E 47 0001
Temporary sector unprotected (1=supported) 90 48 0001
Sector protect/unprotected scheme 92 49 0004
Simultaneous R/W operation (0=not supported) 94 4A 0000
Burst mode type (0=not supported) 9 6 4B 0000
Page mode type (0=not supported) 98 4C 0000
47
P/N:PM1220
KH29LV040C
REV. 1.2, DEC. 09, 2005
ORDERING INFORMATION
P ART NO. ACCESS OPERATING STANDBY PACKA GE Remark
TIME(ns) CURRENT MAX.(mA) CURRENT MAX.(uA)
KH29LV040CPC-70 70 3 0 5 32 Pin PDIP
KH29LV040CPC-90 90 3 0 5 32 Pin PDIP
KH29LV040CQC-70 7 0 3 0 5 32 Pin PLCC
KH29LV040CQC-90 9 0 3 0 5 32 Pin PLCC
KH29LV040CPC-70G 70 30 5 32 Pin PDIP PB free
KH29LV040CPC-90G 90 30 5 32 Pin PDIP PB free
KH29LV040CQC-70G 7 0 3 0 5 32 Pin PLCC PB free
KH29LV040CQC-90G 9 0 3 0 5 32 Pin PLCC PB free
48
P/N:PM1220
KH29LV040C
REV. 1.2, DEC. 09, 2005
PART NAME DESCRIPTION
KH 29 LV 70C T C G
OPTION:
G: Lead-free package
blank: normal
SPEED:
70: 70ns
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0˚C to 70˚C)
PACKAGE:
P:PDIP
Q: PLCC
REVISION:
C
DENSITY & MODE:
040: 4M, x8 Equal Sector
TYPE:
L, LV: 3V
DEVICE:
29:Flash
040
49
P/N:PM1220
KH29LV040C
REV. 1.2, DEC. 09, 2005
PACKAGE INFORMATION
50
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KH29LV040C
REV. 1.2, DEC. 09, 2005
51
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KH29LV040C
REV. 1.2, DEC. 09, 2005
REVISION HISTORY
Revision No. Description Page Date
1.0 1. Removed "Preliminary" P1 JUL/01/2005
2. Modified "Package Information" P49, 50
1.1 1. Modified "Low power co nsumption--active current" fro m 20mA(Max.) P1 A UG/30/2005
to 30mA(Max.)
2. Added descriptio n about Pb-free devices are RoHS Co mpliant P1
1.2 1. Mo dified content erro r P40,43 DEC/09/2005
KH29LV040C
MACRONIX INTERNATIONAL CO., LTD .
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
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TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
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TEL:+65-6346-5505
FAX:+65-6348-8096
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TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
