5821 ruru 5823 BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS _ [ wwwnorear TFAMATYT OmMnow~Tnec | | ste yA Meaty byeP-B: CLOCK L DATA IN > GROUND SHIFT REGISTER JT ENABLE 2 GROUND [8 | Dwg No PP-026 BSOLUTE MAXIMUM RATINGS at 25C Free-Air Temperature yut Voltage, Vay, (UCN5821A).....---- 002 ee eee 50V (UCN5822A).... 00-2022 eee eee 80V (UCN5823A).....-----+ 22ers 100 V ic Supply Voltage, Voy. ----- +++: 15V it Voltage Range, Viner cteeeeteee 0.3 VtoV,,+0.3V tinuous Output Current, lor ccct cet eeeeseesetttet 500 mA kage Power Dissipation, Pol cee ce eee 2.08 W* 2) srating Temperature Range, TT 90C to +85C 4 Cc 4 = | Y | BiMOS I 8-BIT SERIAL-INPUT, LATCHED DRIVERS A merged combination of bipolar and MOS technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. The three devices in this series each have an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. Except for maximum driver output voltage ratings, the UCN5821A, UCN5822A, and UCN5823< are identical. BiIMOS II devices have much higher data-input rates than the original BIMOS circuits. With a 5 V logic supply, they will typically operate at better than 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. FEATURES @ 3.3 MHz Minimum Data Input Rate m@ CMOS, NMOS, TTL Compatible @ Internal Pull-Down Resistors m@ Low-Power CMOS Logic & Latches @ High-Voltage Current-Sink Outputs @ 16-Pin Dual In-Line Plastic Package ADEs: OS Il 8-BIT SERIAL-INPUT, LATCHED DRIVERS YTRICAL CHARACTERISTICS at T, = +25C, V_,, = 5 V, (unless otherwise specified). Applicable Limits icteristic Symbol Devices Test Conditions Min. Max. Units it Leakage Current loex UCN5821A Vour = 50 Vv 50 pA | Vout = 50 V, Ty = +70C 100 pA | UCN5822A | V4, = 80V 50 pA | Vour = 80 V, T, = +70C 100 pA UCN5823A Voyr = 100 V _ 50 LA Vour = 100 V, T, = +70C 100 pA stor-Emitter Vegisar) ALL lout = 100 mA 1.1 Vv ation Voitage 12 200 mA 13 v OUT loyr = 350 MA, Vo, = 7.0 V 1.6 V Voltage Vino) ALL ; _ 0.8 Vv Vines) ALL Vop = 12 V 10.5 Vv Vop = 10V 8.5 Vv Vop = 9-0 V 3.5 _ V Resistance Ay ALL Vop = 12 V 50 _ kQ Vap = 10V 50 ~ kQ Vop = 5:0 V 50 kQ 'y Current IpD(ON) ALL One Driver ON, Vp, = 12 V 4.5 mA One Driver ON, V,, = 10 V _ 3.9 mA One Driver ON, Vp, = 5.0 V _ 2.4 mA loD(oFF) ALL Vop = 5-0 V, All Drivers OFF, All Inputs =OV} 1.6 mA Vop = 12 V, All Drivers OFF, All Inputs =0 V _ 2.9 mA 5821 traru 5823 BiMOS If 8-BIT SERIAL-INPUT, LATCHED DRIVERS Serial Data present at the input is trans- ack Le ferred to the shift register on the logic 0 to A D | logic 1 transition of the CLOCK input pulse. | On succeeding CLOCK pulses, the registers DATA IN a a sit qa, ration towards the SERIAL . The SERIAL DATA must E F | c appear at the input prior to the rising edge of stRORE a the CLOCK input waveform. Information present at any register is transferred to its respective latch when the our ie PL STROBE is high (serial-to-parallel conver- |. G sion). The latches will continue to accept new data as long as the STROBE is held high. OUT N | | | Applications where the latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data Owg No A-12,627 entry. TIMING CONDITIONS When the ENABLE input is high, all of the (Vp = 5-0 V, T, = +25C, Logic Levels are V,,,, and Ground) output buffers are disabled (OFF) without DD affecting the information stored in the latches or shift register. With the ENABLE input low, A. Minimum Data Active Time Before Clock Pulse the outputs are controlled by the state of the (Data Set-Up Time) . 20... eee 75 ns latches. B. Minimum Data Active Time After Clock Pulse (Data Hold Time). 6... 0. eee etnies 75 ns C. Minimum Data Pulse Width... 2.0.2... ee eee 150 ns D. Minimum Clock Pulse Width... 2.00.00 cc eee 150 ns E. Minimum Time Between Cleck Activation and Strobe ........... 300 ns F. Minimum Strobe Pulse Width ........0. 0.0.0.0 0 cee eee eee 100 ns G. Typical Time Between Strobe Activation and Output Transition... 0. eens 500 ns TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data | Clock Data |Strobe Output Input jimput}l, 1, by esssesseeeeeee I, Output | Input | 1, bby ceeseseeeeeeee I, | Emable | 1, by by sss 1, H TPH Ry Ry ereeeeeeeeee R, R, L Fo fl Ry Ry wee R, R, X LTR, Ry Ry eee R, R, KX KK oeeeeeeeeees Xx X L Ry, Ry Ry veceeeeeees Rs Py Py Pay cesses Ps P, H PP a Pa crseseeesseees P, L Py Py Pa cscs Py X KK seeesceees X H H H Ho we H L = Low Logic Level H=High LogicLevel X=lIrreievant P-=Present State R = Previous State 3-177