72P51339L6BBGI - Integrated Device Technology

AUGUST 2005

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION

589,824 bits

1,179,648 bits

2,359,296 bits

4,718,592 bits

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT72P51339

IDT72P51349

IDT72P51359

IDT72P51369

FEATURES

••

•Choose from among the following memory density options:

IDT72P51339 



Total Available Memory = 589,824 bits

IDT72P51349 



Total Available Memory = 1,179,648 bits

IDT72P51359 



Total Available Memory = 2,359,296 bits

IDT72P51369 



Total Available Memory = 4,718,592 bits

••

•Configurable from 1 to 8 Queues

••

•Default configuration of 8 or 4 symmetrical queues

••

•Default multi-queue device configurations

– IDT72P51339: 2,048 x 36 x 8Q

– IDT72P51349: 4,096 x 36 x 8Q

– IDT72P51359: 8,192 x 36 x 8Q

– IDT72P51369: 16,384 x 36 x 8Q

••

•Default configuration can be augmented via the queue address

bus

••

•Number of queues and individual queue sizes may be

configured at master reset though serial programming

••

•200 MHz High speed operation (5ns cycle time)

••

•3.6ns access time

••

•Independent Read and Write access per queue

••

•User Selectable Bus Matching Options:

– x36 in to x36 out – x18 in to x36 out – x9 in to x36 out

– x36in to x18out – x18 in to x18 out – x9 in to x18 out

– x36in to x9out – x18 in to x9 out – x9 in to x9 out

••

•User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL

••

•100% Bus Utilization, Read and Write on every clock cycle

••

•Selectable First Word Fall Through (FWFT) or IDT standard

mode of operation

••

•Ability to operate on packet or word boundaries

••

•Mark and Re-Write operation

••

•Mark and Re-Read operation

••

•Individual, Active queue flags (OR / EF, IR / FF, PAE, PAF, PR)

••

•8 bit parallel flag status on both read and write ports

••

•Direct or polled operation of flag status bus

••

•Expansion of up to 64 queues and/or 32Mb logical configura-

tion using up to 8 multi-queue devices in parallel

••

•JTAG Functionality (Boundary Scan)

••

•Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

••

•HIGH Performance submicron CMOS technology

••

•Industrial temperature range (-40°C to +85°C) is available

••

•Green parts available, see Ordering Information

MULTI-QUEUE FLOW-CONTROL DEVICE

FSTR

WEN

PAF

FF/IR

WRADD

WADEN

WCLK

PAFn

x36, 18 or x9

DATA IN

ESTR

PAE

RDADD

RADEN

PAEn

x36, x18 or x9

DATA OUT

EF/OR

WRITE CONTROL

Din Qout

PRn

READ CONTROL

WRITE FLAGS

READ FLAGS

6716 drw01

REN

RCLK

WCS RCS

FUNCTIONAL BLOCK DIAGRAM

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Table of Contents

Features ........................................................................................................................................................................................................................1

Description ...................................................................................................................................................................................................................5

Pin configuration .........................................................................................................................................................................................................7

Detailed Description ....................................................................................................................................................................................................8

Pin Descriptions......................................................................................................................................................................................................... 10

Pin number table ........................................................................................................................................................................................................ 16

Recommended DC operating conditions ................................................................................................................................................................ 17

Absolute maximum ratings........................................................................................................................................................................................ 17

DC electrical characteristics ..................................................................................................................................................................................... 18

AC electrical characteristics...................................................................................................................................................................................... 20

Functional description.............................................................................................................................................................................................. 22

Serial Programming.............................................................................................................................................................................................. 23

Default Programming ............................................................................................................................................................................................23

Parallel Programming ...........................................................................................................................................................................................23

Queue Description ..................................................................................................................................................................................................... 25

Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25

Standard mode operation ..................................................................................................................................................................................... 26

Read Queue Selection and Read Operation .........................................................................................................................................................27

Switching Queues on the Write Port ...................................................................................................................................................................... 29

Switching Queues on the Read Port ..................................................................................................................................................................... 31

Flag Description......................................................................................................................................................................................................... 42

P AFn Flag Bus Operation..................................................................................................................................................................................... 42

Full Flag Operation............................................................................................................................................................................................... 42

Empty or Output Ready Flag Operation (EF/OR) ..................................................................................................................................................42

Almost Full Flag....................................................................................................................................................................................................43

Almost Empty Flag................................................................................................................................................................................................ 43

Packet Ready Flag...............................................................................................................................................................................................47

Packet Mode Demarcation bits..............................................................................................................................................................................49

JTAG Interface ............................................................................................................................................................................................................ 82

JTAG AC electrical characteristics ............................................................................................................................................................................86

Ordering Information................................................................................................................................................................................................. 87

List of Tables

Table 1 — Device programming mode comparison ........................................................................................................................................................ 22

Table 2 — Setting the queue programming mode during master reset.............................................................................................................................22

T able 3 — Mode Configuration ......................................................................................................................................................................................25

Table 4 — Write Address Bus, WRADD[7:0]...................................................................................................................................................................26

Table 5 — Read Address Bus, RDADD[7:0].................................................................................................................................................................. 27

Table 6 — Write Queue Switch Operation ......................................................................................................................................................................30

T able 7 — Read Queue Switch Operation .....................................................................................................................................................................32

Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32

Table 9 — Flag operation boundaries and Timing..........................................................................................................................................................45

Table 10 — Packet Mode V alid Byte for x36 bit word configuration ................................................................................................................................. 48

Table 1 1 — Bus-Matching Set-Up..................................................................................................................................................................................52

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

List of Figures

Figure 1. Multi-Queue Flow-Control Device Block Diagram..............................................................................................................................................6

Figure 2a. AC Test Load................................................................................................................................................................................................19

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19

Figure 3. Reference Signals .......................................................................................................................................................................................... 22

Figure 4. Device Programming Hierarchy .....................................................................................................................................................................24

Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25

Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................25

Figure 7. Write Port Switching Queues Signal Sequence................................................................................................................................................ 29

Figure 8. Switching Queues Bus Efficiency.....................................................................................................................................................................29

Figure 9. Simultaneous Queue Switching .......................................................................................................................................................................30

Figure 10. Read Port Switching Queues Signal Sequence .............................................................................................................................................31

Figure 1 1. Switching Queues Bus Efficiency ...................................................................................................................................................................31

Figure 12. Simultaneous Queue Switching .....................................................................................................................................................................32

Figure 13. MARK and Re-Write Sequence ....................................................................................................................................................................33

Figure 14. MARK and Re-Read Sequence ...................................................................................................................................................................33

Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK .............................................................................................................................34

Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................34

Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................35

Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ...............................................................................................................35

Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ...............................................................................................................................37

Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK ..............................................................................................................................37

Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38

Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK .................................................................................................................38

Figure 23. Leaving a MARK active on the Write Port......................................................................................................................................................39

Figure 24. Leaving a MARK active on the Read Port.....................................................................................................................................................39

Figure 25. Inactivating a MARK on the Write Port Active .................................................................................................................................................40

Figure 26. Inactivating a MARK on the Read Port Active ................................................................................................................................................40

Figure 27. 36bit to 36bit word configuration ....................................................................................................................................................................49

Figure 28. 36bit to 18bit word configuration ....................................................................................................................................................................49

Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49

Figure 30. 18bit to 36bit word configuration ....................................................................................................................................................................50

Figure 31. 18bit to 18bit word configuration ....................................................................................................................................................................50

Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50

Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51

Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51

Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................51

Figure 36. Bus-Matching Byte Arrangement...................................................................................................................................................................53

Figure 37. Master Reset................................................................................................................................................................................................54

Figure 38. Default Programming .................................................................................................................................................................................... 55

Figure 39. Parallel Programming ...................................................................................................................................................................................56

Figure 40. Queue Programming via Write Address Bus.................................................................................................................................................. 57

Figure 41. Queue Programming via Read Address Bus .................................................................................................................................................57

Figure 42. Serial Port Connection for Serial Programming..............................................................................................................................................57

Figure 43. Serial Programming......................................................................................................................................................................................58

Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................59

Figure 45. Write Queue Select and Mark ....................................................................................................................................................................... 60

Figure 46. Write Operations in First Word Fall Through mode .......................................................................................................................................61

Figure 47. Full Flag Timing in Expansion Configuration..................................................................................................................................................62

Figure 48. Read Queue Select, Read Operation (IDT mode)......................................................................................................................................... 63

Figure 49. Read Queue Select, Read Operation (FWFT mode).....................................................................................................................................64

Figure 50. Read Queue Select and Mark (IDT mode)....................................................................................................................................................65

Figure 51. Output Ready Flag Timing (In FWFT Mode).................................................................................................................................................66

Figure 52. Read Queue Selection with Read Operations (IDT mode).............................................................................................................................67

Figure 53. Read Queue Select, Read Operation and OE Timing.................................................................................................................................... 68

Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................69

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 55. Reading in Packet Mode during a Queue change .........................................................................................................................................70

Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71

Figure 57. Data Output (Receive) Packet Mode of Operation .........................................................................................................................................72

Figure 58. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 73

Figure 59. Almost Full Flag Timing .................................................................................................................................................................................73

Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode) .........................................................................................................................74

Figure 61. Almost Empty Flag Timing ............................................................................................................................................................................. 74

Figure 62. PAEn/PRn - Direct Mode - Status Word Selection .........................................................................................................................................75

Figure 63. PAFn - Direct Mode - Status Word Selection .................................................................................................................................................75

Figure 64. PAEn - Direct Mode, Flag Operation............................................................................................................................................................. 76

Figure 65. PAFn - Direct Mode, Flag Operation.............................................................................................................................................................77

Figure 66. PAFn Bus - Polled Mode ..............................................................................................................................................................................78

Figure 67. Expansion using ID codes ............................................................................................................................................................................79

Figure 68. Expansion using WCS/RCS .........................................................................................................................................................................80

Figure 69. Expansion Connection Read Chip Select (RCS)........................................................................................................................................... 81

Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81

Figure 71. Boundary Scan Architecture ......................................................................................................................................................................... 82

Figure 72. T AP Controller State Diagram .......................................................................................................................................................................83

Figure 73. Standard JT AG Timing.................................................................................................................................................................................. 86

List of Figures (Continued)

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

DESCRIPTION

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices are single chips with up to 32 discrete configurable FIFO queues.

All queues within the device have a common data input bus, (write port) and

a common data output bus, (read port). Data written into the write port is directed

to a specific queue via an internal de-multiplex operation, addressed by the write

address bus (WRADD). Data read from the read port is accessed from a specific

queue via an internal multiplex operation, addressed by the read address bus

(RDADD). Data writes and reads can be performed at high speeds up to

200MHz, with access times of 3.6ns. Data write and read operations are totally

independent of each other, a queue maybe selected on the write port and a

different queue on the read port or both ports may select the same queue

simultaneously.

The device provides Full flag and Empty flag status for the queue selected

for write and read operations respectively. Also a Programmable Almost Full

and Programmable Almost Empty flag for each queue is provided. Two 8 bit

programmable flag busses are available, providing status of queues not

selected for write or read operations. When 8 or less queues are configured

in the device these flag busses provide an individual flag per queue, when more

than 8 queues are used, either a Polled or Direct mode bus operation provides

the flag busses with all queues status.

Bus Matching is available on this device, either port can be 9 bits, 18 bits or

36 bits wide. When Bus Matching is used the device ensures the logical transfer

of data throughput in a Little Endian manner.

A packet mode of operation is also provided. Packet mode provides a packet

ready flag output (PR) indicating when at least one (or more) packets of data

within a queue is available for reading. The Packet Ready indicator is generated

upon detection of the start and end of packet demarcation bits. The multi-queue

device then provides the user with an internally generated packet ready status

per queue.

The user has full flexibility configuring queues within the device, being able

to program the total number of queues between 1 and 32, the individual queue

depths being independent of each other. The programmable flag positions are

also user programmable. All programming is done via a dedicated serial port.

If the user does not wish to program the multi-queue device, a default option is

available that configures the device in a predetermined manner.

A Master Reset must be provided to the device. A Master Reset latches in

configuration/setup pins and must be performed before further programming of

the device can take place. On the rising edge of master reset the device operating

mode is set, the device programming mode (serial, parallel or default) is set and

the expansion configuration device type (master or slave) is set.

The multi-queue flow-control device has the capability of operating its I/O in

either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected

via the IOSEL input. The core supply voltage (VDD) to the multi-queue is 1.8V,

however the output levels can be set independently via a separate supply,

VDDQ.

A JTAG test port is provided, here the multi-queue flow-control device has

a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard

Test Access Port and Boundary Scan Architecture.

See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an

outline of the functional blocks within the device.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

x9, x18, x36

Qout

OUTPUT

Q0 - Q35

WRADD

WADEN

INPUT

DEMUX

WCLK WEN

Write Control

Logic

Din

Write Pointers

Active Q

Flags

PAF

General Flag

Monitor

FSTR

PAFn

FF/IR

FSYNC

PAF

Reset

Logic

Serial

Multi-Queue

Programming

PAE/ PAF

Offset

TMS

TDI

TDO

TCK

TRST

BM[3:0]

MRS

SCLK

SENI

RCLK

REN

Read Control

Logic

Read Pointers

Active Q

Flags

PAE

General Flag

Monitor ESTR

EF/OR

ESYNC

RDADD

RADEN

FXO

FXI

EXI

EXO

6714 drw02

x9, x18, x36

ID0

ID1

ID2

Device ID

3 Bit

PKT

Packet

Mode Logic

JTAG

Logic

D35, D17, D8 = TEOP

D34, D16, D8 = TSOP

PRn/PAEn

SENO

DFM

MAST

PAE

Upto 8

FIFO

Queues

4.7 Mbit

Dual Port

Memory

OUTPUT

MUX

D0 - D35

RCS

IO Level Control

IOSEL

Vref

WCS

D35, D17, D8 = REOP

D34, D16, D8 = RSOP

Figure 1. Multi-Queue Flow-Control Device Block Diagram

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

D14

D13 D12 D10 Q9

D7 Q6D4 Q3D1 ID1TCK TDO Q12 Q14 Q15

D15

D16 D11 D9 Q8

D6 Q5D3 Q2D0 ID0

TMS TDI Q11 Q13 Q19

D17

D18 D19 D8 Q7

D5 Q4D2 Q1

TRST Q0

IOSEL ID2 Q10 Q17 Q18

D20

D21 D22 V

DDQ

Q16 Q21 Q20

D23

D24 D25 V

DDQ

GND GND Q24 Q23 Q22

D26

D27 D28 V

DDQ

GND GND

GND GND Q27 Q26 Q25

D29

D30 D31 V

GND GND

GND GND Q30 Q29 Q28

D32

D33 D34 V

GND GND

GND GNDGND GND

GND GND Q33 Q32 Q31

BM3

QSEL0 D35 V

GND GND

GND GNDGND GND

GND GND PKT Q35 Q34

QSEL1

GND VREF V

GND GND

GND GND GND MAST FM

DFM DF V

DDQ

GND GND

GND GND BM2 BM1 BM0

SENO

MSENI SO V

DDQ

GND GND OE RDADD0 RDADD1

WRADD1

WRADD0 SCLK V

DDQ

RDADD2 RDADD3 RDADD4

WRADD4

WRADD3 WRADD2 WADEN PAE3

PAF3PAE6PAF6PAE7

PAF7PAE

IR/FF OR/EF RDADD5 RDADD6 RDADD7

WRADD6

WRADD5 FSYNC FSTR PAE2

PAF2PAE5PAF5FWFT

PAF4RCS

PAF PR RADEN ESTR ESYNC

WRADD7

FXI FXO PAF0PAE1

PAF1PAE4

WEN REN

WCLK RCLK

WCS MRS PAE0

12 3 4 135126117108 9 14 15 16

6716 drw03

A1 BALL PAD CORNER

EXO EXI

PIN CONFIGURATION

PBGA (BB256-1, order code: BB)

TOP VIEW

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

DETAILED DESCRIPTION

MULTI-QUEUE STRUCTURE

The IDT multi-queue flow-control device has a single data input port and

single data output port with up to 32 FIFO queues in parallel buffering between

the two ports. The user can setup between 1 and 8 queues within the device.

These queues can be configured to utilize the total available memory, providing

the user with full flexibility and ability to configure the queues to be various depths,

independent of one another.

MEMORY ORGANIZATION/ ALLOCATION

The memory is organized into what is known as “blocks”, each block being

256 x36 bits. When the user is configuring the number of queues and individual

queue sizes the user must allocate the memory to respective queues, in units

of blocks, that is, a single queue can be made up from 0 to m blocks, where m

is the total number of blocks available within a device. Also the total size of any

given queue must be in increments of 256 x36. For the IDT72P51339,

IDT72P51349, IDT72P71759 and IDT72P51369 the Total Available Memory

is 128, 256, and 512 blocks respectively (a block being 256 x36). Queues can

be built from these blocks to make any size queue desired and any number of

queues desired.

BUS WIDTHS

The input port is common to all queues within the device, as is the output port.

The device provides the user with Bus Matching options such that the input port

and output port can be either x9, x18 or x36 bits wide, the read and write port

widths can be set independently of one another. Because a ports are common

to all queues the width of the queues is not individually set. The input width of

all queues are the same and the output width of all queues are the same.

WRITING TO AND READING FROM THE MULTI-QUEUE

Data being written into the device via the input port is directed to a discrete

queue via the write queue address input. Conversely, data being read from the

device read port is read from a queue selected via the read queue address input.

Data can be simultaneously written into and read from the same queue or

different queues. Once a queue is selected for data writes or reads, the writing

and reading operation is performed in the same manner as a conventional IDT

synchronous FIFO, utilizing clocks and enables, there is a single clock and

enable per port. When a specific queue is addressed on the write port, data

placed on the data inputs is written to that queue sequentially based on the rising

edge of a write clock provided setup and hold times are met. Conversely, data

is read on to the output port after an access time from a rising edge on a read clock.

The operation of the write port is comparable to the function of a conventional

FIFO operating in standard IDT mode. Write operations can be performed on

the write port provided that the queue currently selected is not full, a full flag output

provides status of the selected queue. The operation of the read port is

comparable to the function of a conventional FIFO operating in FWFT mode.

When a queue is selected on the output port, the next word in that queue will

automatically fall through to the output register. All subsequent words from that

queue require an enabled read cycle. Data cannot be read from a selected

queue if that queue is empty, the read port provides an Empty flag indicating

when data read out is valid. If the user switches to a queue that is empty, the

last word from the previous queue will remain on the output bus. In addition to

First Word Fall Through (FWFT) the device can operate in IDT Standard mode

or packet mode. In IDT Standard mode the read port provides a word to the

output bus (Qout) for each clock cycle that REN is asserted. Refer to Figure 48,

Read Queue Select, Read Operation (IDT Mode). In packet mode the device

asserts a packet ready status flag to indicate one or more packets are available

for reading.

As mentioned, the write port has a full flag, providing full status of the selected

queue. Along with the full flag a dedicated almost full flag is provided, this almost

full flag is similar to the almost full flag of a conventional IDT FIFO. The device

provides a user programmable almost full flag for all 8 queues and when a

respective queue is selected on the write port, the almost full flag provides status

for that queue. Conversely, the read port has an Empty flag, providing status

of the data being read from the queue selected on the read port. As well as the

Empty flag the device provides a dedicated almost empty flag. This almost empty

flag is similar to the almost empty flag of a conventional IDT FIFO. The device

provides a user programmable almost empty flag for each 8 queues and when

a respective queue is selected on the read port, the almost empty flag provides

status for that queue.

PROGRAMMABLE FLAG BUSSES

In addition to these dedicated flags, full & almost full on the write port and Output

Ready & almost empty on the read port, there are two flag status busses. An

almost full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty

flag status bus is provided, again this bus is 8 bits wide. The purpose of these

flag busses is to provide the user with a means by which to monitor the data levels

within queues that may not be selected on the write or read port. As mentioned,

the device provides almost full and almost empty registers (programmable by

the user) for each of the 8 queues in the device.

In the IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-

control devices the user has the option of utilizing anywhere between 1 and 8

queues, therefore the 8 bit flag status busses are multiplexed between the 8

queues, a flag bus can only provide status for 2 of the 8 queues at any moment,

this is referred to as a “Status Word”, such that when the bus is providing status

of queues 1 through 8, this is status word 1, when it is queues 9 through 16, this

is status word 2 and so on up to status word 16. If less than 8 queues are setup

in the device, there are still 4 status words, such that in “Polled” mode of operation

the flag bus will still cycle through 4 status words. If for example only 22 queues

are setup, status words 1 and 2 will reflect status of queues 1 through 8 and 9

through 16 respectively. Status word 3 will reflect the status of queues 17 through

22 on the least significant 6 bits, the most significant 2 bits of the flag bus are don’t

care. The remaining status words are not used as there are no queues to report.

The flag busses are available in two user selectable modes of operation,

“Polled” or “Direct”. When operating in polled mode a flag bus provides status

of each status word sequentially, that is, on each rising edge of a clock the flag

bus is updated to show the status of each status word in order. The rising edge

of the write clock will update the almost full bus and a rising edge on the read

clock will update the almost empty bus. The mode of operation is always the same

for both the almost full and almost empty flag busses. When operating in direct

mode, the status word on the flag bus is selected by the user. So the user can

actually address the status word to be placed on the flag status busses, these

flag busses operate independently of one another. Addressing of the almost full

flag bus is done via the write port and addressing of the almost empty flag bus

is done via the read port.

PACKET READY

The multi-queue flow-control device also offers a “Packet Mode” operation.

Packet Mode is user selectable. In packet mode with a x36 bit word length, users

can define the length of packets or frame by using the two most significant bits

of the word. In a 36-bit word, bit 34 is used to mark the Start of Packet (SOP)

and bit 35 is used to mark the End of Packet (EOP) as shown in Table 10. When

writing data into a given queue , the first word being written is marked, by the

user setting bit 34 as the “Start of Packet” (SOP) and the last word written is

marked as the “End of Packet” (EOP) with all words written between the Start

of Packet (SOP) marker (bit 34) and the End of packet (EOP) packet marker

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

(bit 35) constituting the entire packet. A packet can be any length the user desires,

up to the total available memory in the multi-queue device. The device monitors

the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read

port is supplied with an additional status flag, “Packet Ready”. The Packet Ready

(PR) flag in conjunction with Empty Flag or Output Ready flag (EF/OR)

indicates when at least one packet is available to read. When in packet mode

the almost empty flag status , provides packet ready flag status for individual

queues.

EXPANSION (IDT STANDARD MODE)

Expansion of multi-queue devices is also possible. Up to 8 devices can be

connected in a parallel bus configuration as indicated in Figure 67, Expansion

using ID codes, and Figure 68, Expansion using

WCS

RCS

providing both

depth expansion and/or queue expansion. Expansion of devices is supported

only in IDT Standard mode. Depth Expansion means expanding the depths of

individual queues. Queue expansion means increasing the total number of

queues available. Depth expansion is possible by virtue of the fact that more

memory blocks within a multi-queue device can be allocated to a fewer number

of queues to increase the depth of each queue. For example, depth expansion

of 8 devices provides the possibility of 8 queues of 4096K bits, each queue being

setup within a single device utilizing all memory blocks available to produce a

single queue. This is the deepest queue that can setup within a device.

For queue expansion a maximum number of 256 queues (32 x 8 queues)

may be setup, with a average of each queue being 16,384K x36 deep using

8 devices, each with 8 queues. If fewer queues are desired, then more memory

blocks will be available to increase queue depths if desired. When connecting

multi-queue devices in expansion configuration all respective input pins (data

& control) and output pins (data & flags), should be “connected” together

between individual devices. Refer to Figure 67, Expansion using ID codes, and

Figure 68, Expansion using

WCS

RCS

for device connection details.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

BM [3:0] Bus Matching HSTL-LVTTL These pins define the bus width of the input write port and the output read port of the device. The bus

(J1, L14,15,16) INPUT widths are set during a Master Rest cycle. The BM[3:0] signals must meet the setup and hold time

requirements of Master Reset and must not toggle/change state after a Master Reset cycle.

D[35:0] Data Input Bus HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge

Din INPUT of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet

(See Pin No. markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs

table for details) may be used, any unused inputs should be tied LOW.

D[35] Transmit End of Packet (TEOP)

D[34] Transmit Start of Packet (TSOP)

D[33:32] User definable bits

D[31:0] Data input bits

DF(1) Default Flag HSTL-LVTTL If the user requires default programming of the multi-queue device, this pin must be setup before Master

(L3) INPUT Reset and must not toggle during any device operation. The state of this input at master reset determines

the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.

DFM(1) Default Mode HSTL-LVTTL The multi-queue device requires programming after master reset. The user can do this serially via the

(L2) INPUT serial port, or via parallel programming or by the default programming option The default programming

option provides a pre-defined configuration. If DFM is LOW at master reset then serial mode will be

selected, if HIGH then default mode is selected.

EF/OR Empty Flag/ HSTL-LVTTL This signal is bi-modal. When IDT Standard mode is selected the pin provides Empty Flag (EF) status.

(P9) Output Ready OUTPUT When FWFT mode is selected the pin provides output ready (OR) status. This output flag provides Output

Ready status for the data word present on the multi-queue flow-control device data output bus, Qout in

FWFT mode. This flag is a 2-stage delayed to match the data output path delay. There is a 3 RCLK cycle

delay in IDT Standard mode and a 4 cycle delay for FWFT mode from the time a given queue is selected

for reads, to the time the OR flag represents the data in that queue. When a selected queue on the read port

is read to empty, the OR flag will go HIGH, indicating that data on the output bus is not valid. The OR flag also

has High-Impedance capability, required when multiple devices are used and the OR flags are tied together.

ESTR PAEn Flag Bus HSTL-LVTTL If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK

(R15) Strobe INPUT and the RDADD bus to select a status word of queues to be placed on to the PAEn bus outputs. A status

word addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH.

If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus

selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed

and SENO has gone LOW.

ESYNC PAEn Bus Sync HSTL-LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus

(R16) OUTPUT during Polled operation of the PAEn bus. During Polled operation each status word of queue status flags

is loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads

status word 1 on to PAEn, the second RCLK rising edge loads status word 2 and so on. The fifth RCLK

rising edge will again load status word 1. During the RCLK cycle that status word 1 of a selected device

is placed on to the PAEn bus, the ESYNC output will be HIGH. For all other status words of that device,

the ESYNC output will be LOW.

EXI PAEn Bus HSTL-LVTTL The EXI input is used when multi-queue devices are connected in expansion configuration and Polled

(T16) Expansion In INPUT PAEn bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The

EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied

LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI

input must be connected to the EXO output of the same device. In expansion configuration the EXI of

the first device should be tied LOW, when direct mode is selected.

EXO PAEn Bus HSTL-LVTTL EXO is an output that is used when multi-queue devices are connected in expansion configuration and

(T15) Expansion Out OUTPUT Polled PAEn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’.

This pin pulses when device N has placed its final (4th) status word on to the PAEn bus with respect to

RCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK

rising edge the first status word of device N+1 will be loaded on to the PAEn bus. This continues through

the chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of

each device in the chain provides synchronization to the user of this looping event.

PIN DESCRIPTIONS

Symbol & Name I/O TYPE Description

(Pin No.)

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

FF/IR Full Flag/ HSTL-LVTTL This pin provides the full flag output for the active Queue, that is, the queue selected on the input port

(P8) Input Ready OUTPUT for write operations, (selected via WCLK, WRADD bus and WADEN). On the 3rd WCLK cycle after a queue

selection, this flag will show the status of the newly selected queue. Data can be written to this queue on

the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during

expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common

line. The device with a queue selected takes control of the FF bus, all other devices place their FF output

into High-Impedance. When a queue selection is made on the write port this output will switch from

High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.

FM(1) Flag Mode HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the

(K16) INPUT FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled

or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.

FSTR PAFn Flag Bus HSTL-LVTTL If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK

(R4) Strobe INPUT and the WRADD bus to select a status word of queues to be placed on to the PAFn bus outputs. A status

word addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH.

If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus

selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed

and SENO has gone LOW.

FSYNC PAFn Bus Sync HSTL-LVTTL FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus

(R3) OUTPUT during Polled operation of the PAFn bus. During Polled operation each status word of queue status flags

is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads

status word 1 on to PAFn, the second WCLK rising edge loads status word 2 and so on. The fifth WCLK

rising edge will again load status word 1. During the WCLK cycle that status word 1 of a selected device

is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other status words of that device,

the FSYNC output will be LOW.

FWFT First Word Fall HSTL-LVTTL First word fall through (FWFT) or IDT Standard mode is selected during a Master Reset cycle. To select

(R11) Through INPUT FWFT mode assert the FWFT signal = HIGH, if FWFT = LOW during the master reset then IDT Standard

mode is selected.

FXI PAFn Bus HSTL-LVTTL The FXI input is used when multi-queue devices are connected in expansion configuration and Polled

(T2) Expansion In INPUT PAFn bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The

FXI receives a token from the previous device in a chain. In single device mode the FXI input must be

tied LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI

input must be connected to the FXO output of the same device. In expansion configuration the FXI of the

first device should be tied LOW, when direct mode is selected.

FXO PAFn Bus HSTL-LVTTL FXO is an output that is used when multi-queue devices are connected in expansion configuration and

(T3) Expansion Out OUTPUT Polled PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’.

This pin pulses when device N has placed its final (4th) status word on to the PAFn bus with respect to

WCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK

rising edge the first status word of device N+1 will be loaded on to the PAFn bus. This continues through

the chain and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of

each device in the chain provides synchronization to the user of this looping event.

ID[2:0](1) Device ID Pins HSTL-LVTTL For the 8Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue

(ID2-C9 INPUT selection takes place the 3 MSb’s (bits 7, 6, 5) of this 8 bit address bus are used to address the specific

ID1-A10 device (the 5-7 LSb’s are used to address the queue within that device). During write/read operations

ID0-B10) the 3 MSb’s of the address are compared to the device ID pins. In an eight device expansion configuration,

the first device in a chain of multi-queue’s (connected in expansion configuration), may be setup as ‘000'

(this is referred to as the Master Device), the second as ‘001’ and so on through to device 8 which is ‘111’,

however the ID does not have to match the device order. In single device mode these pins should be

setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The

ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during

any device operation. Note, the device selected as the ‘Master’ must be ID ‘000’. In serial programming,

the master device (ID 000) must be programmed last.

Symbol & Name I/O TYPE Description

Pin No.

PIN DESCRIPTIONS (CONTINUED)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

IOSEL IO Select LVTTL This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are

(C8) INPUT required then IOSEL should be tied HIGH (VDDQ). If LVTTL I/O are required then it should be tied LOW.

MAST(1) Master Device HSTL-LVTTL The state of this input at Master Reset determines whether a given device (within a chain of devices), is the

(K15) INPUT Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The

master device is the first to take control of all outputs after a master reset, all slave devices go to High-

Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this

pin must be set HIGH.

MRS Master Reset HSTL-LVTTL A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required

(T9) INPUT after master reset.

OE Output Enable HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue

(M14) INPUT data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will

be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be

in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be

in High Impedance until that device has been selected on the Read Port, at which point OE provides three-

state of that respective device.

PAE Programmable HSTL-LVTTL This pin provides the Almost-Empty flag status for the Queue that has been selected on the output port

(P10) Almost-Empty OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected

Flag Queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is

synchronized to RCLK.

PAEn/PRn Programmable HSTL-LVTTL On the 32Q device the PAEn/PRn bus is 8 bits wide. During a Master Reset this bus is setup for either

(PAE7-P11 Almost-Empty OUTPUT Almost Empty mode or Packet mode. This output bus provides PAE/PRn status of 8 queues (1 status word),

PAE6-P12 Flag Bus/Packet within a selected device, having a maximum of 16 status words. During Queue read/write operations

PAE5-R12 Ready Flag Bus these outputs provide programmable empty flag status or packet ready status, in either direct or polled

PAE4-T12 mode. The mode of flag operation is determined during master reset via the state of the FM input.

PAE3-P13 This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices.

PAE2-R13 During direct operation the PAEn/PRn bus is updated to show the PAE/PR status of a status word of queues

PAE1-T13 within a selected device. Selection is made using RCLK, ESTR and RDADD. During Polled operation

PAE0-T14) the PAEn/PRn bus is loaded with the PAE/PRn status of multi-queue flow-control status words sequentially

based on the rising edge of RCLK. PAE or PR operation is determined by the state of PKT during master

reset.

PAF Programmable HSTL-LVTTL This pin provides the Almost-Full flag status for the Queue that has been selected on the input port for

(R8) Almost-Full Flag OUTPUT write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected

Queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is

synchronized to WCLK.

PAFn Programmable HSTL-LVTTL On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status

(PAF7-P7 Almost-Full Flag OUTPUT of 8 queues (1 status word), within a selected device, having a maximum of 16 status words. During Queue

PAF6-P6 Bus read/write operations these outputs provide programmable full flag status, in either direct or polled mode.

PAF5-R6 The mode of flag operation is determined during master reset via the state of the FM input. This flag bus

PAF4-R7 is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct

PAF3-P5 operation the PAFn bus is updated to show the PAF status of a status word of queues within a selected

PAF2-R5 device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn

PAF1-T5 bus is loaded with the PAF status of multi-queue flow-control status words sequentially based on the rising

PAF0-T4) edge of WCLK.

PKT(1) Packet Mode HSTL-LVTTL The state of this pin during a Master Reset will determine whether the part is operating in Packet mode

(J14) INPUT providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,

or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will

operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read

port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.

If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and

the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected.

Packet Ready utilizes user marked locations to identify start and end of packets being written into the device.

PIN DESCRIPTIONS (CONTINUED)

Symbol & Name I/O TYPE Description

Pin No.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

PIN DESCRIPTIONS (CONTINUED)

PR Packet Ready HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected

(R9) Fl a g OUTPUT for read operations. During a master reset the state of the PKT input determines whether Packet mode

of operation will be used. If Packet mode is selected, then the condition of the PR flag and EF/OR signal

are asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end

of a packet when writing data into a queue. Using the Start Of Packet (SOP) and End Of Packet (EOP)

markers, the multi-queue device sets PR LOW if one or more “complete” packets are available in the queue.

A complete packet(s) must be written before the user is allowed to switch queues.

Q[35:0] Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge

Qout OUTPUT of RCLK provided that REN is LOW, OE is LOW and the Queue is selected. Note, that in Packet Ready

(See Pin No. mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more

table for details) detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.

QSEL[1:0] Queue Select HSTL-LVTTL The QSEL pins provides various queue programming options. Refer to Table 2, for details.

(QSEL1-K1 INPUT 1. A QSEL value of 00, enables the user to program the number of queues using the Write Address bus.

QSEL0-J2 2. A QSEL value of 01, enables the user to program the number of queues using the Read Address bus.

3. A QSEL value of 10, Selects a configuration of 4 queues.

4. A QSEL value of 11, selects a configuration of 8 queues

RADEN Read Address HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to

(R14) Enable INPUT be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided

that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN

should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,

that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the

part has been completed and SENO has gone LOW.

RCLK Read Clock HSTL-LVTTL When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output

(T10) INPUT bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK

while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the

PAEn/PRn flag status word to be placed on the PAEn/PRn bus during direct flag operation. During polled

flag operation the PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized

to RCLK. The PAE, PR and OR outputs are all synchronized to RCLK. During device expansion the EXO

and EXI signals are based on RCLK. RCLK must be continuous and free-running.

RCS Read Chip HSTL-LVTTL The RCS signal in concert with REN signal provides control to enable data on to the output read data bus.

(R10) Select INPUT During a Master Reset cycle the RCS it is don’t care signal.

RDADD Read Address HSTL-LVTTL For the 8Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first

[7:0] Bus INPUT function of RDADD is to select a Queue to be read from. The least significant 5 bits of the bus, RDADD[4:0]

(RDADD7-P16 are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,

RDADD6-P15 RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion

RDADD5-P14 mode. An in expansion configuration the 3 MSb’s will address a device with the matching ID code. The

RDADD4-N16 address present on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is

RDADD3-N15 HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this

RDADD2-N14 RCLK edge). Two RCLK rising edges after read queue select, data will be placed on to the Qout outputs

RDADD1-M16 from the newly selected queue, regardless of REN due to the first word fall through effect.

RDADD0-M15) The second function of the RDADD bus is to select the status word of queues to be loaded on to the

PAEn/PRn bus during strobed flag mode. The least significant 4 bits, RDADD[3:0] are used to select the

status word of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5] are again

used to select 1 of 8 possible multi-queue devices that may be connected in expansion configuration.

Address bits RDADD[4] is don’t care during status word selection. The status word address present

on the RDADD bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that

data can be placed on to the Qout bus, read from the previously selected Queue on this RCLK edge).

Please refer to Table 5 for details on RDADD bus.

REN Read Enable HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.

(T11) INPUT In the FWFT mode, a queue to be read from can be selected via RCLK, RADEN and the RDADD address

bus regardless of the state of REN. A read enable is not required to cycle the PAEn/PRn bus (in polled

mode) or to select the PAEn status word, (in direct mode).

Symbol & Name I/O TYPE Description

Pin No.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

PIN DESCRIPTIONS (CONTINUED)

SCLK Serial Clock HSTL-LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input

(N3) INPUT clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device

on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed

the SCLK of all devices should be connected to the same source.

SENI Serial Input HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the

(M2) Enable INPUT part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are

cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial

loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain

to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI

input of the master device (or single device), should be controlled by the user.

SENO Serial Output HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device

(M1) Enable OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO

will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also

go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.

If multiple devices are cascaded and serial programming of the devices will be used, the SENO output

should be connected to the SENI input of the next device in the chain. When serial programming of the

first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and

so on throughout the chain. When a given device in the chain is fully programmed the SENO output

essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.

When this output goes LOW, serial loading of all devices has been completed.

SI Serial In HSTL-LVTTL During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.

(L1) INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion

mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO

has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device

connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.

SO Serial Out HSTL-LVTTL This output is used in expansion configuration and allows serial data to be passed through devices in the

(M3) OUTPUT chain to complete programming of all devices. The SI of a device connects to SO of the previous device

in the chain. The SO of the final device in a chain should not be connected.

TCK(2) JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test

(A8) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge

of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs

to be tied to GND.

TDI(2) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,

(B9) Input INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

TDO(2) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan

(A9) Output OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction

SHIFT-DR and SHIFT-IR controller states.

TMS(2) JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

(B8) Select INPUT device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

TRST(2) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

(C7) INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG

function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure

proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An

internal pull-up resistor forces TRST HIGH if left unconnected.

WADEN Write Address HSTL-LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to

(P4) Enable INPUT be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided

that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN

should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,

Symbol & Name I/O TYPE Description

(Pin No.)

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

PIN DESCRIPTIONS (CONTINUED)

NOTES:

1. Inputs should not change after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 82-86 and Figures 71-73.

WADEN Write Address HSTL-LVTTL that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part

(Continued) Enable INPUT has been completed and SENO has gone LOW.

WCLK Write Clock HSTL-LVTTL When enabled by WEN, the rising edge of WCLK writes data into the selected Queue via the input

(T7) INPUT bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of

WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also

select the flag status word to be placed on the PAFn bus during direct flag operation. During polled flag

operation the PAFn bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK.

The PAFn, PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and

FXI signals are based on WCLK. The WCLK must be continuous and free-running.

WCS Write Chip HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.

(T8) Select INPUT

WEN Write Enable HSTL-LVTTL The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A

(T6) INPUT queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless

of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK

cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn

bus (in polled mode) or to select the PAFn status word , (in direct mode).

WRADD Write Address HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The

[7:0] Bus INPUT first function of WRADD is to select a Queue to be written to. The least significant 5 bits of the bus,

(WRADD7-T1 WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. In expansion

WRADD6-R1 configuration the most significant 3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices

WRADD5-R2 (dependant on the number of queues addressed) that may be connected in expansion configuration. These

WRADD4-P1 3 MSb’s will address a device with the matching ID code. The address present on the WRADD bus will

WRADD3-P2 be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data present on the Din

WRADD2-P3 bus can be written into the previously selected queue on this WCLK edge and on the next rising WCLK

WRADD1-N1 also, providing that WEN is LOW). Two WCLK rising edges after write queue select, data can be written

WRADD0-N2) into the newly selected queue.

The second function of the WRADD bus is to select the status word of queues to be loaded on to the PAFn

bus during strobed flag mode. The least significant 4 bits, WRADD[3:0] are used to select the status word

of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to

select 1 of 8 possible multi-queue devices that may be connected in expansion configuration. Address bits

WRADD[4] is don’t care during status word selection. The status word address present on the WRADD

bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be

written into the previously selected queue on this WCLK edge). Please refer to Table 4 for details on the

WRADD bus.

VDD +1.8V Supply Power These are VDD power supply pins and must all be connected to a +1.8V supply rail.

(See pg. 16)

VDDQ O/P Rail Voltage Power These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected

(See pg. 16) to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected

to +1.8V.

GND Ground Pin Ground These are Ground pins and must all be connected to the GND supply rail.

(See pg. 16)

Vref Reference HSTL This is a Voltage Reference input and must be connected to a voltage level determined from the table

(K3) Voltage INPUT "Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL

inputs. For LVTTL I/O mode this input should be tied to GND.

Symbol & Name I/O TYPE Description

Pin No.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

PIN NUMBER TABLE

Symbol Name I/O TYPE Pin Number

D[35:0] Data Input Bus HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),

Din INPUT D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5,

D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7

Q[35:0] Data Output Bus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),

Qout OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14 ,

Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,

Q(1,0)-C(11,10)

VDD +1.8V Supply Power D(7-10), E(6,7,10,11), F(5,12), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(5,12), M(6,7,10,11), N(7-10)

VDDQ O/P Rail Voltage Power D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)

GND Ground Pin Ground E(8-9), F(6-11), G(6-11), H(5-12), J(1,5-12), K(2,6-11,14), L(6-11), M(8-9)

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Symbol Rating Commercial Unit

VTERM Terminal Voltage –0.5 to +2.9(2) V

with respect to GND

TSTG Storage Temperature –55 to +125 °C

IOUT DC Output Current –50 to +50 mA

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 1.7 1.8 1.9 V

VDDQ Output Rail Voltage for I/Os  LVTTL 2.375 2.5 2.625 V

 eHSTL 1.7 1.8 1.9 V

 HSTL 1.4 1.5 1.6 V

GND Supply Voltage 0 0 0 V

VIH(2) Input High Voltage  LVTTL 1.7 — 2.625 V

 eHSTL VREF+0.2 — — V

 HSTL VREF+0.2 — — V

VIL Input Low Voltage  LVTTL -0.3 — 0.7 V

 eHSTL — — VREF-0.2 V

 HSTL — — VREF-0.2 V

VREF(1) Voltage Reference Input  eHSTL 0.8 0.9 1.0 V

(HSTL only)  HSTL 0.68 0.75 0.9 V

TAOperating Temperature Commercial 0 — 70 °C

TAOperating Temperature Industrial -40 — 85 °C

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

NOTES:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. VDD terminal only.

Symbol Parameter(1) Conditions Max. Unit

CIN(2,3) Input VIN = 0V 10(3) pF

Capacitance

COUT(1,2) Output VOUT = 0V 15 pF

Capacitance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

NOTES:

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

3. CIN for Vref is 20pF.

NOTE:

1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. VIH AC Component = VREF + 0.4V

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

DC ELECTRICAL CHARACTERISTICS

(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70 °C;Industrial: VDD = 1.8V ± 0.10V, T A = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

ILI Input Leakage Current –10 10 µA

ILO Output Leakage Current –10 10 µA

VOH(3) Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

VOL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

IDD1(1,2) Active VDD Current (VDD = 1.8V) I/O = LVTTL — 80 mA

I/O = HSTL — 150 mA

I/O = eHSTL — 150 m A

IDD2(1, 5) Standby VDD Current (VDD = 1.8V) I/O = LVTTL — 2 5 mA

I/O = HSTL — 100 mA

I/O = eHSTL — 100 m A

IDDQ(1,2) Active VDDQ Current (VDDQ = 2.5V LVTTL) I/O = LVTTL — 10 mA

(VDDQ = 1.5V HSTL) I/O = HSTL — 1 0 mA

(VDDQ = 1.8V eHSTL) I/O = eHSTL — 10 mA

NOTES:

1. Both WCLK and RCLK toggling at 20MHz.

2. Data inputs toggling at 10MHz.

3. Total Power consumed: PT = [(VDD x IDD) + (VDDQ x IDDQ)].

4. Outputs are not 3.3V tolerant.

5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.

The following inputs should be pulled to VDD: WEN, REN, SENI, MRS, TDI, TMS and TRST.

All other inputs are don't care and should be at a known state.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Input Pulse Levels 0.25 to 1.25V

Input Rise/Fall Times 0.4ns

Input Timing Reference Levels 0.75

Output Reference Levels VDDQ/2

HSTL

1.5V AC TEST CONDITIONS

Figure 2b. Lumped Capacitive Load, Typical Derating

AC TEST LOADS

Figure 2a. AC Test Load

Input Pulse Levels 0.4 to 1.4V

Input Rise/Fall Times 0.4ns

Input Timing Reference Levels 0.9

Output Reference Levels VDDQ/2

EXTENDED HSTL

1.8V AC TEST CONDITIONS

Input Pulse Levels GND to 2.5V

Input Rise/Fall Times 1ns

Input Timing Reference Levels VDD/2

Output Reference Levels VDDQ/2

2.5V LVTTL

2.5V AC TEST CONDITIONS

6716 drw04

50Ω

VDDQ/2

I/O Z0 = 50Ω

6716 drw04a

20 30 50 80 100 200

Capacitance (pF)

∆t

(Typical, ns)

NOTE:

1. VDDQ = 1.5V ± 0.1V.

NOTE:

1. VDDQ = 1.8V ± 0.1V.

NOTE:

1. VDDQ = 2.5V ± 0.125V.

OUTPUT ENABLE & DISABLE TIMING

tOE & tOLZ

100mV

tOHZ

100mV

Output

Normally

LOW

Output

Normally

HIGH

VCC/2

6716 drw05

Output

Enable

Output

Disable

VCC/2

NOTE:

1. REN is HIGH.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Commercial Com'l & Ind'l(1)

IDT72P51339L5 IDT72P51339L6

IDT72P51349L5 IDT72P51349L6

IDT72P51359L5 IDT72P51359L6

IDT72P51369L5 IDT72P51369L6

Symbol Parameter Min. Max. Min. Max. Unit

fSClock Cycle Frequency (WCLK & RCLK) — 200 — 166 MHz

tAData Access Time 0.6 3.6 0.6 3.7 ns

tCLK Clock Cycle Time 5 — 6 — ns

tCLKH Clock High Time 2.25 — 2.7 — ns

tCLKL Clock Low Time 2.25 — 2.7 — ns

tDS Data Setup Time 1.5 — 2.0 — ns

tDH Data Hold Time 0.5 — 0.5 — ns

tENS Enable Setup Time 1.5 — 2.0 — ns

tENH Enable Hold Time 0.5 — 0.5 — ns

tRS Reset Pulse Width 30 — 30 — ns

tRSS Reset Setup Time 15 — 15 — ns

tRSF Reset Output Status — 10 — 10 ns

tRSR Reset Recovery Time 10 — 10 — ns

tOLZ (OE-Qn)(2) Output Enable to Output in Low-Impedance 0.6 3.6 0.6 3.7 ns

tOHZ(2) Output Enable to Output in High-Impedance 0.6 3.6 0.6 3.7 ns

tOE Output Enable to Data Output Ready 0.6 3.6 0.6 3.7 ns

fCClock Cycle Frequency (SCLK) — 10 — 10 MHz

tSCLK Serial Clock Cycle 100 — 100 — ns

tSCKH Serial Clock High 45 — 45 — ns

tSCKL Serial Clock Low 45 — 45 — ns

tSDS Serial Data In Setup 2 0 — 20 — ns

tSDH Serial Data In Hold 1. 2 — 1. 2 — ns

tSENS Serial Enable Setup 20 — 20 — ns

tSENH Serial Enable Hold 1.2 — 1.2 — ns

tSDO SCLK to Serial Data Out — 2 0 — 2 0 n s

tSENO SCLK to Serial Enable Out — 2 0 — 2 0 n s

tSDOP Serial Data Out Propagation Delay 0.6 3.7 0.6 3.7 ns

tSENOP Serial Enable Propagation Delay 0.6 3.7 0.6 3.7 ns

tPCSF Programming Complete to Status Flag — 7+1 SCLK — 7+1 SCLK clock cycles

tAS Address Setup 1.5 — 2.0 — ns

tAH Address Hold 0.5 — 0.5 — ns

tWFF Write Clock to Full Flag — 3.6 — 3. 7 ns

tREF Read Clock to Empty Flag — 3. 6 — 3 .7 n s

tSTS PAE/PAF Strobe Setup 1.5 — 1.5 — ns

tSTH PAE/PAF Strobe Hold 0.5 — 0.5 — ns

tQS Queue Setup 1.5 — 2.0 — ns

tQH Queue Hold 0.5 — 0.5 — ns

tWAF WCLK to PAF flag 0 . 6 3. 6 0. 6 3. 7 n s

tRAE RCLK to PAE flag 0.6 3.6 0.6 3.7 ns

tPAF Write Clock to Synchronous Almost-Full Flag Bus 0.6 3.6 0.6 3.7 ns

tPAE Read Clock to Synchronous Almost-Empty Flag Bus 0 .6 3. 6 0. 6 3.7 ns

tPAELZ(2) RCLK to PAE Flag Bus to Low-Impedance 0. 6 3. 6 0 .6 3. 7 ns

AC ELECTRICAL CHARACTERISTICS

(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

NOTES:

1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.

2. Values guaranteed by design, not currently tested.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

AC ELECTRICAL CHARACTERISTICS (CONTINUED)

(Commercial: VDD = 1.8V ± 0.10V, TA = 0°C to +70°C;Industrial: VDD = 1.8V ± 0.10V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

tPAEHZ(2) RCLK to PAE Flag Bus to High-Impedance 0. 6 3. 6 0. 6 3. 7 ns

tPAFLZ(2) WCLK to PAF Flag Bus to Low-Impedance 0. 6 3. 6 0. 6 3. 7 ns

tPAFHZ(2) WCLK to PAF Flag Bus to High-Impedance 0. 6 3. 6 0. 6 3. 7 n s

tFFHZ(2) WCLK to Full Flag/Input Ready to High-Impedance 0.6 3.6 0.6 3.7 ns

tFFLZ(2) WCLK to Full Flag/Input Ready to Low-Impedance 0.6 3.6 0.6 3.7 ns

tEFLZ(2) RCLK to Empty Flag/Output Ready Flag to Low-Impedance 0.6 3.6 0.6 3.7 ns

tEFHZ(2) RCLK to Empty Flag/Output Ready Flag to High-Impedance 0.6 3.6 0.6 3.7 ns

tFSYNC WCLK to PAF Bus Sync to Output 0.6 3. 6 0. 6 3.7 ns

tFXO WCLK to PAF Bus Expansion to Output 0. 6 3. 6 0 .6 3. 7 ns

tESYNC RCLK to PAE Bus Sync to Output 0.6 3.6 0.6 3.7 ns

tEXO RCLK to PAE Bus Expansion to Output 0. 6 3 .6 0. 6 3. 7 ns

tPR RCLK to Packet Ready Flag 0. 6 3. 6 0. 6 3. 7 n s

tSKEW1 SKEW time between RCLK and WCLK for FF/IR and EF/OR 5— 6—ns

tSKEW2 SKEW time between RCLK and WCLK for PAF and PAE 5— 6—ns

tSKEW3 SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7] 5 — 6 — ns

tSKEW4 SKEW time between RCLK and WCLK for PR and EF/OR 5— 6—ns

tXIS Expansion Input Setup 1.5 — 2.0 — ns

tXIH Expansion Input Hold 0.5 — 0.5 — ns

tPPMS Parallel Programming Setup 15 — 15 — ns

tPPMH Parallel Programming Hold 5 — 5 — ns

Commercial Com'l & Ind'l(1)

IDT72P51339L5 IDT72P51339L6

IDT72P51349L5 IDT72P51349L6

IDT72P51359L5 IDT72P51359L6

IDT72P51369L5 IDT72P51369L6

Symbol Parameter Min. Max. Min. Max. Unit

NOTES:

1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.

2. Values guaranteed by design, not currently tested.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

FUNCTIONAL DESCRIPTION

MASTER RESET

A Master Reset is performed by toggling the MRS input from HIGH to LOW

to HIGH. During a master reset all internal multi-queue device setup and control

registers are initialized and require programming either serially by the user via

the serial port, or via parallel programming or by using the default settings. Refer

to Figure 4, Device Programming Hierarchy for the programming hierarchy

structure. During a master reset the state of the following inputs determine the

functionality of the part, these pins should be held HIGH or LOW.

PKT – Packet Mode

FM – Flag bus Mode

BM [3:0] – Bus Matching options

MAST – Master Device

ID0, 1, 2 – Device ID

DFM – Programming mode, serial or default

DF – Offset value for PAE and PAF

Once a master reset has taken place, the device must be programmed either

serially or via the default method before any read/write operations can begin.

See Figure 37, Master Reset for relevant timing.

PROGRAMMING MODE CAPTURED

On the rising of /MRS the programming mode signals (QSEL 0 &1,

DEFAULT) are captured. Once the programming mode signals are captured

(latched), refer to Table 1 for details. It will then require a number of clock cycles

for the device to complete the configuration. Configuration completion is indicated

when the SENO signal transitions from high to low. The configuration completion

indication is consistent with the previous MQ device.

QSEL0

QSEL1

Default mode

(DFM)

See Table 2 for definition of value

6716 drw06

MRS

See Table 2 for definition of value

DFM = LOW for Serial Programming mode

Figure 3. Reference Signals

Programmable Parameter Serial Programming Parallel Programming Default Programming

Number of Queues Any number from 1 to 8 Any number from 1 to 8 4 or 8

Queue Depth Each queue depth can be The total memory is evenly divided The total memory is evenly divided

individualized across the queues across the queues

PAE

PAF

Offset Value Programmable to any value Fixed value Fixed value

Bus Matching Any combination of x9 or x18 or x36 can Any combination of x9 or x18 or x36 Any combination of x9, x18, or x36 can

be selected using the BM[3:0] bits. can be selected using the BM[3:0] bits. be selected using the BM[3:0] bits

I/O voltage LVTTL, eHSTL, HSTL LVTTL, eHSTL, HSTL LVTTL, eHSTL, HSTL

TABLE 1 — DEVICE PROGRAMMING MODE COMPARISON

QSEL 1 QSEL 0

MRS

Default

Mode

(DFM)

Queue Programming Method

6716 drw07

00 RESERVED

100 RESERVED

10 RESERVED

10 Serial programming mode

01 Enables the user to program the number

of Queues using the Write Address bus

01 Enables the user to program the number

of Queues using the Read Address bus

11 Selects 4 Queue

111 Selects 8 Queue

TABLE 2 — SETTING THE QUEUE PROGRAMMING MODE DURING MASTER RESET

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

SERIAL PROGRAMMING

The multi-queue flow-control device is a fully programmable device, provid-

ing the user with flexibility in how queues are configured in terms of the number

of queues, depth of each queue and position of the PAF/PAE flags within

respective queues. All user programming is done via the serial port after a master

reset has taken place. Internally the multi-queue device has setup registers

which must be serially loaded, these registers contain values for every queue

within the device, such as the depth and PAE/PAF offset values. The

IDT72P51339/72P51349/72P51359/72P51369 devices are capable of up to

8 queues and therefore contain 128 sets of registers for the setup of each queue.

During a Master Reset if the DFM (Default Mode) input is LOW, then the device

will require serial programming by the user. It is recommended that the user

utilize a ‘C’ program provided by IDT, this program will prompt the user for all

information regarding the multi-queue setup. The program will then generate

a serial bit stream which should be serially loaded into the device via the serial

port. For the IDT72P51339/72P51349/72P51359/72P51369 devices the

serial programming requires a total number of serially loaded bits per device,

(SCLK cycles with SENI enabled), calculated by: 19+(Qx72) where Q is the

number of queues the user wishes to setup within the device.

Once the master reset is complete and MRS is HIGH, the device can be

serially loaded. Data present on the SI (serial in), input is loaded into the serial

port on a rising edge of SCLK (serial clock), provided that SENI (serial in

enable), is LOW. Once serial programming of the device has been successfully

completed the device will indicate this via the SENO (serial output enable) going

active, LOW. Upon detection of completion of programming, the user should

cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI

once programming of a device is complete. Therefore, SENO will go LOW after

programming provided SENI is LOW, once SENI is taken HIGH again, SENO

will also go HIGH. The operation of the SO output is similar, when programming

of a given device is complete, the SO output will follow the SI input.

If devices are being used in expansion configuration the serial ports of devices

should be cascaded. The user can load all devices via the serial input port control

pins, SI & SENI, of the first device in the chain. Again, the user may utilize the

‘C’ program to generate the serial bit stream, the program prompting the user

for the number of devices to be programmed. The SENO and SO (serial out)

of the first device should be connected to the SENI and SI inputs of the second

device respectively and so on, with the SENO & SO outputs connecting to the

SENI & SI inputs of all devices through the chain. All devices in the chain should

be connected to a common SCLK. The serial output port of the final device should

be monitored by the user. When SENO of the final device goes LOW, this

indicates that serial programming of all devices has been successfully com-

pleted. Upon detection of completion of programming, the user should cease all

programming and take SENI of the first device in the chain inactive, HIGH.

As mentioned, the first device in the chain has its serial input port controlled

by the user, this is the first device to have its internal registers serially loaded

by the serial bit stream. When programming of this device is complete it will take

its SENO output LOW and bypass the serial data loaded on the SI input to its

SO output. The serial input of the second device in the chain is now loaded with

the data from the SO of the first device, while the second device has its SENI

input LOW. This process continues through the chain until all devices are

programmed and the SENO of the final device (or master device, ID = '000')

goes LOW.

Once all serial programming has been successfully completed, normal

operations, (queue selections on the read and write ports) may begin. When

connected in expansion configuration, the IDT72P51339/72P51349/72P51359/

72P51369 devices require a total number of serially loaded bits per device to

complete serial programming, (SCLK cycles with SENI enabled), calculated by:

n[19+(Qx72)] where Q is the number of queues the user wishes to setup within

the device, where n is the number of devices in the chain.

See Figure 42, Serial Port Connection and Figure 43, Serial Programming

for connection and timing information.

DEFAULT PROGRAMMING

During a Master Reset if the DFM (Default Mode) input is HIGH the multi-

queue device will be configured for default programming, (serial programming

is not permitted). Default programming provides the user with a simpler,

however limited means to setup the multi-queue flow-control device, rather than

using the serial programming method. The default mode will configure a multi-

queue device with the maximum number of queues setup, and the available

memory allocated equally between the queues. The values of the PAE/PAF

offsets is determined by the state of the DF (default) pin during a master reset.

For the IDT72P51339/72P51349/72P51359/72P51369 devices the default

mode will setup 8 queues, each queue being 512 x 36, 1024 x 36, 2048 x36,

and 4096 x 36 deep respectively. For each device, the value of the PAE/PAF

offsets is determined at master reset by the state of the DF input. If DF is LOW

then both the PAE & PAF offset will be 8, if HIGH then the value is 128.

When configuring the IDT72P51339/72P51349/72P51359/72P51369 de-

vices in default mode the user simply has to apply WCLK cycles after a master

reset, until SENO goes LOW, this signals that default programming is complete.

These clock cycles are required for the device to load its internal setup registers.

When a single multi-queue device is used, the completion of device program-

ming is signaled by the SENO output of a device going from HIGH to LOW. Note,

that SENI must be held LOW when a device is setup for default programming

mode.

When multi-queue devices are connected in expansion configuration, the

SENI of the first device in a chain can be held LOW. The SENO of a device should

connect to the SENI of the next device in the chain. The SENO of the final device

is used to indicate that default programming of all devices is complete. When the

master (ID='000') SENO goes LOW normal operations may begin. Again, all

devices will be programmed with their maximum number of queues and the

memory divided equally between them. Please refer to Figure 38, Default

Programming.

PARALLEL PROGRAMMING

During a Master Reset cycle (i.e. the MRS signal transitions from HIGH to

LOW then LOW to HIGH) if the DFM (Default Mode) input signal is HIGH and

the QSEL 1 input signal is LOW the Multi-Queue Flow Control device is

configured for Parallel Programming. Parallel Programming enables the

number of queues within the device to be set through either the Write Address

(WRADD) bus or Read Address (RDADD) bus after the Master Reset cycle.

Within Parallel Programming mode the Multi-Queue (MQ) device program-

mable parameters are; number of queues, queue depth, PAE/PAF flag offset

value, bus matching and the I/O voltage level. As previously indicated, the

number of queues are configured using the write or read address bus,

however bus matching is set during the Master Reset cycle. The value that is

set during the Master Reset cycle is determined by the Bus Matching (BM) bits.

For the IDT72P51339/72P51349/72P51359/72P51369 devices in Parallel

Programming Mode the value of the PAE/PAF offsets at master reset is

determined by the state of the DF input. If DF is LOW then both the PAE & PAF

offset will be 8, if HIGH then the value is 128.

When configuring the IDT72P51339/72P51349/72P51359/72P51369

devices in Parallel Programming Mode the user simply has to apply WCLK

cycles after a master reset, untilSENO goes LOW, this signals that Parallel

Programming is complete. These clock cycles are required for the device to

load its internal setup registers. When a single multi-queue device is used, the

completion of device programming is signaled by the SENO output of a device

going from HIGH to LOW. Note, that SENI must be held LOW when a device

is setup for Parallel Programming mode.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 4. Device Programming Hierarchy

Master Reset Cycle

Device

Programming

Mode Selected

Device Operating Mode

Selected

(Packet Mode) (FIFO Mode)

Expansion

Device Type

Selected

Master

Device

6716 drw08

Parallel Queue

Programming

Serial

Programming

Default

Programming

Slave

Device

(IDT Mode) (FWFT Mode) (IDT Mode) (FWFT Mode)

When Multi-Queue devices are connected in an Expansion Configuration,

the SENI signal of the first device in a chain must be held LOW. The SENO signal

of a device should connect to the SENI of the next device in the chain. The SENO

of the final device is used to indicate that the programming of all devices is

complete. When the master device (ID=’000') SENO signal goes LOW the

internal programming is complete and queue write/read operation may begin.

Please refer to Figure 39, Parallel Programming for signal timing details.

PROGRAMMING HIERARCHY

Configuring the device is a 2 stage sequence. The first stage is to set the

expansion device type, the desired programming mode and the device

operating mode during the master reset cycle (i.e. on the rising edge of Master

Reset (MRS)). The second stage is to set values such as PAE/PAF, number

of queues, queue depth, etc. using the programming mode (serial, parallel,

default) selected in stage 1. Refer to Figure 4, Device Programming Hierarchy.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Operational Modes

Packet Mode FIFO Mode

IDT Standard FWFT Mode IDT Standard FWFT Mode

Mode Mode

Configuration Signals Modes

PKT FWFT

LO W L OW FIFO mode - IDT Standard Mode

LOW HIGH FIFO mode - FWFT

HIGH LOW Packet mode - IDT Standard Mode

HIGH HIGH Packet mode - FWFT

QUEUE DESCRIPTION

CONFIGURATION OF THE IDT MULTI-QUEUE FLOW-CONTROL DEVICE

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices can be configured in distinct modes, namely Packet mode, FIFO

6716 drw09

RCLK

Qout

REN

Last Data Word

Figure 5. IDT Standard mode illustrated (Read Port)

TABLE 3 — MODE CONFIGURATION

6716 drw10

RCLK

Qout

Data Bus

REN

Last Data Word

Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port)

In FWFT mode the read port signal EF/OR is configured for output ready (OR)

signaling. OR is an active LOW signal. When OR is HIGH, it signifies there is no

available word to read. On the write port, signal FF/IR is configured for input

In IDT Standard mode the read port signal EF/OR is configured for empty

flag (EF) signaling. EF is an active LOW signal. When EF is LOW it signifies the

selected (present) queue is empty. On the write port, signal FF/IR is configured

mode, Standard mode, and FWFT mode. To configure the device operational

mode set the configuration pins (PKT, FWFT) as indicated in Table 3, Mode

Configuration.

for full flag (FF) signaling. FF is an active LOW signal. When FF is LOW it signifies

the selected (present) queue is full. Refer to Figure 5, IDT Standard mode

illustrated (Read Port).

ready (IR) signaling. IR is an active LOW signal. When IR is LOW it signifies the

write port is ready for writing into the selected queue. Refer to Figure 6, FWFT

mode illustrated (Read Port).

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

STANDARD MODE OPERATION

WRITE QUEUE SELECTION AND WRITE OPERATION

(STANDARD MODE)

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices can be configured up to a maximum of 8 queues which data can

be written via a common write port using the data inputs (Din), write clock

(WCLK) and write enable (WEN). The queue to be written is selected by the

address present on the write address bus (WRADD) during a rising edge on

WCLK while write address enable (WADEN) is HIGH. The state of WEN does

not impact the queue selection. The queue selection requires 4 WCLK cycle.

All subsequent data writes will be to this queue until another queue is selected.

Standard mode operation is defined as individual words will be written to the

device as opposed to Packet Mode where complete packets are written. The

write port is designed such that 100% bus utilization can be obtained. This

means that data can be written into the device on every WCLK rising edge

including the cycle that a new queue is being addressed.

Changing queues requires 4 WCLK cycles on the write port (see Figure 44,

Write Queue Select, Write Operation and Full flag Operation). WADEN goes

high signaling a change of queue (clock cycle “A”). The address on WRADD

at that time determines the next queue. Data presented during each cycle, will

be written to the active queue, provided WEN is LOW. If WEN is HIGH (inactive),

data will not be written in a queue. The write port discrete full flag will update to

show the full status of the newly selected queue. Data present on the data input

bus (Din), can be written into the newly selected queue on the rising edge of

WCLK a change of queue, provided WEN is LOW and the queue is not full. If

the selected queue is full at the point of its selection, any writes to that queue will

be prevented. Data cannot be written into a full queue.

Refer to Figure 44, Write Queue Select, Write Operation and Full flag

Operation, Figure 46, Write Operations in First Word Fall Through for timing

diagrams and Figure 47, Full Flag Timing in Expansion Configuration for timing

diagrams.

TABLE 4 — WRITE ADDRESS BUS, WRADD[7:0]

Operation WCLK WADEN FSTR WRADD[7:0]

Write

Queue

Select

Device Select

(Compared to

ID2,1,0)

Write Queue Address

(2 bits = 4 Queues

3 bits = 8 Queues)

765 43 210

765 4 3210

Device Select

(Compared to

ID2,1,0)

X Status Word

Address

PAFn

Quadrant

Select

Q0 : Q7 → PAF0 : PAF7

Status Word

Address Queue Status on PAFn Bus

0000

6716 drw11

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

READ QUEUE SELECTION AND READ OPERATION

(STANDARD MODE)

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices can be configured up to a maximum of 8 queues which data can

be read via a common read port using the data outputs (Qout), read clock

(RCLK) and read enable (REN). An output enable, OE control pin is also

provided to allow High-Impedance selection of the Qout data outputs. The multi-

queue device read port operates in standard IDT mode and “First Word Fall

Through” mode (see Figure 46, Write Operations in First Word Fall Through).

The queue to be read is selected by the address presented on the read address

bus (RDADD) during a rising edge on RCLK while read address enable

(RADEN) is HIGH. The state of REN does not impact the queue selection. The

queue selection requires 4 RCLK cycles. All subsequent data reads will be from

this queue until another queue is selected.

Standard mode operation is defined as individual words will be read from the

device. The read port is designed such that 100% bus utilization can be

obtained. This means that data can be read out of the device on every RCLK

rising edge including the cycle that a new queue is being addressed.

Changing queues requires a minimum of four RCLK cycles on the read port

(see Figure 48, Read Queue Select, Read Operation). RADEN goes high

signaling a change of queue (clock cycle “D”). The address on RDADD at that

time determines the next queue. Data presented during that cycle will be

read.Reading data can continue from the active, provided REN is LOW. If REN

is HIGH (inactive) for these two clock cycles, data will not be read from the queue.

If a new selected queue is empty, any reads from that queue will be prevented.

Data cannot be read from an empty queue. Remember that OE allows the user

to place the data output bus (Qout) into High-Impedance and the data can be

read in to the output register regardless of OE.

Refer to Table 5, for Read Address Bus arrangement. Also, refer to Figures

13, 15, and 16 for read queue selection and read port operation timing diagrams.

Operation RCLK RADEN ESTR RDADD[7:0]

Read Queue

Select

Device Select

(Compared to

ID2,1,0)

Read Queue Address

(2 bits = 4 Queues

3 bits = 8 Queues)

765 43 210

765 4 3210

Device Select

(Compared to

ID2,1,0)

X Status Word

Address

PAEn/PRn

Quadrant

Select

Status Word

Address Queue Status on PAEn/PRn Bus

6716 drw12

Q0 : Q7 → PAF0 : PAF7

0000

TABLE 5 — READ ADDRESS BUS, RDADD[7:0]

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

PACKET MODE OPERATION

The Packet mode operation provides the capability where, user defined

packets or frames can be written to the device as opposed to Standard mode

where individual words are written. For clarification, in Packet Mode, a packet

can be written to the device with the starting location designated as Transmit Start

of Packet (TSOP) and the ending location designated as Transmit End of Packet

(TEOP). In conjunction, a packet read from the device will be designated as

Receive Start of Packet (RSOP) and a Receive End of Packet (REOP). The

minimum size for a packet is four words (SOP, two words of data and EOP). The

4 words must be the largest word that is configured. For example in a x18 to

x9 bus matching configuration the four words must be x18 bit words. The almost

empty flag bus becomes the “Packet Ready” PR flag bus when the device is

configured for packet mode. Valid packets are indicated when both PR and OR

are asserted.

WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)

Changing queues requires 4 WCLK cycles on the write port (see Figure 54,

Writing in Packet Mode during a Queue Change). WADEN goes high signaling

a change of queue (clock cycle “B” or “I”). The address on WRADD at the rising

edge of WCLK determines the next queue. Data presented on Din during that

cycle (“B” or “I”) and the next cycle (“C” or “J”) can continue to be written to

the active (old) queue (QA or QB respectively), provided WEN is LOW (active).

If WEN is HIGH (inactive) for these two clock cycles (H), data will not be written

in to the previous queue (QA). The write port discrete full flag will update to show

the full status of the newly selected queue (QB) at this last cycle’s rising edge (“D”

or “K”). Data values presented on the data input bus (Din), can be written into

the newly selected queue (QX) on the rising edge of WCLK on the third cycle

(“E”) following a request for change of queue, provided WEN is LOW (active)

and the new queue is not full. If a selected queue is full (FF is LOW), then writes

to that queue will be prevented. Note, data cannot be written into a full queue.

Refer to Figure 54, Writing in Packet Mode during a Queue Change for timing

diagrams.

READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)

Changing queues requires 4 RCLK cycles on the read port (see Figure 55,

Reading in Packet Mode during a Queue Change). RADEN goes high

signaling a change of queue (clock cycle “B” or “I”). The address on RDADD

at the rising edge of RCLK determines the queue. As illustrated in Figure 55

during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue to

be read from the active (old) queue (QA or QB respectively), provided both REN

and OE are LOW (active) simultaneously with changing queues. In applications

where the multi-queue flow-control device is connected to a shared bus, an

output enable, OE control pin is also provided to allow High-Impedance selection

of the data outputs (Qout).

Refer to Figure 55, Reading in Packet Mode during a Queue Change as

well as Figure 38, 39, 40, 41, and 42 for timing diagrams and Table 5, for Read

Address bus arrangement.

Note, the almost empty flag bus becomes the “Packet Ready” flag bus when

the device is configured for packet ready mode.

EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES

Expansion can take place only in IDT Standard mode. In the 8 Queue multi-

queue device, the WRADD address bus is 8 bits wide. The 7 Least Significant

bits (LSbs) are used to address one of the 32 available queues within a single

multi-queue device. The Most Significant bit (MSbs) is used when a device is

connected in expansion configuration with up to 8 devices connected in width

expansion, each device having its own bit address. When logically expanded

with multiple parts, each device is statically setup with a unique chip ID code on

the ID pins, ID0, ID1, and ID2. A device is selected when the Most Significant

bit of the WRADD address bus matches the ID code. The maximum logical

expansion is 64 queues (8 queues x 8 devices).

Note: The WRADD bus is also used in conjunction with FSTR (almost full flag

bus strobe), to address the almost full flag bus during direct mode of operation.

Refer to Table 4, for Write Address bus arrangement. Also, refer to Figure

47, Full Flag Timing Expansion Configuration, Figure 51, Output Ready Flag

Timing (In Expansion Configuration), and Figure 67, Expansion using ID

codes, for timing diagrams.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

SWITCHING QUEUES ON THE WRITE PORT

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices can be configured up to a maximum of 8 queues. Data is written into

a queue using the Data Input (Din) bus, Write Clock (WCLK) and Write Enable

(WEN) signals. Selecting a queue occurs by placing the queue address on the

Write Address bus (WRADD) during a rising edge of WCLK while Write Address

Enable (WADEN) is HIGH. For reference, the state of Write Enable (WEN) is

a “Don’t Care” during a queue selection. WEN has significance during the queue

mark operation. Selecting a queue requires 4 WCLK cycles. Refer to Figure

7, Write Port Switching Queues Signal Sequence.

WCLK

QS-1

Queue

address

Queue

address

QS0 QS1 QS2 QS3

WRADD

WADEN

6716 drw13

Queue Switch Cycle

Figure 7. Write Port Switching Queues Signal Sequence

WCLK

WEN

Din

6716 drw14

Queue Switch Cycles*

WADEN

PQ PQ PQ NQ NQ

Figure 8. Switching Queues Bus Efficiency

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device supports changing (switching) queues every four (4) clock cycles.

To switch from the Present Queue (PQ) to another queue requires a queue

address to be placed on the Write Address Bus (WRADD) bus and a rising edge

of Write Clock (WCLK) and Write Address Enable (WADEN) is HIGH. There

are no restrictions as to the order to which queues are selected or switched into

or out of.

For maximum efficiency, during the 4 clock cycles required to switch queues

the IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-control

device can continue to write into the Present Queue (PQ). The Present Queue

is defined as the current selected queue. Refer to Figure 8, Switching Queues

Bus Efficiency.

NOTES:

1. PQ = Present Queue

NQ = Next Queue

* Requires 4 clock cycles to switch queues.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Queue Switch IDT Mode FWFT Mode

Cycle

QS-1 Queue Switch Initiated, Rewrite/No Rewrite selection Queue Switch Initiated, Rewrite/No Rewrite selection

QS0 Queue MARK / Un-MARK Queue MARK / Un-MARK

QS1 ——

QS2 • PAF signal updated for Next Queue (NQ) • PAF signal updated for Next Queue (NQ)

• Packet Ready (PR) signal updated • Packet Ready (PR) signal updated

• Full Flag (FF) updated for NQ • IR flag updated for NQ

QS3 Start of Write Data Operation Start of Write Data Operation

TABLE 6 — WRITE QUEUE SWITCH OPERATION

6716 drw15

WCLK

WEN

Din

WADEN

RCLK

REN

RADEN

Qout PQ PQ PQ PQ PQ PQ

PQ PQ PQ PQ PQ NQ

Figure 9. Simultaneous Queue Switching

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device supports writing and reading from either the same queue of from

different queues. The device also supports simultaneous queue switching on

the write and read ports. The simultaneous queue switching may occur with

either the Write Clock and Read Clock synchronous or asynchronous to each

other. For reference refer to Figure 9, Simultaneous Queue Switching.

The multi-queue flow-control device requires 4 clock cycles to switch queues

on the write port. Refer to Table 6, Write Queue Switch Operation for a detailed

description of each queue switch clock cycle.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

SWITCHING QUEUES ON THE READ PORT

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol devices can be configured up to a maximum of 8 queues. Data is read from

a queue using the Data Output (Qout) bus, Read Clock (RCLK) and Read

Enable (REN) signals. Selecting a queue on the read port occurs by placing

the queue address on the Read Address bus (RDADD) during a rising edge

of RCLK while Read Address Enable (RADEN) is HIGH. For reference, the

state of Read Enable (REN) is a “Don’t Care” during a read port queue selection.

REN has significance during the queue mark operation. Selecting a queue

requires 4 WCLK cycles. Refer to Figure 10, Read Port Switching Queues

Signal Sequence.

RCLK

QS-1

Queue

address

Queue

address

QS0 QS1 QS2 QS3

RDADD

RADEN

6716 drw16

Queue Switch Cycle

Figure 11. Switching Queues Bus Efficiency

Figure 10. Read Port Switching Queues Signal Sequence

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device supports changing (switching) queues every four (4) clock cycles.

To switch from the Present Queue (PQ) to another queue requires a queue

address to be placed on the Read Address Bus (RDADD) bus and a rising edge

of Read Clock (RCLK) and Read Address Enable (RADEN) is HIGH. There

are no restrictions as to the order to which queues are selected or switched into

or out of.

For maximum efficiency, during the 4 clock cycles required to switch queues

the IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-control

device can continue to read from the Present Queue (PQ). The Present Queue

is defined as the current selected queue. Refer to Figure 11, Switching Queues

Bus Efficiency.

RCLK

REN

Qout

6716 drw17

Queue Switch Cycles

RADEN

PQ PQ PQ PQ NQ NQ

NOTE:

PQ = Present Queue

NQ = Next Queue

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

SIMULTANEOUS QUEUE SWITCHING

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device supports reading and writing from either the same queue of from

different queues. The device also supports simultaneous queue switching on

the read and write ports. The simultaneous queue switching may occur with

either the Read Clock and Write Clock synchronous or asynchronous to each

other. For reference refer to Figure 12, Simultaneous Queue Switching.

6716 drw18

WCLK

WEN

Din

WADEN

RCLK

REN

RADEN

Qout PQ PQ PQ PQ PQ PQ

PQ PQ PQ PQ NQ

Figure 12. Simultaneous Queue Switching

TABLE 7 — READ QUEUE SWITCH OPERATION

PQ NQ Supported Comment

Not Marked Not Marked Yes Queue Switch is ignored

Not Marked Marked Yes Add Mark to current queue

Marked Not Marked, No Reread Not Allowed

Marked Not Marked, Reread Ye s Remove Mark

Marked Marked, No Reread Not Allowed

Marked Marked, Reread Y e s Keep Mark

TABLE 8 — SAME QUEUE SWITCH

Legend:

PQ = Present Queue

NQ = Next Queue

Queue Switch IDT Mode FWFT Mode

Cycle

QS-1 Queue Switch Initiated, Re-read/No Re-read selection Queue Switch Initiated, Re-read/No Re-read selection

QS0 Queue MARK / Un-MARK Queue MARK / Un-MARK

QS1 ——

QS2 • PAE signal updated for Next Queue (NQ) • PAE signal updated for Next Queue (NQ)

• Packet Ready (PR) signal updated • Packet Ready (PR) signal updated

• Empty Flag (EF) updated for NQ

QS3 Start of Read Data Operation • Start of Read Data Operation

• OR updated for NQ

The multi-queue flow-control device requires 4 clock cycles to switch queues

on the read port, refer to Table 7, Read Queue Switch Operation for a detailed

description of each queue switch clock cycles.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

QUEUE MARKing

The overall intent of the MARK function is to provide the ability to either re-

write and/or re-read information that is stored into a queue.

A queue can be MARKed by either the write port or the read port. The MARK

operation is port independent. The same queue can be marked by the write port

and the read port simultaneously. Only the active queue can be MARKed,

multiple queues can NOT be MARKed by a port. A port (write or read) may only

designate one queue MARKed at a time. Upon a queue switch a decision must

be made as to whether to return to the Marked location or the last access address.

MARK AND REWRITE/ MARK AND REREAD

The MARK functionality operates in any mode combination (Packet mode,

IDT Standard Mode, FIFO Mode, FWFT Mode), FWFT). Queues on the Write

Port are MARKed using the WCLK & WADEN signals. Queues on the Read

Port are MARKed using the RCLK and RADEN signals. Refer to the following

timing diagrams for additional queue MARK details. Refer to Figure 13 through

18 for further information.

6716 drw29

Present Queue (PQ)

QS-1

WCLK

QS3

QS0

QS1

QS2

WEN

WADEN

DIN

Next Queue (NQ)

•@QS-1, if WEN=0 and WADEN=1, PQ will be updated in QS0,1, and 2, and NQ data will be written in QS3.

•@QS-1, if WEN_N=1 and WADEN=1, there is no update for PQ during QS0-QS2. Next time PQ is switched back, data will be written into last update

location (rewrite).

•@QS0, WADEN status is used to determine if a “mark” is requested for NQ. If WADEN=1 in QS0, NQ will be marked. In FIFO mode, the first NQ

position after QS is marked (latch WFCR values before QS3), data can’t be read out beyond this location. In packet mode, every SOP position is

marked till next SOP comes, then the mark moves to new position.

•@QS0, if WADEN=0, NQ is not marked. Figure 13. MARK and Re-Write Sequence

•@QS-1 (A), if REN=0 and RADEN=1, (request for a Queue Switch occurs RADEN=1 and simultaneously reading from a queue) the Queue Address

•@QS-1, if REN=1 and RADEN=1, (request for a Queue Switch occurs RADEN =1) the Queue Address Register will be updated in QS2. The Present

Queue address pointer will not increment during QS0-QS2. The Next time PQ is selected, the data will be from the last addressed location.

•@QS0, RADEN status is used to determine if a “mark” is requested for NQ. If RADEN=1 in QS0, NQ will be mark. In FIFO mode, first NQ position after

QS is marked (latch RFCR values before QS3), data can’t overwrite this location. In packet mode, every SOP position is marked till next SOP comes,

then the mark moves to new position. Figure 14. MARK and Re-Read Sequence

6716 drw30

Present Queue

QS-1

QS3

QS0

QS1

QS2

RCLK

REN

RADEN

QOUT

Next Queue

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK

WCLK

Wr i t e Queue

Select Cycle

Wr i t e Queue

MARK Cycle

WADEN

Write Queue MARK

This rising edge of

WCLK is the start of

the 1st cycle

B A

WADEN

ACTI ON

1 1 Selects a Queue & MARK the Queue

1 0 Selects a Queue

6716 drw31

Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK

6716 drw32

RCLK

Read Queue

MARK Cycle

RADEN

ACTI ON

1 1

1 0

Read Queue MARK

This rising edge of RCLK is

the start of the 1st cycle

Selects a Queue & MARK the Queue

Selects a Queue

Read Queue

Select Cycle

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK

6716 drw33

WCLK

Write Queue

Select Cycle

WADEN

Write Queue UN-M A RK

Thi s risi ng edge of

WCLK is the start

of the 1

cycl e.

WADEN

ACTI ON

1 1 Selects a Queue and MARK the Queue

1 0 Selects a Queue and Remove MARK

Write Queue

MARK Cycle

Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK

6716 drw34

RCLK

Read Queue

Select Cycle

RADEN

Read Queue U N-M A RK

Thi s risi ng edge of

RCLK is the start

of the 1

st cycl e.

RADEN

ACTI ON

1 1 Selects a Queue and MARK the Queue

1 0 Selects a Queue & Remove MARK

Read Queue

MARK Cycle

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

MARK OPERATIONAL NOTES:

IN PACKET MODE

Write Port

- MARKing a location can only occur during a Queue switch cycle

- There is only one MARKed location within a Queue

- Only 1 packet can be MARKed at a time within a Queue.

- In packet mode, for a full packet re-write the MARK must occur at the SOP location of the packet.

- In packet mode data can be re-written from the MARK

- In packet mode the MARK moves from packet to packet within a queue when the next packet is written.

- The sequence to move the MARK to the next packet is, first an EOP must occur, then a valid write occurs.

6716 drwX35

EOP SOP

Queue MARK

MARK Move Sequence

Read Port

- MARKing can only occur during a Queue switch cycle

- Only 1 packet can be MARKed at a time within a Queue.

- In packet mode, MARK is moved to a location of the packet.

-In packet mode the MARK can be moved from SOP (start of packet) to SOP (start of packet) within the queue by a valid read.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK

WCLK

Wri te Queue

Select Cycle

Wri t e Queue

MARK Cycle

WADEN

W ri t e Queue M A RK

Thi s ri sing edge of

WCLK is the start of the

cycle

B A

6716 drw36

WADEN

ACTI ON

1 1 Selects the Queue and MARK the Queue

1 0 Selects a Queue

Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK

Thi s risi ng edge of

RCLK is the start

cycle

B A

6716 drw37

ACTI ON

1 1 Selects the Queue and MARK the Queue

1 0 Selects a Queue

RCLK

Read Queue

Select Cycle

RADEN

Read Queue MARK

of the

RADEN

Read Queue

MARK Cycle

MARK Operational Notes:

In FIFO Mode

Write Port

- MARKing can only occur during a Queue switch cycle

- The entire Queue is MARKed at a time.

- In IDT Standard/FWFT mode, MARK is used to mark the first location

of the Queue.

- In IDT Standard/FWFT mode the MARK can NOT be moved within the

queue.

Read Port

- MARKing can only occur during a Queue switch cycle

- Only the first location of the Queue can be MARKed in Standard /FWFT

mode.

- In IDT Standard mode the MARK can NOT be moved location to location

within the queue.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK

Thi s ri si ng edge of

WC LK i s the start

cycle

B A

6716 drw38

ACTI ON

1 0 Selects a Queue and UN-MARK the Queue

WCLK

Write Queue

Select Cycle

WADEN

Write Queue UN-MARK

of the

WADEN

Write Queue

MARK Cycle

Un-MARKing a Queue

UN-MARKing a Queue in FIFO Mode

Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK

Thi s ri si ng edge of

RCLK is the start

1st cycl e

B A

6716 drw39

ACTI ON

1 0 Selects a Queue and UN-MARK the Queue

RCLK

Read Queue

Select Cycle

RADEN

Read Queue UN-MARK

of the

RADEN

Read Queue

MARK Cycle

UN-MARK Operational Notes:

In FIFO Mode

Write Port

- Un-MARKing can only occur during a Queue switch cycle.

- In FIFO Mode, UN-MARKing a Queue can be accomplished by either

switching to the same queue or switching to another queue.

- Note only 1 queue can be marked at any given time.

- In Standard/FIFO mode the MARK can NOT be moved location to

location within the queue.

Read Port

- Un-MARKing can only occur during a Queue switch cycle.

- In Standard/FIFO mode, UN-MARKing a Queue can be accomplished

by either switching to the same queue or switching to another queue.

- Note only 1 queue can be marked at any given time.

- In Standard/FIFO mode the MARK can NOT be moved location to

location within the queue.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Leaving a MARK Active

During a Queue switch the value of WEN for the write port and REN for the

read port determines whether the MARK remains active or is de-activated.

Figure 23. Leaving a MARK active on the Write Port

6716 drw40

WCLK

Write Queue

Select Cycle

Leaving a MARK active on the Write Port

Leave the MARK

(A rewrite

request)

Write Queue

MARK Cycle

WADEN

WEN

Figure 24. Leaving a MARK active on the Read Port

6716 drw41

RCLK

Read Queue

Select Cycle

Leaving a MARK active on the Read Port

Leave the MARK

(A re-read

request)

Read Queue

MARK Cycle

RADEN

REN

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 25. Inactivating a MARK on the Write Port Active

6716 drw42

WCLK

Write Queue

Select Cycle

Inactivating a MARK on the Write Port

Inactivate the

Write Port MARK

(No re-write)

Write Queue

MARK Cycle

WADEN

WEN

Figure 26. Inactivating a MARK on the Read Port Active

6716 drw43

RCLK

Read Queue

Select Cycle

Inactivating a MARK on the Read Port

Inactivate the

Read Port MARK

(No re-read)

Read Queue

MARK Cycle

RADEN

REN

Inactivating a MARK

During a Queue switch the value of WEN for the write port and REN for the

read port determines whether the MARK remains active or is de-activated.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

6716 drw44

1st Cycle

Action WEN

(active LOW)

Operation 0 0 0 0

Selects a

Queue 0 1 0 1

Operation 1 0 1 0

Operation 1 1 1 1

2nd Cycle

WADEN

(active HIGH)

WEN

(active LOW)

WADEN

(active HIGH)

Write Cycle

6716 drw45

1st Cycle

Action REN

(active LOW)

Operation 0 0 0 0

Selects a

Queue 0 1 0 1

Operation 1 0 1 0

Operation 1 1 1 1

2nd Cycle

RADEN

(active HIGH)

REN

(active LOW)

RADEN

(active HIGH)

Read Cycle

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

FLAG DESCRIPTION

PAFn FLAG BUS OPERATION

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device can be configured for up to 8 queues, each queue having its own

almost full status. An active queue has its flag status output to the discrete flags,

FF and PAF, on the write port. Queues that are not selected for a write operation

can have their PAF status monitored via the PAFn bus. The PAFn flag bus is

8 bits wide, so that 8 queues at a time can have their status output to the bus.

If 9 or more queues are setup within a device then there are 2 methods by which

the device can share the bus between queues, “Direct” mode and “Polled” mode

depending on the state of the FM (Flag Mode) input during a Master Reset. If

8 or less queues are setup within a device then each will have its own dedicated

output from the bus. If 8 or less queues are setup in single device mode, it is

recommended to configure the PAFn bus to polled mode as it does not require

using the write address (WRADD).

FULL FLAG OPERATION

The multi-queue flow-control device provides a single Full Flag output, FF.

The FF flag output provides a full status of the queue currently selected on the

write port for write operations. Internally the multi-queue flow-control device

monitors and maintains a status of the full condition of all queues within it, however

only the queue that is selected for write operations has its full status output to the

FF flag. This dedicated flag is often referred to as the “active queue full flag”.

When queue switches are being made on the write port, the FF flag output

will switch to the new queue and provide the user with the new queue status,

on the 3rd cycle after a new queue selection is made. The user then has a full

status for the new queue one cycle ahead of the WCLK rising edge that data

can be written into the new queue. That is, a new queue can be selected on

the write port via the WRADD bus, WADEN enable and a rising edge of WCLK.

On the 4th rising edge of WCLK, the FF flag output will show the full status of the

newly selected queue. On the forth rising edge of WCLK following the queue

selection, data can be written into the newly selected queue provided that data

and enable setup & hold times are met.

Note, the FF flag will provide status of a newly selected queue three WCLK

cycle after queue selection, which is one cycle before data can be written to that

queue. This prevents the user from writing data to a queue that is full, (assuming

that a queue switch has been made to a queue that is actually full).

The FF flag is synchronous to the WCLK and all transitions of the FF flag occur

based on a rising edge of WCLK. Internally the multi-queue device monitors and

keeps a record of the full status for all queues. It is possible that the status of a

FF flag maybe changing internally even though that flag is not the active queue

flag (selected on the write port). A queue selected on the read port may

experience a change of its internal full flag status based on read operations.

See Figure 44, Write Queue Select, Write Operation and Full Flag

Operation and Figure 47, Full Flag Timing in Expansion Configuration for timing

information.

EXPANSION CONFIGURATION - FULL FLAG OPERATION

When multi-queue devices are connected in Expansion configuration the FF

flags of all devices should be connected together, such that a system controller

monitoring and managing the multi-queue devices write port only looks at a

single FF flag (as opposed to a discrete FF flag for each device). This FF flag

is only pertinent to the queue being selected for write operations at that time.

Remember, that when in expansion configuration only one multi-queue device

can be written to at any moment in time, thus the FF flag provides status of the

active queue on the write port.

This connection of flag outputs to create a single flag requires that the FF flag

output have a High-Impedance capability, such that when a queue selection is

made only a single device drives the FF flag bus and all other FF flag outputs

connected to the FF flag bus are placed into High-Impedance. The user does

not have to select this High-Impedance state, a given multi-queue flow-control

device will automatically place its FF flag output into High-Impedance when none

of its queues are selected for write operations.

When queues within a single device are selected for write operations, the FF

flag output of that device will maintain control of the FF flag bus. Its FF flag will

simply update between queue switches to show the respective queue full status.

The multi-queue device places its FF flag output into High-Impedance based

on the 1-3 bit ID code (1 if two multi-queue are configured with a maximum total

of 256 queues, 2 if four devices are used totalling a maximum of 256 queues,

and 3 if there are up to eight devices with a maximum total of 256 queues) found

in the 1-3 most significant bits of the write queue address bus, WRADD. If the

1-3 most significant bits of WRADD match the 1-3 bit ID code setup on the static

inputs, ID0, ID1 and ID2 then the FF flag output of the respective device will be

in a Low-Impedance state. If they do not match, then the FF flag output of the

respective device will be in a High-Impedance state. See Figure 47, Full Flag

Timing in Expansion Configuration for details of flag operation, including when

more than one device is connected in expansion.

EMPTY OR OUTPUT READY FLAG OPERATION (EF/OR)

The multi-queue flow-control device provides a single Empty or Output

Ready flag output, EF/OR. The OR provides an empty status or data Output

Ready status for the data word currently available on the output register of the

read port. The rising edge of an RCLK cycle that places new data onto the output

new data word is actually valid. Internally the multi-queue flow-control device

monitors and maintains a status of the empty condition of all queues within it,

however only the queue that is selected for read operations has its Output Ready

(empty) status output to the OR flag, giving a valid status for the word being read

at that time.

The nature of the first word fall through operation means that when the last

data word is read from a selected queue, the OR flag will go HIGH on the next

enabled read, that is, on the next rising edge of RCLK while REN is LOW.

When queue switches are being made on the read port, the OR flag will switch

to show status of the new queue in line with the data output from the new queue.

When a queue selection is made the first data from that queue will appear on

the Qout data outputs 4 RCLK cycles later, the OR will change state to indicate

validity of the data from the newly selected queue on this 3rd RCLK cycle also.

The previous cycles will continue to output data from the previous queue and

the OR flag will indicate the status of those outputs. Again, the OR flag always

indicates status for the data currently present on the output register.

The OR flag is synchronous to the RCLK and all transitions of the OR flag occur

based on a rising edge of RCLK. Internally the multi-queue device monitors and

keeps a record of the Output Ready (empty) status for all queues. It is possible

that the status of an OR flag may be changing internally even though that

respective flag is not the active queue flag (selected on the read port). A queue

selected on the write port may experience a change of its internal OR flag status

based on write operations, that is, data may be written into that queue causing

it to become “not empty”.

See Figure 48, Read Queue Select, Read Operation and Figure 51, Output

Ready Flag Timing for details of the timing.

EXPANSION – EMPTY FLAG OPERATION

When multi-queue devices are connected in Expansion configuration, the EF

flags of all devices should be connected together, such that a system controller

monitoring and managing the multi-queue devices read port only looks at a

single EF flag (as opposed to a discrete EF flag for each device). This EF flag

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

is only pertinent to the queue being selected for read operations at that time.

Remember, that when in expansion configuration only one multi-queue device

can be read from at any moment in time, thus the EF flag provides status of the

active queue on the read port.

This connection of flag outputs to create a single flag requires that the EF flag

output have a High-Impedance capability, such that when a queue selection is

made only a single device drives the EF flag bus and all other EF flag outputs

connected to the EF flag bus are placed into High-Impedance. The user does

not have to select this High-Impedance state, a given multi-queue flow-control

device will automatically place its EF flag output into High-Impedance when none

of its queues are selected for read operations.

When queues within a single device are selected for read operations, the EF

flag output of that device will maintain control of the EF flag bus. Its EF flag will

simply update between queue switches to show the respective queue status.

The multi-queue device places its EF flag output into High-Impedance based

on the 1-3 bit ID code (1 if two multi-queue are configured with a maximum total

of 256 queues, 2 if four devices are used totalling a maximum of 256 queues,

and 3 if there are up to eight devices with a maximum total of 256 queues) found

in the 3 most significant bits of the read queue address bus, RDADD. If the 3 most

significant bits of RDADD match the 1-3 bit ID code setup on the static inputs, ID0,

ID1 and ID2 then the EF flag output of the respective device will be in a Low-

Impedance state. If they do not match, then the EF flag output of the respective

device will be in a High-Impedance state. See Figure 51, Output Ready Flag

Timing for details of flag operation, including when more than one device is

connected in expansion.

ALMOST FULL FLAG

As previously mentioned the multi-queue flow-control device provides a

single Programmable Almost Full flag output, PAF. The PAF flag output provides

a status of the almost full condition for the active queue currently selected on the

write port for write operations. Internally the multi-queue flow-control device

monitors and maintains a status of the almost full condition of all queues within

it, however only the queue that is selected for write operations has its full status

output to the PAF flag. This dedicated flag is often referred to as the “active queue

almost full flag”. The position of the PAF flag boundary within a queue can be

at any point within that queues depth. This location can be user programmed

via the serial port or one of the default values (8 or 128) can be selected if the

user has performed default programming.

As mentioned, every queue within a multi-queue device has its own almost

full status, when a queue is selected on the write port, this status is output via the

PAF flag. The PAF flag value for each queue is programmed during multi-queue

device programming (along with the number of queues, queue depths and

almost empty values). The PAF offset value, m, for a respective queue can be

programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory

depth for that queue. The PAF value of different queues within the same device

can be different values.

When queue switches are being made on the write port, the PAF flag output

will switch to the new queue and provide the user with the new queue status,

on the third cycle after a new queue selection is made, on the same WCLK cycle

that data can actually be written to the new queue. That is, a new queue can

be selected on the write port via the WRADD bus, WADEN enable and a rising

edge of WCLK. On the third rising edge of WCLK following a queue selection,

the PAF flag output will show the full status of the newly selected queue. The PAF

is flag output is double register buffered, so when a write operation occurs at

the almost full boundary causing the selected queue status to go almost full the

PAF will go LOW 2 WCLK cycles after the write. The same is true when a read

occurs, there will be a 2 WCLK cycle delay after the read operation.

So the PAF flag delay from a write operation to PAF flag LOW is 2 WCLK +

tWAF. The delay from a read operation to PAF flag HIGH is tSKEW2 + WCLK +

tWAF.

Note, if tSKEW is violated there will be one added WCLK cycle delay.

The PAF flag is synchronous to the WCLK and all transitions of the PAF flag

occur based on a rising edge of WCLK. Internally the multi-queue device

monitors and keeps a record of the almost full status for all queues. It is possible

that the status of a PAF flag maybe changing internally even though that flag is

not the active queue flag (selected on the write port). A queue selected on the

read port may experience a change of its internal almost full flag status based

on read operations. The multi-queue flow-control device also provides a

duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail

in a later section of the data sheet.

See Figures 23 and 24 for Almost Full flag timing and queue switching.

ALMOST EMPTY FLAG

As previously mentioned the multi-queue flow-control device provides a

single Programmable Almost Empty flag output, PAE. The PAE flag output

provides a status of the almost empty condition for the active queue currently

selected on the read port for read operations. Internally the multi-queue flow-

control device monitors and maintains a status of the almost empty condition of

all queues within it, however only the queue that is selected for read operations

has its empty status output to the PAE flag. This dedicated flag is often referred

to as the “active queue almost empty flag”. The position of the PAE flag boundary

within a queue can be at any point within that queues depth. This location can

be user programmed via the serial port or one of the default values (8 or 128)

can be selected if the user has performed default programming.

As mentioned, every queue within a multi-queue device has its own almost

empty status, when a queue is selected on the read port, this status is output via

the PAE flag. The PAE flag value for each queue is programmed during multi-

queue device programming (along with the number of queues, queue depths

and almost full values). The PAE offset value, n, for a respective queue can be

programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory

depth for that queue. The PAE value of different queues within the same device

can be different values.

When queue switches are being made on the read port, the PAE flag output

will switch to the new queue and provide the user with the new queue status,

on the third cycle after a new queue selection is made, on the same RCLK cycle

that data actually falls through to the output register from the new queue. That

is, a new queue can be selected on the read port via the RDADD bus, RADEN

enable and a rising edge of RCLK. On the third rising edge of RCLK following

a queue selection, the data word from the new queue will be available at the

output register and the PAE flag output will show the empty status of the newly

selected queue. The PAE is flag output is double register buffered, so when a

read operation occurs at the almost empty boundary causing the selected queue

status to go almost empty the PAE will go LOW 2 RCLK cycles after the read.

The same is true when a write occurs, there will be a 3 RCLK cycle delay after

the write operation.

So the PAE flag delay from a read operation to PAE flag LOW is 2 RCLK +

tRAE. The delay from a write operation to PAE flag HIGH is tSKEW2 + RCLK +

tRAE.

Note, if tSKEW is violated there will be one added RCLK cycle delay.

The PAE flag is synchronous to the RCLK and all transitions of the PAE flag

occur based on a rising edge of RCLK. Internally the multi-queue device

monitors and keeps a record of the almost empty status for all queues. It is possible

that the status of a PAE flag maybe changing internally even though that flag is

not the active queue flag (selected on the read port). A queue selected on the

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

write port may experience a change of its internal almost empty flag status based

on write operations. The multi-queue flow-control device also provides a

duplicate of the PAE flag on the PAE[7:0] flag bus, this will be discussed in detail

in a later section of the data sheet.

See Figures 25 and 26 for Almost Empty flag timing and queue switching.

PAFn - DIRECT BUS

If FM is LOW at master reset then the PAFn bus operates in Direct (addressed)

mode. In direct mode the user can address the status word of queues they

require and it will be placed on to the PAFn bus. For example, consider the

operation of the PAFn bus when 26 queues have been setup. To output status

of the first status word, Queue[0:7] the WRADD bus is used in conjunction with

the FSTR (PAF flag strobe) input and WCLK. The address present on the 4

least significant bits of the WRADD bus with FSTR HIGH will be selected as the

status word address on a rising edge of WCLK. To address status word 0,

Queue[0:7] the WRADD bus should be loaded with “0010000”, the PAFn bus

will change status to show the new status word selected 1 WCLK cycle after status

word selection. PAFn[0:7] gets status of queues, Queue[0:7] respectively.

To address status word 1, Queue[8:15], the WRADD address is “00100001”.

PAFn[0:7] gets status of queues, Queue[8:15] respectively. To address the 2nd

status word, Queue[16:23], the WRADD address is “00100010”. PAF[0:7] gets

status of queues, Queue[16:23] respectively. To address the 3rd status word,

Queue[24:31], the WRADD address is “00100011”. PAF[0:1] gets status of

queues, Queue[24:25] respectively. Remember, only 26 queues were setup,

so when status word 4 is selected the unused outputs PAF[2:7] will be don't care

states.

Note, that if a read or write operation is occurring to a specific queue, say

queue ‘x’ on the same cycle as a status word switch which will include the queue

‘x’, then there may be an extra WCLK cycle delay before that queues status is

correctly shown on the respective output of the PAFn bus. However, the active

PAF flag will show correct status at all times.

Status words can be selected on consecutive clock cycles, that is the status

word on the PAFn bus can change every WCLK cycle. Also, data present on

the input bus, Din, can be written into a Queue on the same WCLK rising edge

that a status word is being selected, the only restriction being that a write queue

selection and PAFn status word selection cannot be made on the same cycle.

If 8 or less queues are setup then queues, Queue[0:7] have their PAF status

output on PAF[0:7] constantly.

When the multi-queue devices are connected in expansion of more than one

device the PAFn busses of all devices are connected together, when switching

between status words of different devices the user must utilize the 1-3 most

significant bits of the WRADD address bus (as well as the 2 LSB’s). These 1-

3 MSb’s correspond to the device ID inputs, which are the static inputs, ID0, ID1

& ID2.

Please refer to Figure 63

PAF

n - Direct Mode Status Word Selection for

timing information. Also refer to Table 4, Write Address Bus, WRADD.

PAFn – POLLED BUS

If FM is HIGH at master reset then the PAFn bus operates in Polled (looped)

mode. In polled mode the PAFn bus only cycles through the number of status

words required to display the status of the number of queues that have been

setup in the part. Every rising edge of the WCLK causes the next status word

to be loaded on the PAFn bus. The device configured as the master (MAST

input tied HIGH), will take control of the PAFn after MRS goes LOW. For the whole

WCLK cycle that the first status word is on PAFn the FSYNC (PAFn bus sync)

output will be HIGH, for all other status words, this FSYNC output will be LOW.

This FSYNC output provides the user with a mark with which they can

synchronize to the PAFn bus, FSYNC is always HIGH for the WCLK cycle that

the first status word of a device is present on the PAFn bus.

When devices are connected in expansion configuration, only one device

will be set as the Master (ID = '000'), MAST input tied HIGH, all other devices

will have MAST tied LOW. The master device is the first device to take control

of the PAFn bus and will place its first status word on the bus on the rising edge

of WCLK. For the next n WCLK cycles (n= number of queues divided by 8 with

n being increased by one for any remainder) the master device will maintain

control of the PAFn bus and cycle its status words through it, all other devices

hold their PAFn outputs in High-Impedance. When the master device has cycled

all of its status words it passes a token to the next device in the chain and that

device assumes control of the PAFn bus and then cycles its status words and

so on, the PAFn bus control token being passed on from device to device. This

token passing is done via the FXO outputs and FXI inputs of the devices (“PAF

Expansion Out” and “PAF Expansion In”). The FXO output of the master device

connects to the FXI of the second device in the chain and the FXO of the second

connects to the FXI of the third and so on. The final device in a chain has its FXO

connected to the FXI of the first device, so that once the PAFn bus has cycled

through all status words of all devices, control of the PAFn will pass to the master

device again and so on. The FSYNC of each respective device will operate

independently and simply indicate when that respective device has taken control

of the bus and is placing its first status word on to the PAFn bus.

When operating in single device mode the FXI input must be connected to

the FXO output of the same device. In single device mode a token is still required

to be passed into the device for accessing the PAFn bus.

Please refer to Figure 66,

PAF

n Bus – Polled Mode for timing information.

PAEn/PRn FLAG BUS OPERATION

The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-

trol device can be configured for up to 8 queues, each queue having its own

almost empty/ packet ready status. An active queue has its flag status output to

the discrete flags, OR, PAE and PR, on the read port. Queues that are not

selected for a read operation can have their PAE/PR status monitored via the

PAEn/PRn bus. The PAEn/PRn flag bus is 8 bits wide, so that 8 queues at a

time can have their status output to the bus. If 9 or more queues are setup within

a device then there are 2 methods by which the device can share the bus

between queues, "Direct" mode and "Polled" mode depending on the state of

the FM (Flag Mode) input during a Master Reset. If 8 or less queues are setup

within a device then each will have its own dedicated output from the bus. If 8

or less queues are setup in single device mode, it is recommended to configure

the PAFn bus to polled mode as it does not require using the write address

(WRADD).

PAEn/PRn - DIRECT BUS

If FM is LOW at master reset then the PAEn/PRn bus operates in Direct

(addressed) mode. In direct mode the user can address the status word of

queues they require to be placed on to the PAEn/PRn bus. For example,

consider the operation of the PAEn/PRn bus when 26 queues have been setup.

To output status of the first status word, Queue[0:7] the RDADD bus is used in

conjunction with the ESTR (PAE/PR flag strobe) input and RCLK. The address

present on the 2 least significant bits of the RDADD bus with ESTR HIGH will

be selected as the status word address on a rising edge of RCLK. So to address

status word 1, Queue[0:7] the RDADD bus should be loaded with “xxxx0000”,

the PAEn/PRn bus will change status to show the new status word selected 1

RCLK cycle after status word selection. PAEn[0:7] gets status of queues,

Queue[0:7] respectively.

To address the second status word, Queue[8:15], the RDADD address is

“xxxx0001”. PAEn[0:7] gets status of queues, Queue[8:15] respectively. To

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

TABLE 9 — FLAG OPERATION BOUNDARIES & TIMING

Output Ready, EF Flag Boundary

I/O Set-Up EF Boundary Condition

In36 to out36 (Almost Empty Mode) EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

In36 to out36 (Packet Mode) EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

In36 to out18 EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

In36 to out9 EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

In18 to out36 EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

In9 to out36 EF Goes LOW after Last Read

(Both ports selected for same queue

when the 1st Word is written in)

NOTE:

D = Queue Depth

FF Timing

Assertion:

Write Operation to FF LOW: tWFF

De-assertion:

Read to FF HIGH: tSKEW1 + tWFF

If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF

Full Flag, FF Boundary

I/O Set-Up FF Boundary Condition

In36 to out36 FF Goes LOW after D+1 Writes

(Both ports selected for same queue (see note below for timing)

when the 1st Word is written in)

In36 to out36 FF Goes LOW after D Writes

(Write port only selected for queue (see note below for timing)

when the 1st Word is written in)

In36 to out18 FF Goes LOW after D Writes

(Both ports selected for same queue (see note below for timing)

when the 1st Word is written in)

In36 to out18 FF Goes LOW after D Writes

(Write port only selected for queue (see note below for timing)

when the 1st Word is written in)

In36 to out9 FF Goes LOW after D Writes

(Both ports selected for same queue (see note below for timing)

when the 1st Word is written in)

In36 to out9 FF Goes LOW after D Writes

(Write port only selected for queue (see note below for timing)

when the 1st Word is written in)

In18 to out36 FF Goes LOW after ([D+1] x 2) Writes

(Both ports selected for same queue (see note below for timing)

when the 1st Word is written in)

In18 to out36 FF Goes LOW after (D x 2) Writes

(Write port only selected for queue (see note below for timing)

when the 1st Word is written in)

In9 to out36 FF Goes LOW after ([D+1] x 4) Writes

(Both ports selected for same queue (see note below for timing)

when the 1st Word is written in)

In9 to out36 FF Goes LOW after (D x 4) Writes

(Write port only selected for queue (see note below for timing)

when the 1st Word is written in)

Programmable Almost Full Flag, PAF & PAFn Bus Boundary

I/O Set-Up PAF & PAFn Boundary

in36 to out36 PAF/PAFn Goes LOW after

(Both ports selected for same queue when the 1st D+1-m Writes

Word is written in until the boundary is reached) (see note below for timing)

in36 to out36 PAF/PAFn Goes LOW after

(Write port only selected for same queue when the D-m Writes

1st Word is written in until the boundary is reached) (see note below for timing)

in36 to out18 PAF/PAFn Goes LOW after

D-m Writes (see below for timing)

in36 to out9 PAF/PAFn Goes LOW after

D-m Writes (see below for timing)

in18 to out36 PAF/PAFn Goes LOW after

([D+1-m] x 2) Writes

(see note below for timing)

in9 to out36 PAF/PAFn Goes LOW after

([D+1-m] x 4) Writes

(see note below for timing)

NOTE:

D = Queue Depth

m = Almost Full Offset value.

Default values: if DF is LOW at Master Reset then m = 8

if DF is HIGH at Master Reset then m= 128

PAF Timing

Assertion: Write Operation to PAF LOW: 2 WCLK + tWAF

De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF

If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF

PAFn Timing

Assertion: Write Operation to PAFn LOW: 2 WCLK* + tPAF

De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF

If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF

* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion

there may be one additional WCLK clock cycle delay.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

TABLE 9 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)

NOTE:

n = Almost Empty Offset value.

Default values: if DF is LOW at Master Reset then n = 8

if DF is HIGH at Master Reset then n = 128

PAEn Timing

Assertion: Read Operation to PAEn LOW: 2 RCLK* + tPAE

De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE

If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE

* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion

there may be one additional RCLK clock cycle delay.

Programmable Almost Empty Flag Bus, PAEn Boundary

I/O Set-Up PAEn Boundary Condition

in36 to out36 PAEn Goes HIGH after

(Both ports selected for same queue when the 1st n+2 Writes

Word is written in until the boundary is reached) (see note below for timing)

in36 to out36 PAEn Goes HIGH after

(Write port only selected for same queue when the n+1 Writes

1st Word is written in until the boundary is reached) (see note below for timing)

in36 to out18 PAEn Goes HIGH after n+1

Writes (see below for timing)

in36 to out9 PAEn Goes HIGH after n+1

Writes (see below for timing)

in18 to out36 PAEn Goes HIGH after

(Both ports selected for same queue when the 1st ([n+2] x 2) Writes

Word is written in until the boundary is reached) (see note below for timing)

in18 to out36 PAEn Goes HIGH after

(Write port only selected for same queue when the ([n+1] x 2) Writes

1st Word is written in until the boundary is reached) (see note below for timing)

in9 to out36 PAEn Goes HIGH after

(Both ports selected for same queue when the 1st ([n+2] x 4) Writes

Word is written in until the boundary is reached) (see note below for timing)

in9 to out36 PAEn Goes HIGH after

(Write port only selected for same queue when the ([n+1] x 4) Writes

1st Word is written in until the boundary is reached) (see note below for timing)

NOTE:

n = Almost Empty Offset value.

Default values: if DF is LOW at Master Reset then n = 8

if DF is HIGH at Master Reset then n = 128

PAE Timing

Assertion: Read Operation to PAE LOW: 2 RCLK + tRAE

De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE

If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE

Programmable Almost Empty Flag, PAE Boundary

I/O Set-Up PAE Assertion

in36 to out36 PAE Goes HIGH after n+2

(Both ports selected for same queue when the 1st Writes

Word is written in until the boundary is reached) (see note below for timing)

in36 to out18 PAE Goes HIGH after n+1

(Both ports selected for same queue when the 1st Writes

Word is written in until the boundary is reached) (see note below for timing)

in36 to out9 PAE Goes HIGH after n+1

(Both ports selected for same queue when the 1st Writes

Word is written in until the boundary is reached) (see note below for timing)

in18 to out36 PAE Goes HIGH after

(Both ports selected for same queue when the 1st ([n+2] x 2) Writes

Word is written in until the boundary is reached) (see note below for timing)

in9 to out36 PAE Goes HIGH after

(Both ports selected for same queue when the 1st ([n+2] x 4) Writes

Word is written in until the boundary is reached) (see note below for timing)

PACKET READY FLAG, PR BOUNDARY

Assertion:

Both the rising and falling edges of PR are synchronous to RCLK.

PR Falling Edge occurs upon writing the first TEOP marker, on input D35,

(assuming a TSOP marker, on input D34 has previously been written). i.e. a

complete packet is available within a queue.

Timing:

From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4

+ 2 RCLK + tPR

If tSKEW4 is violated:

PR goes LOW after tSKEW4 + 3 RCLK + tPR

De-assertion:

PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.

i.e. there are no more complete packets available within the queue.

Timing:

From RCLK rising edge Reading the RSOP word the PR goes HIGH after:

3 RCLK + tPR

(Please refer to Figure 57, Data Output (Receive) Packet Mode of Operation

for timing diagram).

PACKET READY FLAG BUS, PRn BOUNDARY

Assertion:

Both the rising and falling edges of PRn are synchronous to RCLK.

PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,

(assuming a TSOP marker, on input D34 has previously been written). i.e. a

complete packet is available within a queue.

Timing:

From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4

+ 2 RCLK* + tPAE

If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE

*If a queue switch is occurring on the read port at the point of flag assertion there

may be one additional RCLK clock cycle delay.

De-assertion:

PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.

i.e. there are no more complete packets available within the queue.

Timing:

From RCLK rising edge Reading the RSOP word the PR goes HIGH after:

3 RCLK* + tPAE

*If a queue switch is occurring on the read port at the point of flag assertion or

de-assertion there may be one additional RCLK clock cycle delay.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

address the third status word, Queue[16:23], the RDADD address is “xxxx0010”.

PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the

fourth status word, Queue[24:31], the RDADD address is “xxxx0011”.

PAE[0:1] gets status of queues, Queue[24:25] respectively. Remember, only

26 queues were setup, so when status word 4 is selected the unused outputs

PAE[2:7] will be don't care states.

Note, that if a read or write operation is occurring to a specific queue, say

queue ‘x’ on the same cycle as a status word switch which will include the queue

‘x’, then there may be an extra RCLK cycle delay before that queues status is

correctly shown on the respective output of the PAEn/PRn bus.

Status words can be selected on consecutive clock cycles, that is the status

word on the PAEn/PRn bus can change every RCLK cycle. Also, data can be

read out of a Queue on the same RCLK rising edge that a status word is being

selected, the only restriction being that a read queue selection and PAEn/PRn

status word selection cannot be made on the same RCLK cycle.

If 8 or less queues are setup then queues, Queue[0:7] have their PAE/PR

status output on PAE[0:7] constantly.

When the multi-queue devices are connected in expansion of more than one

device the PAEn/PRn busses of all devices are connected together, when

switching between status words of different devices the user must utilize the 3

most significant bits of the RDADD address bus (as well as the 2 LSB’s). These

3 MSb’s correspond to the device ID inputs, which are the static inputs, ID0, ID1

& ID2.

Please refer to Figure 62,

PAE

n - Direct Mode Status Word Selection

for timing information. Also refer to Table 5, Read Address Bus, RDADD.

PAEn – POLLED BUS

If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled

(looped) mode. In polled mode the PAEn/PRn bus automatically cycles through

the 4 status words within the device regardless of how many queues have been

setup in the part. Every rising edge of the RCLK causes the next status word

to be loaded on the PAEn/PRn bus. The device configured as the master (MAST

input tied HIGH), will take control of the PAEn/PRn after MRS goes LOW. For

the whole RCLK cycle that the first status word is on PAEn/PRn the ESYNC

(PAEn/PRn bus sync) output will be HIGH, for all other status words, this ESYNC

output will be LOW. This ESYNC output provides the user with a mark with which

they can synchronize to the PAEn/PRn bus, ESYNC is always HIGH for the

RCLK cycle that the first status word of a device is present on the PAEn/PRn

bus.

When devices are connected in expansion configuration, only one device

will be set as the Master (ID='000'), MAST input tied HIGH, all other devices

will have MAST tied LOW. The master device is the first device to take control

of the PAEn/PRn bus and will place its first status word on the bus on the rising

edge of RCLK after the MRS input goes LOW. For the next n RCLK cycles

(n=number of queues divided by 8 with n incrementing by one should there be

a remainder) the master device will maintain control of the PAEn/PRn bus and

cycle its status words through it, all other devices hold their PAEn/PRn outputs

in High-Impedance. When the master device has cycled all of its status words

it passes a token to the next device in the chain and that device assumes control

of the PAEn/PRn bus and then cycles its status words and so on, the PAEn/PRn

bus control token being passed on from device to device. This token passing

is done via the EXO outputs and EXI inputs of the devices (“PAE Expansion Out”

and “PAE Expansion In”). The EXO output of the master device connects to the

EXI of the second device in the chain and the EXO of the second connects to

the EXI of the third and so on. The final device in a chain has its EXO connected

to the EXI of the first device, so that once the PAEn/PRn bus has cycled through

all status words of all devices, control of the PAEn/PRn will pass to the master

device again and so on. The ESYNC of each respective device will operate

independently and simply indicate when that respective device has taken control

of the bus and is placing its first status word on to the PAEn/PRn bus.

When operating in single device mode the EXI input must be connected to

the EXO output of the same device. In single device mode a token is still required

to be passed into the device for accessing the PAEn bus.

PACKET READY FLAG

The 36-bit multi-queue flow-control device provides the user with a Packet

Ready feature. During a Master Reset Packet Mode is selected by PKT = HIGH.

The PR discrete flag, provides a packet ready status of the active queue selected

on the read port. A packet ready status is individually maintained on all queues;

however only the queue selected on the read port has its packet ready status

indicated on the PR output flag. A packet is available on the output for reading

when both PR and OR are asserted LOW. If less than a full packet is available,

the PR flag will be HIGH (packet not ready). In packet mode, no words can be

read from a queue until a complete packet has been written into that queue,

regardless of REN.

When packet mode is selected the Programmable Almost Empty bus, PAEn,

becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM =

LOW during a master reset), the PRn bus provides packet ready status in 8

queue increments. The PRn bus supports either Polled or Direct modes of

operation. The PRn mode of operation is configured through the Flag Mode

(FM) bit during a Master Reset.

When the multi-queue is configured for packet mode operation, the two most

significant bits of the 36-bit data bus are used as “packet markers”. On the write

port these are bits D34 (Transmit Start of Packet,) D35 (Transmit End of Packet)

and on the read port Q34, Q35. All four bits are monitored by the packet control

logic as data is written into and read out from the queues. The packet ready status

for individual queues is then determined by the packet ready logic.

On the write port D34 is used to “mark” the first word being written into the

selected queue as the “Transmit Start of Packet”, TSOP. To further clarify, when

the user requires a word being written to be marked as the start of a packet, the

TSOP input (D34) must be HIGH for the same WCLK rising edge as the word

that is written. The TSOP marker is stored in the queue along with the data it was

written in until the word is read out of the queue via the read port.

On the write port D35 is used to “mark” the last word of the packet currently

being written into the selected queue as the “Transmit End of Packet” TEOP.

When the user requires a word being written to be marked as the end of a packet,

the TEOP input must be HIGH for the same WCLK rising edge as the word that

is written in. The TEOP marker is stored in the queue along with the data it was

written in until the word is read out of the queue via the read port.

The packet ready logic monitors all start and end of packet markers both as

they enter respective queues via the write port and as they exit queues via the

read port. The multi-queue internal logic increments and decrements a packet

counter, which is provided for each queue. The functionality of the packet ready

logic provides status as to whether at least one full packet of data is available

within the selected queue. A partial packet in a queue is regarded as a packet

not ready and PR (active LOW) will be HIGH. In Packet mode, no words can

be read from a queue until at least one complete packet has been written into

the queue, regardless of REN. For example, if a TSOP has been written and

some number of words later a TEOP is written a full packet of data is deemed

to be available, and the PR flag and OR will go active LOW. Consequently if reads

begin from a queue that has only one complete packet and the RSOP is detected

on the output port as data is being read out, PR will go inactive HIGH. OR will

remain LOW indicating there is still valid data being read out of that queue until

the REOP is read. The user may proceed with the reading operation until the

current packet has been read out and no further complete packets are available.

If during that time another complete packet has been written into the queue and

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

BYTE A

BYTE BBYTE CBYTE D

D0/Q0

D35/Q35

TMOD1 (D33)

RMOD1 (Q33)

TMOD2 (D32)

RMOD2 (Q32) VALID BYTES

0 0 A, B, C, D

01A

1 0 A, B

1 1 A, B, C

D15/Q15

D23/Q23

D31/Q31

D34/Q34

D33/Q33

D32/Q32

MOD 2

MOD 1

SOP

EOP

D7/Q7

6716 drw19

TABLE 10 — PACKET MODE VALID BYTE FOR x36 BIT WORD CONFIGURATION

the PR flag will again gone active, then reads from the new packet may follow

after the current packet has been completely read out.

The packet counters therefore look for start of packet markers followed by end

of packet markers and regard data in between the TSOP and TEOP as a full

packet of data. The packet monitoring has no limitation as to how many packets

are written into a queue, the only constraint is the depth of the queue. Note, there

is a minimum allowable packet size of four words, inclusive of the TSOP marker

and TEOP marker.

The packet logic does expect a TSOP marker to be followed by a TEOP

marker.

If a second TSOP marker is written after a first, it is ignored and the logic

regards data between the first TSOP and the first subsequent TEOP as the full

packet. The same is true for TEOP; a second consecutive TEOP mark is ignored.

On the read side the user should regard a packet as being between the first

RSOP and the first subsequent REOP and disregard consecutive RSOP

markers and/or REOP markers. This is why a TEOP may be written twice, using

the second TEOP as the “filler” word.

As an example, the user may also wish to implement the use of an “Almost

End of Packet” (AEOP) marker. For example, the AEOP can be assigned to

data input bit D33. The purpose of this AEOP marker is to provide an indicator

that the end of packet is a fixed (known) number of reads away from the end

of packet. This is a useful feature when due to latencies within the system,

monitoring the REOP marker alone does not prevent “over reading” of the data

from the queue selected. For example, an AEOP marker set 4 writes before the

TEOP marker provides the device connected to the read port with and “almost

end of packet” indication 4 cycles before the end of packet.

The AEOP can be set any number of words before the end of packet

determined by user requirements or latencies involved in the system.

See Figure 55, Reading in Packet Mode during a Queue Change, Figure

57, Data Output (Receive) Packet Mode of Operation.

PACKET MODE – MODULO OPERATION

The internal packet ready control logic performs no operation on these

modulo bits, they are only informational bits that are passed through with the

respective data byte(s).

When utilizing the multi-queue flow-control device in packet mode, the user

may also want to consider the implementation of “Modulo” operation or “valid

byte marking”. Modulo operation may be useful when the packets being

transferred through a queue are in a specific byte arrangement even though

the data bus width is 36 bits. In Modulo operation the user can concatenate bytes

to form a specific data string through the multi-queue device. A possible scenario

is where a limited number of bytes are extracted from the packet for either

analysis or filtered for security protection. This will only occur when the first 36

bit word of a packet is written in and the last 36 bit word of packet is written in.

The modulo operation is a means by which the user can mark and identify specific

data within the Queue.

On the write port data input bits, D32 (transmit modulo bit 2, TMOD2) and D33

(transmit modulo bit 1, TMOD1) can be used as data markers. An example of

this could be to use D32 and D33 to code which bytes of a word are part of the

packet that is also being marked as the “Start of Marker” or “End of Marker”.

Conversely on the read port when reading out these marked words, data

outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo bit 1,

RMOD1) will pass on the byte validity information for that word. Refer to Table

10 for one example of how the modulo bits may be setup and used. See Figure

57, Data Output (Receive) Packet Mode of Operation.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

6716 drw20

35 0

NOTES:

1. A Start of Packet (SOP) and End of Packet (EOP) may not occur within a same word.

2. The x36 bit words locate SOP and EOP as follows;

a. bit 35 is EOP

b. bit 34 is SOP.

6716 drw21

17 0

32, 34 <15:0>

35,33 <31:16>

(even word)

(odd word)

NOTES:

1. In a 36 bit word to 18 bit word configuration the 36 bit word is converted to two (2)

18 bit words.

2. An SOP and EOP may not occur within a same word.

3. The x18 bit even words (0,2,4, etc.) contain demarcation bits 32 (ASOP) and 34

(SOP).

4. The x18 bit odd words (1,3,5, etc.) contain demarcation bits 33 (AEOP) and 35

(EOP).

6716 drw22

0 8

34 <7:0>

32 <15:8>

33 <23:16>

35 <31:24>

NOTES:

1. In a 36 bit word to 9 bit word configuration the 36 bit word is converted into four (4)

9 bit words.

2. An SOP and EOP may not occur within a same word.

3. The x9 bit words contain the demarcation bits as follows;

a. Bit 8 in Word “A” is the Start of Packet (SOP)

b. Bit 8 in Word “B” is the Almost Start of Packet (ASOP).

c. Bit 8 in Word “C” is the Almost End of Packet (AEOP).

d. Bit 8 in Word “D” is the End of Packet (EOP).

PACKET MODE DEMARCATION BITS

The IDT72P51339/72P51349/72P51359/72P51369 can be configured for

packet mode operation. In packet mode the IDT72P51339/72P51349/72P51359/

72P51369 provides the functionality to demarcate packets within a queue. The

demarcation functionality is only available in packet mode and is used to

generate the Packet Ready (PR) flag.

The demarcation of packets/information is accomplished with the demarcation

bits [35:32]. The demarcation bit assignments are; bit 35 End of Packet (EOP),

bit 34 Start of Packet (SOP), bit 33 Almost End of Packet (AEOP) and bit 32 Almost

Start of Packet (ASOP).

During packet mode bus matching, which is the ability to set the write interface

and read interface to independent word lengths (i.e. 9 bit word, 18 bit word, 36

bit word), the demarcation bits are located within their respective word length.

For example within a 36 bit to 36 bit word bus matching configuration bit 35 is

designated as the End of Packet (EOP) and bit 34 is Start of Packet (SOP). In

an 18 bit to 18 bit word bus matching configuration bit 17 is designated End of

Packet (EOP) and bit 16 is Start of Packet. The minimum packet word length

required by the IDT72P51339/72P51349/72P51359/72P51369 is four (4) of

the largest words specified within a bus matching configuration. Refer to Figure

27-35 for designated locations of the demarcation bits within a specific word

configuration.

Figure 27. 36bit to 36bit word configuration

Figure 28. 36bit to 18bit word configuration Figure 29. 36bit to 9bit word configuration

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

6716 drw23

35 34 33 32 0

<15:0>, 1

<15:0>

NOTES:

1. In a 18bit word to 36 bit word configuration two (2) eighteen bit words are concatenated to form one x36

bit word.

2. The x36 bit words contain demarcation bits as follows;

a. Bit 35 is End of Packet (EOP)

b. Bit 34 is Start of Packet (SOP).

c. Bit 33 Almost End of Packet (AEOP).

d. Bit 32 Almost Start of Packet (ASOP).

NOTES:

1. An SOP and EOP may not occur within a same word.

2. The x18 bit words contain the demarcation bits as follows;

a. Bit 17 is the End of Packet (EOP).

b. Bit 16 is the Start of Packet (SOP).

3. In this configuration there is no ASOP or AEOP demarcation bits.

6716 drw24

17 0 16

NOTES:

1. In a 18 bit word to 9 bit word configuration a single eighteen bit word is converted into two (2) nine bit words.

2. The x9 bit words contain demarcation bits as follows;

a . Bit 17 is End of Packet (EOP)

b . Bit 16 is Start of Packet (SOP).

3. An SOP and EOP may not occur within the same word.

4. In this configuration there is no ASOP or AEOP demarcation bits.

6716 drw24a

0 8

17 <7:0>

17 <15:8>

Figure 30. 18bit to 36bit word configuration

Figure 31. 18bit to 18bit word configuration

Figure 32. 18bit to 9bit word configuration

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

NOTES:

1. In a 9 bit word to 36 bit word configuration four (4), nine bit words are concatenated

to form one x36 bit word.

2. The x36 bit words contain demarcation bits as follows;

a. Bit 35 is End of Packet (EOP)

b. Bit 34 is Start of Packet (SOP).

c. Bit 33 Almost End of Packet (AEOP).

d. Bit 32 Almost Start of Packet (ASOP).

6716 drw25

35 34 33 32 0

<7:0>, 3

<7:0>, 2

<7:0>, 1

<7:0>

NOTES:

1. In a 9 bit word to 18 bit word configuration two (2), nine bit words are concatenated

to form one x18 bit word.

2. The x18 bit words contain demarcation bits as follows;

a. Bit 17 is End of Packet (EOP)

b. Bit 16 is Start of Packet (SOP).

3. An SOP and EOP may not occur within the same word.

6716 drw26

17 16

NOTES:

1. An SOP and EOP may not occur within the same word.

2. Bit 8 of the x9 bit even words (0,2,4, etc.) is checked for a Start of Packet (SOP).

3. Bit 8 of the x9bit odd words (1,3,5, etc.) is checked for End of Packet (EOP).

4. The minimum packet word length is 4 words.

6716 drw27

Figure 33. 9bit to 36bit word configuration

Figure 34. 9bit to 18bit word configuration

Figure 35. 9bit to 9bit word configuration

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

BM3 BM2 BM1 BM0 Write Port Read Port

0 0 0 0 x36 x36

0 0 0 1 x36 x18

0 0 1 0 x36 x9

0 0 1 1 x18 x36

0 1 0 1 x18 x18

0 1 1 0 x18 x9

0 1 0 0 x9 x36

0 1 1 1 x9 x18

1 0 0 1 x9 x9

TABLE 11 — BUS-MATCHING SET-UP

BUS MATCHING OPERATION

Bus Matching operation between the input port and output port is available.

During a master reset of the multi-queue the state of the three setup pins, BM

[3:0] (Bus Matching), determine the input and output port bus widths as shown

in Table 11, “Bus Matching Set-Up”. 9 bit words, 18 bit words and 36 bit words

can be written into and read from the queues. When writing to or reading from

the multi-queue in a bus matching mode, the device orders data in a “Little

Endian” format. See Figure 36, Bus Matching Byte Arrangement for details.

The Full flag and Almost Full flag operation is always based on writes and

reads of data widths determined by the write port width. For example, if the input

port is x36 and the output port is x9, then four data reads from a full queue will

be required to cause the full flag to go HIGH (queue not full). Conversely, the

Empty flag and Almost Empty flag operations are always based on writes and

reads of data widths determined by the read port. For example, if the input port

is x18 and the output port is x36, two write operations will be required to cause

the Empty flag (EF) of an empty queue to go HIGH (queue is not empty).

Note, that the input port serves all queues within a device, as does the output

port, therefore the input bus width to all queues is equal (determined by the input

port size) and the output bus width from all queues is equal (determined by the

output port size).

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

1st: Read from Queue

2nd: Read from Queue

3rd: Read from Queue

4th: Read from Queue

6716 drw28

Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0

(a) x36 INPUT to x36 OUTPUT

(b) x36 INPUT to x18 OUTPUT

Read from Queue

1st: Read from Queue

2nd: Read from Queue

BYTE ORDER ON OUTPUT PORT: Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0

Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0

1st: Write to Queue

2nd: Write to Queue

3rd: Write to Queue

4th: Write to Queue

BYTE ORDER ON INPUT PORT:

DCBA

(e) x9 INPUT to x36 OUTPUT

Read from Queue

BYTE ORDER ON OUTPUT PORT:

D35-D27 D26-D18 D17-D9 D8-D0

Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0

D35-D27 D26-D18 D17-D9 D8-D0

(d) x18 INPUT to x36 OUTPUT

Read from Queue

BYTE ORDER ON INPUT PORT:

D35-D27 D26-D18 D17-D9 D8-D0

1st: Write to Queue

2nd: Write to Queue

BYTE ORDER ON OUTPUT PORT:

D35-D27 D26-D18 D17-D9 D8-D0

ABC D

Write to Queue

BYTE ORDER ON INPUT PORT:

Figure 36. Bus-Matching Byte Arrangement

NOTE:

1. Please refer to Table 11, Bus-Matching set-up for details.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

PAF

tRSF

PAE

tRSF

tRSF LOGIC "1" if OE is LOW and device is Master

HIGH-Z if OE is HIGH or Device is Slave

LOGIC "1" if Master Device

HIGH-Z if Slave Device

LOGIC "0" if Master Device

HIGH-Z if Slave Device

LOGIC "0" if Master Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

PAFn

PAEn

PRn

6716 drw46

HIGH = Offset Value is 128

LOW = Offset value is 8

tRSS

FF/IR

tRSF

HIGH-Z if Slave Device

LOGIC "0" if Master Device

EF/OR

tRS

MRS

WEN

REN

tRSS

FSTR,

ESTR

tRSR

SENI

WADEN,

RADEN

tRSS

DFM

HIGH = Queue Programming

LOW = Serial Programming

tRSS

HIGH = Polled mode

LOW = Strobed (Direct)

ID0, ID1,

ID2

tRSS

HIGH = Packet Ready Mode

MAST

PKT

HIGH = Master Device

LOW = Slave Device

tRSS

QSEL [1:0] See Table 2, for setting the Queue Programming

tRSS

tRSF

HIGH-Z if Slave Device

LOGIC "0" if Master Device

NOTE:

1. OE can toggle during this period. Figure 37. Master Reset

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 38. Default Programming

DFM MRS

SENI SENO

MQ1

WCLK

Serial Enable

(must be tied

LOW)

WCLK

Default Mode

DFM = 1

Master Reset

Default Programming

Complete

DFM MRS

SENI SENO

MQ2

WCLK

DFM MRS

SENI SENO

MQn

WCLK

RCLK

WEN

WADEN

RADEN

6716 drw47

tWFF

tENS

tREF

tPCWQ

tQS tQH

tPCRQ

HIGH - Z

(Slave Device)

SENO

(MQ1)

tSENO

SENO

(MQ2)

SENO

(MQn)

tSENO

WCLK

MRS

1st Device in Chain

1st 2nd nth

3rd

2nd Device in Chain

1st 2nd nth

Final Device in Chain

1st 2nd nth

Programming

Complete

tSENO

Serial Port Connection for Default Programming

SI SO XSI SOXSI SOX

DFM

QSEL

[1:0]

NOTES:

1. This diagram illustrates multiple devices connected in expansion.

The SENO of the final device in a chain is the "programming complete" signal.

2. SENI of the first device in the chain must be held LOW

3. The SENO of a device should connect to the SENI of the next device in the chain.

The final device SENO is used to indicate programming complete.

4. When Default Programming is complete the SENO of the final device will go LOW.

5. SCLK is not used and can be tied LOW.

6. Programming of all devices must be complete (SENO of the final device is LOW),

before any write or read port operations can take place, this includes queue selections.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 39. Parallel Programming

RCLK

WEN

WADEN

RADEN

6716 drw47a

WFF

ENS

PCWQ

PCRQ

HIGH - Z

SENO

1st 2nd nth

3rd

SENO

WCLK

MRS

DFM

QSEL1

QSEL0

NOTES:

1. The SENO is the "programming complete" signal.

2. SENI must be held LOW.

3. When Parallel Programming is complete the SENO of the device will go LOW.

4. SCLK is not used and must be tied LOW.

5. Programming of the device must be complete (SENO of the device is LOW),

before any write or read port operations can take place, this includes queue selections.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 42. Serial Port Connection for Serial Programming

DFM MRS

SENI SENO

MQ1

SI SO

SCLK

DFM MRS

SENI SENO

MQ2

SI SO

SCLK

DFM MRS

SENI SENO

MQn

Master

ID=‘OOO’

SI SO

SCLK

Serial Enable

Serial Input

Serial Clock

Default Mode

DFM = 0

Master Reset

Serial Loading

Complete

6716 drw50

Figure 40. Queue Programming via Write Address Bus

WCLK

6716 drw48

ENS

WFF

WAF

PAF

WEN

WADEN

WRADD Qx

ENS

PAF

Active Bus

PAF-Qx

Figure 41. Queue Programming via Read Address Bus

RCLK

RDADD

tAH

tAS

tQH

tQS

RADEN

r-2 r-1 r r+3

r+1

tENS

REN

r+4

tENS

tREF

tRAE

PAE

6716 drw49

Active Bus

PAE-Qx(6)

tPAE

r+2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 43. Serial Programming

RCLK

WEN

6716 drw51

REF

PCSF

ENS

LOW

SENO

(MQ1)

WCLK

(MQ1)

MRS

SCLK

SENI

(MQ1)

RSR

SENO

1st 2nd nth 1st 2nd nth 1st 2nd nth

SENS

SENO

(MQ2)

SENO

(MQ8)

SDS

SDH

SENO

SCLK

SCKL

SCKH

Programming Complete

1st Device in Chain 2nd Device in Chain Final Device in Chain

SDO

SDOP

SENOP

LOW

NOTES:

1. SENI can be toggled during serial loading. Once serial programming of a device is complete, the SENI and SI inputs become transparent. SENI → SENO and SI → SO.

2. DFM is LOW and QSEL0 = HIGH, QSEL1 = HIGH during Master Reset to provide Serial programming mode, DF is don't care.

3. When SENO of the final device is LOW no further serial loads will be accepted.

4. n = 19+(Qx72); where Q is the number of queues required for the IDT72P51339/72P51349/72P51359/72P51369.

5. This diagram illustrates 8 devices in expansion.

6. Programming of all devices must be complete (SENO of the final device is LOW), before any write or read port operations can take place, this includes queue selections.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 44. Write Queue Select, Write Operation and Full Flag Operation

WCLK

tDH

Qy WD-2

tDH tDS

Qy WD

tDS tDH

tDS

tWFFtWFF

*G* *H*

tENH

*I* *J* *K*

tWFF

*L*

Qy WD-1

6716 drw52

tSKEW1

tQS tQH

Previous Q, Word, W

Qy, W

tAS tAH

*AA* *BB* *CC* *DD* *EE* *FF*

tENS

tAH

tAS

tQH

tQS

tDH

tDS

tWFF

*C* *D* *E* *F**B*

*GG*

tWFF

Qy, W

123

WADEN

tQH

tQS

tAH

tAS

WRADD

WEN

Din

Previous Q Status

*A*

RCLK

REN

RDADD

RADEN

Qout

No Writes

Queue Full

tENS

Qy, W

NOTE:

OE is active LOW.

Cycle:

*A* Queue, Qx is selected on the write port.

The FF flag is providing status of a previously selected queue, within the same device.

*AA* Queue, Qy is selected for read operations.

*B* The FF flag provides status of previous queue for 3 WCLK cycles.

*BB* Current word is kept on the output bus since REN is HIGH.

*C* The FF flag output updates to show the status of Qx, it is not full.

*CC* Word W+1 is read from the previous queue regardless of REN due to FWFT.

*D* Word, Wd is written into Qx. This causes Qx to go full.

*DD* The next available Word W0 of Qy is read out regardless of REN, 3 RCLK cycles after queue selection. This is FWFT operation.

*E* Queue, Qy is selected within the same device as Qx. A write to Qx cannot occur on this cycle because it is full, FF is LOW.

*EE* No reads occur, REN is HIGH. Word, W0 is read from Qy, this causes Qy to go “not full”, FF flag goes HIGH after time, tSKEW1 + tWFF. Note, if tSKEW1 is violated the time FF HIGH will be: tSKEW1 + WCLK + tWFF.

*F* Again, a write to Qx cannot occur on this cycle because it is full, FF is LOW.

*FF* Word, W1 is read from Qy.

*G* The FF flag updates after time tWFF to show that queue, Qy is not full.

*H* Word, Wd-2 is written into Qy.

*I* Word, Wd-1 is written into Qy.

*J* Word, Wd is written into Qy, this causes Qy to go full, FF goes LOW.

*K* A write to Qy cannot occur on this cycle because it is full, FF is LOW.

*L* Qy goes “not full” based on reading word W1 from Qy on cycle *FF*.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 45. Write Queue Select and Mark

WCLK

6716 drw53

ENS

*C* *D* *E* *F* *G* *H*

ENH

*I* *J* *K*

WADEN

WRADD

WEN

Din

*A* *B* *L*

D-1

ENS

ENH

NOTES:

1. Only 1 queue can be marked at any given time.

2. Marking a queue can only occur during a queue switch.

Cycle:

*A* Queue "X" is selected but not marked.

*E* Queue "Y" is selected and marked.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

6716 drw54

W1 W2 W3

WCLK

ENH

WEN

RCLK

SKEW1

REN

W1 Qy

W2 Qy W3 QyLast Word Read Out of Queue

Qout

REF

ENS

Figure 46. Write Operations in First Word Fall Through mode

NOTES:

1. Qy has previously been selected on both the write and read ports.

2. OE is LOW.

3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

WCLK

WADEN

WRADD D

(Device 1)

WEN

Din

HIGH-Z

RCLK

Addr=00111011

(Device 2)

RDADD

RADEN

*A*

Qout

6716 drw55

SKEW1

-Q

Word W

*CC* *DD*

Previous Q W

WFF

1 Q5

WFF

ENS

ENH

FFHZ

WFF

HIGH-Z

FFLZ

*F* *G* *H* *I* *J* *K*

FFLZ

*AA*

Previous Q W

X-1

*BB*

ENS

1 Q27

WFF

ENH

FFHZ

HIGH-Z

Addr=00100101

*C* *D* *E*

*B*

REN

ENS

ENH

Figure 47. Full Flag Timing in Expansion Configuration

Cycle:

*A* Queue, Q27 of device 1 is selected on the write port.

The FF flag of device 1 is in High-Impedance, the write port of device 2 was previously selected.

WEN is HIGH so no write occurs. The FF flag stays in High-Impedance for 3 WCLK cycles.

*AA* Queue, Q5 of device 1 is selected on the read port.

*BB* Word, Wx-1 is held on the outputs for 2 RCLK cycles after a read Queue switch.

*C* The FF flag of device 2 goes to High-Impedance and the FF flag of device 1 goes to Low-Impedance, logic HIGH indicating that D1 Q27 is not full.

WEN is HIGH so no write occurs.

*CC* Word, Wx is read from the previously selected queue.

*D* Word, Wd is written into Q27 of D1. This write operation causes Q27 to go full, FF goes LOW.

*DD* The first word from Q5 of D1 selected on cycle *AA* is read out. This read caused Q5 to go not full, therefore the FF flag will go HIGH after: tSKEW1 + tWFF.

Note if tSKEW1 is violated the time to FF flag HIGH is tSKEW1 + WLCK + tWFF.

*E* Queue, Q5 of device 1 is selected on the write port. No write occurs on this cycle.

*G* The FF flag updates to show the status of D1 Q5, it is not full, FF goes HIGH.

*H* Word, Wd is written into Q5 of D1. This causes the queue to go full, FF goes LOW.

*I* No write occurs regardless of WEN, the FF flag is LOW preventing writes. The FF flag goes HIGH due to the read from Q5 of D1 on cycle *CC*. (This read is not an enabled read).

*J* Queue, Q9 of device 2 is selected on the write port.

*K* The FF flag of device 1 goes to High-Impedance, this device was deselected on the write port on cycle *I*. The FF flag of device 2 goes to Low-Impedance and provides status of Q9 of D2.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 48. Read Queue Select, Read Operation (IDT mode)

RCLK

6716 drw56

tAH

tAS

tQH

tQS

tAtA

Wn+1

W0Q

tREF

*G* *H* *I* *J*

*K*

tAH

tAS

RDADD

tQH

tQS

RADEN

REN

tENS tENH tENS

QOUT

Wn-3 Q

Wn-2

Wn-1

*A* *B* *C* *D* *E* *F*

Wn-4 Q

Cycle:

*A* Word Wn-4 is on the Qout bus from the present selected queue.

*B* QP Wn-3 is read from the Qout bus.

*C* Reads are disabled, Wn-2 is placed on Qout bus.

*D* A new queue, QF is selected for read operations.

*E* Word Wn-2 from QP remains on Qout bus.

*F* QP Wn-1 is read.

*G* The next word available in present queue QP, Wn+1 is read from Qout bus.

*H* The next word available in the new queue, QF-W0 is placed on the output bus. A new queue, QG is selected for read operations. (This queue is an empty queue).

*I* Word, W1 is read from QF.

*J* Word, W2 is read from QF.

*K* Word W2 from QF remains on the output bus because QG is empty. W2 is the last word in QG.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 49. Read Queue Select, Read Operation (FWFT mode)

RCLK

6716 drw57

RDADD

RADEN

REN

ENS

ENH

ENS

OUT

n-3

n-2

Present Q, Q

n-1

n+1

n+2

REF

Present Q

*A* *B* *C* *D* *E* *F* *G* *H* *I*

*J*

Cycle:

*A* Word Wn-2 is read from a previously selected queue Qp on the read port.

*B* Wn-1 is read out.

*C* Reads are disabled, Wn-1 remains on the output bus.

*D* A new queue, QF is selected for read operations.

*E* Word Wn in Qp is read out.

*F* Wn+1 is read out.

*G* Wn+2 is read out.

*H* The next word available in the new queue, QF-W0 falls through to the output bus regardless of REN. A new queue, QG is selected for read operations.

*I* QF W1 is read out.

*J* Word W1 from QF remains on the output bus because QF is empty. The Output Ready Flag, OR goes HIGH to indicate that the current word is not valid, i.e. QF is empty.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 50. Read Queue Select and Mark (IDT mode)

RCLK

6716 drw58

*K*

RDADD

RADEN

REN

ENS

ENH

ENS

*A* *B* *C* *D* *E* *F* *G* *H* *I*

ENH

*J*

NOTES:

1. Only 1 queue can be marked at any given time.

2. Marking a queue can only occur during a queue switch.

Cycle:

*D* Queue "F" is selected but not marked.

*H* Queue "G" is selected and marked.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 51. Output Ready Flag Timing (In FWFT Mode)

REF

*H* *I* *J* *K*

Last Word

*D* *E* *F*

RCLK

RADEN

RDADD

ENS

REN

Qout

WCLK

WRADD

WADEN

Din

WEN

*A* *B* *C* *G*

PQ PQ PQPQ

6716 drw59

ENS

ENH

Cycle:

*A* Queue 30 is selected for read operations. It requires 4 clock cycles to switch queues.

*B* Reads are now enabled. A word from the previously selected queue will be read out.

*C* Another word from Present Queue (PQ) is read.

*D* Another word from PQ is read.

*E* Wd is read from Q30 of D1. This happens to be the last word of Q30, therefore OR goes HIGH to indicate that the data on the Qout is not valid (Q30 was read to empty).

Word, Wd remains on the output bus. Queue 15 is selected for read operations.

*F* The last word of Q30 remains on the Qout bus, OR is HIGH, indicating that this word has been previously read.

*G* The last word of queue 30 remains on the Qout bus.

*H* The last word of queue 30 remains on the Qout bus.

*I* The next word, available from the newly selected queue, Q15 is now read out. This will occur regardless of REN, due to FWFT mode.

*J* A word, is read from Q15.

*K* The OR flag stays LOW to indicate that Q15 has additional words available for reading.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 52. Read Queue Selection with Read Operations (IDT mode)

RCLK

6716 drw60

ENS

D+2

D+4

ENH

*M* *N* *O* *P* *Q*

D+3

123

D+2

*G* *H* *I* *J*

ENS

ENH

123

D+1

*K* *L*

RDADD

RADEN

REN

OUT

D+1

ENS

ENH

*A* *B* *C* *D* *E* *F*

Cycle:

*A* Word Wd+1 is read from the present selected queue, Qp.

*B* Reads are disabled, word Wd+1 remains on the output bus.

*C* A new queue, Qn is selected for read port operations. Qp WD+1 remains on Qout bus.

*D* REN is not asserted therefore no read operation occurs, Qp WD+1 remains on Qout bus.

*E* REN is not asserted therefore no read operation occurs, Qp WD+1 remains on Qout bus.

*F* REN is not asserted therefore no read operation occurs, Qp WD+1 remains on Qout bus.

*G* Word WD of Qn is read out.

*H* Word WD+1 of Qn is read out.

*I* Word WD+2 of Qn is read out.

*J* The queue, Qp is again selected.

*K* Current Word is kept on the output bus since REN is HIGH.

*L* Word Qn WD+2 reamins on the Qout bus.

*M* Word Qn WD+2 reamins on the Qout bus.

*N* Word Wd+2 is read from Qp.

*O* Word WD+3 for Qp is read out.

*P* Word WD+4 for Qp is read out.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 53. Read Queue Select, Read Operation and

Timing

RCLK

6716 drw61

*K* *L*

OHZ

REF

No Read

is Empty

*M*

ENS

REF

*E* *G* *H*

*F* *I*

ENH

ENS

*D*

RADEN

RDADD Q

Qout t

OLZ

REN

Previous Data in Output Register

*B*

*A* *C* *J*

NOTES:

1. The Output Ready flag, OR is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus will go to Low-Impedance after time tOLZ.

The data currently in the output register will be available on the output bus (Qout) after time tOE.

2. In expansion configuration the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled.

Cycle:

*A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty.

*B* No data will fall through on this cycle, the previous queue was read to empty.

*C* Previous data kept on output bus since there is no read operation.

*D* Previous data kept on output bus since there is no read operation.

*E* Word, W0 from QA is read out regardless of REN due to FWFT operation. The OR flag goes LOW indicating that Word W0 is valid.

*F* Reads are disabled therefore word, W0 of QA remains on the output bus.

*G* Reads are again enabled so word W1 is read from QA.

*H* Word W2 is read from QA.

*I* Queue, QB is selected on the read port. This queue is actually empty. Word, W3 is read from QA.

*J* Word, W4 is read from QA.

*K* Word W5 is read from QA.

*L* Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, tOHZ.

*M* Output Ready flag, OR goes HIGH to indicate that QB is empty. Data on the output port is no longer valid.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 54. Writing in Packet Mode during a Queue change

NOTES:

1. Minimum allowable packet size is four (4) 36 bit words or equivalent.

2. Maximum allowable packet size is the depth of the queue.

3. TSOP and TEOP may not be a "1" in the same word.

WCLK

WRADD

WADEN

Din

Data QA

TEOP QB

TEOP

TSOP QB

Data

WEN

TEOP

(D35)

TSOP

(D34)

Data

BCD

(1)

EFGH I J

(1)

6716 drw62

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 55. Reading in Packet Mode during a Queue change

RCLK

RDADD

RADEN

Qout

Data Q

REOP Q

RSOP Q

Data Q

Data

REN

REOP

(Q35)

RSOP

(Q34)

REOP

BCD EFGH I J K L

1212

6716 drw63

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

ENS

*A* *B*

ENH

First Word Data Word

*C*

WCLK

TSOP

(D34)

TEOP

(D35)

WEN

D0-D31

TAEOP

(D33)

ASOP

(D32)

6716 drw64

Data Word Data Word Last Word

Figure 56. Writing Demarcation Bits (Packet Mode)

NOTES:

1. Device is configured in packet mode.

2. REN is HIGH.

3. If tSKEW4 is violated PR may take one additional RCLK cycle.

4. PR will always go LOW on the same cycle or 1 cycle ahead of OR going LOW, (assuming the last word of the packet is the last word in the queue).

5. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

RSOP

(Q34)

REOP

(Q35)

tPR

tENS

REN

Q0-Q31 Q1Wo Q1Wn

Q1W1

AEOP

(Q33)

ASOP

(Q32)

RCLK

Q1Wn

-1

Q1Wn

-2

Q1Wn

-3

*A* *B* *D* *E*

6716 drw65

tREF

tAtAtA

Q1W2

*C*

Figure 57. Data Output (Receive) Packet Mode of Operation

NOTE:

1. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN.

2. The PR flag will go HIGH on cycle *C* regardless of REN.

3. The OR flag will go HIGH (preventing further reads), when the last complete packet has been read out. If there is a partial packet (an incomplete packet) in the queue the OR flag will remain HIGH until further writes have

completed the packet.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

WCLK

AFLZ

FFHZ

6716 drw66

WAF

*J*

ENS

D-m

WAF

ENH

*E* *G*

*F*

*D* *H*

WADEN

WRADD D

PAF

(Device 1)

WEN

Din

HIGH-Z

PAF

(Device 2)

*B*

*A* *C* *I*

Figure 58. Almost Full Flag Timing and Queue Switch

Figure 59. Almost Full Flag Timing

WCLK

WEN

PAF

RCLK

WAF

REN

6716 drw67

D - (m+1) words in Queue

(

2) D - m words in Queue D-(m+1) words

in Queue

WAF

ENH

ENS

SKEW2

ENH

ENS

CLKL

Cycle:

*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.

*B* No write occurs, WEN is HIGH.

*C* No write occurs, WEN is HIGH.

*D* No write occurs, WEN is HIGH.

*E* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.

*F* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.

*G* The PAF flag goes LOW based on the write 2 cycles earlier.

*H* No write occurs, WEN is HIGH.

*I* The PAF flag goes HIGH due to the queue switch to Q9.

NOTE:

1. The waveform shows the PAF flag operation when no queue switch occurs and a queue is selected on both the write and read ports is being written to then read

from at the almost full boundary.

2. Flag Latencies:

Assertion: 2*WCLK + tWAF

De-assertion: tSKEW2 + WCLK + tWAF

3. If tSKEW2 is violated there will be one extra WCLK cycle.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode)

Figure 61. Almost Empty Flag Timing

RCLK

AELZ

6716 drw68

OLZ

RAE

AEHZ

n+1

HIGH-Z

*F* *G*

*E* *H* *I*

RADEN

RDADD

PAE

(Device 1)

REN

Qout

HIGH-Z

PAE

(Device 2)

HIGH-Z

*B* *C*

*A* *D*

WCLK

ENH

CLKH

CLKL

WEN

PAE

RCLK

ENS

n+1 words in Queue

RAE

SKEW2

RAE

REN

6716 drw69

ENS

ENH

n+2 words in Queue n+1 words in Queue

Cycle:

*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.

*B* No read occurs, REN is HIGH.

*C* No read occurs, REN is HIGH.

*D* No read occurs, REN is HIGH

*E* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore

PAE will go LOW 2 RCLK cycles later.

*F* Q15 of device 1 is selected.

*G* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.

*H* Word, W0 is read from Q15 due to the FWFT operation.

*I* The PAE flag goes HIGH to show that Q15 is not almost empty.

NOTE:

1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read

from at the almost empty boundary.

Flag Latencies:

2. Assertion: 2*RCLK + tRAE

De-assertion: tSKEW2 + RCLK + tRAE

3. If tSKEW2 is violated there will be one extra RCLK cycle.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Figure 62.

PAE

n - Direct Mode - Status Word Selection

RCLK

STH

STS

001xxx10

6716 drw70

001xxx11

Device 1

Status Word 3

001xxx00

Device 1

Status Word 0

STS

STH

PAE

Device 1 Status Word 2

PAE

Device 1 Status Word 3

RDADD

ESTR

Device 1

Status Word 2

PAEn/

PRn

PAE

Device 1

Status Word

RADEN

ENH

ENS

ENH

ENS

Figure 63.

PAF

n - Direct Mode - Status Word Selection

WCLK

001xxx11

Device 1

Status Word 3

001xxx10

Device 1

Status Word 2

STS

STH

PAF

Device 1 Status Word 1

Device 1

Status Word

PAF

Device 1 Status Word 3

STH

STS

001xxx01

WRADD

FSTR

Device 1

Status Word 1

PAFn

6716 drw71

WADEN

ENH

ENS

ENH

ENS

NOTES:

1. Status words can be selected on consecutive cycles.

2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.

3. There is a latency of 2 RCLK for the PAEn bus to switch.

NOTES:

1. Status words can be selected on consecutive cycles.

2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.

3. There is a latency of 2 WCLK for the PAFn bus to switch.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

WCLK

Prev PAEn

RCLK

D5 SW 3

101 00011

tAH

tRAE

D5 SW 3

tPAEHZ

tPAEZL

xxxx xxx1

tSKEW3

xxxx xxx0

D5 SW 3

tSTH

tPAE

6716 drw72

tRAE

*DD* *EE* *GG*

*FF*

xxxx xxx0

D5 SW 3

tENH

tENS

D5 Q24

Wy+1

D5 Q24

Wy+3

D5 Q24

Wy+2

D5 Q24

Wa+1

D5 Q17

tAtA

tDH

D3Q8

D5Q24

011 01000

D4 SW 2

100 00100

*D* *E* *F* *G*

tQH

tQS

tAH

tAS tAH

tAS

tENH

tSTH

tSTS

tRAE

D5 Q24

status

ESTR

RDADD

101 11000

D5Q24

tAS

tAH

tAS

Previous value loaded on to PAE bus

RADEN

tQH

tQS

tSTS

Device 5 PAE

*AA* *BB*

D5 Q17 Status

Bus PAEnPrevious value loaded on to PAE bus

REN

Device 5 -Qn

D5 Q17

WEN

WADEN

FSTR

tAH

101 11000

tAS

WRADD D5Q24

*A* *B*

tQH

tQS

tENS

Device 5 PAEn

Wp+1

Writes to Previous Q

tDH

tDS tDH

*C*

*H*

Wp+2

*CC*

Wp+3

tDS tDS

Figure 64.

PAE

n - Direct Mode, Flag Operation

Cycle:

*A* Queue 24 of Device 5 is selected for write operations.

Word, Wp is written into the previously selected queue.

*AA* Queue 24 of Device 5 is selected for read operations.

A status word from another device has control of the PAEn bus.

The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.

*B* Word Wp+1 is written into the previously selected queue.

*BB* Current Word is kept on the output bus since REN is HIGH.

*C* Word Wp+2 is written into the previously selected queue.

*CC* Word Wa+1 of D5 Q17 is read due to FWFT.

*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,

tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).

*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.

Status word 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before

the PAEn bus changes to the new selection.

*E* Queue 8 of Device 3 is selected for write operations.

Word Wn+1 is written into Q24 of D5.

*EE* Word, Wy+1 is read from Q24 of D5.

*F* No writes occur.

*FF* Word, Wy+2 is read from Q24 of D5.

The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and status word 4 is placed onto the outputs. The device of the previously selected

status word now places its PAEn outputs into High-Impedance to prevent bus contention.

The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].

*G* Status word 3 of device 4 is selected on the write port for the PAFn bus.

*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.

The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

RCLK

*G*

D - M + 2

*I*

D0 Q31

D6 Q2

*F*

D0 Q31

111 00000

D7 SW 0

110 00010

*D* *E*

STH

STS

D6Q2

D-M+1

X +1

OLZ

REN

RADEN

ESTR

WRADD

000 11111

RDADD D0Q31

*A* *B*

000 00011

STH

STS

6716 drw73

0xxx xxxx

D0SW3

*BB* *CC* *DD* *EE* *FF*

PAFLZ

1xxx xxxx

D0SW3 D0SW3

PAF

0xxx xxxx

D0SW3 1xxx xxxx

D0SW3 D0SW3 0xxx xxxx

PAFHZ

HIGH-Z

PAFLZ

WAF

*AA*

Device 0 PAFn

Bus PAFnD

SW y

Prev.

PAFn

SW y

Device 0

PAF

Qout W

D0 quad3

FSTR

WCLK

SKEW3

D0 Q31

WEN

ENS

ENH

WADEN

Din

Word W

D0 Q31

y+1

D0 Q31

y+2

D0 Q31

*C*

*H*

HIGH - Z

*GG*

Figure 65.

PAF

n - Direct Mode, Flag Operation

Cycle:

*A* Queue 31 of device 0 is selected for read operations.

The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.

*AA* Status word 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected status word, Quad Y of device X.

*B* No read operation.

*BB* Queue 31 of device 0 is selected on the write port.

*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.

*CC* PAFn continues to show status of Quad4 D0.

The PAFn bus is updated with the status word selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.

The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.

*D* A new status word, Quad 0 of Device 7 is selected for the PAFn bus.

Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from

LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.

*DD* No write operation.

*E* No read operations occur, REN is HIGH.

*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.

The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.

Word, Wy is written into D0 Q31.

*F* Queue 2 of Device 6 is selected for read operations.

*FF* Word, Wy+1 is written into D0 Q31.

*G* Word, Wd-m+2 is read out due to FWFT operation.

*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.

Word, Wy+2 is written into D0 Q31.

*H* No read operation.

*I* Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

WCLK

6716 drw74

FSYNC

FSYNC0

(MASTER)

FXO0 /

FXI1

FXO

FSYNC

FSYNC1

(SLAVE)

FXO1 /

FXI2

FXO

FSYNC

FSYNC2

(SLAVE)

FXO2 /

FXI0

FXO

PAFn

PAF

FSYNC

D0SW1 D0SW2 D0SW3 D0SW4 D1SW1 D1SW2 D1SW3 D1SW4 D2SW1 D2SW2 D2SW3 D2SW4 D0SW1 D0SW2

Figure 66.

PAF

n Bus - Polled Mode

NOTE:

1. This diagram is based on 3 devices connected in expansion configuration.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

WRADD

WADEN

FSTR

PAFn

FSYNC

PAF

SCLK

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SO FXO EXO

WRADD

WADEN

FSTR

PAFn

FSYNC

PAF

SCLK

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SO FXO

EXO

SI FXI

EXI

WRADD

WADEN

WCLK

WEN

FSTR

PAFn

FSYNC

PAF

SCLK

RCLK

REN

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SENO FXO EXO

Q0-Q35

SI FXI

EXI

DEVICE

(Master, ID = ‘000')

Full Sync2 Empty Sync 2

Full Sync n Empty Sync n

SENO

SENI

DONE

6716 drw75

D0-D35

Q0-Q35

D0-D35

SENO

SENI

Write Queue Select

Full Strobe

Programmable Almost Full

Write Address

Full Sync1

Full Flag

Almost Full Flag

Serial Clock

Read Queue Select

Empty Strobe

Programmable Almost Empty

Read Address

Empty Sync 1

Empty/Output Ready Flag

Almost Empty Flag

DEVICE

PR Packet Reads

WCLK

WEN

RCLK

REN

SI FXI EXI

Data Bus

Write Clock

Write Enable

Output Data Bus

Read Clock

Read Enable

Serial Programming Data Input

D0-D35 Q0-Q35

SENI

Serial Enable

WCS RCS

WCLK

WEN

RCLK

REN

WCS RCS

Figure 67. Expansion using ID codes

NOTES:

1 . If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO

outputs are DNC (Do Not Connect).

2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

WRADD

WADEN

WCLK

WEN

FSTR

PAFn

FSYNC

PAF

SCLK

RCLK

REN

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SO FXO EXO

SI FXI EXI

WRADD

WADEN

WCLK

WEN

FSTR

PAFn

FSYNC

PAF

SCLK

RCLK

REN

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SO FXO EXO

SI FXI EXI

WRADD

WADEN

WCLK

WEN

FSTR

PAFn

FSYNC

PAF

SCLK

RCLK

REN

ESTR

PAEn

ESYNC

PAE

RDADD

RADEN

SENO FXO EXO

Q0-Q35

SI FXI EXI

Data Bus

Write Clock

Write Enable

Write Queue Select

Full Strobe

Programmable Almost Full

Write Address

Full Sync1

Full Flag

Almost Full Flag

Serial Clock

Output Data Bus

Read Clock

Read Enable

Read Queue Select

Empty Strobe

Programmable Almost Empty

Read Address

Empty Sync 1

Empty/Output Ready Flag

Almost Empty Flag

Serial Programming Data Input

SLAVE

DEVICE

Full Sync2 Empty Sync 2

Full Sync n Empty Sync n

SENO

SENI

DONE

6716 drw75a

D0-D35

Q0-Q35

D0-D35

D0-D35 Q0-Q35

SENI

PR Packet Reads

Serial Enable

SENO

SENI

WCS

WCS1

WCS

WCS2

WCS

WCS0

RCS RCS1

RCS RCS2

RCS RCS0

ID = 001

SLAVE

DEVICE

ID = 010

MASTER

DEVICE

ID = 000

Figure 68. Expansion using

WCS

RCS

NOTES:

1 . If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO

outputs are DNC (Do Not Connect).

2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

RCLK

REN

Qout1

AEBCD FGHIJ

Q1_A Q1_B Q1_C

Q2_A

Q1_D

Q2_B

Q3_C

Q1_E

Q1_A Q1_B Q1_C Q1_D Q1_EQ2_A Q2_B Q3_C

RCS1

RCS2

Qout2

Qout3

RCS3

Q_Bus

ENH

ENS

ENH

ENS

ENH

ENS

ENH

ENS

ENH

ENS

ENH

ENS

ENH

6716 drwA

Figure 69. Expansion Connection Read Chip Select (

RCS

)

NOTE:

1. RCS signals are mutually exclusive, (i.e.. only one RCS signal can be asserted (low) at a time).

AEBCD FGHIJ

Device 2Device 1 Device 1 Device 2Device 1 Device 3 Device 1

No writeNo write

WCLK

WEN

WCS1

WCS2

Din

WCS3

6716 drwB

ENH

ENS

ENH

ENS

ENH

ENS

ENH

ENS

ENH

ENS

Figure 70. Expansion Connection Write Chip Select (

WCS

)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

TAP

Cont-

roller

Mux

DeviceID Reg.

Boundary Scan Reg.

Bypass Reg.

clkDR, ShiftDR

UpdateDR

TDO

TDI

TMS

TCLK

TRST

clklR, ShiftlR

UpdatelR

Instruction Register

Instruction Decode

Control Signals

6716 drw76

JTAG INTERFACE

Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to

support the JTAG boundary scan interface. The IDT72P51339/72P51349/

72P51359/72P51369 incorporates the necessary tap controller and modified

pad cells to implement the JTAG facility.

Note that IDT provides appropriate Boundary Scan Description Language

program files for these devices.

The Standard JTAG interface consists of four basic elements:

••

•Test Access Port (TAP)

••

•TAP controller

••

•Instruction Register (IR)

••

•Data Register Port (DR)

The following sections provide a brief description of each element. For a

complete description refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

The Figure below shows the standard Boundary-Scan Architecture

Figure 71. Boundary Scan Architecture

TEST ACCESS PORT (TAP)

The Tap interface is a general-purpose port that provides access to the

internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)

and one output port (TDO).

THE TAP CONTROLLER

The Tap controller is a synchronous finite state machine that responds to

TMS and TCLK signals to generate clock and control signals to the Instruction

and Data Registers for capture and update of data.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

Test-Logic

Reset

Run-Test/

Idle

Select-

DR-Scan

Select-

IR-Scan

111

Capture-IR

Capture-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Exit1-IR

Exit2-IR

Update-IR

6716 drw77

Shift-DR

Shift-IR

Pause-IR

Input = TMS

Figure 72. TAP Controller State Diagram

NOTES:

1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.

2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).

3. TAP controller must be reset before normal Queue operations can begin.

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1) for the full state diagram.

All state transitions within the TAP controller occur at the rising edge of the

TCLK pulse. The TMS signal level (0 or 1) determines the state progression

that occurs on each TCLK rising edge. The TAP controller takes precedence

over the Queue and must be reset after power up of the device. See TRST

description for more details on TAP controller reset.

Test-Logic-Reset All test logic is disabled in this controller state enabling

the normal operation of the IC. The TAP controller state machine is designed

in such a way that, no matter what the initial state of the controller is, the Test-

Logic-Reset state can be entered by holding TMS at high and pulsing TCK five

times. This is the reason why the Test Reset (TRST) pin is optional.

Run-Test-Idle In this controller state, the test logic in the IC is active only if

certain instructions are present. For example, if an instruction activates the self

test, then it will be executed when the controller enters this state. The test logic

in the IC is idles otherwise.

Select-DR-Scan This is a controller state where the decision to enter the

Data Path or the Select-IR-Scan state is made.

Select-IR-Scan This is a controller state where the decision to enter the

Instruction Path is made. The Controller can return to the Test-Logic-Reset state

other wise.

Capture-IR In this controller state, the shift register bank in the Instruction

last two significant bits are always required to be “01”.

Shift-IR In this controller state, the instruction register gets connected

between TDI and TDO, and the captured pattern gets shifted on each rising edge

of TCK. The instruction available on the TDI pin is also shifted in to the instruction

Exit1-IR This is a controller state where a decision to enter either the Pause-

IR state or Update-IR state is made.

Pause-IR This state is provided in order to allow the shifting of instruction

Exit2-DR This is a controller state where a decision to enter either the Shift-

IR state or Update-IR state is made.

Update-IR In this controller state, the instruction in the instruction register is

latched in to the latch bank of the Instruction Register on every falling edge of

TCK. This instruction also becomes the current instruction once it is latched.

Capture-DR In this controller state, the data is parallel loaded in to the data

registers selected by the current instruction on the rising edge of TCK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These

controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and

Update-IR states in the Instruction path.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

THE INSTRUCTION REGISTER

The Instruction register allows an instruction to be shifted in serially into the

processor at the rising edge of TCLK.

The Instruction is used to select the test to be performed, or the test data

at the completion of the shifting process when the TAP controller is at Update-

IR state.

The instruction register must contain 4 bit instruction register-based cells

which can hold instruction data. These mandatory cells are located nearest the

serial outputs they are the least significant bits.

TEST DATA REGISTER

The Test Data register contains three test data registers: the Bypass, the

Boundary Scan register and Device ID register.

These registers are connected in parallel between a common serial input

and a common serial data output.

The following sections provide a brief description of each element. For a

complete description, refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

TEST BYPASS REGISTER

The register is used to allow test data to flow through the device from TDI

to TDO. It contains a single stage shift register for a minimum length in serial path.

When the bypass register is selected by an instruction, the shift register stage

is set to a logic zero on the rising edge of TCLK when the TAP controller is in

the Capture-DR state.

The operation of the bypass register should not have any effect on the

operation of the device in response to the BYPASS instruction.

THE BOUNDARY-SCAN REGISTER

The Boundary Scan Register allows serial data TDI be loaded in to or read

out of the processor input/output ports. The Boundary Scan Register is a part

of the IEEE 1149.1-1990 Standard JTAG Implementation.

THE DEVICE IDENTIFICATION REGISTER

The Device Identification Register is a Read Only 32-bit register used to

specify the manufacturer, part number and version of the processor to be

determined through the TAP in response to the IDCODE instruction.

IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is

dropped in the 11-bit Manufacturer ID field.

For the IDT72P51339/72P51349/72P51359/72P51369, the Part Number

field contains the following values:

Device Part# Field (HEX)

IDT72P51339 0474

IDT72P51349 0475

IDT72P51359 0476

IDT72P51369 0477.

JTAG DEVICE IDENTIFICATION REGISTER

31(MSb) 28 27 12 11 1 0(LSB)

V ersion (4 bits) Part Number (16-bit) Manufacturer ID (1 1-bit)

0X0 0X33 1

JTAG INSTRUCTION REGISTER

The Instruction register allows instruction to be serially input into the device

when the TAP controller is in the Shift-IR state. The instruction is decoded to

perform the following:

••

•Select test data registers that may operate while the instruction is

current. The other test data registers should not interfere with chip

operation and the selected data register.

••

•Define the serial test data register path that is used to shift data between

TDI and TDO during data register scanning.

The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode

16 different possible instructions. Instructions are decoded as follows.

JTAG INSTRUCTION REGISTER DECODING

Hex Instruction Function

Value

00 EXTEST Select Boundary Scan Register

01 SAMPLE/PRELOAD Select Boundary Scan Register

02 IDCODE Select Chip Identification data register

03 HIGH-IMPEDANCE JTAG

0F BYPASS Select Bypass Register

The following sections provide a brief description of each instruction. For

a complete description refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

EXTEST

The required EXTEST instruction places the IC into an external boundary-

test mode and selects the boundary-scan register to be connected between TDI

and TDO. During this instruction, the boundary-scan register is accessed to

drive test data off-chip via the boundary outputs and receive test data off-chip

via the boundary inputs. As such, the EXTEST instruction is the workhorse of

IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts

and of logic cluster function.

IDCODE

The optional IDCODE instruction allows the IC to remain in its functional mode

and selects the optional device identification register to be connected between

TDI and TDO. The device identification register is a 32-bit shift register

containing information regarding the IC manufacturer, device type, and version

code. Accessing the device identification register does not interfere with the

operation of the IC. Also, access to the device identification register should be

immediately available, via a TAP data-scan operation, after power-up of the

IC or after the TAP has been reset using the optional TRST pin or by otherwise

moving to the Test-Logic-Reset state.

SAMPLE/PRELOAD

The required SAMPLE/PRELOAD instruction allows the IC to remain in a

normal functional mode and selects the boundary-scan register to be connected

between TDI and TDO. During this instruction, the boundary-scan register can

be accessed via a date scan operation, to take a sample of the functional data

entering and leaving the IC. This instruction is also used to preload test data

into the boundary-scan register before loading an EXTEST instruction.

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AUGUST 4, 2005

HIGH-IMPEDANCE

The optional High-Impedance instruction sets all outputs (including two-state

as well as three-state types) of an IC to a disabled (high-impedance) state and

selects the one-bit bypass register to be connected between TDI and TDO.

During this instruction, data can be shifted through the bypass register from TDI

to TDO without affecting the condition of the IC outputs.

BYPASS

The required BYPASS instruction allows the IC to remain in a normal

functional mode and selects the one-bit bypass register to be connected

between TDI and TDO. The BYPASS instruction allows serial data to be

transferred through the IC from TDI to TDO without affecting the operation of

the IC.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES

(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

AUGUST 4, 2005

TDO

TDI/

TMS

TCK

TRST

Notes to diagram:

t1 =

TCKLOW

t2 =

TCKHIGH

t3 =

TCKFALL

t4 = t

TCKRISE

t5 =

tRST

(reset pulse width)

t6 = tRSR (reset recovery)

6716 drw78

t1t2

TCK

Figure 73. Standard JTAG Timing

SYSTEM INTERFACE PARAMETERS

Parameter Symbol Test

Conditions Min. Max. Units

JTAG Clock Input Period tTCK - 100 - ns

JTAG Clock HIGH tTCKHIGH -40-ns

JTAG Clock Low tTCKLOW -40-ns

JTAG Clock Rise Time tTCKRISE --5

(1) ns

JTAG Clock Fall Time tTCKFALL --5

(1) ns

JTAG Reset tRST -50-ns

JTAG Reset Recovery tRSR -50-ns

JTAG

AC ELECTRICAL CHARACTERISTICS

(VDD = 2.5V ± 5%; Tcase = 0°C to +85°C)

IDT72P51339

IDT72P51349

IDT72P51359

IDT72P51369

Parameter Symbol Test Conditions Min. Max. Units

Data Output tDO(1) -20ns

Data Output Hold tDOH(1) 0-ns

Data Input tDS trise=3ns 10 - ns

tDH tfall=3ns 10 -

NOTE:

1. 50pf loading on external output signals. NOTE:

1. Guaranteed by design.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1533

San Jose, CA 95138 fax: 408-284-2775 email: Flow-Controlhelp@idt.com

www.idt.com

Plastic Ball Grid Array (PBGA, BB256-1)

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Low Power

6716 drw79

Commercial Only

Commercial and Industrial

IDT XXXXX

Device Type

Power

Speed

Package

Process /

Temperature

Range

BLANK

(1)

72P51339 589,824 bits  1.8V Multi-Queue Flow-Control Device

72P51349 1,179,648 bits  1.8V Multi-Queue Flow-Control Device

72P51359 2,359,296 bits  1.8V Multi-Queue Flow-Control Device

72P51369 4,718,592 bits  1.8V Multi-Queue Flow-Control Device

Clock Cycle Time (t

CLK

)

Speed in Nanoseconds

Green

ORDERING INFORMATION

NOTES:

1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.

2. Green parts are available. For specific speeds contact your sales office.

DATASHEET DOCUMENT HISTORY

02/04/2005 pg. 11.

08/01/2005 pgs. 1, 3, 7, 9, 11, 13, 15, 17, 18, 20, 21, 25-28, 30-32, 45, 54-56, 58-66, 73, 74, 78, 80 and 87.