Rev 1.01 – November 2006 www.enpirion.com
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ENPIRION
EN5310
1A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inducto
r
RoHS Compliant
Description
The EN5310 is a Power System on a Chip DC-
DC converter. It is specifically designed to meet
the precise voltage and fast transient
requirements of present and future high-
performance, low-power processor, DSP, FPGA,
memory boards and system level applications in
a distributed power architecture. Advanced circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver high-
quality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
only three external components that include
small value input and output ceramic capacitors
and a soft-start capacitor.
The EN5310 significantly helps in system design
and productivity by offering greatly simplified
board design, layout and manufacturing
requirements. In addition, a reduction in the
number of vendors required for the complete
power solution helps to enable an overall system
cost savings.
Typical Application Circuit
VID Output
Voltage Select
VOUT
VIN
VSENSE
22µF
10µF
15nF
VOUT
VS0
VS1
VS2
POK
PGNDAGND
SS
PVIN
AVIN
Features
• 1000mA output current capacity
• External inductor is NOT required
• RoHS compliant, MSL3 rated to 260°C
• 5MHz operating frequency
• More than 90% efficient
• VOUT accuracy of 2% over line, load and
temperature
• 1/2 the board area of discrete component
solutions
• Very fast transient response
• All high speed switching signals contained
inside the part
• Wide input voltage range of 2.375V to 5.5V
• Digital voltage selector with options for
common output voltages from 0.8V to 3.3V
• External divider option for programming
output voltages from 0.9V to 4.0V
• Output enable pin and Power OK signal
• Programmable soft-start time
• Programmable over-current protection
• Thermal shutdown, short circuit, over-voltage
and under-voltage protection
Applications
• VOIP phones, video telephones
• Broadband, networking, LAN/WAN, optical
telecommunications equipment
• Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
• Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V rails
Ordering Information
Part Number Temp Rating
(°C) Package
EN5310DC-T 0 to 70 36-pin DFN T&R
EN5310DI-T -40 to +85 36-pin DFN T&R
EN5310DC-E DFN Evaluation Board
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Pin Configuration
This diagram is a top-view of the component and represents the on-board layout requirements
for the landing pads and thermal connection points. Specific dimensions for the pads are
presented on page 10. Pin 1 of the device is signified by the white dot marked on the top of the
device.
Block Diagram
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Typical Efficiency
VIN = 3.3V and VOUT = 2.5V
40%
50%
60%
70%
80%
90%
100%
0 200 400 600 800 1000 1200
Ou tp u t Cu r ren t (mA)
Absolute Maximum Ratings
CAUTION: Stresses in excess of the absolute maximum ratings can cause permanent damage to the
device. Exposure to absolute maximum ratings for extended periods can adversely affect device
reliability.
PARAMETER SYMBOL MIN MAX UNITS
Input Supply Voltage VIN -0.5 6.5 V
Input Voltage – Enable -0.5 VIN V
Input Voltage – VS0, VS1 & VS2 (Note 1) -0.5 2.8 V
Storage Temperature Range TSTG -65 150 °C
Operating Junction Temperature TJ 150 °C
MSL per JEDEC J-STD-020A Level 3 260 °C
ESD Rating (based on Human Body Model) 2000 V
NOTES:
1. VS0, VS1 and VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as
required.
Thermal Characteristics
PARAMETER SYMBOL TYPICAL UNITS
Thermal Resistance: Junction to Ambient (0 LFM)
(Note 2) θJA 36 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 6 °C/W
NOTES:
2. Based on a four-layer board and proper thermal design.
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Electrical Characteristics
NOTE: VIN=3.3V and over operating temperature range unless otherwise noted. Typical values are at
TA = 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input
Voltage VIN 2.375 5.5 V
Quiescent Supply
Current IQ
No switching, AVIN = 3.3V,
PVIN = 3.3V, ENABLE=0V 15 mA
No-Load Operating
Current INL
Includes PWM, gate drive and
inductor ripple current. 35 mA
Switching
Frequency FOSC 5 MHz
Thermal Overload
Trip Point TJ 160 °C
VOUT
Range VOUT Using external voltage divider 0.9 V
Accuracy VOUT Over line, load and temperature 2.0 %
Line Regulation VOUT VIN = 2.5 to 5.0 volts 3 mV
Load Regulation VOUT ILOAD = 0 to 1A 3 mV
VOUT TA= 0 to 70ºC +0.25
-0.45 %
Temperature
Regulation VOUT TA= -40 to 85ºC + 0.65
-0.55 %
Transient Response (IOUT = 0% to 100% or 100% to 0% of Rated Load)
Peak Deviation VOUT VIN = 5V, 1.2V < VOUT < 3.3V 2 5 %
Output Voltage Ripple
Peak-to-peak VOUT-PP
VIN = 5.0V, VOUT = 1.2V, IOUT = 1A,
COUT = 20uF, 2 x 10µF X5R or X7R
ceramic capacitors
12 mV
Maximum Continuous Output Current (Note 3)
Output Current IOUT 1000 mA
Enable Operation
Disable Threshold VDISABLE
Max voltage to ensure the converter
is disabled 0.8 V
Enable Threshold VENABLE
Min voltage to ensure the converter
is enabled 1.8 V
Power OK Operation
POK low voltage VPOK IPOK = 1mA 0.4 V
Max POK Voltage VPOK Supply voltage applied to POK 5.5 V
NOTES:
3. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
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Pin Descriptions
PIN NAME FUNCTION
1 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
2 XFB
External feedback voltage input. Option for programming the output voltage with a
resistor divider on VOUT.
3 VSENSE
Remote voltage sense input. Connect this pin to the load voltage at the point to be
regulated.
4 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
5 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
6 ENABLE Enable input. An input high enables operation. An input low disables operation.
7 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
8 XOV
Over-Voltage set-point input. When using an external voltage divider and the XFB pin.
When VS0, VS1 and VS2 are left OPEN or pulled high, an additional voltage divider
separate from the XFB pin is required to set the OVP set-point. In this mode, the OVP
function is disabled if this voltage divider is not present.
9
10
11
12
PGND Power ground for the power stage circuits.
13
14
15
16
17
18
VOUT Voltage and power output.
19 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
20
21
22
23
PGND Power ground for the power stage circuits.
24 NC NO CONNECT – Do not electrically connect this pin to PCB. See Note 4.
25
26
27
28
PVIN Power voltage input for the power stage circuits.
29 VS2 Voltage select line 2 input. See Table 1.
30 ROCP Over-Current trip point adjust input. Used for adjusting the OCP trip point.
31 VS1 Voltage select line 1 input. See Table 1.
32 AVIN Analog voltage input for the controller circuits.
33 AGND Analog ground for the controller circuits.
34 VS0 Voltage select line 0 input. See Table 1.
35 POK Power OK is an open drain transistor for power system state indication.
36 SS Soft-Start node. A capacitor is connected between this pin and AGND.
NOTES:
4. This pin is used for engineering test purposes and reserved for future use. Solder, but do not electrically connect
this pin to the PCB.
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Theory of Operation
Synchronous Buck Converter
The EN5310 is a synchronous, pin
programmable power supply with integrated
power MOSFET switches and inductor. The
nominal input voltage range is 2.5-5.0V. The
output can be set to common voltages by
connecting appropriate combinations of 3 voltage
selection pins to ground. If different voltage
levels are required, provision is also made to
allow external programming. The feedback
control loop is voltage-mode and the part uses a
low-noise PWM topology. Up to 1A of output
current can be drawn from this converter. The
5MHz operating frequency enables the use of
small-size output capacitors.
The power supply also has protection features
such as:
• Programmable over-current protection (to
protect the IC from excessive load current)
• Thermal shutdown (to protect the
converter from getting too hot)
• Over-voltage protection that stops the
PWM switching and turns on the lower N-
MOSFET at 120% of the programmed
output voltage in order to protect the load
from an OV condition.
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Additional features include:
• Soft-start circuit, limiting the in-rush
current when the converter is powered up.
• Power good circuit indicating whether the
output voltage is within 90%-120% of the
programmed voltage.
Output Voltage Programming
The EN5310 output voltage is programmed using
one of two methods. Common output voltages
are achieved by tying one or more of the three
Voltage Select pins (VS0, VS1 & VS2) to ground
(see Table 1). If all three are left floating, the
output voltage and over voltage thresholds are
determined by the voltages presented at the XFB
and XOV pins respectively. These voltages
should be set by way of resistor dividers between
VOUT to GND with the midpoint going to XFB and
XOV.
Use an appropriate resistor ratio such that the
desired output voltage across the resistor pair
causes the XFB pin to be 0.8V at the nominal
set-point. It is recommended that the resistor
values used should be in the 20K-40K range.
Contact Enpirion Applications Support for more
specific information. If Over-Voltage protection is
required, the output of a second divider to XOV
should be set such that 0.96V is present at the
desired trip point. By design, if both resistor
dividers are the same, the OV trip-point will be
20% above the nominal output voltage.
XFB
22µF
10µF
15 nF
VOUT
POK
PGNDAGND
SS
PVIN
AVIN
XOV
VOUT
VIN
Table 1: Output Voltage Select Table
VS2* VS1* VS0* Output Voltage
0 0 0 3.3V
0 0 1 2.5V
0 1 0 1.8V
0 1 1 1.5V
1 0 0 1.25V
1 0 1 1.2V
1 1 0 0.8V**
1 1 1 User Selectable
** 0.8V ref only, not guaranteed performance
*NOTE: The VS0, VS1 and VS2 pins are defaulted to a ‘1’
with an internal pull-up resistor. Only connect these pins to
AGND if a ‘0’ is required. If a ‘1’ is required, then leave the
pin floating.
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Capacitor Selection
The EN5310 needs about 10-20uF of input
capacitance. Low-cost, low-ESR ceramic
capacitors must be used as input capacitors for
this converter and it is required that they be rated
X5R or X7R. In some applications, lower value
capacitors are needed in parallel with the larger,
lossy capacitors in order to provide high
frequency decoupling.
The EN5310 has been optimized for use with
about 20µF of ceramic output capacitance. It is
required that these be low-cost, low-ESR,
ceramic capacitors rated X5R or X7R. (See the
Enpirion application note on ripple comparison
for optimum selection of number and value of
these capacitors based on ripple requirements.)
In order to eliminate high-frequency switching
spikes on the output ripple, usually a low-value,
low-ESR ceramic capacitor is used in parallel
with the larger capacitors right at the load.
Enable Operation
The ENABLE pin provides a means to shut down
the power FET switching or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation.
Soft-Start Operation
The SS pin in conjunction with a small capacitor
between this pin and AGND provides the soft
start function to limit the in-rush current during
start-up. During start-up of the converter the
reference voltage to the error amplifier is
gradually increased to its final level by an internal
current source of typically 10uA. The whole soft-
start procedure is designed to take 1ms - 3ms
with a 15-30nF soft start capacitor, but can be
programmed by capacitor selection using the
following equation:
Rise Time: TR = Css*80k
POK Operation
The POK signal is an open drain signal from the
converter indicating the output voltage is within
the specified range. The POK signal will be a
logic high when the output voltage is within 90% -
120% of the programmed output voltage. If the
output voltage goes outside of this range, the
POK signal will be a logic low until the output
voltage has returned to within this range. In the
event of an over-voltage condition the POK
signal will go low and will remain in this condition
until the output voltage has dropped to 95% of
the programmed output voltage before returning
to the high state (see also Over Voltage
Protection)
Over-Current Protection
The cycle-by-cycle current limit function is
achieved by sensing the current flowing through
the sense P-MOSFET and a signal generated by
a differential amplifier with a preset over-current
threshold. During a particular cycle, if the over-
current threshold is exceeded, the power P-
MOSFET is turned off and the power N-MOSFET
is turned on to protect the P-MOSFET. If the
over-current condition is removed, the over-
current protection circuit will enable the PWM
operation. If the over-current condition persists,
the converter will eventually go through a full
soft-start cycle. This circuit is designed to provide
high noise immunity.
It is possible to adjust the over-current set point
by connecting a resistor between ROCP and
GND
(increase the trip point) or PVIN (decrease the
trip point). The voltage at the ROCP pin is
designed to be 0.8V. (see application note for
details)
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
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POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation once
the Junction temperature exceeds approximately
160ºC. Once the junction temperature drops by
approx 25ºC, the converter will re-start with a
normal soft-start.
Low Input Voltage Operation
Circuitry is provided to ensure that when the
input voltage is below the specified voltage
range, the operation of the converter is controlled
and predictable. Circuits for hysteresis, input de-
glitch and output leading edge blanking are
included to ensure high noise immunity and
prevent false tripping.
Compensation
The EN5310 is internally compensated through
the use of a type 3 compensation network and is
optimized for use with about 20µF of output
capacitance and will provide excellent loop
bandwidth and transient performance for most
applications. (See the section on Capacitor
Selection for details on recommended capacitor
types.) In some cases modifications to the
compensation may be required. For more
information, contact Enpirion Applications
Engineering support.
Layout Considerations
The EN5310 Layout Guidelines application note
provides more details on specific layout
recommendations for this part. The following are
general layout guidelines to consider.
The CMOS chip inside the EN5310 has two
grounds: AGND for the controller, and PGND for
the power stage. These two grounds need to be
connected outside the package at one point
through a low-impedance trace. The connection
should be made such that the impedance
between the connection point and the AGND pad
on the package is minimized. Since the internal
voltage sensing circuit is based on AGND, the
connection of the two grounds should also be
made such that the best voltage regulation can
be achieved. The soft-start capacitor, the voltage
programming resistors, and any other external
control component should be tied to AGND.
The placement of the input decoupling capacitors
between PVIN and PGND is very critical. These
components should be placed such that they
have the lowest inductance traces to PVIN and
PGND.
There are two thermal pads underneath the
device. The centrally located pad is PGND, and,
depending on the number of layers of the PC
board, it needs to be connected to a thermal
plane in order to conduct heat away from the
device. Note that if any of the thermal planes is
also connected to AGND, the impedance
between this point and the GND connection of
the load needs to be minimized in order to get
the best possible load regulation. The pad
opposite the VOUT pins is connected to VOUT. This
VOUT pad should be connected to a top layer
copper area as large as possible to conduct
more heat away from the package. This will also
help minimize the trace length to the output filter
caps.
Pin 19 is a connected to a noisy internal node
and is brought out for test purposes only. Keep
all sensitive signal traces as far as possible from
this pin. Ideally, on the top layer there should be
no traces or vias underneath the package
between this pin and the VOUT thermal pad.
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Packaging Information
Mechanical Drawing and Nominal Dimensions
Bottom View
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Landing Pad Information
The Enpirion DFN package is footprint compatible with the JEDEC standard 36-pin TSSOP package
code DD. The reference document and board layout diagram appear below.
JEDEC Solid State Technology Association TSSOP (Plastic Thin Shrink Small Outline Package) standardized
package code DD. This TSSOP standard package is defined in the JEDEC document MO-153, Issue F, dated
05/01, which defines 57 variations on package size, lead pitch, and lead count.
Contact Information
Enpirion, Inc.
685 Route 202/206
Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
