HI-8382, HI-8383
The HI-8382 and HI-8383 bus interface products are silicon
gate CMOS devices designed as a line driver in accordance
with the ARINC 429 bus specifications.
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-8382 to be used in a variety of
applications. Both logic and synchronization inputs feature
built-in 2,000V minimum ESD input protection as well as TTL
and CMOS compatibility.
The differential outputs of the HI-8382 are independently
programmable to either the high speed or low speed ARINC
429 output rise and fall time specifications through the use of
two external capacitors. The output voltage swing is also
adjustable by the application of an external voltage to the VREF
input. The HI-8382 has on-chip Zener diodes in series with a
fuse to each differential output protecting the ARINC bus from
an overvoltage failure. The outputs each have a series
resistance of 37.5 ohms. The HI-8383 is identical to the HI-
8382 except that the series resistors are 13 ohms and the
overvoltage protection circuitry has been eliminated.
The updated HI-318X and HI-8585 ARINC 429 line drivers are
recommended for all new designs where logic signals must be
converted to ARINC 429 levels such as a user ASIC, the
HI-3282 or HI-8282A ARINC 429 Serial Transmitter/Dual
Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or the
HI-8783 ARINC interface device. Holt products are readily
available for both industrial and military applications. Please
contact the Holt Sales Department for additional information,
including data sheets for any of the Holt products
.
mentioned
above
PIN CONFIGURATION (Top View)GENERAL DESCRIPTION
!
!
!
!
!
!
!
!
Low power CMOS
TTL and CMOS compatible inputs
Programmable output voltage swing
Adjustable ARINC rise and fall times
Operates at data rates up to 100 Kbits
Overvoltage protection
Industrial and extended temperature ranges
DSCC SMD part number
FEATURES
FUNCTION
ARINC 429 DIFFERENTIAL LINE DRIVER
HI-8382
_
+
TRUTH TABLE
(See Page 6 for additional package pin configurations)
VREF
STROBE
SYNC
DATA(A)
CA
AOUT
-V
GND +V
N/C
BOUT
CB
DATA(B)
CLOCK
V1
N/C
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
HI-8382C / CT / CM-01 / CM-03
SMD # 5962-8687901EA
16 - PIN CERAMIC SIDE-BRAZED DIP
SYNC CLOCK DATA(A) DATA(B) AOUT BOUT COMMENTS
X L X X 0V 0V NULL
L X X X 0V 0V NULL
H H L L 0V 0V NULL
H H L H -V +V LOW
H H H L +V -V HIGH
H H H H 0V 0V NULL
REF REF
REF REF
( Rev. ) 09/11DS8382 F
September 2011
ARINC 429
Differential Line Driver
HOLT INTEGRATED CIRCUITS
www.holtic.com
(
Figure 2. FUNCTIONAL BLOCK DIAGRAM
REF
B
CGND -V
DATA (A)
DATA (B)
SYNC
CLOCK
V1
STROBE
A
CV+V
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
CURRENT
REGULATOR
OUTPUT
DRIVER (A)
OUT
B
OUT
A
CL
RL
FA
FB
OUTPUT
DRIVER (B)
R/2
OUT
R/2OUT
Not included on HI-8383
OVER VOLTAGE
CLAMPS
DATA (A)
OUT
DATA (B)
INPUTS TO ARINC BUS
A
OUT
B
REF
V
1
V
SYNC
CLOCK
-V
+V
STROBE
GND
B
A
C
C
-15V
+15V+5V
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input. Each logic
input, including the power enable ( ) input, are
TTL/CMOS compatible. Besides reducing chip current drain,
also floats each output. However the overvoltage
fuses and diodes of the HI-8382 are not switched out.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-8382;
typically +15V, -15V and +5V. The chip also works with ±12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2V . If a value of
V other than +5V is needed, a separate +5V power supply
is required for pin V .
With the DATA (A) input at a logic high and DATA (B) input at a
logic low, A will switch to the +V rail and B will
switch to the -V rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULL state).
The driver output impedance, R , is nominally 75 ohms.
The rise and fall times of the outputs can be calibrated through
the selection of two external capacitor values th re
connected to the C and C input pins. Typical values for
high-speed operation (100KBPS) are C = C = 75pF and for
low-speed operation (12.5 to 14KBPS) C = C = 500pF.
STROBE
STROBE
REF
REF
OUT REF OUT
REF
OUT
1
AB
AB
AB
at a
The driver can be externally powered down by applying a logic
high to the input pin. If this feature is not being used,
the pin should be tied to ground.
The C and C pins are inputs to unity gain amplifiers.
Therefore they must be allowed to swing to -5V. Provision to
STROBE
AB
switch capacitors must be done with analog switches that
allow voltages below their ground.
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The recom-
mended sequence is +V followed by V , always ensuring that
+V is the most positive supply. The -V supply is not critical
and can be asserted at any time.
Both ARINC outputs of the HI-8382 are protected by internal
fuses capable of sinking between 800 - 900 mA for short
periods of time (125µs).
POWER SUPPLY SEQUENCING
1
Figure 1. ARINC 429 BUS APPLICATION
FUNCTIONAL DESCRIPTION
HI-8382, HI-8383
HOLT INTEGRATED CIRCUITS
2
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PIN DESCRIPTIONS
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER SYMBOL CONDITIONS OPERATING RANGE MAXIMUM UNIT
Differential Voltage V Voltage between +V and -V terminals 40 V
Supply Voltage +V +10.8 to +16.5 V
-V -10.8 to -16.5 V
V +5 ±5% +7 V
Voltage Reference V For ARINC 429 +5 ±5% 6 V
For Applications other than ARINC 0 to 6 6 V
Input Voltage Range V GND -0.3 V
V1 +0.3 V
Output Short-Circuit Duration See Note: 1
Output Overvoltage Protection See Note: 2
Operating Temperature Range T Extended -55 to +125 °C
Industrial -40 to +85 °C
Storage Temperature Range T Ceramic & Plastic -65 to +150 °C
Lead Temperature Soldering, 10 seconds +275 °C
Junction Temperature T +175 °C
Power Dissipation P 16-Pin Ceramic DIP See Note: 3 1.725 W
28-Pin Ceramic LCC See Note: 3 1.120 W
28-Pin Plastic PLCC See Note: 3 2.143 W
32-Pin CERQUAD See Note: 3 1.725 W
Thermal Resistance, Ø 16-Pin Ceramic DIP 86.5 °C/W
(Junction-to-Ambient) 28-Pin Ceramic LCC 133.7 °C/W
28-Pin Plastic PLCC 70.0 °C/W
32-Pin CERQUAD 86.5 °C/W
Note 1. Heatsinking may be required for Output Short Circuit at +125°C and for 100KBPS at +125°C.
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than ±12.0V with respect to GND. (HI-8382 only)
Note 3. Derate above +25°C, 11.5mW/°C for 16-PIN DIP and 32-PIN CERQUAD, 7.5 mW/°C for 28-PIN LCC, 14.2 mW/°C for 28-PIN PLCC
DIF
1
REF
IN
A
STG
J
D
JA
>
<
SYMBOL FUNCTION DESCRIPTION
V POWER THE REFERENCE VOLTAGE USED TO DETERMINE THE OUTPUT VOLTAGE SWING
INPUT A LOGIC HIGH ON THIS INPUT PLACES THE DRIVER IN POWER DOWN MODE
SYNC INPUT SYNCHRONIZES DATA INPUTS
DATA (A) INPUT DATA INPUT TERMINAL A
C INPUT CONNECTION FOR DATA (A) SLEW-RATE CAPACITOR
A OUTPUT ARINC OUTPUT TERMINAL A
-V POWER -12V to -15V
GND POWER 0.0V
+V POWER +12V to +15V
B OUTPUT ARINC OUTPUT TERMINAL B
C INPUT CONNECTION FOR DATA (B) SLEW-RATE CAPACITOR
DATA (B) INPUT DATA INPUT TERMINAL B
CLOCK INPUT SYNCHRONIZES DATA INPUTS
V POWER +5V ±5%
REF
A
OUT
OUT
B
1
STROBE
HI-8382, HI-8383
HOLT INTEGRATED CIRCUITS
3
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V = V = +5.0V, T = Operating Temperature Range (unless otherwise specified).1 REF A
+V = +15V, -V = -15V, V = V = +5.0V, T = Operating Temperature Range (unless otherwise specified).1 REF A
Figure 3. SWITCHING WAVEFORMS
-9.5V to -10.5V
+9.5V to +10.5V
-4.75V to -5.25V
2.0V
+4.75V to +5.25V
2.0V
0.5V
0.5V
-4.75V to -5.25V
+4.75V to +5.25V
DATA (A) 0V
DATA (B) 0V
AOUT 0V
BOUT 0V
DIFFERENTIAL
OUTPUT 0V
()ABOUT - OUT
50%
50%
VREF
ADJUST
BY CA
tPHL
ADJUST
BY CA
-VREF 50%
50%
tPLH
tR
+VREF
-VREF
ADJUST
BY CB
ADJUST
BY CB
tF
2VREF
-2VRE
HIGH
NULL
LOW
NOTE: OUTPUTS UNLOADED
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Rise Time ( , ) = = 75pF See Figure 3. 1.0 2.0 µs
Fall Time ( , ) = = 75pF See Figure 3. 1.0 2.0 µs
Propagtion Delay Input to Output = = 75pF See Figure 3. 3.0 µs
Propagtion Delay Input to Output = = 75pF See Figure 3. 3.0 µs
AB t CC
AB t CC
tCC
tCC
OUT OUT R A B
OUT OUT F A B
PLH A B
PHL A B
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Supply Current +V (Operating) (+V) No Load (0 - 100KBPS) +11 mA
Supply Current -V (Operating) (-V) No Load (0 - 100KBPS) -11 mA
Supply Current (Operating) ( ) No Load (0 - 100KBPS) 500 µA
Supply Current (Operating) ( ) No Load (0 - 100KBPS) 500 µA
Supply Current +V (Power Down) (+V) STROBE = HIGH 475 uA
Supply Current -V (Power Down) (-V) STROBE = HIGH -475 uA
Supply Current +V (During Short Circuit Test) (+V) Short to Ground (See Note: 1) 150 mA
Supply Current -V (During Short Circuit Test) (-V) Short to Ground (See Note: 1) -150 mA
Output Short Circuit Current (Output High) Short to Ground =0 (See Note: 2) -80 mA
Output Short Circuit Current (Output Low) Short to Ground =0 (See Note: 2) +80 mA
Input Current (Input High) 1.0 µA
Input Current (Input Low) -1.0 µA
Input Voltage High 2.0 V
Input Voltage Low 0.5 V
Output Voltage High (Output to Ground) No Load (0 -100KBPS) +V +V V
-. +.
Output Voltage Low (Output to Ground) No Load (0 -100KBPS) -V -V V
-. +.
Output Voltage Null No Load (0-100KBPS) -250 +250 mV
Input Capacitance 15 pF
I
I
VIV
VIV
I
I
I
I
IV
IV
I
I
V
V
V
V
V
C
CCOP
CCOP
1 CCOP 1
REF CCOP REF
CCPD
CCPD
SC
SC
OHSC MIN
OLSC MIN
IH
IL
IH
IL
OH 25 25
OL 25 25
NULL
IN See Note 1
REF REF
REF REF
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
HI-8382, HI-8383
HOLT INTEGRATED CIRCUITS
4
ORDERING INFORMATION
Notes:
1. All data taken on devices soldered to a single layer copper PCB (3" X 4.5" X .062").
2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms,C=30nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms,C=10nF. Data not presented forC=30nF
as this is considered unrealistic for high speed operation.
5. Similar results would be obtained with AOUT shorted to BOUT.
6. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
7. Data will vary depending on air flow and the method of heat sinking employed.
in still air
HI-8382 PACKAGE THERMAL CHARACTERISTICS
(1) Process Flows M and DSCC always have Tin/Lead (Sn/Pb) solder lead finish.
(2) DSCC SMD# 5962-8687901EA. Only available in “C” package with Sn/Pb solder lead finish.
(3) Gold terminal finish is Pb-Free, RoHS compliant.
HI - (Ceramic)838xxx-xx
37.5 Ohms Yes
13 Ohms No
PART
NUMBER
8382
8383
OUTPUT SERIES
RESISTANCE FUSE
A and B Shorted To GroundOUT OUT 5, 6, 7
1
2
PACKAGE STYLE ARINC 429 SUPPLY CURRENT (mA) JUNCTION TEMP, Tj (°C)
DATA RATE
16 Lead Ceramic SB DIP
Ta = 25°C Ta = 85°C Ta = 125°C Ta = 25°C Ta = 85°C Ta = 125°C
Low Speed 60.1 55.7 52.4 110 157 194
High Speed 63.1 56.3 52.3 100 150 182
Low Speed 62.1 56.2 53.0 90 145 180
High Speed 64.0 56.2 52.2 86 144 176
3
4
28 Lead PLCC
MAXIMUM ARINC LOAD 7
1
2
PACKAGE STYLE ARINC 429 SUPPLY CURRENT (mA) JUNCTION TEMP, Tj (°C)
DATA RATE
16 Lead Ceramic SB DIP
Ta = 25°C Ta = 85°C Ta = 125°C Ta = 25°C Ta = 85°C Ta = 125°C
Low Speed 17.6 17.2 17.0 48 107 142
High Speed 25.4 24.5 24.2 56 110 150
Low Speed 17.9 17.4 17.1 41 103 145
High Speed 25.8 24.8 24.4 47 112 147
3
4
28 Lead PLCC
HI-8382, HI-8383
TEMPERATURE
RANGE
BURN
IN
-40°C to +85°C No
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
No
Yes
Yes
T
M
DSCC
PART
NUMBER
T
M-01
M-03
Blank
FLOW
I
NOTES
(1)
(1) & (2)
PACKAGE
DESCRIPTION
16 PIN CERAMIC SIDE BRAZED DIP (16C) Gold
PART
NUMBER
C
28 PIN CERAMIC LEADLESS CHIP CARRIER (28S) Gold
32 PIN CERQUAD (32U) not available with ‘M’ flow Tin/Lead Solder
S
U
LEAD
FINISH NOTES
(3) & (1)
(3) & (1)
HOLT INTEGRATED CIRCUITS
5
ADDITIONAL PIN CONFIGURATIONS
(See page 1 for the 16-pin Ceramic Side-Brazed DIP Package )
(1) NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-3182PJxx and HI-3183PJxx are drop-in replacements for the
older HI-8382Jxx and HI-8383Jxx respectively.
HI - (Plastic)838xJ x x
4 3 2 1 28 27 62
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
CLOCK
N/C
DATA (B)
C
N/C
N/C
N/C
B
N/C
DATA (A)
N/C
N/C
C
N/C
N/C
A
SYNC
N/C
V
V
N/C
N/C
STROBE
REF
1
N/C
A
-V
GND
+V
B
N/C
OUT
OUT
HI-8382J
HI-8382JT
28-PIN PLASTIC PLCC
4 3 2 1 28 27 26
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
CLOCK
N/C
DATA (B)
C
N/C
N/C
N/C
B
N/C
DATA (A)
N/C
N/C
C
N/C
N/C
A
SYNC
N/C
V
V
N/C
N/C
STROBE
REF
1
N/C
A
-V
GND
+V
B
N/C
OUT
OUT
HI-8382S
HI-8382ST
28-PIN CERAMIC LCC
N/C
N/C
N/C
N/C
DATA(B)
C
N/C
N/C
B
B
OUT
5678910111213
30
31
32
1
2
3
4
20
19
18
17
16
15
14
N/C
N/C
+V
GND
N/C
-V
N/C
CLOCK
V
N/C
V
SYNC
N/C
1
REF
STROBE
N/C
N/C
N/C
DATA(A)
C
N/C
N/C
N/C
A
A
OUT
HI-8382U
HI-8382UT
29 28 27 26 25 24 23 22 21
32-PIN J-LEAD CERQUAD
37.5 Ohms Yes
13 Ohms No
PACKAGE
DESCRIPTION
28 PIN PLASTIC PLCC (28J) (1)
28 PIN PLASTIC PLCC (28J) (1)
PART
NUMBER
8382J
OUTPUT SERIES
RESISTANCE FUSE
8383J
TEMPERATURE
RANGE
BURN
IN
-40°C to +85°C No
-55°C to +125°C No
T
PART
NUMBER
T
Blank
FLOW
I
LEAD
FINISH
PART
NUMBER
100% Matte Tin (Pb-free, RoHS compliant)
F
Tin / Lead (Sn / Pb) Solder
Blank
HI-8382, HI-8383
HOLT INTEGRATED CIRCUITS
6
REVISION HISTORY
P/N Rev Date Description of Change
E
F 09/16/11 Realigned pin names and numbers with package pin locations in Additional Pin
Configuration drawings.
DS8382 02/26/09 Clarified the temperature ranges, and Note (1) in the Ordering Information.
HI-8382, HI-8383
HOLT INTEGRATED CIRCUITS
7
HI-8382 PACKAGE DIMENSIONS
inches (millimeters)
Package Type: 16C
16-PIN CERAMIC SIDE-BRAZED DIP
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BASE
PLANE
SEATING
PLANE
.050 ±.005
(1.270 ±.127)
.295 ±.010
(7.493 ±.254)
PIN 1
.018 ± .002
(.457 ±.051)
.010 ±.002
(.254 ±.051)
.035 ± .010
(.889 ±.254)
.810
(20.574)
.300 ± .010
(7.620 ±.254)
.100
(2.54) BSC
.200
(5.080) max
.125
(3.175) min
max
28-PIN PLASTIC PLCC inches (millimeters)
Package Type: 28J
.045 x 45°
.453 ±.003
(11.506 ±.076)
SQ.
.490 ±.005
(12.446 ±.127)
SQ.
.045 x 45°
.173 ±.008
(4.394 ±.203)
PIN NO. 1 IDENT
PIN NO. 1
.410 ±.020
(10.414 ±.508)
.031 ±.005
(.787 ±.127)
.017 ±.004
(.432 ±.102)
.050
(1.27) BSC
DETAIL A
.035
.889
R
.010 ± .001
(.254 ± .03)
.020
(.508) min
See Detail A
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
8
HI-8382 PACKAGE DIMENSIONS
28-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters)
Package Type: 28S
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.451 ±.009
(11.455 ±.229)
SQ.
.080 ±.020
(2.032 ±.508)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
.050 ±.005
(1.270 ±.127)
.025 ±.003
(.635 ±.076)
PIN 1
.008R ± .006
(.203R ±.152)
PIN 1
.050
(1.270) BSC
.020
(.508) INDEX
32-PIN J-LEAD CERQUAD inches (millimeters)
Package Type: 32U
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.040
(1.016)
.190
(4.826)
.420 ±.012
(10.668 ±.305)
.588 ±.008
(14.935 ±.203)
.019 ±.003
(.483 ±.076)
.488 ±.008
(12.395 ±.203)
.450 ±.008
(11.430 ±.203)
.550 ±.009
(13.970 ±.229)
.520 ±.012
(13.208 ±.305)
31
32
1
2
.083 ±.009
(2.108 ±.229)
.050 BSC
(1.270)
typ
max
HOLT INTEGRATED CIRCUITS
9
