256-Position SPI-Compatible
Digital Potentiometer
AD5160
Rev. A
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FEATURES
256-position
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI-compatible interface
Power-on preset to midscale
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 45 ppm/°C
Low power, IDD = 8 μA
Wide operating temperature: –40°C to +125°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAM
SPI INTERFACE
WIPER
REGISTER
CS
SDI
CLK
GND
V
DD
A
W
B
Figure 1.
PIN CONFIGURATION
A
B
CS
SDI
1
2
3
45
8
7
6
W
V
DD
GND
CLK
TOP VIEW
(Not to Scale)
AD5160
Figure 2.
GENERAL DESCRIPTION
The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers1 or variable resistors but with
enhanced resolution, solid-state reliability, and superior low
temperature coefficient performance.
The wiper settings are controllable through an SPI-compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 μA allows for usage in portable battery-operated
applications.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5160
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 kΩ Version .................................. 3
10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4
Timing Characteristics—All Versions ....................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................8
Test Circuits ..................................................................................... 12
SPI Interface .................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider ............................... 14
SPI-Compatible 3-Wire Serial Bus .......................................... 15
ESD Protection ........................................................................... 15
Power-Up Sequence ................................................................... 15
Layout and Power Supply Bypassing ....................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/09—Rev. 0 to Rev. A
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 1 ............................................................................ 3
Changes to Resistor Noise Voltage Density Parameter,
Table 1 ................................................................................................ 3
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 2 ............................................................................ 4
Changes to Resistor Noise Voltage Density Parameter,
Table 2 ................................................................................................ 4
Added Endnote to Table 3 ............................................................... 5
Changes to Table 4 ............................................................................ 6
Changes to the Rheostat Operation Section ............................... 14
Deleted Terminal Voltage Operating Range Section and
Figure 41, Renumbered Figures Sequentially ............................. 13
Changes to Figure 40 and Figure 41 ............................................. 15
Changes to Ordering Guide .......................................................... 17
5/03—Revision 0: Initial Version
AD5160
Rev. A | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2R-DNL RWB, VA= no connect −1.5 ±0.1 +1.5 LSB
Resistor Integral Nonlinearity2
R-INL RWB, VA= no connect −4 ±0.75 +4 LSB
Nominal Resistor Tolerance3∆RAB T
A = 25°C −30 +30 %
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, wiper = no connect 45 ppm/°C
Wiper Resistance RW 50 120 Ω
Potentiometer Divider Mode Specifications apply to all VRs
Resolution N 8 Bits
Differential Nonlinearity4DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4
INL −1.5 ±0.6 +1.5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −6 −2.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 +2 +6 LSB
RESISTOR TERMINALS
Voltage Range5VA, VB, VW GND VDD V
Capacitance A, Capacitance B6CA,B f = 1 MHz, measured to GND, code = 0x80 45 pF
Capacitance W6
CW f = 1 MHz, measured to GND, code = 0x80 60 pF
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 μA
Input Capacitance6
CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3 8 μA
Power Dissipation7PDISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 0.2 mW
Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%, code = midscale ±0.02 ±0.05 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x80 1.2 MHz
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS V
A = 5 V, VB = 0 V, ±1 LSB error band 1 μs
Resistor Noise Voltage Density eN_WB R
WB = 2.5 kΩ 6 nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
AD5160
Rev. A | Page 4 of 16
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2R-DNL RWB, VA= no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2
R-INL RWB, VA= no connect −2 ±0.25 +2 LSB
Nominal Resistor Tolerance3∆RAB T
A = 25°C −30 +30 %
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD,
Wiper = no connect
45 ppm/°C
Wiper Resistance RW V
DD = 5 V 50 120 Ω
Potentiometer Divider Mode Specifications apply to all VRs
Resolution N 8 Bits
Differential Nonlinearity4DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4
INL −1 ±0.3 +1 LSB
Voltage Divider Temperature
Coefficient
∆VW/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −3 −1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 3 LSB
RESISTOR TERMINALS
Voltage Range5VA,B,W GND VDD V
Capacitance A, Capacitance B6CA,B f = 1 MHz, measured to GND, code =
0x80
45 pF
Capacitance W6
CW f = 1 MHz, measured to GND, code =
0x80
60 pF
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 μA
Input Capacitance6
CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3 8 μA
Power Dissipation7PDISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 0.2 mW
Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%, code = midscale ±0.02 ±0.05 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x80 600/100/40 kHz
Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz, RAB =
10 kΩ
0.05 %
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS VA = 5 V, VB = 0 V,
±1 LSB error band
2 μs
Resistor Noise Voltage Density eN_WB R
WB = 5 kΩ 9 nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
AD5160
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ1 Max Unit
SPI INTERFACE TIMING CHARACTERISTICS1, 2 Specifications Apply to All Parts
Clock Frequency fCLK 25 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns
Data Setup Time tDS 5 ns
Data Hold Time tDH 5 ns
CS Setup Time tCSS 15 ns
CS High Pulse Width tCSW 40 ns
CLK Fall to CS Fall Hold Time tCSH0 0 ns
CLK Fall to CS Rise Hold Time tCSH1 0 ns
1 See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a
voltage level of 1.5 V.
2 Guaranteed by design and not subject to production test.
AD5160
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
VA, VB, VW to GND VDD
Maximum Current IMAX1
IWB, IWA Pulsed ±20 mA
IWB, IWA Continuous
5 kΩ, 10 kΩ 4.7 mA
50 kΩ 0.95 mA
100 kΩ 0.48 mA
Digital Inputs and Output Voltage to GND 0 V to +7 V
Temperature
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature −65°C to +150°C
Thermal Resistance (SOT-23 Package)2
θJA Thermal Impedance 206ºC/W
θJC Thermal Impedance 91°C/W
Reflow Soldering (Pb-Free)
Peak Temperature 260°C
Time at Peak Temperature 10 sec to 40 sec
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and applied
voltage across any two of the A, B, and W terminals at a given resistance.
2 Package power dissipation = (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5160
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A
B
CS
SDI
1
2
3
45
8
7
6
W
V
DD
GND
CLK
TOP VIEW
(Not to Scale)
AD5160
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin Mnemonic Description
1 W W Terminal.
2 VDD Positive Power Supply.
3 GND Digital Ground.
4 CLK Serial Clock Input. Positive edge triggered.
5 SDI Serial Data Input.
6 CS Chip Select Input, Active Low. When CS returns high, data loads into the DAC register.
7 B B Terminal.
8 A A Terminal.
AD5160
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
3209664 128 160 192 224 256
RHEOSTAT MODE INL (LSB)
0.8 5V
3V
Figure 4. R-INL vs. Code vs. Supply Voltages
5V
3V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE DNL (LSB)
0.8
CODE (Decimal)
3209664 128 160 192 224 256
Figure 5. R-DNL vs. Code vs. Supply Voltages
_40°C
+25°C
+85°C
+125°C
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
POTENTIOMETER MODE INL (LSB)
0.8
CODE (Decimal)
3209664 128 160 192 224 256
Figure 6. INL vs. Code, VDD = 5 V
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
3209664 128 160 192 224 256
POTENTIOMETER MODE DNL (LSB)
0.8 –40°C
+25°C
+85°C
+125°C
Figure 7. DNL vs. Code, VDD = 5 V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
POTENTIOMETER MODE INL (LSB)
0.8
CODE (Decimal)
3209664 128 160 192 224 256
5V
3V
Figure 8. INL vs. Code vs. Supply Voltages
5V
3V
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
3209664 128 160 192 224 256
POTENTIOMETER MODE DNL(LSB)
1.0
Figure 9. DNL vs. Code vs. Supply Voltages
AD5160
Rev. A | Page 9 of 16
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE INL (LSB)
0.8
CODE (Decimal)
32096
64 128 160 192 224 25
6
°C
+25°C
+85°C
+125°C
–40
Figure 10. R-INL vs. Code, VDD = 5 V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE DNL (LSB)
0.8
CODE (Decimal)
3209664 128 160 192 224 256
_40°C
+25°C
+85°C
+125°C
Figure 11. R-DNL vs. Code, VDD = 5 V
TEMPERATURE (°C)
0 40 80 120–40
0
1.5
FSE, FULL-SCALE ERROR (LSB)
0 40 80 120–40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 12. Full-Scale Error vs. Temperature
0 40 80 120–40
0
1.5
ZSE, ZERO-SCALE ERROR (μA)
TEMPERATURE (°C)
0 40 80 120–40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 13. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)
0 40 80 120–40
0.1
1
10
IDD SUPPLY CURRENT (μA)
VDD = 5.5V
VDD = 2.7V
Figure 14. Supply Current vs. Temperature
I
A
SHUTDOWN CURRENT (nA)
TEMPERATURE (°C)
0
0
70
20
10
30
40
50
60
40 80 120–40
V
DD
= 5V
Figure 15. Shutdown Current vs. Temperature
AD5160
Rev. A | Page 10 of 16
CODE (Decimal)
–50
0
50
100
150
200
3209664 128 160 192 224 256
RHEOSTAT MODE TEMPCO (ppm/°C)
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
CODE (Decimal)
–20
0
20
40
60
80
100
120
140
160
3209664 128 160 192 224 256
POTENTIOMETER MODE TEMPCO (ppm/°C)
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 510 634.725Hz
MAG (A/R) –9.049dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 100 885.289Hz
MAG (A/R) –9.014dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
AD5160
Rev. A | Page 11 of 16
10k 100k 1M 10M
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–10.5
REF LEVEL
–5.000dB
/DIV
0.500dB
START 1 000.000Hz STOP 1 000 000.000Hz
R = 5kΩ
R = 10kΩ
R = 50kΩ
R = 100kΩ
5kΩ– 1.026 MHz
10kΩ– 511 MHz
50kΩ– 101 MHz
100kΩ– 54 MHz
VW
CLK
Ch 1 200mV
BW
Ch 2 5.00 V
BW
M 100ns A CH2 3.00 V
1
2
Figure 22. –3 dB Bandwidth @ Code = 0x80 Figure 25. Digital Feedthrough
VW
CS
Ch 1 100mV
BW
Ch 2 5.00 V
BW
M 200ns A CH1 152mV
1
2
V
A
= 5V
V
B
= 0V
FREQUENCY (Hz)
10k100 100k 1M1k
0
20
40
60
PSRR (dB)
CODE = 0x80, V
A
= V
DD
, V
B
= 0V
PSRR @ V
DD
= 3V DC ± 10% p-p AC
PSRR @ V
DD
= 5V DC ± 10% p-p AC
Figure 23. PSRR vs. Frequency Figure 26. Midscale Glitch, Code 0x80 to 0x7F
I
DD
(μA)
FREQUENCY (Hz)
10k
800
700
600
500
400
300
900
200
100
100k 1M 10M
0
CODE = 0x55
CODE = 0xFF
V
DD
= 5V
VW
CS
Ch 1 5.00V
BW
Ch 2 5.00 V
BW
M 200ns A CH1 3.00 V
1
2
V
A
= 5V
V
B
= 0V
Figure 24. IDD vs. Frequency Figure 27. Large Signal Settling Time, Code 0xFF to 0x00
AD5160
Rev. A | Page 12 of 16
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
V
MS
AW
B
DUT V+ = V
DD
1LSB = V+/2
N
V+
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V
MS1
I
W
= V
DD
/R
NOMINAL
V
MS2
V
W
R
W
= [V
MS1
– V
MS2
]/I
W
AW
B
DUT
Figure 30. Test Circuit for Wiper Resistance
ΔV
ΔV
ΔV
ΔV
MS
%
DD
%
PSS (%/ %) =
V+ = V
DD
10%
PSRR (dB) = 20 LOG
MS
DD
( )
V
DD
V
A
V
MS
AW
B
V+
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
OP279
W
5V
B
V
OUT
OFFSET
GND OFFSET
BIAS
ADUT
V
IN
Figure 32. Test Circuit for Inverting Gain
B
A
V
IN
OP279
W
5V
V
OUT
OFFSET
GND
OFFSET
BIAS
DUT
Figure 33. Test Circuit for Noninverting Gain
+15V
–15V
W
A
2.5V
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 34. Test Circuit for Gain vs. Frequency
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=0.1V
I
SW
0.1V
Figure 35. Test Circuit for Incremental On Resistance
W
BV
CM
I
CM
A
NC
GND
NC
V
SS
V
DD
DUT
NC = NO CONNECT
Figure 36. Test Circuit for Common-Mode Leakage Current
AD5160
Rev. A | Page 13 of 16
SPI INTERFACE
Table 6. Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
27 2
0
SDI
CLK
CS
V
OUT
1
0
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 37. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT)
t
CSHO
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
CH
SDI
CLK
CS
VOUT
1
0
1
0
1
0
V
DD
0
±1LSB
(DATA IN)
Dx Dx
Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
AD5160
Rev. A | Page 14 of 16
THEORY OF OPERATION
The AD5160 is a 256-position digitally controlled variable
resistor (VR) device.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
final two or three digits of the model number as listed in the
Ordering Guide section determine the nominal resistance value,
for example, in model AD5160BRJZ10, the 10 represents 10 kΩ;
and in AD5160BRJZ50, the 50 represents 50 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings.
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 60 Ω
wiper contact resistance, such connection yields a minimum of
60 Ω resistance between Terminal W and Terminal B.
The second connection is the first tap point, which corresponds
to 99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for Data 0x01.
The third connection is the next tap point, representing 138 Ω
(2 × 39 Ω + 60 Ω) for Data 0x02, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at 9961 Ω (RAB − 1 LSB + RW). Figure 39
shows a simplified diagram of the equivalent RDAC circuit
where the last resistor string is not accessed; therefore, there is
1 LSB less of the nominal resistance at full scale in addition to
the wiper resistance.
B
RDAC
LATCH
AND
DECODER
W
A
R
S
R
S
R
S
R
S
D7
D6
D4
D5
D2
D3
D1
D0
Figure 39. Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR +×= 256
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
D (Dec.) RWB (Ω) Output State
255 9961 Full Scale (RAB − 1 LSB + RW)
128 5060 Midscale
1 99 1 LSB
0 60 Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
60 Ω is present. Take care to limit the current flow between W
and B in this state to a maximum pulse current of no more than
20 mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance (RWA ). When
these terminals are used, the B terminal can be opened. Setting
the resistance value for RWA starts at a maximum value of
resistance and decreases as the data loaded in the latch increases
in value. The general equation for this operation is
W
ABWA RR
D
DR +×
−
=256
256
)( (2)
For RAB = 10 kΩ and the B terminal is open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
Table 8. Codes and Corresponding RWA Resistance
D (Dec.) RWA (Ω) Output State
255 99 Full Scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
AD5160
Rev. A | Page 15 of 16
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by
the 256 positions of the potentiometer divider. The general
equation defining the output voltage at VW with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B is
B
A
WV
D
V
D
DV
256
256
256
)( −
+= (3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as
B
WA
A
WB
WV
DR
V
DR
DV
256
)(
256
)(
)( += (4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors (RWA and RWB) and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
SPI-COMPATIBLE 3-WIRE SERIAL BUS
The AD5160 contains a 3-wire SPI-compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in . Table 6
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see ). Figure 37
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures are shown in Figure 40 and
Figure 41. This applies to SDI, CLK, and CS, which are the
digital input pins.
LOGIC
340Ω
GND
Figure 40. ESD Protection of Digital Pins
A,B,W
GND
Figure 41. ESD Protection of Resistor Terminals
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals, it is important to power VDD/GND
before applying any voltage to the A, B, and W terminals;
otherwise, the diode forward biases such that VDD is powered
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD,
digital inputs, and then VA/B/W. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. Keep the leads to the inputs as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Bypass supply
leads to the device with disc or chip ceramic capacitors of
0.01 μF to 0.1 μF. To minimize any transient disturbance and
low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors at the supplies (see Figure 42). To
minimize the ground bounce, join the digital ground remotely
to the analog ground at a single point.
AD5160
V
DD
C1
C3
GND
10μF0.1μF
+
V
DD
Figure 42. Power Supply Bypassing
AD5160
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
COMP LI ANT TO JEDE C STANDARDS MO-178- BA
121608-A
8°
4°
0°
SEATING
PLANE
1.95
BSC
0.65 BSC
0.60
BSC
76
1234
5
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.22 MAX
0.08 MIN
0.38 MAX
0.22 MIN
0.60
0.45
0.30
PIN 1
INDICATOR
8
Figure 43.
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (Ω) Temperature Package Description Package Option Branding
AD5160BRJZ5-R22 5 k −40°C to +125°C SOT-23 RJ-8 D6Q
AD5160BRJZ5-RL72 5 k −40°C to +125°C SOT-23 RJ-8 D6Q
AD5160BRJZ10-R22 10 k −40°C to +125°C SOT-23 RJ-8 D09
AD5160BRJZ10-RL72 10 k −40°C to +125°C SOT-23 RJ-8 D09
AD5160BRJZ50-R22 50 k −40°C to +125°C SOT-23 RJ-8 D0A
AD5160BRJZ50-RL72 50 k −40°C to +125°C SOT-23 RJ-8 D0A
AD5160BRJZ100-R22 100 k −40°C to +125°C SOT-23 RJ-8 D0B
AD5160BRJZ100-RL72 100 k −40°C to +125°C SOT-23 RJ-8 D0B
AD5160EVAL3 Evaluation Board
1 The AD5160 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
2 Z = RoHS Compliant Part.
3 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03434-0-1/09(A)
