8155(H)/8156(H) 8155(H)/8156(H) 2048-Bit Static MOS RAM with I/O Ports and Timer DISTINCTIVE CHARACTERISTICS @ 256 word x 8-bits @ Single +5 V power supply @ Completely static operation @ internal address latch 2 programmable 8-bit [/O ports @ 1 programmable 6-bit 1/O port Programmable 14-bit binary counter/timer Multiplexed address and data bus GENERAL DESCRIPTION The 8155(H) and 8156(H) are RAM and I/O chips to be used in the 8085AH MPU system. Tha RAM portion is designed with 2K bit static cells organized as 256 x B. They have a maximum access time of 400ns to permit use with no wait states in 8085AH CPU. The 8155H-2 and 8156H-2 have maximum access times of 330ns for use with the 8085AH. The !/O portion consists of three general purpose 1/0 ports. One of the three ports can be programmed to be status pins, thus allowing the other two ports to operate in handshake mode. A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse for the CPU system depending on timer mode. BLOCK DIAGRAM 10/M sovan, | Bas RAM eH] ALE > WR___> RESET TIMER TIMER CLK _| TIMER OUT T] |] Porta nm PORT B B 8 PByPB, 1 | porte e| K 8 rears | LL Voo(+5V) Vgg(0V) 8D003810 *B155H = CE, 8156H = CE 3-246 Publication Rev. 00934 c Issue Date: April 1987 Amendment 40CONNECTION DIAGRAM Top View DIPs PC; 10 40 [7 Vec pc, (] 2 39 PCa TIMER iN (_] 3 38 PC, RESET C_l4 37 [] PCy Pcs (J5 36 [7] PB, TIMER OUT (_] 6 35 [_] PB. io/M (]7 34 [7] PBs CEor CE C]s 33 [7] PB, Ro CJ] 9 32 [] PB WR (Lj 10 31 (7) PB. ALE ([] 11 30 [] PB, AD, ([] 12 29 [_] PB, AD, (7) 13 28 [_] PA, AD, (_] 14 27 [7] PAs AD, ((] 15 26 [} PAs ap, [7] 16 25 [] PA, ADs [(] 17 24 [] PA AD, [J 18 23 [7] PA2 AD, [] 19 22 [[) PA, Vgg [J 20 21 [7] PAg cpo0ss84 Note: Pin 1 is marked for orientation. 3-247 @ = on ai ~~ <= = ~ o _ a a ~ =8155(H)/8156(4) ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type c. Device Number d. Speed Option e. Optional Processing o_o DB 8155 = B LL @. OPTIONAL PROCESSING Blank = Standard Processing B = Burnin d. SPEED OPTION Blank = 2.5 MHz -2= 3 MHz c. DEVICE NUMBER/DESCRIPTION 8155(H)/8156(H) 2048-Bit Static MOS RAM with I/O Ports and Timer b. PACKAGE TYPE P = 40-Pin Plastic DIP (PD 640) D =40-Pin Ceramic DIP (CD 040) a. TEMPERATURE RANGE* Blank = Commercial (0 to + 70C} |= Industrial (~40 to + 85C) Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD 8155 sales office to confirm availability of specific valid 8155H combinations, to check on newly released valid combinations, 8155-2 and to obtain additional data on AMD's standard military P,D 8155H-2 grade products. 8156 . oo . oe 8156H *This device is also available in Military temperature range. 562 See MOS Microprocessors and Peripherais Military Handbook 8156- (Order #09275A/0} for electrical performance characteris- 8156H-2 tics. 81558 8155HB 8155-28 D, ID 8155H-2B 8156B 8156HB 8156-28 8156H-2B 3-248PIN DESCRIPTION Pin No. Name 1/0 Description 4 RESET | The Reset signal is a pulse provided by the 8085AH to initialize the system. Input high on this line resets the chip and initiatizes the three 1/0 ports to input mode. The width of RESET pulse should typically be 600ns. (Two 8085AH clack cycle times). a = or gi ~ = ~ eo aA on a _~ = 12-19 ADpo-AD7 /O These are 3-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is latched into the address latch on the falling edge of the ALE. The address can be either for the memory section or the |/O section depending on the polarity of the 10/M input signal. The 8-bit data is either written into the chip or read from the chip depending on the status of WRITE or READ input signal. 8 CE OR CE t Chip Enable: On the 8155(H) this pin is CE and is active low. On the 8156(H) this pin is CE and is active high. 9 RB I Input low on this line with the Chip Enable active enables the ADpo.7 buffers. If 10/M pin is LOW, the RAM content will be read out to the AD bus. Otherwise, the content of the selected I/O port will be read to the AD bus. 10 WR ! Input low on this line with the Chip Enable active causes the data on the AD lines to be written to the ARAM or I/O ports, depending on the polarity of 10/M. 11 ALE I Address Latch Enable: This control! signa! latches the address on the ADp.7 lines and the state of the Chip Enable and 1O/M into the chip at the falling edge of ALE. 7 1O/M 1 |O/MEMORY Select: This line selects the memory if LOW and selects the IO if HIGH. 21-28 PAg-PA7 VO These 8 pins are general purpose 1/O pins. The in/out direction is selected by programming the Command/Status Register. 29-36 PBo-PB7 70 These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the Command/Status Register. 37-39, PCo-PC5 0 These 6 pins can function as either input port, output port, or as control 1, 2,5 signals for PA and PB. Programming is done through the C/S Register. When PCo.5 are used as control signals, they will provide the following: PGo-A INTR (Port A Interrupt) PCy-A BF (Port A Buffer Full) PCo-A STB (Port A Strobe) PC3-B INTR (Port B Interrupt) PC4-B BF (Port B Buffer Full) PCs5-B STB (Port B Strobe) 3 TIMER IN | This is the timer input to the counter timer. 6 TIMER Oo This pin is the timer output. This output can be either a square wave or OUT a pulse depending on the timer mode. 40 Voc +5 volt supply. 20 Vss Ground reference. 3-2498155(H)/8156(H) DETAILED DESCRIPTION The 8155(H)/8156(H) includes the following operational fea- tures: @ 2K Bit Static RAM organized as 256x8 @ Two 86-bit 1/O ports (PA and PB) and one 6-bit 1/O port (PC) @ 14-bit down counter The I/O portion contains four registers (Command/Status, PAp.7, PBo.7, PCo-5). The 1O/M (lIO/Memory Setect) pin selects the I/O or the memory (RAM) portion. Detailed descriptions of memory, I/O ports and timer functions will follow. The 8-bit address on the AD lines, the Chip Enable input, and 10/M are all latched on chip at the falling edge of ALE. A LOW on the 1O/M must be provided to select the memory section. SE (amn6155/H) \ oR CE (Am8156/H) om / \ ADy-AD, ADDRESS x DATA VALIO ALE _/l \ >< [l AD on WA Note: For detailed timing diagram information, see Read/Write Cycle Timing Diagrams \ 4 / WFO008872 and Switching Characteristics. Figure 1. Memory Read/Write Cycle PROGRAMMING INFORMATION The Command/Status Register The command register consists of eight latches, one for each bit. Four bits (0-3) define the mode of the ports. Two bits (4-5) enable or disable the interrupt from Port C when it acts as control port, and the last two bits (6-7) are for the timer. The C/S register contents can be altered at any time by using the I/O address XXXXX000 during a WRITE operation. The meaning of each bit of the command byte is defined as follows: 7 6 5 4 3 2 4 9 TM, | Ty] 168| ta | PC} Pc,| Pe | PA L J L J Le Defines P: Aor 0 = Input Ls Defines PBS; 1 = Output 00 = ALT 1 it = ALT 2 Latinas Pos 01 = ALT3 WO= ALTA Enable Port A interrupt 1 = Enable Enable Port B 0 = Disable Interrupt 0 = NOP Do not atfect counter operation. Ot = STOP - NOP if timer has not started; stop Counting if the timer is running . 10 = STOP after TC - Stop immediately after present TC is reached (NOP if timer TIMER COMMAND has not started). 11 = START Load mode and CNT length and start immediately alter loading (it timer is not presently running). If timer is running, start the new mode and CNT length immediately alter present TC is reached. DFO03361 Figure 2. Command/Status Register Bit Assignment 3-250Reading the Command/Status Register The status register consists of seven latches, one for each bit: six (0-5) for the status of the ports and one (6) for the status of the timer. The status of the timer and the I/O section can be polled by reading the C/S Register (Address XXXXX000). Status word format is shown below: AD, AD, ADs AD, AD, AD, AD, ADy wre) 68 |INTRI INTE} A | INTR BF A A BF lL Port A interrupt Request == Port A Butfer FulfEmpty (Input/Output) Timer -____ Port A interrupt Enable 1 __..__--=ee- Port B interrupt Request Lee. Port 8 Butter Ful/Empty (InpuyOutput) sc nts Port B Interrupt Enabled ber ne Timer interrupt (This bit is latched high when terminal count is reached. i is Feset by reading the C/S register and by hardware reset.) DF003370 Figure 3. Command/Status Register Status Word Format Input/Output Section The I/O section of the 8155(H)/8156(H) consists of four registers as described below. Command/Status Register (C/S) This register is as- signed the address XXXXXOOO. The C/S address serves a dual purpose. When the C/S register is selected during WRITE operation, a command is written into the command register. The contents of this register are not accessible through the pins. When the C/S (XXXXX000) is selected during a READ operation, the status information of the |/O ports and the timer becomes available on the ADpo.7 lines. @ PA Register This register can be programmed to be either input or output ports, depending on the status of the contents of the C/S Register. Also, depending on the command, this port can operate in either the basic mode or the strobed mode (see timing diagram). The I/O pins assigned in relation to this register are PAo.7. The address of this register is XXXXX001. @ PB Register This register functions the same as PA Register. The |/O pins assigned are PBo.7. The address of this register is XXXXX010. e@ PC Register This register has the address XXXXX011 and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control signals for PA and PB properly programming the AD2 and ADzg bits of the C/S register. When PCp.5 is used as a control port, 3 bits are assigned for Port A and 3 for Port B. The first bit is an interrupt that the 8155(H) sends out. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. See Table 1. When the ''C"' port is programmed to either ALT3 or ALT4, the contro! signals for PA and PB are initialized as follows: Control Input Mode Output Mode BF LOW LOW INTR LOW HIGH STB Input Control Input Control The set and reset of INTR and BF with respect to STB, WA and RD timing are shown in Strobed 1/O Timing Diagrams. To summarize, the registers assignments are: i) No. of Address | Pinouts Functions Bits XXXXX000! Internal |Command/Status Register 8 XXXXX001| PAp.7 |General Purpose 1/O Port 8 XXXXX010} PBo.7 |General Purpose I/O Port 8 XXXXX011; PCo.g {General Purpose I/O Port or| 6 Control Lines The following diagram shows how I/O Ports A and B are structured within the 8155(H) and 8156(H): WRITE PORT ux Str INTERNAL DATA GUS: READ PORT AFO003060 Figure 4. 8155(H)/8156(H) One Bit of Port A or Port B Notes: 1. Output Mode 2. Simple Input 3. Strobed Input Multiplexer Control 4. =1 for output mode. = 0 for input mode. Read Port = (IO/M =1) (AD=0) (CE active) (Port address selected) Write Port = (1O/M = 1) (WR=0) (CE active) (Port address selected) Note in the diagram that when the !/O ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation when appropriately addressed. Note also that the output latch is cleared when the port enters the input mode. The output latch cannot be loaded by writing to the port if the port is in the input mode. The result is that each time a port mode is changed from input to output, the output pins will go LOW. When the 8155(H)/8156(H) is RESET, the output latches are all cleared and all 3 ports enter the input mode. When in the ALT 1 or ALT 2 modes, the bits of Port C are structured like the diagram above in the simple input or output mode, respectively. Reading from an input port with nothing connected to the pins will provide unpredictable results. 3-251 o =_- a wn ~ = ~ a a ao a ~ <=8155(H)/8156(H) Table 1. Table of Port Control Assignment Pin ALT 1 ALT 2 ALT 3 ALT 4 PCO Input Port Output Port |A INTR (Port A Interrupt) A INTR (Port A Interrupt) PC1 Input Port Output Port |A BF (Port A Buffer Full) A BF (Port A Buffer Full) PC2 Input Port Output Port jA STB (Port A Strobe) A STB (Port A Strobe) PC3 Input Port Output Port [Output Port B INTR (Port B interrupt) PC4 Input Port Output Port |Output Port B BF (Port B Buffer Full) PC5 Input Port Output Port |Output Port B STB (Port B Strobe) Timer Section The timer is a 14-bit down counter that counts the "timer input" pulses and provides either a square wave or pulse when terminal count (TC) is reached. The timer has the 1/O address XXXXX100 for the low order byte of the register and the I/O address XXXXX101 for the high order byte of the register. To program the timer, the COUNT LENGTH REG is loaded first, one byte at a time, by selecting the timer addresses. Bits 0 - 13 will specify the length of the next count, and bits 14 - 15 will specify the timer output mode. The value loaded into the count length register can have any value from 2} through SFFFy in bits 0- 13. There are four modes to choose from: 0-Puts out LOW during secand haif of count 1~-Square wave 2-Single pulse upon TC being reached 3-FRepetitive single pulse every time TC is readied and automatic reload of counter upon TC being reached until instructed to stop by a new command loaded into C/S. Bits 6 7 of the Command/Status Register Contents are used to start and stop the counter. There are four commands to choose from. (See the further description on Command/ Status Register.) C/S7 C/S6 0 0 NOP - Do not affect counter operation. 0 1 STOP -NOP if timer has not started; stop counting if the timer is running. 1 0 STOP AFTER TC - Stop immediately after present TC is reached (NOP if timer has not started). 1 1 START - Load mode and CNT length and start immediately after loading {if timer is not presently running). If timer is running, start the new mode and CNT length imme- diately after present TC is reached. [tm | t0] te | te | [ Me [Ms | tis | te L - l TIMER MODE [Ls [ts | t% [Tt [ [| 7% | L J LSB OF CNT LENGTH MSB OS CNT LENGTH Figure 5. Timer Format M2 and M1 define the timer mode as follows: M2 M1 0 0 Puts out LOW during second half of count. 0 1 Square wave, i.e., the period of the square wave equals the count length programmed with automatic reload at terminal count. 1 0 Single pulse upon TC being reached. 1 1 Automatic reload, i.., single pulse every time TC is reached. Note: In case of an asymmetric count, i.., 9, larger half of the count will be HIGH, the larger count will stay active as shown in Figure 5. Lr WFO007260 Note: 5 and 4 refer to the number of clock cycles in that time period. Figure 6. Asymmetric Count The counter in the B155(H) is not initialized to any particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore, counting cannot begin following RESET until a START command is issued via the C/S register. 3-2528185A Minimum System Configuration Figure 7 shows a minimum system using three chips, containing 256 Bytes RAM, 2K Bytes EPROM, 38 I/O Pins, 1 Interval Timer, and 4 Interrupt Levels. 8085AH 16K EPROM AF004680 Figure 7. 8085AH Minimum System Configuration (Memory Mapped 1/0) (H)9SL8/(H)Ssiy 3-2538155(H)/8 156(H) 6086 Five-Ghip System Figure 8 shows a five-chip system containing 1.25K Bytes RAM, 2K Bytes EPROM, 38 I/O Pins, 1 Interval Timer, and 2 Interrupt Levels. ec ow FD ALE cE PORTA 10 16K EPROM DATA ADOR om RESET READY PORT Yee ior Mg) 8K SRAM MAg %Do.7 AFO04700 Figure 8. 8088 Five-Chip System Configuration 3-254ABSOLUTE MAXIMUM RATINGS Storage Temperature 00.0.0... -65C to + 150C Voc with Respect to Vsg .........c cece -0.5 to +70 V All Signal Voltages With Respect to Vgg.....ccececcecseseeeeeeeees -0.5 V to #70 V Power Dissipation ...............cccccccsscesevsseeseeeaesanee 1.5 W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TA)........ecceecsescetssecsseeeeees 0 to +70C Supply Voltage (Vcc) 8155/8156 oo. cc ccccccececnscesnceeseens 8155H/8156H. Supply Current (icc) 8155/8156. ec cecceeesesecerecarsenevenese 8155H/8156H Industrial (I) Devices Temperature (Ta).... -40 to +85C Supply Voltage (VOC) .......cccceeccscseeeseaeeeees 5 V +10% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified Parameters Description Test Conditions Min Max Units VIL Input Low Voltage -0.5 0.8 Volts VIH Input High Voltage 2.0 Voct 0.5} Volts VoL Output Low Voltage loL=2 mA 0.45 Volts Vou Output High Voltage loH = 400 pA 2.4 Volts lit Input Leakage Vin=Voc to 0 V +10 vA ILo Output Leakage Current 0.45 V <Vout <Voc +10 BA 8155, 8156 180 mA loc Yoo Supply Current 8155H, 8156H 125 mA 8155H, 8155 +100 BA li (CE) Chip Enable Leakage Vin = Voc to 0 V 8156H, 8156 -100 BA SWITCHING TEST INPUT/OUTPUT WAVEFORM 24 20 2.0 TEST POINTS 08 08 0.45 WF007340 Inputs are driven at 2.4 V for a Logic ''1"' and 0.45 V for a Logic 0". Timing measurements are made at 2.0 V for a Logic "1" and 0.8 V for a Logic "0". SWITCHING TEST CIRCUIT OEVICE TEST CL = 150pF 1. I TC002191 Cy Includes Jig Capacitance See Section 6 for Thermal Characteristics Information 3-255 oa _ a or ~ <= ~ a _ ol a _~ <=8155(H)/8156(H) SWITCHING CHARACTERISRICS over operating ranges unless otherwise specified 8155, 8156 8155-2, 8156-2 8155H, 8156H 8155H-2, 8156H-2 Parameters Description Min Max Min Max Units taL Address to Latch Setup Time 50 30 ns LA Address Hold Time after Latch 80 30 ns tLe Latch to READ/WRITE Control 100 40 ns tap Valid Data Out Delay from READ Control 170 140 ns tad Address Stable to Data Out Valid 400 330 ns tLo Latch to Data Out Valed 350 270 ns twt ORI > TIMER-IN (For Writes Which Start 360 200 ns tLe Latch Enable Width 100 70 ns tRpF Data Bus Float After READ 0 100 0 80 ns to. READ/WRITE Control to Latch Enabie 20 10 ns tCLL WRITE Control to Latch Enable for C/S Register 125 126 ns tcc READ/WRITE Control Width 250 200 ns tow Data in to WRITE Setup Time 150 100 ns two Data in Hold Time After WRITE 25 25 ns trav Recovery Time Between Controls 300 200 ns twe WAITE to Port Output 400 300 ns ter Port Input Setup Time 70 50 ns trp Port Input Hold Time 50 10 ns tsBF Strobe to Buffer Full 400 300 ns tss Strobe Width 200 +50 ns tRBE READ to Buffer Empty 400 300 ns tsi Strobe to INTR On 400 300 ns trDI READ to INTR Off 400 300 ns tpss Port Setup Time to Strobe 50 0 ns tpHS Port Hold Time After Strobe 120 100 ns tsBE Strobe to Buffer Empty 400 300 ns twBF WRITE to Buffer Full 400 300 ns twt WRITE to INTR Off 400 300 ns tre TIMER-IN to TIMER-OUT Low 400 300 ns ttH TIMER-IN to TIMER-OUT High 400 300 ns tRDE Data Bus Enable from READ Controi 10 10 ns ty TIMER-IN Low Time 80 40 ns te TIMER-IN High Time 120 70 ns 3-256SWITCHING WAVEFORMS DATA VALID to WF007273 8155(H)/8156(H) Read Cycle CE (ametssn) On CE (Am8156H) ADy-AD, DATA VALIO teu WF007283 8155(H)/8156(H) Write Cycle 3-257 (H)9Si-8/(H)ssie8155(H)/8156(H) SWITCHING WAVEFORMS (Cont'd.) BF INPUT DATA FROM PORT WF007290 Strobed Input Mode J twer fotsr we CN Ww w f/f / OUTPUT DATA TO PORT twe WF007301 Strobed Output Mode Input Output wor oe oaragus, XX WFO007310 WF007320 *Data bus timing is shown in Read/Write Cycle diagrams. Basic 1/O Timing Waveform 3-258SWITCHING WAVEFORMS (Cont'd.) LOAD COUNTER FROM CLA RELOAD COUNTER FROM CLA = 2 i 1 5 ( 4 i 4a 4 2 I 1 5 ( is tg TIMER iN awe & & tcyc TIMER OUT (NOTE 1) tte ef try THER OUT NOTE 1 / (SQUARE WAVE) \ . J _ ) a / _ he | tH WF007330 Note 1: The timer output is periodic if in an automatic reload mode (M1 mode bit = 1). Timer Output Waveform Countdown from 5 to 1 (H)9SL8/(H)Ssie 3-259