www.irf.com 1
6/29/06
IRF7807ZPbF
HEXFET® Power MOSFET
Notes through are on page 10
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
l100% Tested for RG
lLead-Free
Applications
lControl FET for Notebook Processor Power
lSynchronous Rectifier MOSFET for
Graphics Cards and POL Converters in
Networking and Telecommunication
Systems
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
SO-8
Absolut e Maximum Rati ngs
Parameter Units
VDS Dr ain-t o-Source Vo ltage V
VGS Gat e- to-S ource Voltage
ID @ TA = 25 °C Co nti n uous D r ai n C ur r e nt, VGS @ 10V
ID @ TA = 70 °C
Co nti n uous D r ai n C ur r e nt, V
GS
@ 10V
A
IDM
Pulsed Dr ain Cur r ent
c
PD @TA = 25°C
Power Dissipation
f
W
PD @TA = 70°C
Power Dissipation
f
Linear Derating Fact or W/°C
TJ Operating Junction and °C
TSTG Stor ag e Tem per atur e Ra ng e
Thermal Resist ance
Parameter Typ. Max. Units
RθJL Junc ti on-to-Drai n Lead ––– 20 °C/W
RθJA
Junction-to-Ambient
f
––– 50
-55 to + 150
2.5
0.02
1.6
Max.
11
8.7
88
± 20
30
PD - 95211B
VDSS RDS(on) max Qg(typ.
)
30V 13.8m
:
@VGS = 10V 7.2nC
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2www.irf.com
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS D rain- to-S ource Breakdown Vol tage 30 ––– ––– V
∆ΒVDSS/∆TJ B reakdo w n Vol t age Tem p. Coef f ic i e nt ––– 0. 0 23 ––– V /°C
RDS(on) Static Drai n- to-Sou rce On-Resistan ce ––– 11 13.8 mΩ
––– 14.5 18.2
VGS(th) Gate Threshold Voltag e 1.35 1.8 2.2 5 V
∆VGS(th) Gate Threshold Voltage Coeff icient ––– - 4.7 ––– mV/°C
IDSS Drain-t o-Source Leakage Cur rent ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reve rse Leakage ––– ––– - 100
gf s F orw a r d Transc onduc tanc e 22 – –– ––– S
QgTo tal Gat e Charge –– – 7.2 1 1
Qgs1 Pre-Vth Gate-to-Source C harge ––– 2.1 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.7 ––– nC
Qgd Gate-to-Drai n Charge ––– 2.7 –––
Qgodr G ate Ch ar g e O v er d r iv e ––– 1. 7 – –– Se e Fi g. 16
Qsw Switch Charge (Qgs2 + Qgd) ––– 3.4 –––
Qoss O utput C harge ––– 2.8 ––– n C
RGGate Resistance ––– 2.5 4.8 Ω
td(on) T urn-On Delay Ti me ––– 6.9 –––
trRise Time ––– 6.2 –––
td(off) Turn-Off Delay Time ––– 10 ––– ns
tfFall Time ––– 3.1 –––
Ciss Input Capacitanc e ––– 770 –––
Coss Output Capacitance ––– 190 ––– pF
Crss Rever s e Tr ansfer Capacitance ––– 100 –––
Aval anche C haract eristi cs
Parameter Units
EAS Single Pul se Avalanche Ener gy
d
mJ
IAR Avalanche Current
c
A
Diode Charac teri stics
Parameter Min. Typ. Max. Units
ISCo nti n uous S o ur c e Cu rr ent – –– ––– 3. 1
(Body Diode) A
ISM Pulsed Source Current ––– ––– 88
(Body Diode)
c
VSD Di ode For war d V ol t a ge ––– ––– 1. 0 V
trr Reve rse Reco ver y Time ––– 31 46 ns
Qrr Reverse Recovery Cha r ge ––– 17 26 nC
Conditions
Max.
63
8.8
ƒ = 1. 0M H z
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 11A
e
MOSFET symbol
VDS = 15V , V GS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 8.8A
VDS = 15V
VGS = 20V
VGS = -20V
VDS = 24V , V GS = 0V
TJ = 25°C, IF = 8.8A, VDD = 15 V
di /dt = 100A/µ s
e
TJ = 25°C, IS = 8.8A, VGS = 0V
e
showing the
integra l revers e
p-n junction di ode.
VGS = 4.5V, ID = 8. 8A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 250µ A
Cla m ped I n duc t iv e Load
VDS = 15V , I D = 8.8A
VDS = 24V , V GS = 0V , TJ = 125°C
–––
ID = 8.8A
VGS = 0V
VDS = 15V
IRF7807ZPbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0 1 10 1000.1 110 100
VDS, Dr ain-to-Source V oltage (V )
0.1
1
10
100
ID, Drain-to-Source Current (A)
20µs PU LSE WID TH
Tj = 25°C
2.5V
VGS
TOP 10V
8.0V
4.5V
3.8V
3.3V
3.0V
2.8V
BOTTOM 2.5V
0 1 10 1000.1 110 100
VDS, Drai n-to- Source V oltage (V )
1
10
100
ID, Drain-to-Source Current (A)
20µs PU LSE WID TH
Tj = 150°C
2.5V
VGS
TOP 10V
8.0V
4.5V
3.8V
3.3V
3.0V
2.8V
BOTTOM 2.5V
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junct ion Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 11A
VGS = 10V
2.0 3.0 4.0 5.0 6.0
VGS, Gate-t o-Source Voltage (V)
1.0
10.0
100.0
ID, Drain-to-Source Current (Α)
VDS = 15V
20µs PU LSE WID TH
TJ = 25°C
TJ = 150°C
IRF7807ZPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to-Source V oltage (V)
10
100
1000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0481216
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 8.8A
0.1 1.0 10.0 100.0 1000.0
VDS , D rain- toSour ce Voltage (V )
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-toD rain Voltage (V )
0.1
1.0
10.0
100.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
IRF7807ZPbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
25 50 75 100 125 150
TJ , Junct ion Tem perature (°C )
0
2
4
6
8
10
12
ID , Drain Current (A)
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
1.0
1.2
1.4
1.6
1.8
2.0
2.2
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration ( s ec)
0.001
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W) τi (sec)
5.770 0.002691
24.37 0.54585
19.86 7.25
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
IRF7807ZPbF
6www.irf.com
D.U.T. VD
S
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150
Start ing TJ, Juncti on Temperatur e (°C )
0
50
100
150
200
250
300
EAS, Single Pulse Avalanche Energy (mJ)
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
ID
TOP 1.2A
1.5A
BOTTOM 8.8A
IRF7807ZPbF
www.irf.com 7
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF7807ZPbF
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs2
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
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SO-8 Part Marking
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SO-8 Package Outline
Dimensions are shown in millimeters (inches)
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IRF7807ZPbF
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Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 1.6mH
RG = 25Ω, IAS = 8.8A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/2006
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
N
OTES:
1
. CONTROLLING DIMENSION : MILL IMETER.
2
. AL L DIMENS IONS ARE SHOWN IN MILLIMETERS(INCHES).
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
