1. Features
•Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
•Internally Organized as 16,384 x 8
•Two-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•1 MHz (5.5V, 2.5V), and 400 kHz (1.8V) Compatibility
•Write Protect Pin for Hardware and Software Data Protection
•64-byte Page Write Mode (Partial Page Writes Allowed)
•Self-timed Write Cycle (5 ms Max)
•High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
•Lead-free/Halogen-free
•8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead
Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 Packages
•Die Sales: Wafer Form, Tape and Reel and Bumped Wafers
2. Description
The AT24C128B provides 131,072 bits of serial electrically erasable and programma-
ble read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini
MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball
dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V)
version.
Two-wire Serial
EEPROM
128K (16,384 x 8)
AT24C128B
Not Recommended
for New Design
Rev. 5296A–SEEPR–1/08
Table 0-1. Pin Configurations
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
GND Ground
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8
7
6
5
1
2
3
4
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead PDIP 8-lead SOIC
8-lead dBGA2
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
8-lead TSSOP
Bottom View
8
7
6
5
1
2
3
4
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead Ultra Thin Mini MAP
Bottom View
8
7
6
5
1
2
3
4
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead Ultra Lead Frame Land Grid Array
Bottom View
2
5296A–SEEPR–1/08
AT24C128B
Figure 3-1. Block Diagram
3. Absolute Maximum Ratings*
Operating Temperature 55C to +125C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground 1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
START
STOP
LOGIC
VCC
GND
WP
SCL
SDA
A
2
A
1
A
0
SERIAL
CONTROL
LOGIC
EN H.V. PUMP/TIMING
EEPROM
DATA RECOVERY
SERIAL MUX
X DEC
D
OUT
/ACK
LOGIC
COMP
LOAD INC
DATA WO R D
ADDR/COUNTER
Y DEC
R/W
D
OUT
D
IN
LOAD
DEVICE
ADDRESS
COMPARATOR
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5296A–SEEPR–1/08
AT24C128B
4. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM
device and negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs
that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as eight 128K devices may be addressed on a single bus
system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device
is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci-
tive coupling that may appear during customer applications, Atmel recommends always
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kor less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected directly to Vcc, all write operations to the memory are inhib-
ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends
using 10kor less.
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5296A–SEEPR–1/08
AT24C128B
5. Memory Organization
AT24C128B, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages of 64
bytes each. Random word addressing requires a 14-bit data word address.
Table 5-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
Table 5-2. DC Characteristics
Notes: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA=25C, f = 1.0 MHz, VCC = +1.8V to 5.5V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O =0V
CIN Input Capacitance (A0,A
1, SCL) 6 pF VIN =0V
Applicable over recommended operating range from: TAI =40C to +85C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA
ISB1
Standby Current
(1.8V option)
VCC = 1.8V VIN =V
CC or VSS
1.0 µA
VCC = 5.5V 6.0 µA
ILI
Input Leakage Current
VCC = 5.0V VIN =V
CC or VSS 0.10 3.0 µA
ILO
Output Leakage
Current
VCC = 5.0V
VOUT =V
CC or VSS 0.05 3.0 µA
VIL Input Low Level(1) VCC x 0.3 V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
5
5296A–SEEPR–1/08
AT24C128B
Table 5-3. AC Characteristics (Industrial Temperature)
Notes: 1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL(connects to VCC): 1.3 k(2.5V, 5.5V), 10 k(1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 50 ns
Input and output timing reference voltages: 0.5 VCC
Applicable over recommended operating range from TAI =40C to +85C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
Symbol Parameter
1.8-volt 2.5, 5.5-volt
UnitsMin Max Min Max
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.3 0.4 µs
tHIGH Clock Pulse Width High 0.6 0.4 µs
tiNoise Suppression Time(1) 100 50 ns
tAA Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs
tBUF
Time the bus must be free before a
new transmission can start(1) 1.3 0.5 µs
tHD.STA Start Hold Time 0.6 0.25 µs
tSU.STA Start Set-up Time 0.6 0.25 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 100 100 ns
tRInputs Rise Time(1) 0.3 0.3 µs
tFInputs Fall Time(1) 300 100 ns
tSU.STO Stop Set-up Time 0.6 0.25 µs
tDH Data Out Hold Time 50 50 ns
tWR Write Cycle Time 5 5 ms
Endurance(1) 25°C, Page Mode, 3.3V 1,000,000 Write
Cycles
6
5296A–SEEPR–1/08
AT24C128B
6. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see Figure 6-1). Data
changes during SCL high periods will indicate a start or stop condition as defined below.
Figure 6-1. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must
precede any other command (see Figure 6-2).
Figure 6-2. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 6-2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge
that it has received each word.
STANDBY MODE: The AT24C128B features a low-power standby mode that is enabled upon
power-up and after the receipt of the stop bit and the completion of any internal operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
SDA
SCL
DATA STABLE DATA STABLE
DATA
CHANGE
SDA
SCL
START STOP
7
5296A–SEEPR–1/08
AT24C128B
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Figure 6-3. Software Reset
Figure 6-4. Bus Timing
Figure 6-5. Write Cycle Timing
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Start bit Stop bitStart bitDummy Clock Cycles
SCL
SDA
123 89
SCL
SDA IN
SDA OUT
tF
tHIGH
tLOW tLOW
tR
tAA tDH tBUF
tSU.STO
tSU.DAT
tHD.DAT
tHD.STA
tSU.STA
twr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
8
5296A–SEEPR–1/08
AT24C128B
Figure 6-6. Output Acknowledge
7. Device Addressing
The 128K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 7-1). The device address word consists of a
mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to
all two-wire EEPROM devices.
Figure 7-1. Device Address
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on
the same bus. These bits must compare to their corresponding hardwired input pins. The A2,
A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the
pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini-
tiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,
the device will return to a standby state.
DATA SECURITY: The AT24C128B has a hardware data protection scheme that allows the user
to write protect the whole memory when the WP pin is at VCC.
SCL
DATA IN
DATA OUT
START ACKNOWLEDGE
9
8
1
MSB
1 0 1 0 A2 A1 A0 R/W
LSB
9
5296A–SEEPR–1/08
AT24C128B
8. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must
then terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8-1).
Figure 8-1. Byte Write
Note: *= DON’T CARE bit
PAGE WRITE: The 128K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller must termi-
nate the page write sequence with a stop condition (see Figure 8-2).
Figure 8-2. Page Write
Note: *= DON’T CARE bit
The data word address lower six bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0”, allowing the read or write sequence to continue.
10
5296A–SEEPR–1/08
AT24C128B
9. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read, and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input “0” but does generate a following stop condition (see Figure 9-1).
Figure 9-1. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition (see Figure 9-2).
Figure 9-2. Random Read
Note: *= DON’T CARE bit
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
12
5296A–SEEPR–1/08
AT24C128B
Notes: 1. “-B” denotes bulk.
2. “-T” denotes and tape and reel. SOIC = 4K. TSSOP, dBGA2, and Mini MAP = 5k. SAP = 3K.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
10. AT24C128B Ordering Information
Ordering Code Voltage Package Operation Range
AT24C128B-PU (Bulk Form Only) 1.8 8P3
Lead-free/Halogen-free
Industrial Temperature
40Cto85C)
AT24C128BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1
AT24C128BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1
AT24C128B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2
AT24C128B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2
AT24C128BY6-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y6
AT24C128BD3-DH-T(2) (NiPdAu Lead Finish) 1.8 8D3
AT24C128BU2-UU-T(2) 1.8 8U2-1
AT24C128B-W-11(3) 1.8 Die Sale Industrial Temperature
40Cto85C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini MAP, Dual No Lead Package, (DFN), (MLP2x3mm)
8D3 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA)
8U2-1 8-ball, die Ball Grid Array Package (dBGA2)
Options
1.8 Low-voltage (1.8V to 5.5V)
13
5296A–SEEPR–1/08
AT24C128B
11. Part marking scheme
11.1 8-PDIP
11.2 8-SOIC
TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L U Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 D B 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark
TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L H Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
2 D B 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark
14
5296A–SEEPR–1/08
AT24C128B
11.3 8-TSSOP
11.4 8-Ultra Thin Mini-MAP
TOP MARK
Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK
| 6: 2006 0: 2010 02 = Week 2
|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
* H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
2 D B 1 * 50 = Week 50
|---|---|---|---|---| 52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0 C00 = Country or Origin
|---|---|---|---|---|---|---|
A A A A A A A AAA = Atmel Lot Number
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
2 D B XX = ATMEL LOT NUMBER TO COORESPOND WITH
|---|---|---| NSEB TRACE CODE LOG BOOK.
H 1 (e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y X X
|---|---|---| Y = SEAL YEAR
* 6: 2006 0: 2010
| 7: 2007 1: 2011
Pin 1 Indicator (Dot) 8: 2008 2: 2012
9: 2009 3: 2013
15
5296A–SEEPR–1/08
AT24C128B
11.5 8-ULA
11.6 dBGA2
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---| XX = ATMEL LOT NUMBER TO COORESPOND WITH
2 D B NSEB TRACE CODE LOG BOOK.
|---|---|---| (e.g. XX = AA, AB, AC,...AX, AY, AZ)
Y X X
|---|---|---|
* Y = BUILD YEAR
| 6: 2006
Pin 1 Indicator (Dot) 7: 2007
8: 2008
Etc...
TOP MARK
LINE 1-------> 2DBU
LINE 2-------> PYMTC
|<-- Pin 1 This Corner
P = COUNTRY OF ORIGIN
Y = ONE DIGIT YEAR CODE
4: 2004 7: 2007
5: 2005 8: 2008
6: 2006 9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
TC = TRACE CODE (ATMEL LOT
NUMBERS TO CORRESPOND
WITH ATK TRACE CODE LOG BOOK)
16
5296A–SEEPR–1/08
AT24C128B
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A
–
–
0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005
–
–
3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
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5296A–SEEPR–1/08
AT24C128B
8S1 - JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
θ 0° – 8°
Ø
Ø
E
E
1
1
N
N
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
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5296A–SEEPR–1/08
AT24C128B
8A2 - TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
19
5296A–SEEPR–1/08
AT24C128B
8Y6 – MAP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3) D
8Y6
10/16/07
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 - - 1.40
A - - 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2
A2
A2
b
(8X)
(8X)
Pin 1 ID
Pin 1 ID
Pin 1
Pin 1
Index
Index
Area
Area
A1
A1
A3
A3
D
E
A
L (8X)
L (8X)
e (6X)
e (6X)
1.50 REF.
1.50 REF.
D2
D2
E2
E2
20
5296A–SEEPR–1/08
AT24C128B
8D3 - ULA
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULA) D3 0
8D3
11/15/05
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX NOTE
A – – 0.40
A1 0.00 – 0.05
D 1.70 1.80 1.90
E 2.10 2.20 2.30
b 0.15 0.20 0.25
e 0.40 TYP
e1 1.20 REF
L 0.25 0.30 0.35
0.10
0.15
b
657
4
3
E
D
8
12
PIN #1 ID
TOP VIEW
L
b
A1
Ae
PIN #1 ID
SIDE VIEW BOTTOM VIEW
e1
21
5296A–SEEPR–1/08
AT24C128B
8U2-1 - dBGA2
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
PO8U2-1 A
6/24/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
A 0.81 0.91 1.00
A1 0.15 0.20 0.25
A2 0.40 0.45 0.50
b 0.25 0.30 0.35 1
D 2.35 BSC
E 3.73 BSC
e 0.75 BSC
e1 0.74 REF
d 0.75 BSC
d1 0.80 REF
1. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
d
A
Side View
Top View
Bottom View
8 Solder Balls
1
A
B
C
D
2
(e1)
e
A1 BALL PAD CORNER
(d1)
1. b
A1
A2
D
A1 BALL PAD CORNER
E
22
5296A–SEEPR–1/08
AT24C128B
Revision History
Doc. Rev. Date Comments
5296A 1/2008
AT24C128B product with date code 2008 work week 14 (814) or later
supports 5Vcc operation
Initial document release
5296A–SEEPR–1/08
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