Silicon SPDT Switch, Reflective, 100 MHz to 44 GHz ADRF5024 Data Sheet RF2 FUNCTIONAL BLOCK DIAGRAM ADRF5024 VSS DRIVER RFC CTRL VDD 16011-001 Ultrawideband frequency range: 100 MHz to 44 GHz Reflective design Low insertion loss with impedance match 1.0 dB typical to 18 GHz 1.4 dB typical to 40 GHz 1.7 dB typical to 44 GHz Low insertion loss without impedance match 0.9 dB typical to 18 GHz 1.7 dB typical to 40 GHz 2.1 dB typical to 44 GHz High input linearity P1dB: 27.5 dBm typical IP3: 50 dBm typical High RF input power handling Through path: 27 dBm Hot switching: 27 dBm No low frequency spurious RF settling time (50% VCTRL to 0.1 dB of final RF output): 17 ns 12-terminal, 2.25 mm x 2.25 mm LGA package Pin compatible with the ADRF5025 low frequency cutoff version RF1 FEATURES Figure 1. APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5024 is a reflective, single-pole double-throw (SPDT) switch manufactured in the silicon process. The ADRF5024 is pin-compatible with the ADRF5025, low frequency cutoff version, which operates from 9 kHz to 44 GHz. This switch operates from 100 MHz to 44 GHz with better than 1.7 dB of insertion loss and 35 dB of isolation. The ADRF5024 has a radio frequency (RF) input power handling capability of 27 dBm for both the through path and hot switching. The ADRF5024 RF ports are designed to match a characteristic impedance of 50 . For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Electrical Specifications section, Typical Performance Characteristics section, and Applications Information section for more details. The ADRF5024 draws a low current of 14 A on the positive supply of +3.3 V and 120 A on negative supply of -3.3 V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)compatible controls. Rev. C The ADRF5024 comes in a 2.25 mm x 2.25 mm, 12-terminal, RoHS-compliant, land grid array (LGA) package and can operate between -40C to +105C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5024 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ...................................................................................... 1 Typical Performance Characteristics .............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept ..........8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications .................................................................................... 3 Applications Information ............................................................. 10 Electrical Specifications ............................................................... 3 Evaluation Board ........................................................................ 10 Absolute Maximum Ratings ........................................................... 5 Probe Matrix Board ................................................................... 12 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13 Power Derating Curves ............................................................... 5 Ordering Guide .......................................................................... 13 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions ............................ 6 REVISION HISTORY 8/2020--Rev. B to Rev. C Changes to Figure 7 and Figure 10 ................................................ 7 5/2020--Rev. A to Rev. B Change to Return Loss Parameter, Table 1 .................................. 3 Changes to Table 2 ........................................................................... 5 Changes to Insertion Loss, Return Loss, and Isolation Section, Figure 7, Figure 8, Figure 10, and Figure 11 ................................. 7 Changes to Theory of Operation Section...................................... 9 5/2018--Rev. 0 to Rev. A Updated Outline Dimensions ..................................................... 13 Changes to Ordering Guide .......................................................... 13 5/2018--Revision 0: Initial Version Rev. C | Page 2 of 13 Data Sheet ADRF5024 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, VCTRL = 0 V or VDD, and case temperature (TCASE) = 25C for 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1/RF2 (On) With Impedance Match Symbol f See Figure 24 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz See Figure 25 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz Without Impedance Match RETURN LOSS RFC and RF1/RF2 (On) With Impedance Match ISOLATION Between RFC and RF1/RF2 Between RF1 and RF2 tRISE, tFALL tON, tOFF Min 100 Typ Max 44,000 Unit MHz 1.0 1.4 1.4 1.4 1.7 dB dB dB dB dB 0.9 1.1 1.5 1.7 2.1 dB dB dB dB dB 17 13 13 18 12 dB dB dB dB dB 21 17 13 12 10 dB dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 42 41 38 36 35 47 45 44 42 38 dB dB dB dB dB dB dB dB dB dB 10% to 90% of RF output 50% VCTRL to 90% of RF output 2 10 ns ns 50% VCTRL to 0.1 dB of final RF output 50% VCTRL to 0.05 dB of final RF output 17 22 ns ns See Figure 24 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz See Figure 25 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz Without Impedance Match SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time RF Settling Time 0.1 dB 0.05 dB Test Conditions/Comments Rev. C | Page 3 of 13 ADRF5024 Parameter INPUT LINEARITY1 1 dB Power Compression Third-Order Intercept SUPPLY CURRENT Positive Supply Current Negative Supply Current DIGITAL CONTROL INPUTS Voltage Low High Current Low and High RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Voltage RF Input Power2 Through Path Data Sheet Symbol P1dB IP3 Min Two tone input power = 12 dBm each tone, f = 1 MHz VDD and VSS pins IDD ISS Typ Max Unit 27.5 50 dBm dBm 14 120 A A CTRL pin VINL VINH 0 1.2 IINL, IINH VDD VSS VCTRL PIN Hot Switching Case Temperature Test Conditions/Comments 200 MHz to 40 GHz 0.8 3.3 <1 3.15 -3.45 0 f = 200 MHz to 40 GHz, TCASE = 85C3 RF signal is applied to RFC or through connected RF1/RF2 RF signal is present at RFC while switching between RF1 and RF2 TCASE -40 1 For input linearity performance over frequency, see Figure 13 to Figure 16. For power derating over frequency, see Figure 2 and Figure 3. 3 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 2 Rev. C | Page 4 of 13 V V A 3.45 -3.15 VDD V V V 27 dBm 27 dBm +105 C Data Sheet ADRF5024 ABSOLUTE MAXIMUM RATINGS For the recommended operating conditions, see Table 1. Table 3. Thermal Resistance Table 2. Package Type CC-12-3, Through Path Rating -0.3 V to +3.6 V -3.6 V to +0.3 V JC 352 Unit C/W POWER DERATING CURVES 2 27.5 dBm 27.5 dBm 21 dBm 0 POWER DERATING (dB) -0.3 V to VDD + 0.3 V 3 mA 135C -65C to +150C 260C -2 -4 -6 -8 -10 -14 10k 100k 1M 10M 100M 1G 10G 100G FREQUENCY (Hz) 16011-002 -12 Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 2 500 V 2000 V 1250 V 0 For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path and hot switching power specifications. 2 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. -2 -4 -6 -8 -10 -12 -14 35 38 41 44 FREQUENCY (GHz) 47 50 16011-003 1 POWER DERATING (dB) Parameter Positive Supply Voltage Negative Supply Voltage Digital Control Input Voltage Voltage Current RF Input Power1 (f = 200 MHz to 40 GHz, TCASE = 85C2) Through Path Hot Switching RF Input Power Under Unbiased Condition1 (VDD, VSS = 0 V) Temperature Junction, TJ Storage Range Reflow ESD Sensitivity Human Body Model (HBM) RFC, RF1, and RF2 Pins Digital Pins Charged Device Model (CDM) Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C ESD CAUTION THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JC is the junction to case bottom (channel to package bottom) thermal resistance. Rev. C | Page 5 of 13 ADRF5024 Data Sheet RFC 2 RF2 GND 12 11 10 ADRF5024 TOP VIEW (Not to Scale) 4 5 6 GND RF1 GND GND 3 9 VSS 8 CTRL 7 VDD NOTES 1. EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PCB. 16011-004 GND 1 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1, 3, 4, 6, 10, 12 2 Mnemonic GND RFC 5 RF1 7 8 9 11 VDD CTRL VSS RF2 EPAD Description Ground. These pins must be connected to the RF/dc ground of the PCB. RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. RF Port 1. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. Positive Supply Voltage. Control Input Voltage. See Figure 6 for the interface schematic. Negative Supply Voltage. RF Port 2. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. INTERFACE SCHEMATICS VDD 16011-005 VDD CTRL 16011-006 RFC, RF1, RF2 Figure 6. CTRL Interface Schematic Figure 5. RFx Pins Interface Schematic Rev. C | Page 6 of 13 Data Sheet ADRF5024 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = -3.3 V, VCTRL = 0 V or VDD, and TCASE = 25C for a 50 system, unless otherwise noted. Insertion loss, return loss and isolation are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. See the Applications Information section for details on the evaluation and probe matrix boards. TCASE TCASE TCASE TCASE TCASE INSERTION LOSS (dB) -1.0 -1.5 -2.0 -2.5 -1.0 -2.0 -2.5 -3.0 -3.5 -3.5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) -4.0 -15 -15 -20 -20 -25 -25 -30 -30 -35 -35 5 10 15 20 25 30 35 40 45 -40 50 0 5 10 15 Figure 8. Return Loss vs. Frequency for RFC and RFx (On) with Impedance Match -20 -20 ISOLATION (dB) -10 -30 -40 -50 45 50 -70 15 20 25 30 20 25 30 35 40 45 50 35 40 45 FREQUENCY (GHz) 50 RFC TO RFx RFx TO RFx -50 -70 10 40 -40 -60 5 35 -30 -60 -80 16011-009 ISOLATION (dB) 0 RFC TO RFx RFx TO RFx 0 30 Figure 11. Return Loss vs. Frequency for RFC and RFx (On) Without Impedance Match -10 -80 25 FREQUENCY (GHz) FREQUENCY (GHz) 0 20 RFC RF1 ON RF2 ON -5 -10 0 15 0 -10 -40 10 Figure 10. Insertion Loss vs. Frequency Without Impedance Match RFC RF1 ON RF2 ON -5 5 FREQUENCY (GHz) Figure 7. Insertion Loss vs. Frequency with Impedance Match 0 0 16011-011 5 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) Figure 9. Isolation vs. Frequency with Impedance Match Figure 12. Isolation vs. Frequency Without Impedance Match Rev. C | Page 7 of 13 16011-012 0 = -55C = -40C = +25C = +85C = +105C -1.5 -3.0 -4.0 TCASE TCASE TCASE TCASE TCASE -0.5 16011-007 INSERTION LOSS (dB) -0.5 0 = -55C = -40C = +25C = +85C = +105C 16011-010 0 ADRF5024 Data Sheet INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT VDD = 3.3 V, VSS = -3.3 V, VCTRL = 0 V or VDD, and TCASE = 25C for a 50 system, unless otherwise noted. All of the large signal performance parameters were measured on the evaluation board. 30 30 28 28 26 24 INPUT P1dB (dBm) 22 20 18 16 20 18 16 5 10 15 20 25 30 35 40 FREQUENCY (GHz) 10 10k 16011-013 0 55 55 50 50 INPUT IP3 (dBm) 60 45 40 35 35 25 25 20 25 30 35 40 20 10k 16011-014 15 FREQUENCY (GHz) 1G 40 30 10 100M 45 30 5 10M Figure 15. Input P1dB vs. Frequency (Low Frequency Detail) 60 0 1M FREQUENCY (Hz) Figure 13. Input P1dB vs. Frequency 20 100k 16011-015 12 12 INPUT IP3 (dBm) 22 14 14 10 24 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 16. Input IP3 vs. Frequency (Low Frequency Detail) Figure 14. Input IP3 vs. Frequency Rev. C | Page 8 of 13 16011-016 INPUT P1dB (dBm) 26 Data Sheet ADRF5024 THEORY OF OPERATION The ADRF5024 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to filter high frequency noise. All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The RF ports are internally matched to 50 . Therefore, external matching networks are not required. However, impedance matching on transmission lines can be used to improve insertion loss and return loss performance at high frequencies. The unselected RF port of the ADRF5024 is reflective. The isolation path provides high isolation between the unselected port and the insertion loss path. The ideal power-up sequence is as follows: 1. 2. 3. The ADRF5024 integrates a driver to perform logic functions internally and provides the user with the advantage of a simplified CMOS/LVTTL-compatible control interface. This driver features a single digital control input pin, CTRL. The logic level applied to the CTRL pin determines which RF port is in the insertion loss state and in the isolation state (see Table 5). 4. Connect GND. Power up VDD and VSS. Power up VSS after VDD to avoid current transients on VDD during ramp-up. Apply the digital control inputs. The relative order of the control inputs is not important. However, powering the digital control inputs before the VDD supply may inadvertently forward bias and damage the internal ESD protection structures. To avoid this damage, use a series 1 k resistor to limit the current flowing in to the control pin. Use pull-up or pull-down resistors if the controller is in a high impedance state after VDD is powered up and the control pins are not driven to a valid logic state. Apply an RF input signal. The ideal power-down sequence is the reverse order of the power-up sequence. Table 5. Control Voltage Truth Table Digital Control Input (VCTRL) Low High RF1 to RFC Isolation (off) Insertion loss (on) Rev. C | Page 9 of 13 RF Path RF2 to RFC Insertion loss (on) Isolation (off) ADRF5024 Data Sheet APPLICATIONS INFORMATION THRU CAL can be used to calibrate out the board loss effects from the ADRF5024-EVALZ evaluation board measurements to determine the device performance at the pins of the IC. Figure 19 shows the typical board loss for the ADRF5024EVALZ evaluation board at room temperature, the embedded insertion loss, and the de-embedded insertion loss for the ADRF5024. EVALUATION BOARD The ADRF5024-EVALZ is a 4-layer evaluation board. The outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. Figure 17 shows the evaluation board stackup. W = 14mil 1.5oz Cu (2.2mil) G = 7mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) T = 2.2mil 0 H = 8mil RO4003 -1 16011-017 0.5oz Cu (0.7mil) 1.5oz Cu (2.2mil) -3 -4 -5 -6 Figure 17. Evaluation Board (Cross Section View) -7 All RF and dc traces are routed on the top copper layer, whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 8 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. WITH IMPEDANCE MATCH 16011-018 WITHOUT IMPEDANCE MATCH -2 Figure 18. Evaluation Board Layout, Top View The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with trace width of 14 mil and ground clearance of 7 mil to have a characteristic impedance of 50 . For optimal RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. The ADRF5024-EVALZ has two layouts implemented, with and without impedance matching. By default, the impedance matched circuit is populated. For more details on this impedance matched circuit, refer to Impedance Matching in the Probe Matrix Board section. THRU LOSS EMBEDDED INSERTION LOSS DEEMBEDDED INSERTION LOSS 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) 16011-021 INSERTION LOSS (dB) TOTAL THICKNESS -62mil 0.5oz Cu (0.7mil) Figure 19. Insertion Loss vs. Frequency Figure 20 shows the actual ADRF5024-EVALZ with its component placement. Two power supply ports are connected to the VDD and VSS test points, TP7 and TP5 (or TP3 and TP1 if using without impedance match circuit), and the ground reference is connected to the GND test point, TP4 or TP8. On the supply traces, VDD and VSS, a 100 pF bypass capacitor filters high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors. A control port is connected to the CTRL test point, TP6 (or TP2 for without impedance match circuit). There are provisions for the resistor capacitor (RC) filter to eliminate dccoupled noise, if needed, by the application. The resistor can also improve the isolation between the RF and the control signal. The RF input and output ports (RFC, RF1, and RF2) are connected through 50 transmission lines to the 2.4 mm RF launchers, J10, J9, and J8 (or J2, J3, and J1 for without impedance match circuit), respectively. These high frequency RF launchers are by contact and are not soldered to the board. A THRU CAL line connects the unpopulated J6 and J7 launchers (or J4 and J5 for without impedance match circuit). This transmission line is used to estimate the loss due to the PCB over the environmental conditions being evaluated. The schematic of the ADRF5024-EVALZ evaluation board is shown in Figure 21. Rev. C | Page 10 of 13 ADRF5024 16011-019 Data Sheet Figure 20. Evaluation Board Component Placement GND RF2 GND 12 11 10 RF2 EPAD VSS GND 1 9 VSS 100pF RFC 2 RFC ADRF5024 VCTRL 0 8 CTRL VDD GND 3 7 VDD RF1 THRU CAL 16011-020 GND 6 5 RF1 GND 4 100pF Figure 21. Simplified Evaluation Board Schematic Table 6. Evaluation Board Components Component C8, C9 J8 to J10 R2 TP5 to TP8 U2 PCB Default Value 100 pF Not applicable 0 Not applicable ADRF5024 08-046672E Description Capacitors, C0402 package 2.4 mm end launch connectors (Southwest Microwave: 1492-04A-5) Resistor, 0402 package Through hole mount test points ADRF5024 SPDT switch, Analog Devices, Inc. Evaluation PCB, Analog Devices Rev. C | Page 11 of 13 ADRF5024 Data Sheet PROBE MATRIX BOARD Impedance Matching The probe matrix board is a 4-layer board. Similar to the evaluation board, this board also uses a 8 mil Rogers RO4003 dielectric. The outer copper layers are 0.5 oz (0.7 mil) copper plated to 1.5 oz (2.2 mil). The RF transmission lines were designed using a CPWG model with a width of 14 mil and ground spacing of 7 mil to have a characteristic impedance of 50 . Impedance matching at the RFx pins can improve the insertion loss and return loss at high frequencies. Figure 24 and Figure 25 show the difference in the transmission lines at the RFC, RF1, and RF2 pins. This same circuit is implemented on the probe matrix boards and the evaluation boards. Figure 22 and Figure 23 show the cross section and top view of the board, respectively. Measurements are made using GSG probes at close proximity to the RFx pins. Unlike the evaluation board, probing reduces reflections caused by mismatch arising from connectors, cables, and board layout, resulting in a more accurate measurement of the device performance. W = 14mil 1.5oz Cu (2.2mil) The dimensions of the 50 lines are 14 mil trace width and 7 mil gap. To implement this impedance matched circuit, a 5 mil trace with a width of 5 mils was inserted between the pin pad and the 50 trace. The calibration kit reference kit does not include the 5 mil matching line, and therefore, the measured insertion loss includes the losses of the matching circuit. G = 7mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) T = 2.2mil RO4003 H = 8mil 0.5oz Cu (0.7mil) Figure 22. Probe Matrix Board (Cross Section View) 16011-023 1.5oz Cu (2.2mil) 16011-021 TOTAL THICKNESS -62mil 0.5oz Cu (0.7mil) 16011-022 Figure 24. With Impedance Match The probe matrix board includes a through reflect line (TRL) calibration kit allowing board loss de-embedding. The actual board duplicates the same layout in matrix form to assemble multiple devices at one time. All S parameters were measured on this board. Rev. C | Page 12 of 13 16011-024 Figure 23. Probe Board Layout (Top View) Figure 25. Without Impedance Match Data Sheet ADRF5024 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.85 0.80 0.75 0.633 BSC 0.567 BSC 0.818 BSC PIN 1 INDICATOR 0.10 x 0.45 0.40 BSC 10 12 1 9 0.75 0.70 0.65 0.80 REF 7 3 6 0.325 0.275 0.225 TOP VIEW END VIEW 0.53 REF 0.250 BOTTOM VIEW 0.200 0.150 0.26 0.22 0.18 PKG-005304 0.85 0.75 0.65 4 0.775 BSC 0.125 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 05-10-2018-C 2.35 2.25 2.15 Figure 26. 12-Terminal Land Grid Array [LGA] 2.25 mm x 2.25 mm Body and 0.75 mm Package Height (CC-12-3) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5024BCCZN ADRF5024BCCZN-R7 ADRF5024-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 12-Terminal Land Grid Array [LGA] 12-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2018-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16011-8/20(C) Rev. C | Page 13 of 13 Package Option CC-12-3 CC-12-3 Marking Code 24 24