AME, Inc.
13
AME8550 V oltage Detector
1. When input voltage (VDD) rises above detect voltage
(VDF), output voltage (VOUT) will be equal to VDD.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (VDD) falls below detect voltage
(VDF), output voltage (VOUT) will be equal to the ground
voltage (VSS) level.
3. When input voltage (VDD) falls to a level below that of
the minimum operating voltage (VMIN), output will become
unstable. In this condition, VDD will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (VDD) rises above the ground volt-
age (VSS) level, output will be unstable at levels below the
minimum operating voltage (VMIN). Between the VMIN and
detect release voltage (VDR) levels, theground voltage (VSS)
level will be maintained.
5. When input voltage (VDD) rises above detect release
voltage (VDR), output voltage (VOUT) will be equal to VDD
after TD delay time.
Q = V x C = I x TD
T= V=VREF
For Example, TD=
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between VDR and VDF represents the
hysteresis range.
n Functional Description
(CMOS output without delay)
1. When input voltage (VDD) rises above detect voltage
(VDF), output voltage (VOUT) will be equal to VDD.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (VDD) falls below detect voltage
(VDF), output voltage (VOUT) will be equal to the ground
voltage (VSS) level.
3. When input voltage (VDD) falls to a level below that of
the minimum operating voltage (VMIN), output will become
unstable. In this condition, VDD will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (VDD) rises above the ground volt-
age (VSS) level, output will be unstable at levels below the
minimum operating voltage (VMIN). Between the VMIN and
detect release voltage (VDR) levels, theground voltage (VSS)
level will be maintained.
5. When input voltage (VDD) rises above detect release
voltage (VDR), output voltage (VOUT) will be equal to VDD.
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between VDR and VDF represents the
hysteresis range.
n Timing Chart
n Functional Description
(CMOS output with delay)
n Timing Chart
Detect Vol tage (VDF)
Min. Operating Voltage (VMIN)
Output Voltage (VOUT)
Ground Voltage (Vss)
Ground Voltage (Vss)
Detect Release Voltage (VDR)
Input Voltage (VDD)
12 345
6
TD
Detect Vol tage (VDF)
Min. Operating Voltage (VMIN)
Output Voltage (VOUT)
Ground Voltage (Vss)
Ground Voltage (Vss)
Detect Release Voltage (VDR)
Input Voltage (VDD)
12 345
6
VxC
IVREF * 1nF
75nA