FS61857-01 1:10 HSTL Zero-Delay Clock Buffer IC AMERICAN MICROSYSTEMS, INC. Advance Information November 2000 1.0 * * Figure 1: Block Diagram Features Generates one bank of ten differential 2.5V HSTL clock outputs (YP0/YN0 to YP9/YN9) from one differential HSTL reference clock input Meets the JEDEC Standard PLL Clock Driver for Registered DIMM Applications External feedback input (FBINP/FBINN) to synchronize all clock outputs to the reference input * Operating frequency 60MHz to 170MHz * * Tight tracking skew (spread-spectrum tolerant) Integrated 25 series damping resistors for driving point-to-point loads * Auto power-down mode if reference input frequency drops below 20MHz * Active-low power-down signal (PWRDWN#) tristates all output drivers and disables the PLL * Packaged in a 48-pin TSSOP FBINP FBINN CKP CKN PLL AGND FS61857 Figure 2: Pin Configuration GND 1 48 GND YN0 2 47 YN5 YP0 3 46 YP5 VDD 4 45 VDD YP1 5 44 YP6 YN1 6 43 YN6 GND 7 42 GND GND 8 41 GND YN2 9 40 YN7 YP2 10 39 YP7 VDD 11 INPUT ZeroDelay OFF PLL Bypass OFF PWR AVDD DWN# OUTPUT CKP CKN YP0YP9 YN0YN9 VDD 12 FBOUT FBOUT P N 2.5V L L H Z Z Z Z 2.5V L H L Z Z Z 2.5V H L H L H L 2.5V H H L H L H CKP 13 CKN 14 VDD 15 FS61857 Table 1: Function Table OFF GND Description The FS61857 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC. Ten differential buffered clock outputs are derived from an onboard openloop PLL. The PLL aligns the frequency and phase of all output clock pairs to the differential reference input clock CLKP/CLKN, including a feedback output clock pair that feeds back to FBINP/FBINN to close the loop. The PLL can be bypassed for test purposes by pulling AVDD to ground. PLL YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4 YN4 YP5 YN5 YP6 YN6 YP7 YN7 YP8 YN8 YP9 YN9 FBOUTP FBOUTN Power Down PWRDWN# AVDD * 2.0 VDD 38 VDD 37 PWRDWN# 36 FBINP 35 FBINN 34 VDD Z AVDD 16 33 FBOUTN AGND 17 32 FBOUTP H GND 18 31 GND L YN3 19 30 YN8 YP3 20 29 YP8 VDD 21 28 VDD YP4 22 27 YP9 GND L L H Z Z Z Z GND L H L Z Z Z Z GND H L H L H L H YN4 23 26 YN9 GND H H L H L H L GND 24 25 GND - - <20MHz Z Z Z Z ISO9001 QS9000 This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. 11.14.00 FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information November 2000 Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME 16 P AVDD 2.5V PLL power supply / Test mode enable. This pin provides the power supply to the internal PLL. When pulled low, the PLL is bypassed and the output clocks directly follow the input clock PLL ground 17 P AGND 13 / 14 DI CKP / CKN 36 / 35 DI FBINP / FBINN 32 / 33 DO FBOUTP / FBOUTN 37 DI PWRDWN# 3/2 YP0 / YN0 5/6 YP1 / YN1 10 / 9 YP2 / YN2 20 / 19 YP3 / YN3 22 / 23 46 / 47 DO YP4 / YN4 YP5 / YN5 44 / 43 YP6 / YN6 39 / 40 YP7 / YN7 29 / 30 YP8 / YN8 27 / 26 YP9 / YN9 DESCRIPTION Reference clock input (true / complementary) Feedback input (true / complementary) Feedback output (true / complementary) Asynchronous power-down input shuts down PLL and tristates all outputs Clock outputs (true / complementary) 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 P GND Ground for all clock outputs 4, 11, 12, 15, 21, 28, 34, 38, 45 P VDD 2.5V power supply for all clock outputs 3.0 3.1 Device Operation When the AVDD pin is pulled low, the reference clock signal bypasses the PLL and is muxed directly through to the outputs. The PLL is powered down, and device acts a fanout buffer. Note that if AVDD is re-established, the PLL requires a power-up and stabilization time to lock to the input clock. The FS61857 precisely aligns the frequency and phase of the differential HSTL output clocks to the differential reference input CKP/CKN by use of an on-chip phaselock loop (PLL). The PLL generates 10 low-skew, lowjitter copies of the reference, with the outputs adjusted for 50% duty cycle. The differential FBOUT clock must be hardwired to the FBINP/FBINN pins to complete the loop. The PLL actively adjusts the output clocks so that there is no phase error between the reference clock and the feedback input. Since the device uses a PLL to lock the output clocks to the input clock, there is a power-up stabilization time that is required for the PLL to achieve phase lock. Note that all inputs and outputs use 2.5V HSTL signal levels. ISO9001 QS9000 PLL Bypass 3.2 Power-Down The FS61857 provides an auto power-down feature that shuts off the PLL and tristates all outputs low if the reference clock drops below 20MHz. The power-down circuit is level sensitive, and detects either a DC high or low on the CKP/CKN input pair. If the input clock rises above 20MHz, the PLL powers back up to re-establish lock. An asynchronous active-low PWRDWN# signal also places the part in the power off state. 2 FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information November 2000 4.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS AVDD GND-0.5 4 V VDD GND-0.5 4 V Input Voltage, dc VI GND-0.5 VDD+0.5 V Output Voltage, dc VO GND-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C Supply Voltage, dc, Clock Buffers (GND = ground) Supply Voltage, dc, Core Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 260 C 2 kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER Supply Voltage Ambient Operating Temperature Range Input Frequency (CKP / CKN) SYMBOL AVDD VDD fCLK TYP. MAX. 2.3 2.5 2.7 Outputs 2.3 2.5 2.7 0 70 Frequency range over which PLL acquires lock 60 170 Frequency range where all timing parameter specification are met 90 170 CKP / CKN 40 60 V C MHz % 0.375 1.5 ns 30 50 MHz Spread-Spectrum Modulation Index m 0 -0.5 % Output Load Capacitance CL 15 pF ISO9001 QS9000 CKP / CKN (over 20% to 80%) UNITS fm Spread-Spectrum Modulation Frequency tr, tf MIN. Core TA Input Duty Cycle Input Rise/Fall Time CONDITIONS/DESCRIPTION 3 FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information November 2000 Table 5: DC Electrical Specifications Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 200 300 mA 100 A Overall Supply Current, Dynamic, with Loaded Outputs IDD VDD = 2.7V, fCLK = 170MHz Supply Current, Static IDDL VDD = 2.7V, PWRDWN# low or fCLK < 20MHz Power Down Input (PWRDWN#) High-Level Input Voltage VIH 1.7 VDD+0.3 V Low-Level Input Voltage VIL GND-0.3 0.7 V -10 10 A VIN GND-0.3 VDD+0.3 V Crossover Voltage VIX VDD/2 -0.2 VDD/2 +0.2 V Differential Voltage VID Magnitude of the difference between the input level on CKP and the input level on CKN 0.36 VDD+0.6 VDD = 2.7V -10 10 A VI = 0V, as seen by an external clock driver 2.5 3.5 pF -12 mA 12 mA Input Leakage Current II VDD = 2.7V Differential Clock Inputs (CKP, CKN, FBINP, FBINN) Input Voltage Level Input Leakage Current Input Loading Capacitance * II CL(in) Differential Clock Outputs (YP0:9, YN0:9, FBOUTP, FBOUTN) High-Level Output Source Current Low-Level Output Sink Current IOH IOL Crossover Voltage VOX Differential Voltage VOD Output Impedance VDD = 2.3V, VO = 1.7V VDD = 2.3V, VO = 2.2V VDD = 2.3V, VO = 0.6V VDD = 2.3V, VO = 0.1V Magnitude of the difference between the output levels on YP0:9, FBOUTP and the output levels on YN0:9, FBOUTN zO Measured at 1.25V, output driving low zOL Measured at 1.25V, output driving high A -100 A 100 VDD/2 -0.2 VDD/2 +0.2 0.70 VDD+0.6 IOZ Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. mA Short Circuit Sink Current * IOSL VO = 2.5V; shorted for 30s, max. mA ISO9001 QS9000 -5 4 5 A Tristate Output Current FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information November 2000 Table 6: AC Timing Specifications Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. PARAMETER SYMBOL Clock Skew, Output to Output * tsk(o) CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Dynamic Phase Offset td Static Phase Offset t Clock Stabilization Time * Measured VX between two output pairs CL = 15pF ps Spread modulation ON ps Spread modulation ON Does not include jitter -120 120 Time required for the PLL to achieve phase lock ps ms Phase-Lock Loop Loop Bandwidth * For calculation of Tracking Skew Phase Angle * For calculation of Tracking Skew Phase Error * From rising edge on CLK to rising edge on FBIN 2.0 MHz -0.031 ps Clock Outputs (1Y0:9, FBOUT) Duty Cycle * dt 45 55 % Jitter, Cycle-cycle * (peak-peak) tj(CC) -75 75 ps Jitter, Period * (peak-peak) tj(P) -75 75 ps Jitter, Half-Period * (peak-peak) tj(1/2P) -100 100 ps Rise Time * tr VO = 0.5V to 2.0V; CL = 15pF 0.75 1.5 ns Fall Time * tf VO = 2.0V to 0.5V; CL = 15pF 0.75 1.5 ns Enable Delay * tDLH via PWRDWN# ns Disable Delay * tDHL via PWRDWN# ns ISO9001 QS9000 5 FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information 5.0 November 2000 Package Information Table 7: 48-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES A MILLIMETERS MIN. MAX. MIN. MAX. - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 D 0.488 0.496 12.40 12.60 E E1 e 0.318 BSC 0.236 0.244 0.018 S 1 E1 E AMERICAN MICROSYSTEMS, INC. 8.10 BSC 6.00 0.019 BSC L 48 6.20 0.50 BSC 0.030 0.45 0.75 0.008 - 0.20 - 0 8 0 8 2 12 REF 12 REF 3 12 REF 12 REF 1 b SEATING PLANE e A D A1 2 S c 3 L 1 Table 8: 48-pin TSSOP (6.1mm) Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 89 C/W nH Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s Lead Inductance, Self L11 Longest lead 3.50 L12 Longest lead to any 1st adjacent lead 1.82 L13 Longest lead to any 2nd adjacent lead 1.17 C11 Longest lead to VSS 0.63 C12 Longest lead to any 1st adjacent lead 0.30 C13 Longest lead to any 2nd adjacent lead 0.03 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 QS9000 6 nH pF pF FS61857-01 AMERICAN MICROSYSTEMS, INC. 1:10 HSTL Zero-Delay Clock Buffer IC Advance Information November 2000 6.0 Ordering Information Table 9: Device Ordering Codes DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION FS61857-01 13810-801 48-pin TSSOP (Thin Shrink Small Outline Package) 0 C to 70 C (Commercial) Tape and Reel Copyright (c) 2001 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 QS9000 7