AMERICAN MICROSYSTEMS, INC.
November 2000
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This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. 11.14.00
FS61857-01
FS61857-01FS61857-01
FS61857-01
1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
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1.0 Features
• Generates one bank of ten differential 2.5V HSTL
clock outputs (YP0/YN0 to YP9/YN9) from one differ-
ential HSTL reference clock input
• Meets the JEDEC Standard PLL Clock Driver for
Registered DIMM Applications
• External feedback input (FBINP/FBINN) to synchro-
nize all clock outputs to the reference input
• Operating frequency 60MHz to 170MHz
• Tight tracking skew (spread-spectrum tolerant)
• Integrated 25Ω series damping resistors for driving
point-to-point loads
• Auto power-down mode if reference input frequency
drops below 20MHz
• Active-low power-down signal (PWRDWN#) tristates
all output drivers and disables the PLL
• Packaged in a 48-pin TSSOP
2.0 Description
The FS61857 is a low skew, low jitter CMOS zero-delay
phase-lock loop (PLL) clock buffer IC. Ten differential
buffered clock outputs are derived from an onboard open-
loop PLL. The PLL aligns the frequency and phase of all
output clock pairs to the differential reference input clock
CLKP/CLKN, including a feedback output clock pair that
feeds back to FBINP/FBINN to close the loop. The PLL
can be bypassed for test purposes by pulling AVDD to
ground.
Table 1: Function Table
INPUT OUTPUT
PLL AVDD PWR
DWN# CKP CKN YP0-
YP9 YN0-
YN9 FBOUT
PFBOUT
N
2.5V L L H Z Z Z Z
OFF 2.5V L H L Z Z Z Z
2.5V H L H L H L H
Zero-
Delay 2.5V H H L H L H L
GNDLLHZZZZ
OFF GNDLHLZZZZ
GNDHLHLHLH
PLL
Bypass GNDHHLHLHL
OFF--<20MHzZZZZ
Figure 1: Block Diagram
FS61857
YP0
YN0
PLL
CKP
CKN
PWRDWN#
AVDD
VDD
GND
AGND
YP1
YN1
YP2
YN2
YP3
YN3
YP4
YN4
YP5
YN5
YP6
YN6
YP7
YN7
YP8
YN8
YP9
YN9
FBOUTP
FBOUTN
Power
Down
FBINP
FBINN
Figure 2: Pin Configuration
1
40
2
3
4
5
6
7
8
39
38
37
36
35
34
33
GND
YN0 YN5
VDD
YP1
9
10
11
12
13
14
15
16
VDDVDD
FBOUTN
17
18
19
20
21
22
23
VDD
YP6
32
31
30
29
28
27
26
25
GND
YN7
FBINP
VDD
FBINN
24
FS61857
VDD
GND
YP0
YN6
PWRDWN#
YN9
FBOUTP
YP7
GND 41
42
44
43
45
46
48
47
GND
YN1
GND
YN2
YP2
VDD
CKN
VDD
CKP
VDD
AVDD
AGND
YP3
GND
YN3
GND
YN4
GND
YP4 YP9
YP8
YN8
GND
YP5
AMERICAN MICROSYSTEMS, INC.
November 2000
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FS61857-01
FS61857-01FS61857-01
FS61857-01
1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
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Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN TYPE NAME DESCRIPTION
16 P AVDD
2.5V PLL power supply / Test mode enable.
This pin provides the power supply to the internal PLL. When pulled low, the PLL is by-
passed and the output clocks directly follow the input clock
17 P AGND PLL ground
13 / 14 DI CKP / CKN Reference clock input (true / complementary)
36 / 35 DI FBINP / FBINN Feedback input (true / complementary)
32 / 33 DO FBOUTP / FBOUTN Feedback output (true / complementary)
37 DI PWRDWN# Asynchronous power-down input shuts down PLL and tristates all outputs
3 / 2 YP0 / YN0
5 / 6 YP1 / YN1
10 / 9 YP2 / YN2
20 / 19 YP3 / YN3
22 / 23 YP4 / YN4
46 / 47 YP5 / YN5
44 / 43 YP6 / YN6
39 / 40 YP7 / YN7
29 / 30 YP8 / YN8
27 / 26
DO
YP9 / YN9
Clock outputs (true / complementary)
1, 7, 8, 18, 24, 25,
31, 41, 42, 48 P GND Ground for all clock outputs
4, 11, 12, 15, 21,
28, 34, 38, 45 P VDD 2.5V power supply for all clock outputs
3.0 Device Operation
The FS61857 precisely aligns the frequency and phase
of the differential HSTL output clocks to the differential
reference input CKP/CKN by use of an on-chip phase-
lock loop (PLL). The PLL generates 10 low-skew, low-
jitter copies of the reference, with the outputs adjusted for
50% duty cycle.
The differential FBOUT clock must be hardwired to the
FBINP/FBINN pins to complete the loop. The PLL ac-
tively adjusts the output clocks so that there is no phase
error between the reference clock and the feedback in-
put.
Since the device uses a PLL to lock the output clocks to
the input clock, there is a power-up stabilization time that
is required for the PLL to achieve phase lock.
Note that all inputs and outputs use 2.5V HSTL signal
levels.
3.1 PLL Bypass
When the AVDD pin is pulled low, the reference clock
signal bypasses the PLL and is muxed directly through to
the outputs. The PLL is powered down, and device acts a
fanout buffer. Note that if AVDD is re-established, the
PLL requires a power-up and stabilization time to lock to
the input clock.
3.2 Power-Down
The FS61857 provides an auto power-down feature that
shuts off the PLL and tristates all outputs low if the refer-
ence clock drops below 20MHz. The power-down circuit
is level sensitive, and detects either a DC high or low on
the CKP/CKN input pair. If the input clock rises above
20MHz, the PLL powers back up to re-establish lock.
An asynchronous active-low PWRDWN# signal also
places the part in the power off state.
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November 2000
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FS61857-01
FS61857-01FS61857-01
FS61857-01
1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
4.0 Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage, dc, Clock Buffers (GND = ground) AVDD GND-0.5 4 V
Supply Voltage, dc, Core VDD GND-0.5 4 V
Input Voltage, dc VIGND-0.5 VDD+0.5 V
Output Voltage, dc VOGND-0.5 VDD+0.5 V
Input Clamp Current, dc (VI < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy
electrostatic discharge.
Table 4: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
AVDD Core 2.3 2.5 2.7
Supply Voltage VDD Outputs 2.3 2.5 2.7 V
Ambient Operating Temperature Range TA070°C
Frequency range over which PLL
acquires lock 60 170
Input Frequency (CKP / CKN) fCLK Frequency range where all timing
parameter specification are met 90 170
MHz
Input Duty Cycle CKP / CKN 40 60 %
Input Rise/Fall Time tr, tfCKP / CKN (over 20% to 80%) 0.375 1.5 ns
Spread-Spectrum Modulation Frequency fm30 50 MHz
Spread-Spectrum Modulation Index δm0-0.5%
Output Load Capacitance CL15 pF
AMERICAN MICROSYSTEMS, INC.
November 2000
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FS61857-01
FS61857-01FS61857-01
FS61857-01
1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
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Table 5: DC Electrical Specifications
Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characteri-
zation data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic,
with Loaded Outputs IDD VDD = 2.7V, fCLK = 170MHz 200 300 mA
Supply Current, Static IDDL VDD = 2.7V, PWRDWN# low or fCLK < 20MHz 100 µA
Power Down Input (PWRDWN#)
High-Level Input Voltage VIH 1.7 VDD+0.3 V
Low-Level Input Voltage VIL GND-0.3 0.7 V
Input Leakage Current IIVDD = 2.7V -10 10 µA
Differential Clock Inputs (CKP, CKN, FBINP, FBINN)
Input Voltage Level VIN GND-0.3 VDD+0.3 V
Crossover Voltage VIX
VDD/2
-0.2
VDD/2
+0.2 V
Differential Voltage VID
Magnitude of the difference between the input
level on CKP and the input level on CKN 0.36 VDD+0.6
Input Leakage Current IIVDD = 2.7V -10 10 µA
Input Loading Capacitance * CL(in) VI = 0V, as seen by an external clock driver 2.5 3.5 pF
Differential Clock Outputs (YP0:9, YN0:9, FBOUTP, FBOUTN)
VDD = 2.3V, VO = 1.7V -12 mA
High-Level Output Source Current IOH VDD = 2.3V, VO = 2.2V -100 µA
VDD = 2.3V, VO = 0.6V 12 mA
Low-Level Output Sink Current IOL VDD = 2.3V, VO = 0.1V 100 µA
Crossover Voltage VOX
VDD/2
-0.2
VDD/2
+0.2
Differential Voltage VOD
Magnitude of the difference between the
output levels on YP0:9, FBOUTP and the
output levels on YN0:9, FBOUTN
0.70 VDD+0.6
zOMeasured at 1.25V, output driving low
Output Impedance zOL Measured at 1.25V, output driving high Ω
Tristate Output Current IOZ -5 5 µA
Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. mA
Short Circuit Sink Current * IOSL VO = 2.5V; shorted for 30s, max. mA
AMERICAN MICROSYSTEMS, INC.
November 2000
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FS61857-01
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1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
Table 6: AC Timing Specifications
Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Clock Skew, Output to Output * tsk(o) Measured VX between two output pairs CL = 15pF ps
Spread modulation ON
Dynamic Phase Offset tdΦSpread modulation ON ps
Static Phase Offset tΦDoes not include jitter -120 120 ps
Clock Stabilization Time * Time required for the PLL to achieve phase lock ms
Phase-Lock Loop
Loop Bandwidth * For calculation of Tracking Skew 2.0 MHz
Phase Angle * For calculation of Tracking Skew -0.031 °
Phase Error * From rising edge on CLK to rising edge on FBIN ps
Clock Outputs (1Y0:9, FBOUT)
Duty Cycle * dt45 55 %
Jitter, Cycle-cycle *
(peak-peak) tj(CC) -75 75 ps
Jitter, Period *
(peak-peak) tj(∆P) -75 75 ps
Jitter, Half-Period *
(peak-peak) tj(∆½P) -100 100 ps
Rise Time * trVO = 0.5V to 2.0V; CL = 15pF 0.75 1.5 ns
Fall Time * tfVO = 2.0V to 0.5V; CL = 15pF 0.75 1.5 ns
Enable Delay * tDLH via PWRDWN# ns
Disable Delay * tDHL via PWRDWN# ns
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November 2000
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FS61857-01
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5.0 Package Information
Table 7: 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A10.002 0.006 0.05 0.15
b 0.0067 0.011 0.17 0.27
c 0.0035 0.008 0.09 0.20
D 0.488 0.496 12.40 12.60
E 0.318 BSC 8.10 BSC
E10.236 0.244 6.00 6.20
e 0.019 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
θ10°8°0°8°
θ212° REF 12° REF
θ312° REF 12° REF
E
1
AMERICAN MI CROSY STEM S, IN C.
E
1
48
be
DA
1
SEATING PLANE
Ac
L
θ
1
θ
3
θ
2
S
Table 8: 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 89 °C/W
Lead Inductance, Self L11 Longest lead 3.50 nH
L12 Longest lead to any 1st adjacent lead 1.82
Lead Inductance, Mutual L13 Longest lead to any 2nd adjacent lead 1.17 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.63 pF
C12 Longest lead to any 1st adjacent lead 0.30
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.03 pF
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FS61857-01
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1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC1:10 HSTL Zero-Delay Clock Buffer IC
1:10 HSTL Zero-Delay Clock Buffer IC
6.0 Ordering Information
Table 9: Device Ordering Codes
DEVICE
NUMBER ORDERING CODE PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
FS61857-01 13810-801 48-pin TSSOP
(Thin Shrink Small Outline Package) 0°C to 70°C (Commercial) Tape and Reel
Copyright © 2001 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: t
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