LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 LM4836 Stereo 2W Audio Power Amplifiers with DC Volume Control, Bass Boost, and Input Mux Check for Samples: LM4836 FEATURES DESCRIPTION * * * * * The LM4836 is a monolithic integrated circuit that provides DC volume control, and stereo bridged audio power amplifiers capable of producing 2W into 4 with less than 1.0% THD+N, or 2.2W into 3 with less than 1.0% THD+N (see Notes below). 1 2 * * * PC98 and PC99 Compliant DC Volume Control Interface Input Mux System Beep Detect Stereo Switchable Bridged/Single-Ended Power Amplifiers Selectable Internal/External Gain and Bass Boost Configurable "Click and Pop" Suppression Circuitry Thermal Shutdown Protection Circuitry APPLICATIONS * * * Portable and Desktop Computers Multimedia Monitors Portable Radios, PDAs, and Portable TVs KEY SPECIFICATIONS * * * * * * PO at 1% THD+N Into 3 (LM4836LQ, LM4836MTE) 2.2 W (typ) Into 4 (LM4836LQ, LM4836MTE) 2.0 W (typ) Into 8 (LM4836) 1.1 W (typ) Single-Ended Mode - THD+N at 85 mW Into 32 1.0% (typ) Shutdown Current 0.2A (typ) Boomer audio integrated circuits were designed specifically to provide high quality audio while requiring a minimum amount of external components. The LM4836 incorporates a DC volume control, stereo bridged audio power amplifiers, selectable gain or bass boost, and an input mux making it optimally suited for multimedia monitors, portable radios, desktop, and portable computer applications. The LM4836 features an externally controlled, lowpower consumption shutdown mode, and both a power amplifier and headphone mute for maximum system flexibility and performance. Note: When properly mounted to the circuit board, the LM4836LQ and LM4836MTE will deliver 2W into 4. The LM4836MT will deliver 1.1W into 8. See the APPLICATION INFORMATION section for LM4836LQ and LM4836MTE usage information. Note: An LM4836LQ and LM4836MTE that have been properly mounted to the circuit board and forced-air cooled will deliver 2.2W into 3. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com Connection Diagram Figure 1. WQFN Package See Package NJB0028A for Exposed-DAP WQFN Figure 2. TSSOP Package See Package PW0028A for TSSOP or PWP0028A for Exposed-DAP HTSSOP 2 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage 6.0V Storage Temperature -65C to +150C -0.3V to VDD +0.3V Input Voltage Power Dissipation (3) Internally limited ESD Susceptibility (4) 2500V ESD Susceptibility (5) 250V Junction Temperature 150C Soldering Information Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C See http://www.ti.com for other methods of soldering surface mount devices. JC (typ)--NJB0028A JA (typ)--NJB0028A 3.0C/W (6) 42C/W JC (typ)--PW0028A 20C/W JA (typ)--PW0028A 80C/W JC (typ)--PWP0028A 2C/W JA (typ)--PWP0028A (7) 41C/W JA (typ)--PWP0028A (8) 54C/W JA (typ)--PWP0028A (9) 59C/W JA (typ)--PWP0028A (10) 93C/W (1) If Military/Aerospace specified devices are required, please contact the Texas Instruments' Sales Office/ Distributors for availability and specifications. (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. (3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA )/JA. For the LM4836, TJMAX = 150C. The typical junction-toambient thermal resistance, when board mounted, is 80C/W for the PW0028A package, 41C/W for the PWP0028A package, and 42C/W for the NJB0028A package. (4) Human body model, 100 pF discharged through a 1.5 k resistor. (5) Machine Model, 220 pF-240 pF discharged through all pins. (6) The given JA is for an LM4836 packaged in an NHW0024A with the exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit board copper. (7) The JA given is for a PWP0028A package whose exposed-DAP is soldered to a 2in2 piece of 1 ounce printed circuit board copper on a bottom side layer through 21 8mil vias. (8) The JA given is for a PWP0028A package whose exposed-DAP is soldered to an exposed 2in 2 piece of 1 ounce printed circuit board copper. (9) The JA given is for a PWP0028A package whose exposed-DAP is soldered to an exposed 1in 2 piece of 1 ounce printed circuit board copper. (10) The JA given is for a PWP0028A package whose exposed-DAP is not soldered to any copper. OPERATING RATINGS Temperature Range TMIN TA TMAX -40C TA 85C 2.7V VDD 5.5V Supply Voltage Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 3 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS FOR ENTIRE IC (1) (2) The following specifications apply for VDD = 5V and TA = 25C unless otherwise noted. Symbol Parameter LM4836 Conditions Typical (3) Limit (4) Units (Limits) 2.7 V (min) 5.5 V (max) 30 mA (max) VDD Supply Voltage IDD Quiescent Power Supply Current VIN = 0V, IO = 0A 15 ISD Shutdown Current Vpin 24 = VDD 0.2 VIH Headphone Sense High Input Voltage 4 V (min) VIL Headphone Sense Low Input Voltage 0.8 V (max) (1) (2) (3) (4) A (max) 2.0 All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown in Figure 71. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Datasheet min/max specification limits are specified by design, test, or statistical analysis. ELECTRICAL CHARACTERISTICS FOR VOLUME ATTENUATORS (1) (2) The following specifications apply for VDD = 5V and TA = 25C unless otherwise noted. Symbol CRANGE Parameter Attenuator Range CRANGE Attenuator Range AM Mute Attenuation (1) (2) (3) (4) 4 Conditions Gain with Vpin 5 4.5V LM4836 Typical (3) Limit (4) Units (Limits) 0 0.5 dB (max) 0 -1.0 dB (min) Attenuation with Vpin 5 = 0V -73 -70 dB (min) Vpin 3 = 5V, Bridged Mode -88 -80 dB (min) Vpin 3 = 5V, Single-Ended Mode -80 -70 dB (min) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown in Figure 71. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Datasheet min/max specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 ELECTRICAL CHARACTERISTICS FOR SINGLE-ENDED MODE OPERATION (1) (2) The following specifications apply for VDD = 5V and TA = 25C unless otherwise noted. Symbol Parameter LM4836 Conditions Limit (4) Units (Limits) THD+N = 1.0%; f = 1kHz; RL = 32 85 mW THD+N = 10%; f = 1 kHz; RL = 32 95 mW 0.065 % CB = 1.0 F, f =120 Hz, VRIPPLE = 200 mVrms 58 dB Signal to Noise Ratio POUT =75 mW, R L = 32, A-Wtd Filter 102 dB Channel Separation f=1kHz, CB = 1.0 F 65 dB PO Output Power THD+N Total Harmonic Distortion+Noise VOUT = 1VRMS, f=1kHz, RL = 10k, AVD =1 PSRR Power Supply Rejection Ratio SNR Xtalk (1) (3) Typical All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown in Figure 71. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Datasheet min/max specification limits are specified by design, test, or statistical analysis. (2) (3) (4) ELECTRICAL CHARACTERISTICS FOR BRIDGED MODE OPERATION (1) (2) The following specifications apply for VDD = 5V and TA = 25C unless otherwise noted. Symbol VOS Parameter Output Offset Voltage PO Output Power THD+N Total Harmonic Distortion+Noise LM4836 Conditions Typical VIN = 0V 10 THD + N = 1.0%; f=1kHz; RL = 3 (5) (6) 2.2 THD + N = 1.0%; f=1kHz; RL = 4 (7) (6) 2 (3) Limit 50 (4) Units (Limits) mV (max) W W THD = 1.5% (max);f = 1 kHz; RL = 8 1.1 1.0 W (min) THD+N = 10%;f = 1 kHz; RL = 8 1.5 W PO = 1W, 20 Hz< f < 20 kHz, RL = 8, AVD = 2 0.3 % PO = 340 mW, RL = 32 1.0 % CB = 1.0 F, f = 120 Hz, VRIPPLE = 200 mVrms; RL = 8 74 dB PSRR Power Supply Rejection Ratio SNR Signal to Noise Ratio VDD = 5V, POUT = 1.1W, RL = 8, A-Wtd Filter 93 dB Xtalk Channel Separation f=1kHz, CB = 1.0 F 70 dB (1) (2) (3) (4) (5) (6) (7) All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown in Figure 71. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Datasheet min/max specification limits are specified by design, test, or statistical analysis. When driving 3 loads and operating on a 5V supply the LM4836MTE exposed DAP must be soldered to the circuit board and forcedair cooled. When driving 3 or 4 loads and operating on a 5V supply, the LM4836LQ must be mounted to the circuit board that has a minimum of 2.5in2 of exposed, uninterrupted copper area connected to the WQFN package's exposed DAP. When driving 4 loads and operating on a 5V supply the LM4836MTE exposed DAP must be soldered to the circuit board. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 5 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL APPLICATION Figure 3. Typical Application Circuit TRUTH TABLE FOR LOGIC INPUTS (1) 6 (1) Mute Mux Control HP Sense Inputs Selected Bridged Output Single-Ended Output 0 0 0 Left In 1, Right In 1 Vol. Adjustable - 0 0 1 Left In 1, Right In 1 Muted Vol. Adjustable 0 1 0 Left In 2, Right In 2 Vol. Adjustable - 0 1 1 Left In 2, Right In 2 Muted Vol. Adjustable 1 X X - Muted Muted If system beep is detected on the Beep in pin (pin 11) and beep is fed to inputs, the system beep will be passed through the bridged amplifier regardless of the logic of the Mute, HP sense, or DC Volume Control pins. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS LM4836MTE THD+N vs Output Power LM4836MTE THD+N vs Frequency Figure 4. Figure 5. LM4836MTE THD+N vs Output Power LM4836MTE THD+N vs Frequency Figure 6. Figure 7. LM4836MTE Power Dissipation vs Output Power LM4836LQ Power Derating Curve Figure 8. Figure 9. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 7 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS (continued) LM4836MTE Power Derating Curve Figure 10 shows the thermal dissipation ability of the LM4836MTE at different ambient temperatures given these conditions: 500LFPM + 2in2: The part is soldered to a 2in2, 1 oz. copper plane with 500 linear feet per minute of forced-air flow across it. 2in2on bottom: The part is soldered to a 2in2, 1oz. copper plane that is on the bottom side of the PC board through 21 8 mil vias. 2in2: The part is soldered to a 2in2, 1oz. copper plane. 1in2: The part is soldered to a 1in2, 1oz. copper plane. Not Attached: The part is not soldered down and is not forced-air cooled. Figure 10. 8 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS THD+N Vs Frequency THD+N Vs Frequency Figure 11. Figure 12. THD+N Vs Frequency THD+N Vs Frequency Figure 13. Figure 14. THD+N Vs Frequency THD+N Vs Frequency Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 9 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) 10 THD+N Vs Frequency THD+N Vs Frequency Figure 17. Figure 18. THD+N Vs Frequency THD+N Vs Frequency Figure 19. Figure 20. THD+N Vs Frequency THD+N Vs Output Power Figure 21. Figure 22. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) THD+N Vs Output Power THD+N Vs Output Power Figure 23. Figure 24. THD+N Vs Output Power THD+N Vs Output Power Figure 25. Figure 26. THD+N vs Output Power THD+N Vs Output Power Figure 27. Figure 28. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 11 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) 12 THD+N Vs Output Power THD+N Vs Output Power Figure 29. Figure 30. THD+N Vs Output Power THD+N Vs Output Power Figure 31. Figure 32. THD+N Vs Output Voltage Docking Station Pins THD+N Vs Output Voltage Docking Station Pins Figure 33. Figure 34. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) Output Power Vs Load Resistance Output Power Vs Load Resistance Figure 35. Figure 36. Output Power Vs Load Resistance Power Supply Rejection Ratio Figure 37. Figure 38. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 13 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) 14 Dropout Voltage Output Power Vs Load Resistance Figure 39. Figure 40. Noise Floor Noise Floor Figure 41. Figure 42. Volume Control Characteristics Power Dissipation Vs Output Power Figure 43. Figure 44. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) Power Dissipation Vs Output Power External Gain/ Bass Boost Characteristics Figure 45. Figure 46. Power Derating Curve Crosstalk Figure 47. Figure 48. Crosstalk Output Power Vs Supply Voltage Figure 49. Figure 50. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 15 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS NON-MTE SPECIFIC CHARACTERISTICS (continued) 16 Output Power Vs Supply Voltage Supply Current Vs Supply Voltage Figure 51. Figure 52. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Output Power vs Load Resistance Output Power vs Load Resistance Figure 53. Figure 54. Output Power vs Load Resistance Power Supply Rejection Ratio Figure 55. Figure 56. Dropout Voltage Output Power vs Load Resistance Figure 57. Figure 58. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 17 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 18 Noise Floor Noise Floor Figure 59. Figure 60. Volume Control Characteristics Power Dissipation vs Output Power Figure 61. Figure 62. Power Dissipation vs Output Power External Gain/ Bass Boost Characteristics Figure 63. Figure 64. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Power Derating Curve Crosstalk Figure 65. Figure 66. Crosstalk Output Power vs Supply voltage Figure 67. Figure 68. Output Power vs Supply Voltage Supply Current vs Supply Voltage Figure 69. Figure 70. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 19 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com APPLICATION INFORMATION EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATIONS The LM4836's exposed-DAP (die attach paddle) packages (MTE and LQ) provide a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane and, finally, surrounding air. The result is a low voltage audio power amplifier that produces 2.1W at 1% THD with a 4 load. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4836's high power performance and activate unwanted, though necessary, thermal shutdown protection. The MTE and LQ packages must have their DAPs soldered to a copper pad on the PCB. The DAP's PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass and heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or backside copper heat sink area with 32(4x8) (MTE) or 6(3x2) (LQ) vias. The via diameter should be 0.012in-0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plating-through and solder-filling the vias. Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4 load. Heatsink areas not placed on the same PCB layer as the LM4836 should be 5in2 (min) for the same supply voltage and load resistance. The last two area recommendations apply for 25C ambient temperature. Increase the area to compensate for ambient temperatures above 25C. In systems using cooling fans, the LM4836MTE can take advantage of forced air cooling. With an air flow rate of 450 linear-feet per minute and a 2.5in2 exposed copper or 5.0in2 inner layer copper plane heatsink, the LM4836MTE can continuously drive a 3 load to full power. The LM4836LQ achieves the same output power level without forced air cooling. In all circumstances and conditions, the junction temperature must be held below 150C to prevent activating the LM4836's thermal shutdown protection. The LM4836's power de-rating curve in the TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS shows the maximum power dissipation versus temperature. Example PCB layouts for the exposed-DAP TSSOP and LQ packages are shown in the RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT section. Further detailed and specific information concerning PCB layout, fabrication, and mounting an LQ (WQFN) package is available in Texas Instruments' AN1187 (literature number SNOA401). PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3 AND 4 LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by a 4 load from 2.1W to 2.0W. This problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION As shown in Figure 3, the LM4836 consists of two pairs of operational amplifiers, forming a two-channel (channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies equally to channel B.) External resistors Rf and Ri set the closed-loop gain of Amp1A, whereas two internal 20k resistors set Amp2A's gain at -1. The LM4836 drives a load, such as a speaker, connected between the two amplifier outputs, -OUTA and +OUTA. 20 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 Figure 3 shows that Amp1A's output serves as Amp2A's input. This results in both amplifiers producing signals identical in magnitude, but 180 out of phase. Taking advantage of this phase difference, a load is placed between -OUTA and +OUTA and driven differentially (commonly referred to as "bridge mode"). This results in a differential gain of AVD = 2 * (Rf/R i) (1) Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. This produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or that the output signal is not clipped. To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the AUDIO POWER AMPLIFIER DESIGN section. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing channel A's and channel B's outputs at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (VDD)2/(22RL)Single-Ended (2) However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation for the same conditions. The LM4836 has two operational amplifiers per channel. The maximum internal power dissipation per channel operating in the bridge mode is four times that of a single-ended amplifier. From Equation 3, assuming a 5V power supply and a 4 load, the maximum single channel power dissipation is 1.27W or 2.54W for stereo operation. PDMAX = 4 * (VDD)2/(22RL)Bridge Mode (3) The LM4836's power dissipation is twice that given by Equation 2 or Equation 3 when operating in the singleended mode or bridge mode, respectively. Twice the maximum power dissipation point given by Equation 3 must not exceed the power dissipation given by Equation 4: PDMAX = (TJMAX - TA)/JA (4) The LM4836's TJMAX = 150C. In the LQ package soldered to a DAP pad that expands to a copper area of 5in2 on a PCB, the LM4836's JA is 20C/W. In the MTE package soldered to a DAP pad that expands to a copper area of 2in2 on a PCB, the LM4836's JA is 41C/W. At any given ambient temperature TA, use Equation 4 to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation 4and substituting PDMAX for PDMAX results in Equation 5. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4836's maximum junction temperature. TA = TJMAX - 2*PDMAX JA (5) For a typical application with a 5V power supply and an 4 load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 99C for the LQ package and 45C for the MTE package. TJMAX = PDMAX JA + TA (6) Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4836's 150C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 21 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com If the result of Equation 2 is greater than that of Equation 3, then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce JA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the JA is the sum of JC, CS, and SA. (JC is the junction-to-case thermal impedance, CS is the case-to-sink thermal impedance, and SA is the sink-to-ambient thermal impedance.) Refer to the TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS curves for power dissipation information at lower output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10 F in parallel with a 0.1 F filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 1.0 F tantalum bypass capacitance connected between the LM4836's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4836's power supply pin and ground as short as possible. Connecting a 1F capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time and can compromise amplifier's click and pop performance. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, PROPER SELECTION OF EXTERNAL COMPONENTS ), system cost, and size constraints. PROPER SELECTION OF EXTERNAL COMPONENTS Optimizing the LM4836's performance requires properly selecting external components. Though the LM4836 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. The LM4836 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-tonoise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain demands input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the AUDIO POWER AMPLIFIER DESIGN section for more information on selecting the proper gain. Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (0.33F in Figure 3). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. Besides effecting system cost and size, the input coupling capacitor has an affect on the LM4835's click and pop performance. When the supply voltage is first applied, a transient (pop) is created as the charge on the input capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional to the input capacitor's size. Higher value capacitors need more time to reach a quiescent DC voltage (usually VDD/2) when charged with a fixed current. The amplifier's output charges the input capacitor through the feedback resistor, Rf. Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired -3dB frequency. As shown in Figure 3, the input resistor (20k) and the input capacitor produce a -3dB high pass filter cutoff frequency that is found using Equation 7. (7) As an example when using a speaker with a low frequency limit of 150Hz, the input coupling capacitor using Equation 7, is 0.063F. The 0.33F input coupling capacitor shown in Figure 3 allows the LM4835 to drive high efficiency, full range speaker whose response extends below 30Hz. 22 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE The LM4836 contains circuitry that minimizes turn-on and shutdown transients or "clicks and pop". For this discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated. While the power supply is ramping to its final value, the LM4836's internal amplifiers are configured as unity gain buffers. An internal current source changes the voltage of the BYPASS pin in a controlled, linear manner. Ideally, the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains unity until the voltage on the bypass pin reaches 1/2 VDD. As soon as the voltage on the bypass pin is stable, the device becomes fully operational. Although the BYPASS pin current cannot be modified, changing the size of CB alters the device's turn-on time and the magnitude of "clicks and pops". Increasing the value of CB reduces the magnitude of turn-on pops. However, this presents a tradeoff: as the size of CB increases, the turn-on time increases. There is a linear relationship between the size of CB and the turn-on time. Here are some typical turnon times for various values of CB: CB TON 0.01F 2ms 0.1F 20ms 0.22F 44ms 0.47F 94ms 1.0F 200ms In order eliminate "clicks and pops", all capacitors must be discharged before turn-on. Rapidly switching VDD may not allow the capacitors to fully discharge, which may cause "clicks and pops". In a single-ended configuration, the output is coupled to the load by COUT. This capacitor usually has a high value. COUT discharges through internal 20k resistors. Depending on the size of COUT, the discharge time constant can be relatively large. To reduce transients in single-ended mode, an external 1k-5k resistor can be placed in parallel with the internal 20k resistor. The tradeoff for using this resistor is increased quiescent current. Figure 71. Resistor for Varying Output Loads DOCKING STATION Applications such as notebook computers can take advantage of a docking station to connect to external devices such as monitors or audio/visual equipment that sends or receives line level signals. The LM4836 has two outputs, Pin 9 and Pin 13, which connect to outputs of the internal input amplifiers that drive the volume control inputs. These input amplifiers can drive loads of >1k (such as powered speakers) with a rail-to-rail signal. Since the output signal present on the RIGHT DOCK and LEFT DOCK pins is biased to VDD/2, coupling capacitors should be connected in series with the load. Typical values for the coupling capacitors are 0.33F to 1.0F. If polarized coupling capacitors are used, connect their "+" terminals to the respective output pin. Since the DOCK outputs precede the internal volume control, the signal amplitude will be equal to the input signal's magnitude and cannot be adjusted. However, the input amplifier's closed-loop gain can be adjusted using external resistors. These resistors are shown in Figure 71 as 20k devices that set each input amplifier's gain to -1. Use Equation 8 to determine the input and feedback resistor values for a desired gain. - Av = RF / Ri (8) Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 23 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com Adjusting the input amplifier's gain sets the minimum gain for that channel. The DOCK outputs adds circuit and functional flexibility because their use supercedes using the inverting outputs of each bridged output amplifier as line-level outputs. STEREO-INPUT MULTIPLEXER (STEREO MUX) The LM4836 has two stereo inputs. The MUX CONTROL pin controls which stereo input is active. Applying 0V to the MUX CONTROL pin selects stereo input 1. Applying VDD to the MUX CONTROL pin selects stereo input 2. BEEP DETECT FUNCTION Computers and notebooks produce a system "beep" signal that drives a small speaker. The speaker's auditory output signifies that the system requires user attention or input. To accommodate this system alert signal, the LM4836's pin 11 is a mono input that accepts the beep signal. Internal level detection circuitry at this input monitors the beep signal's magnitude. When a signal level greater than VDD/2 is detected on pin 11, the bridge output amplifiers are enabled. The beep signal is amplified and applied to the load connected to the output amplifiers. A valid beep signal will be applied to the load even when MUTE is active. Use the input resistors connected between the BEEP IN pin and the stereo input pins to accommodate different beep signal amplitudes. These resistors are shown as 200k devices in Figure 71. Use higher value resistors to reduce the gain applied to the beep signal. The resistors must be used to pass the beep signal to the stereo inputs. The BEEP IN pin is used only to detect the beep signal's magnitude: it does not pass the signal to the output amplifiers. The LM4836's shutdown mode must be deactivated before a system alert signal is applied to BEEP IN pin. MICRO-POWER SHUTDOWN The voltage applied to the SHUTDOWN pin controls the LM4836's shutdown function. Activate micro-power shutdown by applying VDD to the SHUTDOWN pin. When active, the LM4836's micro-power shutdown feature turns off the amplifier's bias circuitry, reducing the supply current. The logic threshold is typically VDD/2. The low 0.7 A typical shutdown current is achieved by applying a voltage that is as near as VDD as possible to the SHUTDOWN pin. A voltage that is less than VDD may increase the shutdown current. Logic Level Truth Table shows the logic signal levels that activate and deactivate micro-power shutdown and headphone amplifier operation. There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. When using a switch, connect an external 10k pull-up resistor between the SHUTDOWN pin and VDD. Connect the switch between the SHUTDOWN pin and ground. Select normal amplifier operation by closing the switch. Opening the switch connects the SHUTDOWN pin to VDD through the pull-up resistor, activating micro-power shutdown. The switch and resistor specify that the SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN pin with active circuitry eliminates the pull up resistor. Table 1. Logic Level Truth Table for SHUTDOWN, HP-IN, and MUX Operation SHUTDOWN PIN HP-IN PIN MUX CHANNEL SELECT PIN OPERATIONAL MODE (MUX INPUT CHANNEL #) Logic Low Logic Low Logic Low Logic Low Bridged Amplifiers (1) Logic Low Logic High Bridged Amplifiers (2) Logic Low Logic Low Logic High Logic Low Single-Ended Amplifiers (1) Logic High Logic High Logic High Single-Ended Amplifiers (2) X X Micro-Power Shutdown MUTE FUNCTION The LM4836 mutes the amplifier and DOCK outputs when VDD is applied to pin 5, the MUTE pin. Even while muted, the LM4836 will amplify a system alert (beep) signal whose magnitude satisfies the BEEP DETECT circuitry. Applying 0V to the MUTE pin returns the LM4836 to normal, unmated operation. Prevent unanticipated mute behavior by connecting the MUTE pin to VDD or ground. Do not let pin 5 float. 24 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 HP SENSE FUNCTION Applying a voltage between 4V and VDD to the LM4836's HP-IN headphone control pin turns off Amp2A and Amp2B, muting a bridged-connected load. Quiescent current consumption is reduced when the IC is in this single-ended mode. Figure 72 shows the implementation of the LM4836's headphone control function. With no headphones connected to the headphone jack, the R1-R2 voltage divider sets the voltage applied to the HP-IN pin (pin 16) at approximately 50mV. This 50mV enables Amp1B and Amp2B, placing the LM4836 in bridged mode operation. The output coupling capacitor blocks the amplifier's half supply DC voltage, protecting the headphones. The HP-IN threshold is set at 4V. While the LM4836 operates in bridged mode, the DC potential across the load is essentially 0V. Therefore, even in an ideal situation, the output swing cannot cause a false single-ended trigger. Connecting headphones to the headphone jack disconnects the headphone jack contact pin from -OUTA and allows R1 to pull the HP Sense pin up to VDD. This enables the headphone function, turns off Amp2A and Amp2B, and mutes the bridged speaker. The amplifier then drives the headphones, whose impedance is in parallel with resistor R2 and R3. These resistors have negligible effect on the LM4836's output drive capability since the typical impedance of headphones is 32. Figure 72 also shows the suggested headphone jack electrical connections. The jack is designed to mate with a three-wire plug. The plug's tip and ring should each carry one of the two stereo output signals, whereas the sleeve should carry the ground return. A headphone jack with one control pin contact is sufficient to drive the HPIN pin when connecting headphones. A microprocessor or a switch can replace the headphone jack contact pin. When a microprocessor or switch applies a voltage greater than 4V to the HP-IN pin, a bridge-connected speaker is muted and Amp1A and Amp2A drive a pair of headphones. Figure 72. Headphone Sensing Circuit Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 25 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com BASS BOOST FUNCTION The LM4836 has a bass-boost feature that enhances the low frequency response in applications using small speakers. The voltage level applied to the BASS BOOST SELECT pin controls the bass-boost function. Applying GND activates the bass-boost mode. In bass-boost mode, the LM4836's gain is increased at low frequencies, with a corner frequency set by the external capacitor, CBASS. Applying VDD defeats the bass-boost mode and selects unity gain. Tying the BASS BOOST SELECT pin to VDD permanently defeats the bass-boost function. Enabling bass-boost forces the output amplifiers to operate with an internally set low frequency gain of 2 (gain of 4 in bridged mode). The capacitor CBASS shown in Figure 3 sets the bass-boost corner frequency. At low frequencies, the capacitor is a virtual open circuit and the feedback resistance consists of two 10k resistors. At high frequencies, the capacitor is a virtual short circuit, which shorts one of the two 10k feedback resistors. The results is bridge amplifier gain that increases at low frequencies. A first-order pole is formed with a corner frequency at fC = 1/(210kCBASS) (9) At f<<fC, the differential gain of this bridged amplifier is 2(10k + 10k) /10k = 4 (10) With CBASS = 0.1F, the first-order pole has a corner frequency of 160Hz. It is assumed when using Equation 9 that CO, Ci, fIC, and fOC, are chosen for the desired low frequency response as explained in the PROPER SELECTION OF EXTERNAL COMPONENTS section. See the TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS section for a graph that includes bass-boost performance with various values of CBASS. DC VOLUME CONTROL The LM4836 has an internal stereo volume control whose setting is a function of the DC voltage applied to the DC VOL CONTROL pin. The volume control's voltage input range is 0V to VDD. The volume range is from 0dB (DC control voltage = 80%VDD) to -80dB (DC control voltage = 0V). The volume remains at 0dB for DC control voltages greater than 80%VDD. When the MODE input is 0V, the LM4836 operates at unity gain, bypassing the volume control. A graph showing a typical volume response versus DC control voltage is shown in the TYPICAL PERFORMANCE CHARACTERISTICS MTE SPECIFIC CHARACTERISTICS section. Like all volume controls, the LM4836's internal volume control is set while listening to an amplified signal that is applied to an external speaker. The actual voltage applied to the DC VOL CONTROL pin is a result of the volume a listener desires. As such, the volume control is designed for use in a feedback system that includes human ears and preferences. This feedback system operates quite well without the need for accurate gain. The user simply sets the volume to the desired level as determined by their ear, without regard to the actual DC voltage that produces the volume. Therefore, the accuracy of the volume control is not critical, as long as the volume changes monotonically, matches well between stereo channels, and the step size is small enough to reach a desired volume that is not too loud or too soft. Since gain accuracy is not critical, there will be volume variation from part-to-part even with the same applied DC control voltage. The gain of a given LM4836 can be set with a fixed external voltage, but another LM4836 may require a different control voltage to achieve the same gain. The typical part-to-part variation can be as large as 8dB for the same control voltage. AUDIO POWER AMPLIFIER DESIGN Audio Amplifier Design: Driving 1W into an 8 Load The following are the desired operational parameters: Power Output: 1 WRMS Load Impedance: 8 Input Level: 1 VRMS Input Impedance: 20 k Bandwidth: 26 100 Hz-20 kHz 0.25 dB Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 The design begins by specifying the minimum supply voltage necessary to obtain the specified output power. One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the TYPICAL PERFORMANCE CHARACTERISTICS section. Another way, using Equation 11, is to calculate the peak output voltage necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the TYPICAL PERFORMANCE CHARACTERISTICS curves, must be added to the result obtained by Equation 11. The result is Equation 12. (11) (12) VDD (VOUTPEAK+ (VODTOP + VODBOT)) The Output Power vs Supply Voltage graph for an 8 load indicates a minimum supply voltage of 4.6V. This is easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom, allowing the LM4836 to produce peak output power in excess of 1W without clipping or other audible distortion. The choice of supply voltage must also not create a situation that violates of maximum power dissipation as explained above in the POWER DISSIPATION section. After satisfying the LM4836's power dissipation requirements, the minimum differential gain needed to achieve 1W dissipation in an 8 load is found using Equation 13. (13) Thus, a minimum gain of 2.83 allows the LM4836's to reach full output swing and maintain low noise and THD+N performance. For this example, let AVD = 3. The amplifier's overall gain is set using the input (Ri) and feedback (Ri) resistors. With the desired input impedance set at 20k, the feedback resistor is found using Equation 14. Rf/Ri = AVD/2 (14) The value of Rf is 30k. The last step in this design example is setting the amplifier's -3dB frequency bandwidth. To achieve the desired 0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth limit. The gain variation for both response limits is 0.17dB, well within the 0.25dB desired limit. The results are an fL = 100Hz/5 = 20Hz (15) fH = 20kHz x 5 = 100kHz (16) and an As mentioned in the PROPER SELECTION OF EXTERNAL COMPONENTS section, Ri and Ci create a highpass filter that sets the amplifier's lower bandpass frequency limit. Find the coupling capacitor's value using Equation 17. Ci 1/(2R ifL) (17) The result is 1/(2*20k*20Hz) = 0.397F (18) Use a 0.39F capacitor, the closest standard value. The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD, determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth product (GBWP) is 300kHz. This is less than the LM4836's 3.5MHz GBWP. With this margin, the amplifier can be used in designs that require more differential gain while avoiding performance,restricting bandwidth limitations. RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT Figure 73 through Figure 77 show the recommended four-layer PC board layout that is optimized for the 8-pin LQ-packaged LM4836 and associated external components. This circuit is designed for use with an external 5V supply and 4 speakers. This circuit board is easy to use. Apply 5V and ground to the board's VDD and GND pads, respectively. Connect 4 speakers between the board's -OUTA and +OUTA and OUTB and +OUTB pads. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 27 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com Figure 73. Recommended LQ PC Board Layout: Component-Side Silkscreen Figure 74. Recommended LQ PC Board Layout: Component-Side Layout 28 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 Figure 75. Recommended LQ PC Board Layout: Upper Inner-Layer Layout Figure 76. Recommended LQ PC Board Layout: Lower Inner-Layer Layout Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 29 LM4836 SNAS045F - JUNE 1999 - REVISED MAY 2013 www.ti.com Figure 77. Recommended LQ PC Board Layout: Bottom-Side Layout 30 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 LM4836 www.ti.com SNAS045F - JUNE 1999 - REVISED MAY 2013 REVISION HISTORY Changes from Revision E (May 2013) to Revision F * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 30 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM4836 31 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM4836LQ/NOPB ACTIVE WQFN NJB 28 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L4836LQ LM4836MTEX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM4836MTE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM4836LQ/NOPB WQFN NJB 28 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM4836MTEX/NOPB HTSSOP PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4836LQ/NOPB WQFN NJB 28 1000 210.0 185.0 35.0 LM4836MTEX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0028A PowerPAD TM - 1.1 mm max height SCALE 1.800 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 A SEATING PLANE PIN 1 ID AREA 28 1 9.8 9.6 NOTE 3 0.1 C 26X 0.65 2X 8.45 14 B 15 4.5 4.3 NOTE 4 0.30 0.19 0.1 C A 28X 1.1 MAX B 0.20 TYP 0.09 SEE DETAIL A 3.15 2.75 0.25 GAGE PLANE 5.65 5.25 THERMAL PAD 0 -8 0.10 0.02 0.7 0.5 (1) DETAIL A TYPICAL 4214870/A 10/2014 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-153, variation AET. www.ti.com EXAMPLE BOARD LAYOUT PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 (3) SOLDER MASK OPENING 28X (1.5) 28X (0.45) SOLDER MASK DEFINED PAD 1 28X (0.45) 28X (1.3) 28 26X (0.65) SYMM (5.5) (9.7) SOLDER MASK OPENING (1.3) TYP 14 15 ( 0.2) TYP VIA (1.3) SEE DETAILS SYMM (0.9) TYP METAL COVERED BY SOLDER MASK (0.65) TYP (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214870/A 10/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3) BASED ON 0.127 THICK STENCIL 28X (1.5) 28X (0.45) METAL COVERED BY SOLDER MASK 1 28X (1.3) 28 26X (0.65) 28X (0.45) (5.5) BASED ON 0.127 THICK STENCIL SYMM 14 15 SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SYMM (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE AREA SCALE:6X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.127 0.152 0.178 3.55 X 6.37 3.0 X 5.5 (SHOWN) 2.88 X 5.16 2.66 X 4.77 4214870/A 10/2014 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA NJB0028A LQA28A (REV B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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