Dual 3 MHz, 800 mA Buck
Regulators with Two 300 mA LDOs
Data Sheet
ADP5033
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and two 300 mA LDOs
Tiny, 16-ball, 2 mm × 2 mm WLCSP package
Regulator accuracy: ±1.8%
Factory programmable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
TYPICAL APPLICATION CIRCUIT
VIN1
2.3V
TO
5.5V
SW1
VOUT1
PGND1
MODE
C5
10µF
L1 1µ H
BUCK1
C2
4.7µF
C1
4.7µF
VIN2
AGND
BUCK2
SW2
VOUT2
PGND2 C6
10µF
L2 1µ H
VOUT3
C7
1µF
VOUT4
C8
1µF
VIN3
C3
1µF
1.7V
TO
5.5V
VIN4
C4
1µF
ENA
ACTIV. AND
UVLO
ENB
ON
OFF PSM/PWM
PWM
EN1
EN2
EN3
EN4
LDO2
(DIGITAL)
EN2
EN3
EN4
MODE
MODE
VOUT1
@
800mA
VOUT2
@
800mA
VOUT3
@
300mA
VOUT4
@
300mA
09788-001
LDO1
(ANALOG)
ADP5033
Figure 1.
GENERAL DESCRIPTION
The ADP5033 combines two high performance buck regulators
and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm ×
2 mm WLCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is above
a predefined threshold. When the load current falls below a
predefined threshold, the regulator operates in power save
mode (PSM), improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor
requirement and noise.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5033 LDO extend the battery life of
portable devices. The ADP5033 LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
The regulators in the ADP5033 are activated by the ENA and ENB
pins. The specific channels controlled by ENA and ENB are set
by factory programming. A high voltage level applied to the enable
pins activates the regulators. The default output voltages are
factory programmable and can be set to a wide range of options.
Table 1. Family Models
Model Channels
Maximum
Current Package
ADP5023 2 Bucks, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10)
ADP5024 2 Bucks, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10)
ADP5034 2 Bucks, 2 LDOs 1.2 A, 300 mA
LFCSP (CP-24-10),
TSSOP (RE-28-1)
ADP5037 2 Bucks, 2 LDOs 800 mA, 300 mA LFCSP (CP-24-10)
ADP5033 2 Bucks, 2 LDOs with
2 EN pins
800 mA, 300 mA WLCSP (CB-16-8)
ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10)
ADP5041 1 Buck, 2 LDOs with
Supervisory, Watchdog,
Manual Reset
1.2 A, 300 mA LFCSP (CP-20-10)
ADP5133 2 Bucks with 2 ENx pins 800 mA WLCSP (CB-16-8)
ADP5134 2 Bucks, 2 LDOs with
precision enable and
power-good output
1.2 A, 300 mA LFCSP (CP-24-10)
Rev. G Document Feedback
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ADP5033 Data Sheet
Rev. G | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
General Specifications ................................................................. 3
BUCK1 and BUCK2 Specifications ........................................... 4
LDO1 and LDO2 Specifications ................................................. 4
Input and Output Capacitor, Recommended Specifications ........ 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Power Management Unit ........................................................... 15
BUCK1 and BUCK2 .................................................................. 16
LDO1 and LDO2 ........................................................................ 17
Applications Information .............................................................. 18
Buck External Component Selection ....................................... 18
LDO Capacitor Selection .......................................................... 20
Power Dissipation and Thermal Considerations ....................... 21
Buck Regulator Power Dissipation .......................................... 21
Junction Temperature ................................................................ 22
PCB Layout Guidelines .................................................................. 23
Typical Application Schematic ..................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
9/14—Rev. F to Rev. G
Changes to Page Layout ................................................................... 1
Changes to Table 1 ............................................................................ 1
Changes to Ordering Guide .......................................................... 26
10/13—Rev. E to Rev. F
Changes to VIN1 Undervoltage Lockout Parameter, Table 2 ..... 3
Changes to Undervoltage Lockout Section ................................. 16
Moved Ordering Guide .................................................................. 26
Changes to Ordering Guide .......................................................... 26
9/13—Rev. D to Rev. E
Changes to Table 1 ............................................................................ 1
Changes to Ordering Guide .......................................................... 25
5/13—Rev. C to Rev. D
Added Table 1; Renumbered Sequentially .................................... 1
Changes to Ordering Guide .......................................................... 25
1/13—Rev. B to Rev. C
Changes to Figure 9 .......................................................................... 9
Changes to Ordering Guide .......................................................... 25
10/12—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Buck Output Voltage Accuracy Parameter, Table 2 ....... 4
Changes to LDO Output Voltage Accuracy Parameter, Table 3 ....... 4
Changes to Figure 6 to Figure 8 ...................................................... 8
Changes to Figure 30 to Figure 32 ................................................ 12
Changes to Figure 36 Caption ....................................................... 13
Changes to Undervoltage Lockout Section ................................. 16
Moved Power Dissipation and Thermal Considerations Section .... 21
Changes to Buck Regulator Power Dissipation Section ............ 21
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
1/12—Rev. 0 to Rev. A
Changes to Features Section and General Description Section .... 1
Changes to Output Characteristics Parameter, Table 2 ................ 4
Changes to Output Characteristics Parameter, Table 3 and
Dropout Voltage Parameter, Table 3 ............................................... 4
Changes to Nominal Input and Output Capacitor Ratings
Parameter, Table 4 ............................................................................. 5
Changes to Table 5 ............................................................................. 6
Changed VIN1= VIN2 = VIN3= VIN4 = 5.0 V to VIN1= VIN2 = VIN3=
VIN4 = 3.6 V ......................................................................................... 8
Changes to Figure 4 to Figure 8 ....................................................... 8
Change to Figure 15 Caption and Figure 17 Caption ................ 10
Changes Figure 19 and Figure 20 ................................................. 10
Changes to Figure 31 and Figure 32............................................. 12
Changes to Figure 33, Figure 37, and Figure 38 ......................... 13
Changes to Buck Regulator Power Dissipation Section ............ 15
Changes to LDO Regulator Power Dissipation Section and
Junction Temperature Section ...................................................... 16
Changes to Undervoltage Lockout Section ................................. 18
Changes to LDO1 and LDO2 Section ......................................... 19
Changes to Output Capacitor Section ......................................... 20
Changes to Table 9 .......................................................................... 21
Change to Input and Output Capacitor Properties Section ..... 22
Changes to Ordering Guide .......................................................... 25
5/11—Revision 0: Initial Version
Data Sheet ADP5033
SPECIFICATIONS
GENERAL SPECIFICATIONS
VIN1 = VIN2 = VIN3 = VIN4 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and
TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN1, VIN2 2.3 5.5 V
THERMAL SHUTDOWN
Threshold TSSD TJ rising 150 °C
Hysteresis TSSD-HYS 20 °C
START-UP TIME1
BUCK1, LDO1, LDO2 tSTART1 250 µs
BUCK2 tSTART2 300 µs
ENA, ENB, MODE INPUTS
Input Logic High VIH 1.1 V
Input Logic Low VIL 0.4 V
Input Leakage Current VI-LEAKAGE 0.05 1 µA
STANDBY CURRENT
All Channels Enabled ISTBY-NOSW No load, no buck switching 108 175 µA
All Channels Disabled ISHUTDOWN TJ = −40°C to +85°C 0.3 1 µA
VIN1 UNDERVOLTAGE LOCKOUT
Low UVLO Input Voltage Rising UVLOVIN1RISE 2.275 V
Low UVLO Input Voltage Falling
UVLO
VIN1 FAL L
1.95
V
1 Start-up time is defined as the time from VIN1 > UVLOVIN1RISE to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal levels.
Rev. G | Page 3 of 28
ADP5033 Data Sheet
BUCK1 AND BUCK2 SPECIFICATIONS
VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.1
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Voltage Range VIN1, VIN2 PWM mode, ILOAD1 = ILOAD2 = 0 mA to 800 mA 2.3 5.5 V
OUTPUT CHARACTERISTICS
Output Voltage Accuracy ∆VOUT1/VOUT1, ∆VOUT2/VOUT2 PWM mode; ILOAD1 = ILOAD2 = 0 mA −1.8 +1.8 %
Line Regulation (∆VOUT1/VOUT1)/∆VIN1,
(∆VOUT2/VOUT2)/∆VIN2
PWM mode −0.05 %/V
Load Regulation (∆VOUT1/VOUT1)/∆IOUT1,
(∆VOUT2/VOUT2)/∆IOUT2
ILOAD = 0 mA to 800 mA, PWM mode −0.1 %/A
PSM CURRENT THRESHOLD
PSM to PWM Operation IPSM 100 mA
OPERATING SUPPLY CURRENT MODE = ground
BUCK1 Only IIN ILOAD1 = 0 mA, device not switching, all
other channels disabled
44 μA
BUCK2 Only IIN ILOAD2 = 0 mA, device not switching, all
other channels disabled
55 μA
BUCK1 and BUCK2 IIN ILOAD1 = ILOAD2 = 0 mA, device not switching,
LDO channels disabled
67 μA
SW CHARACTERISTICS
SW On Resistance RPFET PFET at VIN1 = 5 V 145 235 mΩ
RPFET PFET at VIN1 = 3.6 V 180 295 mΩ
RNFET NFET at VIN1 = 5 V 110 190 mΩ
R
NFET
NFET at VIN1 = 3.6 V
125
220
mΩ
Current Limit ILIMIT1, ILIMIT2 PFET switch peak current limit 1100 1350 mA
ACTIVE PULL-DOWN RPDWN-B Channel disabled 75 Ω
OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1 AND LDO2 SPECIFICATIONS
VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT =
1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN3, VIN4 1.7 5.5 V
OPERATING SUPPLY CURRENT
Bias Current per LDO2 IVIN3BIAS/IVIN4BIAS IOUT3 = IOUT4 = 0 µA 10 30 µA
IOUT3 = IOUT4 = 10 mA 60 100 µA
IOUT3 = IOUT4 = 300 mA 165 245 µA
Total System Input Current
I
IN
Includes all current into VIN1, VIN2, VIN3, and VIN4
LDO1 or LDO2 Only IOUT3 = IOUT4 = 0 µA, all other channels disabled 53 µA
LDO1 and LDO2 Only IOUT3 = IOUT4 = 0 µA, buck channels disabled 74 µA
OUTPUT CHARACTERISTICS
Output Voltage Accuracy ∆VOUT3/VOUT3,
∆VOUT4/VOUT4
100 µA < IOUT3 < 300 mA, 100 µA < IOUT4 < 300 mA −1.8 +1.8 %
Line Regulation (∆VOUT3/VOUT3)/∆VIN3,
(∆VOUT4/VOUT4)/∆VIN4
IOUT3 = IOUT4 = 1 mA −0.03 +0.03 %/V
Load Regulation3 (∆VOUT3/VOUT3)/∆IOUT3,
(∆VOUT4/VOUT4)/∆IOUT4
IOUT3 = IOUT4 = 1 mA to 300 mA 0.001 0.003 %/mA
Rev. G | Page 4 of 28
Data Sheet ADP5033
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DROPOUT VOLTAGE4 VDROPOUT VOUT3 = VOUT4 = 5.2 V, IOUT3 = IOUT4 = 300 mA 50 mV
VOUT3 = VOUT4 = 3.3 V, IOUT3 = IOUT4 = 300 mA 65 110 mV
VOUT3 = VOUT4 = 2.5 V, IOUT3 = IOUT4 = 300 mA 85 mV
VOUT3 = VOUT4 = 1.8 V, IOUT3 = IOUT4 = 300 mA 165 mV
CURRENT-LIMIT THRESHOLD5 ILIMIT3, ILIMIT4 335 600 mA
ACTIVE PULL-DOWN RPDWN-L Channel disabled 600 Ω
POWER SUPPLY REJECTION RATIO PSRR
Regulator LDO1
10 kHz, V
IN3
= 3.3 V, V
OUT3
= 2.8 V, I
OUT3
= 1 mA
60
dB
100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 62 dB
1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 63 dB
Regulator LDO2 10 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 54 dB
100 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 57 dB
1 MHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 64 dB
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 This is the input current into VIN3/VIN4, which is not delivered to the output load.
3 Based on an endpoint calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.7 V.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 5.
Parameter Symbol Min Typ Max Unit
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS
BUCK1, BUCK2 Input Capacitor Rating
C
MIN1
, C
MIN2
4.7
40
µF
BUCK1, BUCK2 Output Capacitor Rating CMIN1, CMIN2 10 40 µF
LDO1, LDO21 Input and Output Capacitor Rating CMIN3, CMIN4 1.0 µF
CAPACITOR ESR RESR 0.001 1 Ω
1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.
Rev. G | Page 5 of 28
ADP5033 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
VIN1 to AGND −0.3 V to +6 V
VIN2 to VIN1
−0.3 V to +0.3 V
PGND1, PGND2 to AGND −0.3 V to +0.3 V
VIN3, VIN4, VOUT1, VOUT2, ENA, ENB,
MODE to AGND
−0.3 V to
(VIN1 + 0.3 V)
VOUT3 to AGND −0.3 V to
(VIN3 + 0.3 V)
VOUT4 to AGND −0.3 V to
(VIN4 + 0.3 V)
SW1 to PGND1 −0.3 V to
(VIN1 + 0.3 V)
SW2 to PGND2 −0.3 V to
(VIN2 + 0.3 V)
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA ΨJB Unit
16-Ball, 0.5 mm Pitch WLCSP 57 14 °C/W
ESD CAUTION
Rev. G | Page 6 of 28
Data Sheet ADP5033
Rev. G | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
1
A
B
C
D
234
BALL A1
INDICATOR
VOUT3
AGND
VIN1
PGND1
VIN4
ENA
VOUT2
SW2
VOUT4
ENB
VIN2
PGND2
VIN3
MODE
VOUT1
SW1
09788-002
Figure 2. Pin Configuration—View from the Top of the Die
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
A1 VOUT3 LDO1 Output Voltage and Sensing Input.
A2 VIN3 LDO1 Input Supply (1.7 V to 5.5 V, VIN4 ≤ VIN1 = VIN2).
A3 VIN4 LDO2 Input Supply (1.7 V to 5.5 V, VIN3 ≤ VIN1 = VIN2).
A3 VOUT4 LDO2 Output Voltage and Sensing Input.
B1 AGND Analog Ground.
B2 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation.
B3 ENA Regulator Enable Pin A, Active High. The regulators turned on with ENA are factory programmed.
B4 ENB Regulator Enable Pin B, Active High. The regulators turned on with ENB are factory programmed.
C1 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V) and UVLO Detection. Connect VIN1 to VIN2.
C2 VOUT1 BUCK1 Output Voltage Sensing Input.
C3 VOUT2 BUCK2 Output Voltage Sensing Input.
C4 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1.
D1 PGND1 Dedicated Power Ground for BUCK1.
D2 SW1 BUCK1 Switching Node.
D3 SW2 BUCK2 Switching Node.
D4 PGND2 Dedicated Power Ground for BUCK2.
ADP5033 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1= VIN2 = VIN3= VIN4 = 3.6 V, TA = 25°C, unless otherwise noted.
09788-139
0
20
40
60
80
100
120
140
2.3 2.8 3.3 3.8 4.3 4.8 5.3
INPUT VOLTAGE (V)
QUI E S CE NT CURRENT (µ A)
Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V,
VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.3 V, All Channels Unloaded
09788-249
4
1
3
T
2
CH1 2.00VCH4 5.00VM40.0µs A CH3 2.2V
T11.20%
BW
CH250.0mAΩ
BW
BW
CH3 5.00V
BW
SW
IOUT
VOUT
EN
Figure 4. Buck1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA
4
1
3
T
2
CH1 2.00V CH4 5.00V M 40. 0µ s A CH3 2.2V
T 11.20%
BW
CH2 50.0mA Ω
BW
BW
CH3 5.00V
BW
SW
IOUT
VOUT
EN
09788-248
Figure 5. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA
00.2 0.4 0.6 0.8
0.1 0.3 0.5 0.7
09788-225
3.270
3.275
3.280
3.285
3.290
3.295
3.300
3.305
3.310
+85°C
+25°C
–40°C
VOUT (V)
IOUT (A)
Figure 6. BUCK1 Load Regulation Across Temperature, VIN = 4.2 V,
VOUT1 = 3.3 V, PWM Mode
1.798
1.800
1.802
1.804
1.806
1.808
1.810
1.812
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOUT (V)
IOUT (A)
+85°C
+25°C
–40°C
09788-224
Figure 7. BUCK2 Load Regulation Across Temperature, VIN = 3.6 V,
VOUT2 = 1.8 V, PWM Mode
0.802
0.803
0.804
0.805
0.806
0.807
0.808
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
V
OUT
(V)
I
OUT
(A)
+25°C
–40°C
09788-226
+85°C
Figure 8. BUCK1 Load Regulation Across Temperature, VIN = 3.6 V,
VOUT1 = 0.8 V, PWM Mode
Rev. G | Page 8 of 28
Data Sheet ADP5033
100
90
80
70
60
50
40
30
20
10
0110 100 1000
I
LOAD
(mA)
EF FICIENCY ( %)
09788-038
V
IN
= 3.9V
V
IN
= 4.2V
V
IN
= 5.5V
Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
VIN = 3.9V
VIN = 4.2V
VIN = 5.5V
09788-039
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09788-036
Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
VIN = 2.4V
VIN = 3.6V
VIN = 4.5V
VIN = 5.5V
09788-035
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, PWM Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09788-034
Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 0.8 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
09788-065
Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 0.8 V, PWM Mode
Rev. G | Page 9 of 28
ADP5033 Data Sheet
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
+25°C
+85°C
–40°C
09788-062
Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature,
VIN1 = 3.9 V, VOUT1 = 3.3 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
+25°C
+85°C
–40°C
09788-063
Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature,
VOUT2 = 1.8 V, Auto Mode
100
90
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
IOUT (A)
EF FICIENCY ( %)
+25°C
+85°C
–40°C
09788-200
Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature,
VOUT1 = 0.8 V, Auto Mode
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.501.21.00.80.60.40.2 I
OUT
(A)
FREQUENCY (MHz)
T
A
= +25°C
T
A
= –40° C
T
A
= +85°C
09788-040
Figure 18. BUCK2 Switching Frequency vs. Output Current, Across
Temperature, VOUT2 = 1.8 V, PWM Mode
2
4
T
1
CH1 50.0mV M 4. 00µ s A CH2 240mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
ISW
VOUT
SW
09788-251
Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
2
4
T
1
CH1 50.0mV M 4. 00µ s A CH2 220mA
T 28.40%
BW
CH2 500mA Ω
CH4 2.00V
BW
ISW
VOUT
SW
09788-250
Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Rev. G | Page 10 of 28
Data Sheet ADP5033
2
4
T
1
CH1 50mV M 400n s A CH2 220mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
ISW
VOUT
SW
09788-027
Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
2
4
T
1
CH1 50mV M 400n s A CH2 220mA
T 28.40%
CH2 500mA Ω
CH4 2.00V
ISW
VOUT
SW
09788-026
Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
CH1 50.0mV
CH3 1.00V CH4 2.00V M 1.00ms A CH3 4.80V
1
3
T 30.40%
T
VOUT
VIN
SW
09788-012
Figure 23. Buck1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, VOUT1 = 3.3 V, PWM Mode
1
4
T
3
CH1 50.0mV
CH3 1.00V CH4 2.00V M 1.00ms A CH3 4.80V
T 30.40%
VOUT
VIN
SW
09788-013
Figure 24. BUCK2 Response to Line Transient, VIN = 4.5 V to 5.0 V,
VOUT2 = 1.8 V, PWM Mode
4
1
T
2
CH1 50.0mV CH4 5.00V M 20. 0µ s A CH2 356mA
T 60.000µ s
CH2 50.0mA Ω
VOUT
IOUT
SW
09788-016
Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
4
1
T
2
CH1 50.0mV CH4 5.00V M 20. 0µ s A CH2 379mA
T 22.20%
CH2 50.0mA Ω
VOUT
I
OUT
SW
09788-015
Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT2 = 1.8 V, Auto Mode
Rev. G | Page 11 of 28
ADP5033 Data Sheet
4
2
T
1
CH1 50.0mV CH4 5.00V M 20. 0µ s A CH2 408mA
T 20.40%
CH2 200mA Ω
VOUT
I
OUT
SW
09788-017
Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA,
VOUT1 = 3.3 V, Auto Mode
4
2
T
1
CH1 100mV CH4 5.00V M 20. 0µ s A CH2 88.0mA
T 19.20%
CH2 200mA Ω
VOUT
I
OUT
SW
09788-018
Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA,
VOUT2 = 1.8 V, Auto Mode
4
1
3
T
2
CH1 5.00V CH4 5.00V M 400ns A CH4 1. 90V
T 50.00%
CH2 5.00V
CH3 5.00V
VOUT1
VOUT2
SW1
SW2
09788-066
Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
2
3
1
CH1 100mA M 40. 0µ s A CH2 4.20V
T 159.400µ s
CH2 5.00V
CH3 1.00V
VOUT
EN
I
IN
09788-022
Figure 30. LDO Startup, VOUT3 = 1.8 V
3.294
3.295
3.296
3.297
3.298
3.299
3.300
3.301
3.302
3.303
3.304
00.1 0.2 0.3
V
IN
= 4.2V
V
IN
= 5.5V
V
IN
= 3.8V
09788-232
V
OUT
(V)
I
OUT
(A)
Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 3.3 V
1.792
1.793
1.794
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
00.1 0.2 0.3
+85°C
–40°C
+25°C
09788-233
V
OUT
(V)
I
OUT
(A)
Figure 32. LDO Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 1.8 V
Rev. G | Page 12 of 28
Data Sheet ADP5033
0
0.5
1.0
1.5
2.0
2.5
3.0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
V
IN
(V)
I
OUT
= 300mA
I
OUT
= 150mA
I
OUT
= 100mA
I
OUT
= 1mA
I
OUT
= 10mA I
OUT
= 100µA
09788-234
V
OUT
(V)
Figure 33. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V
00.05 0.10 0.15 0.20 0.25
GRO UND CURRE NT (µ A)
LOAD CURRENT ( A)
09788-136
0
5
10
15
20
25
30
35
40
45
50
Figure 34. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
2
T
1
CH1 100mV M 40.0µs A CH2 52.0mA
T 19.20%
CH2 100mA Ω
VOUT
IOUT
09788-019
Figure 35. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA,
VOUT3 = 2.8 V
2
3
T
1
CH1 20.0mV
CH3 1.00V M 100µ s A CH3 4.80V
T 28.40%
VOUT
VIN
09788-014
Figure 36. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V,
VOUT3 = 2.8 V
60
55
50
45
40
35
30
25
0.001 0.01 0.1 110 100
I
LOAD
(mA)
RMS NOISE (µV)
V
IN
= 5V
V
IN
= 3.3V
09788-255
Figure 37. LDO Output Noise vs. Load Current, Across Input Voltage,
VOUT3 = 2.8 V
60
65
55
50
45
40
35
30
25
0.001 0.01 0.1 110 100
I
LOAD
(mA)
RMS NOISE (µV)
09788-256
V
IN
= 5V
V
IN
= 3.3V
Figure 38. LDO Output Noise vs. Load Current, Across Input Voltage,
VOUT3 = 3.0 V
Rev. G | Page 13 of 28
ADP5033 Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
PSRR (dB)
100µA
1mA
10mA
50mA
100mA
150mA
09788-050
Figure 39. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
PSRR (dB)
100µA
1mA
10mA
50mA
100mA
150mA
09788-051
Figure 40. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
PSRR (dB)
100µA
1mA
10mA
50mA
100mA
150mA
09788-053
Figure 41. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
PSRR (dB)
100µA
1mA
10mA
50mA
100mA
150mA
09788-052
Figure 42. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V
Rev. G | Page 14 of 28
Data Sheet ADP5033
Rev. G | Page 15 of 28
THEORY OF OPERATION
ENABLE
AND MODE
CONTROL LDO
CONTROL
LDO
UNDERVOLTAGE
LOCK OUT
SOFT START
PWM/
PSM
CONTROL
BUCK2
DRIVER
AND
ANTISHOOT
THROUGH
SOFT START
PWM/
PSM
CONTROL
BUCK1
DRIVER
AND
ANTISHOOT
THROUGH
OSCILLATOR
THERMAL
SHUTDOWN
SYSTEM
UNDERVOLTAGE
LOCKOUT
PWM
COMP
GM ERROR
AMP
GM ERROR
AMP
PSM
COMP
PSM
COMP
LOW
CURRENT
I
LIMIT
PWM
COMP
LOW
CURRENT
I
LIMIT
R1
R2
ADP5033
V
OUT1
V
OUT2
VIN1
SW1
PGND1
ENA ENBK1
ENBK2
ENLDO1
ENLDO2
ENB VDDA
VIN3 AGND VOUT3
PGND2
MODE
SW2
VIN2
LDO
CONTROL
LDO
UNDERVOLTAGE
LOCK OUT
R3
R4
VDDA
VIN4 VOUT4
ENLDO1
600Ω
ENBK2
75Ω
ENBK1 75Ω
ENLDO1 600Ω
B
A
Y
SEL
OPMODE
MODE2
09788-003
VDDA
Figure 43. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5033 is a micropower management unit (μPMU)
combing two step-down (buck) dc-to-dc convertors and two
low dropout linear regulators (LDO). The high switching
frequency and tiny 16-ball WLCSP package allow for a small
power management solution.
To combine these high performance regulators into the μPMU,
there is a system controller allowing them to operate together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not change
with the load current. If the MODE pin is at logic low, the
switching regulators operate in auto PWM/PSM mode. In this
mode, the regulators operate at fixed PWM frequency when the
load current is above the power saving current threshold. When
the load current falls below the power save current threshold,
the regulator in question enters PSM where the switching occurs in
bursts. The burst repetition is a function of the current load and
the output capacitor value. This operating mode reduces the
switching and quiescent current losses.
The auto PWM/PSM mode transition is controlled independently
for each buck regulator. The two bucks operate synchronized to
each other.
When a regulator is turned on, the output voltage ramp is
controlled through a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current opera-
tion, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
ADP5033 Data Sheet
Rev. G | Page 16 of 28
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout (UVLO)
circuitry is integrated in the system. If the input voltage on VIN1
drops below a typical 2.15 V UVLO threshold, all channels shut
down. In the buck channels, both the power switch and the
synchronous rectifier turn off. When the voltage on VIN1 rises
above the UVLO threshold, the part is enabled once more.
Alternatively, the user can request a new device model with a
UVLO set at a higher level, suitable for 5 V supply applications.
For these models, the device reaches the turn-off threshold when
the input supply drops to 3.65 V typical. To order a device with
options other than the default options listed in the Ordering
Guide section, contact your local Analog Devices, Inc., sales or
distribution representative.
In case of a thermal or UVLO event, the active pull-down resistors
(if factory enabled) are enabled to discharge the output capacitors
quickly. The pull-down resistors remain engaged until the
thermal fault event is no longer present or the input supply
voltage falls below the VPOR voltage level. The typical value of
VPOR is approximately 1 V.
Enable/Shutdown
The ADP5033 has two enable pins (ENA and ENB). A high
level applied to the enable pins enables a certain selection of
regulators defined by factory programming. For example, the
ADP5033 can be factory programmed to enable BUCK1 and
LDO2 with ENA and BUCK2 and LDO1 with ENB. When both
enables are low, all regulators are turned off. When both enable
pins are high, all regulators are turned on. All possible regulator
combinations can be factory programmed to operate with the
ENA and ENB pins.
Figure 44 shows the regulator activation timings for the ADP5033
when both enables are connected to VINx. Figure 44 also shows
the active pull-down activation.
BUCK1 AND BUCK2
The two bucks use a fixed frequency and high speed current
mode architecture. The bucks operate with an input voltage of
2.3 V to 5.5 V.
Control Scheme
The bucks operate with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a PSM control scheme at light loads to lower the
regulation power losses. When operating in fixed frequency
PWM mode, the duty cycle of the integrated switches is adjusted
and regulates the output voltage. When operating in PSM at
light loads, the output voltage is controlled in a hysteretic
manner, with higher output voltage ripple. During part of this
time, the converter is able to stop switching and enters an idle
mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
VIN1
VOUT3
VOUT4
VOUT1
VUVLO
VOUT2
VPOR
BUCK2
PULL-DOWN
BUCK1, LDO1, LDO2
PULL-DOWNS
50µs (MIN)
30µs (MIN)
50µs (MIN)
30µs (MIN)
09788-148
Figure 44. Regulators Sequencing on the ADP5033 (ENx = VINx)
Data Sheet ADP5033
PSM
The bucks smoothly transition to PSM operation when the load
current decreases below the PSM current threshold. When either of
the bucks enters PSM, an offset is induced in the PWM regulation
level, which makes the output voltage rise. When the output
voltage reaches a level approximately 1.5% above the PWM
regulation level, PWM operation is turned off. At this point,
both power switches are off, and the buck enters an idle mode.
The output capacitor discharges until the output voltage falls to
the PWM regulation voltage, at which point the device drives
the inductor to make the output voltage rise again to the upper
threshold. This process is repeated while the load current is
below the PSM current threshold.
The ADP5033 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces both bucks to operate in PWM mode. A logic level
low sets the bucks to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The bucks employ a
scheme that enables this current to remain accurately controlled,
independent of input and output voltage levels. This scheme
also ensures that there is very little hysteresis between the PSM
current threshold for entry to and exit from the PSM. The PSM
current threshold is optimized for excellent efficiency over all
load currents.
Oscillator/Phasing of Inductor Switching
The ADP5033 ensures that both bucks operate at the same
switching frequency when both bucks are in PWM mode.
Additionally, the ADP5033 ensures that when both bucks are in
PWM mode, they operate out of phase, whereby the BUCK2 PFET
starts conducting exactly half a clock period after the BUCK1
PFET starts conducting.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possibility
of a hard short at the output, the switching frequency is reduced
to half the internal oscillator frequency. The reduction in the
switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the output
voltage in a controlled manner upon startup, thereby limiting
the inrush current. This prevents possible input voltage drops
when a battery or a high impedance power source is connected
to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the output.
The negative current limit prevents the inductor current from
reversing direction and flowing out of the load.
100% Duty Operation
With a dropin input voltage or with an increase in load current,
the buck may reach a limit where, even with the PFET switch on
100% of the time, the output voltage drops below the desired
output voltage. At this limit, the buck transitions to a mode where
the PFET switch stays on 100% of the time. When the input
conditions change again and the required duty cycle falls, the
buck immediately restarts PWM regulation without allowing
overshoot on the output voltage.
Active Pull-Downs
All regulators have optional, factory programmable, active pull-
down resistors discharging the respective output capacitors when
the regulators are disabled by the ENx pins or by a faulty condition.
The pull-down resistors are connected between VOUTx and
AGND. Active pull-downs are disabled when the regulators are
turned on. The typical value of the pull-down resistor is 600 Ω for
the LDOs and 75 Ω for the bucks. Figure 44 shows the activation
timings for the active pull-down during regulator activation and
deactivation.
LDO1 AND LDO2
The ADP5033 contains two LDOs with low quiescent current
and low dropout voltage, and provides up to 300 mA of output
current. Drawing a low 25 μA quiescent current (typical) at no load
makes the LDO ideal for battery-operated portable equipment.
Each LDO operates with an input voltage of 1.7 V to 5.5 V. The
wide operating range makes these LDOs suitable for cascading
configurations where the LDO supply voltage is provided from
one of the buck regulators.
Each LDO also provides high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with just a small 1 µF ceramic input and output capacitor.
LDO1 is optimized to supply analog circuits because it offers
better noise performance compared to LDO2. LDO1 should be
used in applications where noise performance is critical.
Rev. G | Page 17 of 28
ADP5033 Data Sheet
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Inductor
The high switching frequency of the ADP5033 bucks allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 μH and 3 μH. Suggested inductors
are shown in Table 9.
The peak-to-peak inductor current ripple is calculated using
the following equation:
L
fV
V
VV
I
SW
IN
OUT
IN
OUT
RIPPLE
×
×
−×
=)
(
where:
fSW is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
2
)
(
RIPPLE
MAX
LOAD
PEAK
I
II +
=
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the bucks are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for
its low core losses and low EMI.
Table 9. Suggested 1.0 μH Inductors
Vendor Model
Dimensions
(mm)
ISAT
(mA)
DCR
(mΩ)
Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
Murata LQM18FN1R0M00B 1.6 × 0.8 × 0.8 150 26
Taiyo Yuden BRC1608T1R0M 1.6 × 0.8 × 0.8 520 180
Coilcraft EPL2014-102ML 2.0 × 2.0 × 1.4 900 59
TDK GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8 230 80
Coilcraft 0603LS-102 1.8 × 1.69 × 1.1 400 81
Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
dc-to-dc converter because of their poor temperature and dc
bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated
using the following equation:
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT is 9.2 μF at 1.8 V, as shown in Figure 45.
Substituting these values in the equation yields
CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF
To guarantee the performance of the bucks, it is imperative that
the effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
0
2
4
6
8
10
12
0123456
DC BIAS V OL TAGE ( V )
CAPACITANCE ( µ F)
09788-004
Figure 45. Typical Capacitor Performance
Rev. G | Page 18 of 28
Data Sheet ADP5033
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
( )
OUT
SW
IN
OUT
SW
RIPPLE
RIPPLE
CLf
V
Cf
I
V×××π
≈
××
=
2
28
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
RIPPLE
RIPPLE
COUT
I
V
ESR ≤
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
The buck regulators require 10 µF output capacitors to guarantee
stability and response to rapid load variations and to transition
into and out of the PWM/PSM modes. In certain applications,
where one or both buck regulators power a processor, the
operating state is known because it is controlled by software.
In this condition, the processor can drive the MODE pin
according to the operating state; consequently, it is possible to
reduce the output capacitor from 10 µF to 4.7 µF because the
regulator does not expect a large load variation when working
in PSM mode (see Figure 47).
Table 10. Suggested 10 μF Capacitors
Vendor Type Model Case Size Voltage Rating (V)
Murata X5R GRM188R60J106 0603 6.3
TDK X5R C1608JB0J106K 0603 6.3
Panasonic X5R ECJ1VB0J106M 0603 6.3
Rev. G | Page 19 of 28
ADP5033 Data Sheet
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
IN
OUT
IN
OUT
MAXLOAD
CIN V
VVV
II )(
)(
−
≥
To minimize supply noise, place the input capacitor as close to
the VINx pin of the buck as possible. As with the output capacitor,
a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Table 11.
Table 11. Suggested 4.7 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating (V)
Murata X5R GRM188R60J475ME19D 0402 6.3
Taiyo Yuden
X5R
JMK107BJ475
0402
6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5033 LDOs are designed for operation with small,
space-saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects the stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or
less is recommended to ensure the stability of the ADP5033.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP5033 to large changes
in load current.
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 µF of output
capacitance is required, increase the input capacitor to match it.
Table 12. Suggested 1.0 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating (V)
Murata X5R GRM155B30J105K 0402 6.3
TDK X5R C1005JB0J105KT 0402 6.3
Panasonic
X5R
ECJ0EB0J105K
0402
6.3
Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5033 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
LDO because of their poor temperature and dc bias characteristics.
Figure 46 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
00 1 2 3 4 5 6
DC BIAS V OL TAGE ( V )
CAPACITANCE ( µ F)
09788-006
Figure 46. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capacitance
accounting for capacitor variation over temperature, component
tolerance, and voltage:
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.85 μF at 1.8 V, as shown in Figure 46.
Substituting these values into the following equation,
CEFF = 0.85 μF × (1 − 0.15) × (1 − 0.1) ≈ 0.65 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5033, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Rev. G | Page 20 of 28
Data Sheet ADP5033
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5033 is a highly efficient micropower management
unit (µPMU), and, in most cases, the power dissipated in the
device is not a concern. However, if the device operates at high
ambient temperatures and maximum loading condition, the
junction temperature can reach the maximum allowable
operating limit (125°C).
When the temperature exceeds 150°C, the ADP5033 turns off
all the regulators, allowing the device to cool down. When the
die temperature falls below 130°C, the ADP5033 resumes
normal operation.
This section provides guidelines to calculate the power dissi-
pated in the device and ensure that the ADP5033 operates
below the maximum allowable junction temperature.
The efficiency for each regulator on the ADP5033 is given by
100%
×=
IN
OUT
P
P
η
(1)
where:
η is the efficiency.
PIN is the input power.
POUT is the output power.
Power loss is given by
PLOSS = PIN − POUT (2a)
or
PLOSS = POUT (1− η)/η (2b)
Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at the
input and all the outputs. Perform the measurements at the
worst-case conditions (voltages, currents, and temperature).
The difference between input and output power is dissipated in
the device and the inductor. Use Equation 4 to derive the power
lost in the inductor and, from this, use Equation 3 to calculate
the power dissipation in the ADP5033 buck converter.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, and the power
lost on each LDO can be calculated using Equation 12. When
the buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 4 to
derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the two LDOs to find
the total dissipated power.
Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of VIN, VOUT, and
IOUT. To account for these variations, it is necessary to include a
safety margin when calculating the power dissipated in the buck.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDO provided
by Equation 12.
BUCK REGULATOR POWER DISSIPATION
The power loss of the buck regulator is approximated by
PLOSS = PDBUCK + PL (3)
where:
PDBUCK is the power dissipation on one of the ADP5033 buck
regulators.
PL is the inductor power losses.
The inductor losses are external to the device, and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
PL ≈ IOUT1(RMS)2 × DCRL (4)
where:
DCRL is the inductor series resistance.
IOUT1(RMS) is the rms load current of the buck regulator.
12
+1
)(
1
r
I
IOUT1
RMS
OUT ×
=
(5)
where r is the normalized inductor ripple current
r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6)
where:
L is the inductance.
fSW is the switching frequency.
D is the duty cycle.
D = VOUT1/VIN1 (7)
The ADP5033 buck regulator power dissipation, PDBUCK, includes
the power switch conductive losses, the switch losses, and the
transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation 8
captures the calculation that must be made to estimate the
power dissipation in the buck regulator.
PDBUCK = PCOND + PSW + PTRAN (8)
The power switch conductive losses are due to the output current,
IOUT1, flowing through the P-MOSFET and the N-MOSFET
power switches that have internal resistance, RDSON-P and
RDSON-N. The amount of conductive power loss is found by
PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1(RMS)2 (9)
where RDSON-P is approximately 0.2 Ω, and RDSON-N is approxi-
mately 0.16 Ω at 25°C junction temperature and VIN1 = VIN2 =
3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and
0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are
0.16 Ω and 0.14 Ω, respectively.
Rev. G | Page 21 of 28
ADP5033 Data Sheet
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10)
where:
CGATE -P is the P-MOSFET gate capacitance.
CGATE -N is the N-MOSFET gate capacitance.
For the ADP5033, the total of (CGATE-P + CGATE-N) is approxi-
mately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
VOUT1 (and from VOUT1 to ground). The amount of transition
loss is calculated by
PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11)
where tRISE and tFALL are the rise time and the fall time of the
switching node, SW. For the ADP5033, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimat-
ing the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (12)
where:
ILOAD is the load current of the LDO regulator.
VIN and VOUT are input and output voltages of the LDO,
respectively.
IGND is the ground current of the LDO regulator.
Power dissipation due to the ground current is small, and it
can be ignored.
JUNCTION TEMPERATURE
In cases where the board temperature TA is known, the thermal
resistance parameter, θJA, can be used to estimate the junction
temperature rise. TJ is calculated from TA and PD using the
formula
TJ = TA + (PD × θJA) (14)
The typical θJA value for the 16-ball, 0.5 mm pitch WLCSP is
57°C/W (see Table 7). A very important factor to consider is
that θJA is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction tempera-
ture is calculated by
TJ = TC + (PD × ΨJB) (15)
where TC is the case temperature and ΨJB is the junction-to-
board thermal resistance provided in Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5033 power
dissipation (PD) due to the losses of all channels by using the
Equation 8 to Equation 13. From this power calculation, the
junction temperature, TJ, can be estimated using Equation 14.
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5033 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBF) is highly affected by increas-
ing the junction temperature. Additional information about
product reliability can be found in the ADI Reliability Handbook,
which can be found at www.analog.com/reliability_handbook.
The total power dissipation in the ADP5033 simplifies to
PD = PDBUCK1 + PDBUCK2 + PDLDO1 + PDLDO2 (13)
Rev. G | Page 22 of 28
Data Sheet ADP5033
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5033 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise interfer-
ence on sensitive circuit nodes.
• Connect VIN1 and VIN2 together close to the IC using
short tracks.
Rev. G | Page 23 of 28
ADP5033 Data Sheet
Rev. G | Page 24 of 28
TYPICAL APPLICATION SCHEMATIC
VIN1
ENA
VIN:
2.3V TO 5.5V
SW1
VOUT1
VCORE
VCORE
VIO
VIO
GPIO
PGND1
MODE
C5
4.7µF
L1 1µH
BUCK1
ACT
C2
4.7µF
C1
4.7µF
VIN2
ENB
AGND
BUCK2
ON
OFF
SW2
VOUT2
PGND2
C6
4.7µF
L2 1µH
VOUT3
C7
1µF
VOUT4
C8
1µF
PROCESSOR
VANA
VDIG
ANALOG
SUBSYSTEM
VIN3
C3
1µF
FROM VIO
(1.7V MIN)
LDO1
VIN4
C4
1µF
FROM VCORE
(1.7V MIN)
A
DP5033
ALWAYS ON
BK1
BK2
LD1
LD2
LDO2
09788-152
Figure 47. Processor System Power Management with PSM/PWM Control
Data Sheet ADP5033
OUTLINE DIMENSIONS
10-19-2012-B
A
B
C
D
0.660
0.600
0.540
SIDE VIEW
0.270
0.240
0.210
0.390
0.360
0.330
0.360
0.320
0.280
COPLANARITY
0.04
SEATING
PLANE
1
2
3
4
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SI DE DOW N)
BALLA1
IDENTIFIER
0.50
REF
1.50
REF
2.040
2.000 SQ
1.960
Figure 48. 16-Ball Wafer Level Chip Scale Package [WLCSP]
Back-Coating Included
(CB-16-8)
Dimensions shown in millimeters
Rev. G | Page 25 of 28
ADP5033 Data Sheet
ORDERING GUIDE
Model1
Temperature
Range
Output
Voltage (V)2 Options
ENA Controlled
Channels3
Package
Description
Package
Option Branding
ADP5033ACBZ-1-R7 −40°C to +125°C VOUT1: 1.2 V,
VOUT2: 3.3 V,
VOUT3: 2.8 V,
VOUT4: 1.8 V
UVLO: low,
pull-downs
on buck
channels only
BUCK2, LDO1 16-Ball WLCSP CB-16-8 LHX
ADP5033ACBZ-2-R7 −40°C to +125°C VOUT1: 1.8 V,
VOUT2: 2.8 V,
VOUT3: 2.8 V,
VOUT4: 3.0 V
UVLO: low,
pull-downs
on all
channels
BUCK1, BUCK2,
LDO1
16-Ball WLCSP CB-16-8 LMD
ADP5033ACBZ-3-R7 −40°C to +125°C VOUT1: 3.0 V,
VOUT2: 1.2 V,
VOUT3: 1.8 V,
VOUT4: 3.0 V
UVLO: low,
pull-downs
on all
channels
BUCK1, LDO1,
LDO2
16-Ball WLCSP CB-16-8 LNC
ADP5033ACBZ-4-R7 −40°C to +125°C VOUT1: 0.9 V,
VOUT2: 0.9 V,
VOUT3: 3.0 V,
VOUT4: 2.8 V
UVLO: low,
pull-downs
disabled
BUCK1, BUCK2 16-Ball WLCSP CB-16-8 LNR
ADP5033ACBZ-5-R7 −40°C to +125°C VOUT1: 3.3 V,
VOUT2: 1.8 V,
VOUT3: 1.2 V,
VOUT4: 1.5 V
UVLO: low,
pull-downs
on all
channels
BUCK1 16-Ball WLCSP CB-16-8 LQ3
ADP5033ACBZ-6-R7 −40°C to +125°C VOUT1: 1.8 V,
VOUT2: 2.5 V,
VOUT3: 3.0 V,
VOUT4: 3.0 V
UVLO: low,
pull-downs
on all
channels
BUCK1, LDO1 16-Ball WLCSP CB-16-8 LQ5
ADP5033ACBZ-7-R7 −40°C to +125°C VOUT1: 1.1 V,
VOUT2: 1.8 V,
VOUT3: 2.5 V,
VOUT4: 3.2 V
UVLO: low,
pull-downs
on all
channels
BUCK1 16-Ball WLCSP CB-16-8 LRB
ADP5033ACBZ-8-R7 −40°C to +125°C VOUT1: 2.8 V,
VOUT2: 1.5 V,
VOUT3: 2.8 V,
VOUT4: 1.8 V
UVLO: low,
pull-downs
on all
channels
BUCK1, BUCK2,
LDO2
16-Ball WLCSP CB-16-8 LRC
ADP5033ACBZ-9-R7 −40°C to +125°C VOUT1: 1.1 V,
VOUT2: 1.8 V,
VOUT3: 1.2 V,
VOUT4: 3.2 V
UVLO: low,
pull-downs
on all
channels
BUCK1 16-Ball WLCSP CB-16-8 LRD
ADP5033-1-EVALZ Evaluation Board for
ADP5033ACBZ-1-R7
1 Z = RoHS Compliant Part.
2 For additional options, contact a local sales or distribution representative. Additional options available include the following:
BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, or 0.9 V.
LDO1 and LDO2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or 0.8 V.
UVLO: low or high.
In addition, for BUCK1, BUCK2, LDO1, and LDO2, active pull-down resistor is programmable to be either enabled or disabled.
3 ENA activated channels (ENB controls the other channels).
Rev. G | Page 26 of 28
Data Sheet ADP5033
NOTES
Rev. G | Page 27 of 28
