Low Cost, High Speed,
Rail-to-Rail Amplifiers
AD8051/AD8052/AD8054
Rev. J
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FEATURES
High speed and fast settling on 5 V
110 MHz, −3 dB bandwidth (G = +1) (AD8051/AD8052)
150 MHz, −3 dB bandwidth (G = +1) (AD8054)
145 V/μs slew rate
50 ns settling time to 0.1%
Single-supply operation
Output swings to within 25 mV of either rail
Input voltage range: −0.2 V to +4 V; VS = 5 V
Video specifications (G = +2)
0.1 dB gain flatness: 20 MHz; RL = 150 Ω
Differential gain/phase: 0.03%/0.03°
Low distortion
−80 dBc total harmonic @ 1 MHz, RL = 100 Ω
Outstanding load drive capability
Drives 45 mA, 0.5 V from supply rails (AD8051/AD8052)
Drives 50 pF capacitive load (G = +1) (AD8051/AD8052)
Low power: 2.75 mA/amplifier (AD8054)
Low power: 4.4 mA/amplifier (AD8051/AD8052)
APPLICATIONS
Active filters
Analog-to-digital drivers
Clock buffer
Consumer video
Professional cameras
CCD imaging systems
CD/DVD ROMs
PIN CONNECTIONS (TOP VIEWS)
8
7
6
5
1
2
3
4
NC
–IN
+IN
NC
NC
AD8051
NC = NO CONNECT
+V
S
V
OUT
–V
S
01062-001
1
2
3
5
4–IN+IN
AD8051
+–
+V
S
V
OUT
–V
S
01062-002
Figure 1. SOIC-8 (R) Figure 2. SOT-23-5 (RJ)
8
7
6
5
1
2
3
4
+
–
+
–
OUT1
–IN1
+IN1
OUT
–IN2
AD8052
+IN2
+VS
–VS
01062-003
V+
+IN B
OUT B
OUT D
+IN D
V–
+IN C
OUT C
AD8054
+IN A
OUT A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
–IN A
–IN B
–IN D
–IN C
0
1062-004
Figure 3. SOIC (R-8) and MSOP (RM-8) Figure 4. SOIC (R-14) and TSSOP (RU-14)
FREQUENCY (MHz)
4.5
0
50
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
5.0
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
(THD ≤ 0.5%) (V)
0.1 1 10
V
S
= 5V
G = –1
R
F
= 2kΩ
R
L
= 2kΩ
0
1062-005
Figure 5. Low Distortion Rail-to-Rail Output Swing
GENERAL DESCRIPTION
The AD8051 (single), AD8052 (dual), and AD8054 (quad) are
low cost, high speed, voltage feedback amplifiers. The amplifiers
operate on +3 V, +5 V, or ±5 V supplies at low supply current.
They have true single-supply capability with an input voltage
range extending 200 mV below the negative rail and within 1 V
of the positive rail.
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage
swings to within 25 mV of each rail, providing maximum output
dynamic range with excellent overdrive recovery.
The AD8051/AD8052/AD8054 are well suited for video
electronics, cameras, video switchers, or any high speed portable
equipment. Low distortion and fast settling make them ideal for
active filter applications.
The AD8051/AD8052 in the 8-lead SOIC, the AD8052 in the
MSOP, the AD8054 in the 14-lead SOIC, and the 14-lead TSSOP
packages are available in the extended temperature range of
−40°C to +125°C.
AD8051/AD8052/AD8054
Rev. J | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connections (Top Views) ......................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
Maximum Power Dissipation ..................................................... 9
ESD Caution .................................................................................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
Circuit Description .................................................................... 16
Application Information ................................................................ 17
Overdrive Recovery ................................................................... 17
Driving Capacitive Loads .......................................................... 17
Layout Considerations ............................................................... 18
Active Filters ............................................................................... 18
Analog-to-Digital and Digital-to-Analog Applications ........ 19
Sync Stripper ............................................................................... 20
Single-Supply Composite Video Line Driver ......................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/09—Rev. I to Rev. J
Changes to Figure 22 ...................................................................... 12
12/08—Rev. H to Rev. I
Change to Settling Time to 0.1% Parameter, Table 1 ................... 3
Updated Outline Dimensions ....................................................... 20
12/07—Rev. G to Rev. H
Changes to Applications .................................................................. 1
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
5/06—Rev. F to Rev. G
Updated Format .................................................................. Universal
Changes to Features, Applications, and General Description ..... 1
Changes to Figure 15 ...................................................................... 12
Changes to the Ordering Guide .................................................... 22
9/04—Rev. E to Rev. F
Changes to Ordering Guide ............................................................. 7
Changes to Figure 15 ...................................................................... 15
3/04—Rev. D to Rev. E
Changes to General Description ..................................................... 2
Changes to Specifications ................................................................. 3
Changes to Ordering Guide ............................................................. 6
2/03—Rev. C to Rev. D
Changes to General Description ..................................................... 1
Changes to Specifications ................................................................. 3
Changes to Absolute Maximum Ratings ........................................ 6
1/03—Rev. B to Rev. C
Changes to General Description ..................................................... 1
Changes to Pin Connections ............................................................ 1
Changes to Specifications ................................................................. 2
Changes to Absolute Maximum Ratings ........................................ 9
Changes to Figure 2 ........................................................................... 9
Changes to Ordering Guide ............................................................. 9
Updated Outline Dimensions ........................................................ 20
AD8051/AD8052/AD8054
Rev. J | Page 3 of 24
SPECIFICATIONS
@ TA = 25°C, VS = 5 V, RL = 2 k to 2.5 V, unless otherwise noted.
Table 1.
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VOUT = 0.2 V p-p 70 110 80 150 MHz
G = −1, +2, VOUT = 0.2 V p-p 50 60 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω to 2.5 V
RF = 806 Ω (AD8051A/
AD8052A)
20 MHz
R
F = 200 Ω (AD8054A) 12 MHz
Slew Rate G = −1, VOUT = 2 V step 100 145 140 170 V/μs
Full Power Response G = +1, VOUT = 2 V p-p 35 45 MHz
Settling Time to 0.1% G = −1, VOUT = 2 V step 50 40 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1 fC = 5 MHz, VOUT = 2 V p-p,
G = +2
−67 −68 dB
Input Voltage Noise f = 10 kHz 16 16 nV/√Hz
Input Current Noise f = 10 kHz 850 850 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.09 0.07 %
R
L = 1 kΩ to 2.5 V 0.03 0.02 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.19 0.26 Degrees
R
L = 1 kΩ to 2.5 V 0.03 0.05 Degrees
Crosstalk f = 5 MHz, G = +2 −60 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.7 10 1.7 12 mV
T
MIN − TMAX 25 30 mV
Offset Drift 10 15 μV/°C
Input Bias Current 1.4 2.5 2 4.5 μA
T
MIN − TMAX 3.25 4.5 μA
Input Offset Current 0.1 0.75 0.2 1.2 μA
Open-Loop Gain RL = 2 kΩ to 2.5 V 86 98 82 98 dB
T
MIN − TMAX 96 96 dB
R
L = 150 Ω to 2.5 V 76 82 74 82 dB
T
MIN − TMAX 78 78 dB
INPUT CHARACTERISTICS
Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range −0.2 to
+4
−0.2 to
+4
V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 72 88 70 86 dB
AD8051/AD8052/AD8054
Rev. J | Page 4 of 24
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 2.5 V 0.015 to
4.985
0.03 to
4.975
V
R
L = 2 kΩ to 2.5 V 0.1 to
4.9
0.025 to
4.975
0.125 to
4.875
0.05 to
4.95
V
R
L = 150 Ω to 2.5 V 0.3 to
4.625
0.2 to
4.8
0.55 to
4.4
0.25 to
4.65
V
Output Current VOUT = 0.5 V to 4.5 V 45 30 mA
T
MIN − TMAX 45 30 mA
Short-Circuit Current Sourcing 80 45 mA
Sinking 130 85 mA
Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF
G = +2 (AD8054) 40 pF
POWER SUPPLY
Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.4 5 2.75 3.275 mA
Power Supply Rejection Ratio ΔVS = ±1 V 70 80 68 80 dB
OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C
RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C
1 Refer to Figure 19.
AD8051/AD8052/AD8054
Rev. J | Page 5 of 24
@ TA = 25°C, VS = 3 V, RL = 2 k to 1.5 V, unless otherwise noted.
Table 2.
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VOUT = 0.2 V p-p 70 110 80 135 MHz
G = −1, +2, VOUT =
0.2 V p-p
50 65 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω to 2.5 V
RF = 402 Ω (AD8051A/
AD8052A)
17 MHz
R
F = 200 Ω (AD8054A) 10 MHz
Slew Rate G = −1, VOUT = 2 V step 90 135 110 150 V/μs
Full Power Response G = +1, VOUT = 1 V p-p 65 85 MHz
Settling Time to 0.1% G = −1, VOUT = 2 V step 55 55 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1 fC = 5 MHz, VOUT = 2 V p-p,
G = −1, RL = 100 Ω to 1.5 V
−47 −48 dB
Input Voltage Noise f = 10 kHz 16 16 nV/√Hz
Input Current Noise f = 10 kHz 600 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, VCM = 1 V
R
L = 150 Ω to 1.5 V 0.11 0.13 %
R
L = 1 kΩ to 1.5 V 0.09 0.09 %
Differential Phase Error (NTSC) G = +2, VCM = 1 V
R
L = 150 Ω to 1.5 V 0.24 0.3 Degrees
R
L = 1 kΩ to 1.5 V 0.10 0.1 Degrees
Crosstalk f = 5 MHz, G = +2 −60 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.6 10 1.6 12 mV
T
MIN − TMAX 25 30 mV
Offset Drift 10 15 μV/°C
Input Bias Current 1.3 2.6 2 4.5 μA
T
MIN − TMAX 3.25 4.5 μA
Input Offset Current 0.15 0.8 0.2 1.2 μA
Open-Loop Gain RL = 2 kΩ 80 96 80 96 dB
T
MIN − TMAX 94 94 dB
R
L = 150 Ω 74 82 72 80 dB
T
MIN − TMAX 76 76 dB
INPUT CHARACTERISTICS
Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range −0.2 to
+2
−0.2 to
+2
V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 88 70 86 dB
AD8051/AD8052/AD8054
Rev. J | Page 6 of 24
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 1.5 V 0.01 to
2.99
0.025 to
2.98
V
R
L = 2 kΩ to 1.5 V 0.0.75 to
2.9
0.02 to
2.98
0.1 to
2.9
0.35 to
2.965
V
R
L = 150 Ω to 1.5 V 0.2 to
2.75
0.125 to
2.875
0.35 to
2.55
0.15 to
2.75
V
Output Current VOUT = 0.5 V to 2.5 V 45 25 mA
T
MIN − TMAX 45 25 mA
Short-Circuit Current Sourcing 60 30 mA
Sinking 90 50 mA
Capacitive Load Drive G = +1 (AD8051/AD8052) 45 pF
G = +2 (AD8054) 35 pF
POWER SUPPLY
Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.2 4.8 2.625 3.125 mA
Power Supply Rejection Ratio ΔVS = 0.5 V 68 80 68 80 dB
OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C
RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C
1 Refer to Figure 19.
AD8051/AD8052/AD8054
Rev. J | Page 7 of 24
@ TA = 25°C, VS = ±5 V, RL = 2 k to ground, unless otherwise noted.
Table 3.
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VOUT = 0.2 V p-p 70 110 85 160 MHz
G = −1, +2, VOUT = 0.2 V p-p 50 65 MHz
Bandwidth for 0.1 dB Flatness G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω,
RF = 1.1 kΩ (AD8051A/
AD8052A)
20 MHz
R
F = 200 Ω (AD8054A) 15 MHz
Slew Rate G = −1, VOUT = 2 V step 105 170 150 190 V/μs
Full Power Response G = +1, VOUT = 2 V p-p 40 50 MHz
Settling Time to 0.1% G = −1, VOUT = 2 V step 50 40 MHz
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VOUT = 2 V p-p,
G = +2
−71 −72 dB
Input Voltage Noise f = 10 kHz 16 16 nV/√Hz
Input Current Noise f = 10 kHz 900 900 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω 0.02 0.06 %
R
L = 1 kΩ 0.02 0.02 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω 0.11 0.15 Degrees
R
L = 1 kΩ 0.02 0.03 Degrees
Crosstalk f = 5 MHz, G = +2 −60 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.8 11 1.8 13 mV
T
MIN − TMAX 27 32 mV
Offset Drift 10 15 μV/°C
Input Bias Current 1.4 2.6 2 4.5 μA
T
MIN − TMAX 3.5 4.5 μA
Input Offset Current 0.1 0.75 0.2 1.2 μA
Open-Loop Gain RL = 2 kΩ 88 96 84 96 dB
T
MIN − TMAX 96 96 dB
R
L = 150 Ω 78 82 76 82 dB
T
MIN − TMAX 80 80 dB
INPUT CHARACTERISTICS
Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range −5.2 to
+4
−5.2 to
+4
V
Common-Mode Rejection Ratio VCM = −5 V to +3.5 V 72 88 70 86 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ −4.98 to
+4.98
−4.97 to
+4.97
V
R
L = 2 kΩ −4.85 to
+4.85
−4.97 to
+4.97
−4.8 to
+4.8
−4.9 to
+4.9
V
R
L = 150 Ω −4.45 to
+4.3
−4.6 to
+4.6
−4.0 to
+3.8
−4.5 to
+4.5
V
Output Current VOUT = −4.5 V to +4.5 V 45 30 mA
T
MIN − TMAX 45 30 mA
Short-Circuit Current Sourcing 100 60 mA
Sinking 160 100 mA
Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF
G = +2 (AD8054) 40 pF
AD8051/AD8052/AD8054
Rev. J | Page 8 of 24
AD8051A/AD8052A AD8054A
Parameter Conditions Min Typ Max Min Typ Max Unit
POWER SUPPLY
Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.8 5.5 2.875 3.4 mA
Power Supply Rejection Ratio ΔVS = ±1 68 80 68 80 dB
OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C
RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C
AD8051/AD8052/AD8054
Rev. J | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Ratings
Supply Voltage 12.6 V
Internal Power Dissipation1
SOIC Packages Observe power
derating curves
SOT-23 Package Observe power
derating curves
MSOP Package Observe power
derating curves
TSSOP Package Observe power
derating curves
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±2.5 V
Output Short-Circuit Duration Observe power
derating curves
Storage Temperature Range (R) −65°C to +150°C
Operating Temperature Range (A Grade) −40°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
1 See Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Specification is for device in free air.
Table 5. Thermal Resistance
Package Type θJA Unit
8-Lead SOIC 125 °C/W
5-Lead SOT-23 180 °C/W
8-Lead MSOP 150 °C/W
14-Lead SOIC 90 °C/W
14-Lead TSSOP 120 °C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8051/AD8052/AD8054 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
While the AD8051/AD8052/AD8054 are internally short-
circuit protected, this cannot be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves.
AMBIENT TEMPERATURE (°C)
–55
0
2.0
1.5
1.0
0.5
5
MAXIMUM POWER DISSIPATION (W)
2.5
MSOP-8
SOIC-8
SOT-23-5
SOIC-14
TSSOP-14
–35 –15 15 35 55 75 95 115
01062-006
Figure 6. Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
ESD CAUTION
AD8051/AD8052/AD8054
Rev. J | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
3
2
–7
–1
–4
–5
–6
1
0
–3
–2
500
NORMALIZED GAIN (dB)
0.1 1 10 100
G = +10
R
F
= 2kΩ
G = +2
R
F
= 2kΩ
G = +5
R
F
= 2kΩ
G = +1
R
F
= 0
V
S
= 5V
GAIN AS SHOWN
R
F
AS SHOWN
R
L
= 2kΩ
V
OUT
= 0.2V p-p
01062-007
Figure 7. AD8051/AD8052 Normalized Gain vs. Frequency; VS = 5 V
FREQUENCY (MHz)
3
2
–7
100
–1
–4
–5
–6
1
0
–3
–2
GAIN (dB)
VS = +3V VS = +5V
VS = ±5V
VSAS SHOWN
G=+1
RL=2kΩ
V
OUT
=0.2Vp-p
0.1 1 10 500
01062-008
Figure 8. AD8051/AD8052 Gain vs. Frequency vs. Supply
FREQUENCY (MHz)
3
2
–7
0.1 500100
–1
–4
–5
–6
1
0
–3
–2
–40°C
+25°C
+85°C
GAIN (dB)
110
V
S
= 5V
G=+1
R
L
=2kΩ
V
OUT
=0.2Vp-p
TEMPERATURE AS SHOWN
01062-009
Figure 9. AD8051/AD8052 Gain vs. Frequency vs. Temperature
1M
FREQUENCY (Hz)
3
0
–3
–6
–7
100k
–5
–4
–2
–1
5
4
2
1
500M
NORMALIZED GAIN (dB)
10M 100M
G = +1
R
F
= 0
G = +2
R
F
= 2kΩ
G = +10
R
F
= 2kΩ
G = +5
R
F
= 2kΩ
V
S
= 5V
GAIN AS SHOWN
R
F
AS SHOWN
R
L
= 5kΩ
V
OUT
= 0.2V p-p
01062-010
Figure 10. AD8054 Normalized Gain vs. Frequency; VS = 5 V
+3V
+5V
±5V
+3V
+5V
6
2
–3
100k
5
4
3
1
0
–1
–2
–4
FREQUENCY (Hz)
500M
GAIN (dB)
G=+1
R
L
=2kΩ
C
L
= 5pF
V
OUT
=0.2Vp-p
±5V
1M 10M 100M
01062-011
Figure 11. AD8054 Gain vs. Frequency vs. Supply
4
0
–4
3
2
1
–1
–2
–3
–5
100
FREQUENCY (MHz)
–40°C
+25°C
+85°C
GAIN (dB)
500
101
V
S
= 5V
R
L
= 2kΩTO 2.5V
C
L
= 5pF
G = +1
V
OUT
= 0.2V p-p
01062-012
Figure 12. AD8054 Gain vs. Frequency vs. Temperature
AD8051/AD8052/AD8054
Rev. J | Page 11 of 24
FREQUENCY (MHz)
6.3
6.2
5.3
0.1 100
5.9
5.6
5.5
5.4
6.1
6.0
5.7
5.8
GAIN FLATNESS (dB)
110
01062-013
V
S
= 5V
G = +2
R
L
= 150Ω
R
F
= 806Ω
V
OUT
= 0.2V p-p
Figure 13. AD8051/AD8052 0.1 dB Gain Flatness vs. Frequency; G = +2
FREQUENCY (MHz)
9
8
–1
5
2
1
0
7
6
3
4
GAIN (dB)
V
S
= +5V
V
OUT
= 2V p-p
V
S
AS SHOWN
G = +2
R
F
= 2kΩ
R
L
= 2kΩ
V
OUT
AS SHOWN
V
S
= ±5V
V
OUT
= 4V p-p
0.1 1 10 100 500
01062-014
Figure 14. AD8051/AD8052 Large Signal Frequency Response; G = +2
FREQUENCY (MHz)
80
70
–20
40
10
0
–10
60
50
20
30 0
–45
–90
–135
–180
GAIN
PHASE
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
50° PHASE
MARGIN
0.01 0.1 1 10 100 500
V
S
= 5V
R
L
= 2kΩ
01062-015
Figure 15. AD8051/AD8052 Open-Loop Gain and Phase vs. Frequency
6.3
5.9
5.4
6.2
6.1
6.0
5.8
5.7
5.6
5.5
110010
FREQUENCY (MHz)
GAIN FLATNESS (dB)
5.3
01062-016
V
S
= 5V
R
F
= 200Ω
R
L
= 150Ω
G = +2
V
OUT
= 0.2V p-p
Figure 16. AD8054 0.1 dB Gain Flatness vs. Frequency; G = +2
FREQUENCY (MHz)
9
8
–1
5
2
1
0
7
6
3
4
GAIN (dB)
0.1 1 10 100 500
01062-017
V
S
= ±5V
V
OUT
= 4V p-p
V
S
AS SHOWN
G = +2
R
F
= 2kΩ
R
L
= 2kΩ
V
OUT
AS SHOWN
V
S
= +5V
V
OUT
= 2V p-p
Figure 17. AD8054 Large Signal Frequency Response; G = +2
GAIN
PHASE
180
135
90
45
0
FREQUENCY (Hz)
80
70
–20
40
10
0
–10
60
50
20
30
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
45° PHASE
MARGIN
30k 100k 1M 10M 100M 500M
V
S
= 5V
R
L
= 2kΩ
C
L
= 5pF
01062-018
Figure 18. AD8054 Open-Loop Gain and Phase Margin vs. Frequency
AD8051/AD8052/AD8054
Rev. J | Page 12 of 24
FUNDAMENTAL FREQUENCY (MHz)
–
20
–30
–110
–70
–80
–90
–100
–50
–60
–40
TOTAL HARMONIC DISTORTION (dBc)
12345678910
V
OUT
= 2V p-p V
S
= 3V, G = –1
R
F
= 2kΩ, R
L
= 100Ω
V
S
= 5V, G = +2
R
F
= 2kΩ, R
L
= 100Ω
V
S
= 5V, G = +1
R
L
= 100Ω
V
S
= 5V, G = +1
R
L
= 2kΩ
V
S
= 5V, G = +2
R
F
= 2kΩ, R
L
= 2kΩ
01062-019
Figure 19. Total Harmonic Distortion
OUTPUT VOLTAGE (V p-p)
05.04.5
–
30
–40
–120
–80
–90
–100
–110
–60
–70
–50
–130
–140
WORST HARMONIC (dBc)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
V
S
= 5V
R
L
= 2kΩ
G = +2
10MHz
5MHz
1MHz
01062-020
Figure 20. Worst Harmonic vs. Output Voltage
0.05
0.00
–0.05
–0.10
–0.15
–0.20
–0.25
0.10
MODULATING RAMP LEVEL (IRE)
0.10
–0.06
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
NTSC SUBSCRIBER (3.58MHz)
DIFFERENTIAL
GAIN ERROR (%)
DIFFERENTIAL
PHASE ERROR (Degrees)
0 102030405060708090100
0 102030405060708090100
R
L
= 150Ω
R
L
= 1kΩ
R
L
= 150Ω
R
L
= 1kΩ
V
S
= 5V, G = +2
R
F
= 2kΩ, R
L
AS SHOWN
V
S
= 5V, G = +2
R
F
= 2kΩ, R
L
AS SHOWN
01062-021
Figure 21. AD8051/AD8052 Differential Gain and Phase Errors
1000
100
1
10 10M100
VOLTAGE NOISE (nV/√Hz)
1k 10k 100k 1M
10
FREQUENCY (Hz)
V
S
= 5V
0
1062-022
Figure 22. Input Voltage Noise vs. Frequency
100
10
0.1
1
10 10M100
CURRENT NOISE (pA/
√
Hz)
1k 10k 100k 1M
FREQUENCY (Hz)
V
S
= 5V
01062-023
Figure 23. Input Current Noise vs. Frequency
0.10
–0.10
0.05
0.00
–0.05
0.2
0.1
0.0
–0.1
–0.2
–0.3
0.3
MODULATING RAMP LEVEL (IRE)
NTSC SUBSCRIBER (3.58MHz)
DIFFERENTIAL
GAIN ERROR (%)
DIFFERENTIAL
PHASE ERROR (Degrees)
RL = 150Ω
RL = 1kΩ
RL = 150Ω
RL = 1kΩ
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
VS = 5V, G = +2
RF = 2kΩ, RL AS SHOWN
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
01062-024
Figure 24. AD8054 Differential Gain and Phase Errors
AD8051/AD8052/AD8054
Rev. J | Page 13 of 24
FREQUENCY (MHz)
–
10
–20
0.1 500100
–50
–80
–90
–100
–30
–40
–70
–60
CROSSTALK (dB)
110
01062-025
V
S
= 5V
R
F
= 2kΩ
R
L
= 2kΩ
V
OUT
= 2V p-p
Figure 25. AD8052 Crosstalk (Output-to-Output) vs. Frequency
FREQUENCY (MHz)
0
–10
–100
–40
–70
–80
–90
–20
–30
–60
–50
CMRR (dB)
V
S
= 5V
0.03 0.1 1 10 100 500
01062-026
Figure 26. CMRR vs. Frequency
FREQUENCY (MHz)
100.000
3.100
0.100
0.031
0.010
31.000
10.000
0.310
1.000
OUTPUT RESISTANCE (Ω)
V
S
=5V
G = +1
0.1 1 10 100 500
01062-027
Figure 27. Closed-Loop Output Resistance vs. Frequency
–
10
–50
–100
–20
–30
–40
–60
–70
–80
–90
–110
FREQUENCY (MHz)
CROSSTALK (dB)
R
L
= 100Ω
R
L
= 1kΩ
V
S
= ±5V
R
F
= 1kΩ
R
L
=AS SHOWN
V
OUT
= 2V p-p
0.1 1 10 100 500
01062-028
Figure 28. AD8054 Crosstalk (Output-to-Output) vs. Frequency
FREQUENCY (MHz)
20
–10
–30
–50
–70
10
0
–20
–40
–60
–80
–PSRR
+PSRR
PSRR (dB)
V
S
= 5V
0.01 0.1 1 10 100 500
01062-029
Figure 29. PSRR vs. Frequency
INPUT STEP (V p-p)
60
0
40
30
20
10
50
70
SETTLING TIME TO 0.1% (ns)
AD8051/AD8052
AD8054
0.5 1.0 1.5 2.0
VS = 5V
G = –1
RL = 2kΩ
01062-030
Figure 30. Settling Time vs. Input Step
AD8051/AD8052/AD8054
Rev. J | Page 14 of 24
LOAD CURRENT (mA)
1.0
0.3
0
0.9
0.4
0.2
0.1
0.7
0.5
0.8
0.6
OUTPUT SATURATION VOLTAGE (V)
VS = 5V V
OH
= +85°C
V
OH
= +25°C
V
OH
= –40°C V
OL
= +85°C
V
OL
= +25°C
V
OL
= –40°C
80 85757065605550454035302520151050
01062-031
Figure 31. AD8051/AD8052 Output Saturation Voltage vs. Load Current
100
90
60
80
70
OPEN-LOOP GAIN (dB)
OUTPUT VOLTAGE (V)
R
L
= 2kΩ
R
L
= 150Ω
V
S
= 5V
05.04.54.03.53.02.52.01.51.00.5
01062-032
Figure 32. Open-Loop Gain vs. Output Voltage
LOAD CURRENT (mA)
1.000
0.500
0
0.875
0.750
0.250
0.125
0.625
0.375
OUTPUT SATURATION VOLTAGE (V)
302724211815129630
+5V – V
OH
(+125°C)
+5V – V
OH
(+25°C)
+5V – V
OH
(–40°C)
V
OL
(+125°C)
V
OL
(+25°C)
V
OL
(–40°C)
01062-033
V
S
= 5V
Figure 33. AD8054 Output Saturation Voltage vs. Load Current
AD8051/AD8052/AD8054
Rev. J | Page 15 of 24
1.5
VOLTS
VIN = 0.1V p-p
G = +1
RL = 2kΩ
VS = 3V
20mV 20ns
0
1062-034
Figure 34. 100 mV Step Response, G = +1
2.5
2.6
2.4
VOLTS
V
S
= 5V
G = +1
R
L
= 2kΩ
50mV 20ns
01062-035
Figure 35. AD8051/AD8052 200 mV Step Response; VS = 5 V, G = +1
VOLTS
3.5
2.5
1.5
0.5
4.5 V
IN
= 1V p-p
G = +2
R
L
= 2kΩ
V
S
= 5V
500mV 20ns
0
1062-036
Figure 36. Large Signal Step Response; VS = 5 V, G = +2
5.0
2.5
VOLTS
V
S
= 5V
G = –1
R
F
= 2kΩ
R
L
= 2kΩ
1V 2µs
0
1062-037
Figure 37. Output Swing; G = −1, RL = 2 kΩ
2.55
2.50
2.45
VOLTS
V
S
= 5V
G = +1
R
L
= 2kΩ
50mV 40ns
01062-038
Figure 38. AD8054 100 mV Step Response; VS = 5 V, G = +1
4
3
2
1
–1
–2
–3
–4
VOLTS
V
S
= ±5V
G = +1
R
L
= 2kΩ
20ns
1V
01062-039
Figure 39. Large Signal Step Response; VS = ±5 V, G = +1
AD8051/AD8052/AD8054
Rev. J | Page 16 of 24
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The AD8051/AD8052/AD8054 are fabricated on the Analog
Devices, Inc. proprietary eXtra-Fast Complementary Bipolar
(XFCB) process, which enables the construction of PNP and
NPN transistors with similar fTs in the 2 GHz to 4 GHz region.
The process is dielectrically isolated to eliminate the parasitic
and latch-up problems caused by junction isolation. These
features allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a differential
output input stage to maximize bandwidth and headroom (see
Figure 40). The smaller signal swings required on the first stage
outputs (nodes SIP, SIN) reduce the effect of nonlinear currents
due to junction capacitances and improve the distortion per-
formance. This design achieves harmonic distortion of −80 dBc
@ 1 MHz into 100  with VOUT = 2 V p-p (gain = +1) on a
single 5 V supply.
The inputs of the device can handle voltages from −0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values do not cause phase reversal; however, the input
ESD devices begin to conduct if the input voltages exceed the
rails by greater than 0.5 V. During this overdrive condition, the
output stays at the rail.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to
drive 45 mA of output current and allows the AD8054 to drive
30 mA of output current with the outputs within 0.5 V of the
supply rails.
I10 R39
V
EE
I2 I3
Q25
Q51
R23 R27
I9
Q36
I5
V
EE
C3
C9
I8
V
CC
I11
I7
R3
R21
R5
Q3
SIP SIN
C7
Q4
R15 R2
R26 Q50
Q22
Q21 Q27
Q7
Q8
Q23
Q31
Q39
Q13 Q1
Q24 Q47
Q11
Q2
Q5
Q40
V
OUT
V
CC
V
IN
P
V
IN
N
V
EE
01062-045
Figure 40. AD8051/AD8052 Simplified Schematic
AD8051/AD8052/AD8054
Rev. J | Page 17 of 24
APPLICATION INFORMATION
OVERDRIVE RECOVERY
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 41, the AD8051/AD8052/
AD8054 recover within 60 ns from negative overdrive and
within 45 ns from positive overdrive.
VOLTS
VS = ±5V
G = +5
RF = 2kΩ
RL = 2kΩ
V/DIV AS SHOWN 100ns
INPUT 1V/DIV
OUTPUT 2V/DIV
01062-040
Figure 41. Overdrive Recovery
DRIVING CAPACITIVE LOADS
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 k in parallel with 50 pF. Figure 42
and Figure 43 show their frequency and time domain responses,
respectively, to a small-signal excitation. The capacitive load
drive of the AD8051/AD8052/AD8054 can be increased by
adding a low value resistor in series with the load. Figure 44
and Figure 45 show the effect of a series resistor on the capaci-
tive drive for varying voltage gains. As the closed-loop gain is
increased, the larger phase margin allows for larger capacitive
loads with less peaking. Adding a series resistor with lower
closed-loop gains accomplishes the same effect. For large
capacitive loads, the frequency response of the amplifier is
dominated by the roll-off of the series resistor and the load
capacitance.
FREQUENCY (MHz)
8
6
4
2
0
–2
–4
–6
–8
–10
GAIN (dB)
–12
0.1 500100110
01062-041
V
S
= 5V
G = +1
R
L
= 2kΩ
C
L
= 50pF
V
OUT
= 200mV p-p
Figure 42. AD8051/AD8052 Closed-Loop Frequency Response; CL = 50 pF
2.60
2.55
2.50
2.45
2.40
VOLTS
V
S
= 5V
G = +1
R
L
= 2kΩ
C
L
= 50pF
50mV 100ns
0
1062-042
Figure 43. AD8051/AD8052 200 mV Step Response; CL = 50 pF
10000
1000
1
CAPACITIVE LOAD (pF)
100
10
A
CL
(V/V)
V
S
= 5V
≤ 30%
OVERSHOOT R
S
= 3Ω
R
S
= 0Ω
123456
V
OUT
C
L
R
S
R
F
R
G
50Ω
V
IN
100mV
STEP
01062-043
Figure 44. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain
1000
100
10
CAPACITIVE LOAD (pF)
A
CL
(V/V)
123456
V
OUT
C
L
R
S
R
F
R
G
50Ω
V
IN
100mV
STEP
V
S
= 5V
≤ 30%
OVERSHOOT
R
S
= 0Ω
R
S
= 10Ω
01062-044
Figure 45. AD8054 Capacitive Load Drive vs. Closed-Loop Gain
AD8051/AD8052/AD8054
Rev. J | Page 18 of 24
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and component
selection. Proper RF design techniques and low parasitic
component selection are necessary.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from the
area near the input pins to reduce parasitic capacitance.
Chip capacitors should be used for supply bypassing. One end
should be connected to the ground plane and the other within
3 mm of each power pin. An additional large (4.7 µF to 10 µF)
tantalum electrolytic capacitor should be connected in parallel,
but not necessarily so close, to supply current for fast, large
signal changes at the output.
The feedback resistor should be located close to the inverting
input pin to keep the parasitic capacitance at this node to a
minimum. Parasitic capacitance of less than 1 pF at the inverting
input can significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50  or 75  and be properly
terminated at each end.
ACTIVE FILTERS
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly affect active filter
performance.
Figure 46 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before analog-to-digital
conversion.
Note that the unused amplifier’s inputs should be tied to ground.
12
13
14
2
16
5
79
10
8
AD8054 AD8054
3
AD8054
R6
1kΩ
R4
2kΩ
R3
2kΩR5
2kΩ
R2
2kΩ
R1
3kΩ
C1
50pF
C2
50pF
V
IN
BAND-PASS
FILTER OUTPUT
01062-046
Figure 46. 2 MHz Biquad Band-Pass Filter Using AD8054
The frequency response of the circuit is shown in Figure 47.
FREQUENCY (Hz)
0
–10
–20
–30
–40
GAIN (dB)
10k 100k 1M 10M 100M
01062-047
Figure 47. Frequency Response of 2 MHz Band-Pass Biquad Filter
AD8051/AD8052/AD8054
Rev. J | Page 19 of 24
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
Figure 50 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50  and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22  series resistor limits the maximum current
that flows and helps to lower the distortion of the ADC.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 k resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
Figure 48 shows the FFT response of the ADC for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
PART# 0
FCLK
FUND
VIN
THD
SNR
SINAD
ENOB
SFDR
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
FFTSIZE 8192
20.0MHz
998.5kHz
–0.51dB
–68.13
54.97
54.76
8.80
71.66
–74.53
–76.06
–76.35
–79.05
–80.36
–75.08
–88.12
–77.87
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
AMPLITUDE (dB)
FREQUENCY (MHz)
0 12 34567 8910
FUND
2ND
5TH 6TH
7TH 8TH 9TH
4TH3RD
01062-049
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
PART# 0
FCLK
FUND
VIN
THD
SNR
SINAD
ENOB
SFDR
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH
FFTSIZE 8192
20.0MHz
9.5MHz
–0.44dB
–57.08
54.65
52.69
8.46
60.18
–60.18
–60.23
–82.01
–78.83
–81.28
–77.28
–84.54
–92.78
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
AMPLITUDE (dB)
FREQUENCY (MHz)
0 12 34567 8910
FUND
2ND
5TH
6TH 7TH
8TH
4TH
3RD
01062-050
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
AD8051
+5V
VREF
AVDD
SELECT
INA-I
10pF
CLOCK
SLEEP
D9
D1
D2
D3
D4
D5
D6
D7
D0
DVDD
AVSS
REFSENSE
AD9201
DVSS
CHIP–SELECT
INB-I
REFT-I
REFB-I
REFB -Q
REFT -Q
INB-Q
INA-Q
D8
DATA OUT
10pF
–5V
10pF
10pF
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
10.1µF 10µF
+5V
+VDD
10µF0.1µF 0.1µF
0.1µF
10µF 0.1µF
10µF 0.1µF
10µF0.1µF 0.1µF
0.1µF
+5V
22Ω
22Ω
22Ω
22Ω
22Ω
1kΩ
1kΩ
0.33µF
0.01µF
1kΩ
10µF0.1µF
10µF0.1µF
50Ω
3
2
7
4
6
01062-048
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
AD8051/AD8052/AD8054
Rev. J | Page 20 of 24
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as analog-to-
digital conversion, it is not desirable to have the sync pulses on
the video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 51
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.
AD8051
0.1µF 10µF
+
100Ω
TO A/D
3V OR 5V
V
BLANK
GROUND
0.4V
IDEO WITH SYNC
GROUND
V
IDEO WITHOUT SYNC
R2
1kΩ
R1
1kΩ
V
IN
3
2
7
4
6
0.8V
(OR 2 × V
BLANK
)
0
1062-051
Figure 51. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync
pulses stripped at the proper level.
The blanking level of the input video pulse is the desired place to
remove the sync information. This level is multiplied by 2 by the
amplifier. This level must be at ground at the output for the sync
stripping action to take place. Since the gain of the amplifier from
the input of R1 to the output is −1, a voltage equal to 2 × VBLANK
must be applied to make the blanking level come out at ground.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
can arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst
case, the dynamic signal swing will approach twice the peak-to-
peak value. The two conditions that define the maximum
dynamic swing requirements are a signal that is mostly low but
goes high with a duty cycle that is a small fraction of a percent,
and the other extreme defined by the opposite condition.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video specifications.
The combination of horizontal and vertical blanking intervals
limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
As a result of the duty cycles between the two extremes
previously presented, a 1 V p-p composite video signal that is
multiplied by a gain of 2 requires about 3.2 V p-p of dynamic
voltage swing at the output for an op amp to pass a composite
video signal of arbitrarily varying duty cycle without distortion.
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts, such
as sync tip compression, unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single 5 V
supply to handle an ac-coupled composite video signal.
The input to the circuit in Figure 52 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of five with minimum visible degradation in the picture.
AD8051
5V
+10µF
4.99kΩ
220µF
+
1000µF
0.1µF
10kΩ
+
47µF
4.99kΩ
0.1µF 10µF
+
COMPOSITE
VIDEO
IN
3
2
7
4
6
R
G
1kΩ
R
F
1kΩ
R
T
75ΩR
L
75Ω
V
OUT
R
BT
75Ω
0
1062-052
Figure 52. Single-Supply Composite Video Line Driver
AD8051/AD8052/AD8054
Rev. J | Page 21 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
PIN 1
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
5
123
4
0.22
0.08
10°
5°
0°
0.50
0.30
0.15 MAX SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-A A
Figure 54. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
AD8051/AD8052/AD8054
Rev. J | Page 22 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0
.95
0
.85
0
.75
Figure 55. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8051/AD8052/AD8054
Rev. J | Page 23 of 24
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8051AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8051AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8051AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8051ARZ1 −40°C to +85°C 8-Lead SOIC_N R-8
AD8051ARZ-REEL1 −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8051ARZ-REEL71 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8051ART-R2 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H2A
AD8051ART-REEL −40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H2A
AD8051ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H2A
AD8051ARTZ-R21 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H06
AD8051ARTZ-REEL1 −40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H06
AD8051ARTZ-REEL71 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H06
AD8052AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8052AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8052AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8052ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8052ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8052ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8052ARM −40°C to +125°C 8-Lead MSOP RM-8 H4A
AD8052ARM-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 H4A
AD8052ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H4A
AD8052ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 H4A#
AD8052ARMZ-REEL71 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H4A#
AD8054AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8054AR-REEL −40°C to +125°C 14-Lead SOIC_N, 13" Tape and Reel R-14
AD8054AR-REEL7 −40°C to +125°C 14-Lead SOIC_N, 7" Tape and Reel R-14
AD8054ARZ1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8054ARZ-REEL1 −40°C to +125°C 14-Lead SOIC_N, 13" Tape and Reel R-14
AD8054ARZ-REEL71 −40°C to +125°C 14-Lead SOIC_N, 7" Tape and Reel R-14
AD8054ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8054ARU-REEL −40°C to +125°C 14-Lead TSSOP, 13" Tape and Reel RU-14
AD8054ARU-REEL7 −40°C to +125°C 14-Lead TSSOP, 7" Tape and Reel RU-14
AD8054ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14
AD8054ARUZ-REEL1 −40°C to +125°C 14-Lead TSSOP, 13" Tape and Reel RU-14
AD8054ARUZ-REEL71 −40°C to +125°C 14-Lead TSSOP, 7" Tape and Reel RU-14
1 Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked.
AD8051/AD8052/AD8054
Rev. J | Page 24 of 24
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01062-0-7/09(J)
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