Memory Array
1024 X 2048
Row Select
I/O Circuit
Pre-Charge Circuit
Column Select
Data
Cont
Data
Cont
Vcc
Vss
A10 A11 A12 A13 A14
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
A15 A16
Preliminary
SD116U128
SD116U128L
Ultra Low Power
128K x 16 CMOS SRAM
Features
•Low-power consumption
- Active: 35mA ICC at 70ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
•70/85/100/120 ns access time
•Equal access and cycle time
•Single +1.8V to2.2V Power Supply
•Tri-state output
•Automatic power-down when deselected
•Multiple center power and ground pins for
improved noise immunity
•Individual byte controls for both Read and
Write cycles
•Available in 44 pin TSOPII / 48-fpBGA / 48-µBGA
Functional Description
The SD116U128 is a Low Power CMOS Static RAM
organized as 131,072 words by 16 bits. Easy memory
expansion is provided by an active LOW (CE) and (OE)
pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
TSOPII / 48-fpBGA / 48-µBGA (See nest page)
Rev.3/9/99
20410 TOWN CENTER LANE, STE 270 s CUPERTINO, CA 95014 s TEL (408) 255-1262 s FAX (408) 255-1359
Logic Block Diagram
1
2
3
12
10
11
8
39
13
9
7
6
4
5
26
25
24
2322
21
14
15
16
17
18
19
20
40
41
42
43
44
38
37
36
35
34
33
32
31
30
29
28
27 A9
A8
A7
A6
A5A4
A3
A2
A1
WE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
CE
Vss
Vcc
A12
A16
A15
A14
A13 A11
A10
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
NC
Vss
Vcc
BHE
BLE
OE
SD116U128/SD116U128L
2
SIDE VIEW
BOTTOM VIEW
48 Ball - 6 x 8
µµ
BGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SYMBOL UNIT:MM
A
D
D1
e
E1
E
C
A1
6
5
4
3
2
1
A B CDEFGH
aaa
b
SOLDER BALL
A1.10+0.10
A1 0.22+0.05
0.35
0.36(TYP)
8.00+0.10
5.25
6.00+0.10
b
c
D
D1
E
E1
e
aaa
3.75
0.75TYP
0.10
1 2 3 4 5 6
Soft Device, Inc. SD116U128 CSP
1 2 3 4 5 6
A
B
C
D
E
F
G
H
BLE
I/O9
I/O10
VSS
VCC
I/O15
I/O16
NC
OE
BHE
I/O11
I/O12
I/O13
I/O14
NC
A8
A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O2
I/O4
I/O5
I/O6
WE
A11
NC
I/O1
I/O3
VCC
VSS
I/O7
I/O8
NC
Top View
Note: NC means no Ball.
Top View
SD116U128 / SD116U128L
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 +4.0 V
Power Dissipation PT −1.0 W
Storage Temperature (Plastic) Tstg -55 +150 0C
Temperature Under Bias Tbias -40 +85 0C
Truth Table
* Key: X = Don’t Care, L = Low, H = High
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16 Power Mode
HXXXXHigh-Z High-Z Standby Standby
L L HLHData Out High-Z Active Low Byte Read
L L H H LHigh-Z Data Out Active High Byte Read
L L HL L Data Out Data Out Active Word Read
LXLLLData In Data In Active Word Write
LXL L HData In High-Z Active Low Byte Write
LXLHLHigh-Z Data In Active High Byte Write
LH H X X High-Z High-Z Active Output Disable
LX X H H High-Z High-Z Active Output Disable
3
Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**)
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature
Parameter Symbol Min Typ Max Unit
VCC 1.8 2.0 2.2 V
Gnd 0.0 0.0 0.0 V
VIH 1.6 -VCC + 0.2 V
VIL -0.5* -0.4 V
Supply Voltage
Input Voltage
AC Test Conditions
Input Pulse Level 0.4V to 1.6V
Input Rise and Fall Time 5ns
Input and Output Timing
Reference Level 1.0V
Output Load Condition
70ns/85ns C
L
= 30pf + 1TTL Load
Load for 100ns/120ns C
L
= 100pf + 1TTL Load
C
L
*
Figure A. * Including Scope and Jig Capacitance
TTL
SD116U128 / SD116U128L
DC Operating Characteristics (Vcc =1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Input Leakage Current IILII Vcc = Max,
Vin = Gnd to Vcc
-1-1-1-1µA
Output Leakage
Current IILOI CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc -1-1-1-1µA
Operating Power
Supply Current ICC CE = VIL , VIN = VIH or VIL ,
IOUT = 0 -5-5-5-5mA
Average Operating
Current ICC1 IOUT = 0mA,
Min Cycle, 100% Duty -35 -35 -30 -30 mA
ICC2 CE < 0.2V
IOUT = 0mA,
Cycle Time=1µs, Duty=100%
-3-3-3-3mA
Standby Power Supply
Current (TTL Level) ISB CE = VIH -0.5 -0.5 -0.5 -0.5 mA
Standby Power Supply
Current (CMOS Level) ISB1 CE > Vcc - 0.2V
VIN < 0.2V or
VIN > Vcc- 0.2V L
-
-
10
2
-
-
10
2
-
-
10
2
-
-
10
2
µA
µA
Output Low Voltage VOL IOL = 2 mA -0.4 -0.4 -0.4 -0.4 V
Output High Voltage VOH IOH = -1 mA 1.6 -1.6 -1.6 -1.6 -V
-70 -100 -120
Unit
Parameter Sym Test Conditions
Min Max Min Max Min Max Min Max
-85
4
Capacitance (f = 1MHz, TA = 250C)
Parameter* Symbol Test Condition Max Unit
Input Capacitance Cin Vin = 0V 7pF
I/O Capacitance CI/O Vin = Vout = 0V 8pF
* This parameter is guaranteed by device characterization and is not production tested.
SD116U128 / SD116U128L
Parameter Sym Unit Note
Read Cycle Time tRC 70 -85 -100 -120 -ns
Address Access Time tAA -70 -85 -100 -120 ns
Chip Enable Access Time tACE -70 -85 -100 -120 ns
Output Enable Access Time tOE -40 -40 -50 -60 ns
Output Hold from Address Change tOH 10 -10 -10 -10 -ns
Chip Enable to Output in Low-Z tLZ 10 -10 -10 -10 -ns 4,5
Chip Disable to Output in High-Z tHZ -30 -35 -40 -45 ns 3,4,5
Output Enable to Output in Low-Z tOLZ 5-5-5-5-ns
Output Disable to Output in High-Z tOHZ -25 -30 -35 -40 ns
BLE, BHE Enable to Output in Low-Z tBLZ 5-5-5-5-ns 4,5
BLE, BHE Disable to Output in High-Z tBHZ -25 -30 -35 -40 ns 3,4,5
BLE, BHE Access Time tBA -40 -40 -50 -60 ns
Read Cycle (9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Write Cycle (11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter Symbol Unit Note
Write Cycle Time tWC 70 -85 -100 -120 -ns
Chip Enable to Write End tCW 60 -70 -80 -90 -ns
Address Setup to Write End tAW 60 -70 -80 -90 -ns
Address Setup Time tAS 0-0-0-0-ns
Write Pulse Width tWP 50 -60 -70 -80 -ns
Write Recovery Time tWR 0-0-0-0-ns
Data Valid to Write End tDW 30 -35 -40 -45 -ns
Data Hold Time tDH 0-0-0-0-ns
Write Enable to Output in High-Z tWHZ -30 -35 -40 -45 ns
Output Active from Write End tOW 5-5-5-5-ns
BLE, BHE Setup to Write End tBW 60 -70 -80 -90 -ns
Min Max Min Max Min Max Min Max
-70 -85 -100 -120
5
Min Max Min Max Min Max Min Max
-70 -85 -100 -120
Timing Waveform of Read Cycle 1
(Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
Data Out
Timing Waveform of Read Cycle 2
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,5)
CE
Previous Data Valid
Address
t
OH
t
AA
t
OE
t
BA
t
BLZ(4,5)
t
BHZ(3,4,5)
t
HZ(3,4,5)
(BLE/BHE)
OE
Data Out Data Valid
High-Z
SD116U128 / SD116U128L
6
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = VIL.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
SD116U128 / SD116U128L
Timing Waveform of Write Cycle 1
(Address Controlled)
Timing Waveform of Write Cycle 2
(CE Controlled)
Timing Waveform of Write Cycle 3
(BLE/BHE Controlled)
Address
High-Z
t
DW
t
DH
t
WP (2)
t
WC
t
CW (3)
t
AW
t
WR (5)
t
AS (4)
Address
Address
Data In
Data In
Data In
Data Out
Data Out
Data Out
CE
CE
CE
BLE/BHE
BLE/BHE
BLE/BHE
WE
WE
WE
t
BW
t
LZ
t
BLZ
t
WHZ (6)
High-Z (8)
High-Z
t
WHZ (6)
High-Z (8)High-Z
High-Z
t
DW
t
DH
t
WP (2)
t
BW
t
AS (4)
t
WR (5)
t
CW (3)
t
AW
t
WC
High-Z
High-Z (8)
t
OW
t
OHZ (6)
t
DW
t
DH
t
WP (2)
t
BW
t
AS (4)
t
CW (3)
t
AW
t
WC
t
WR (5)
7
SD116U128 / SD116U128L
8
Notes (Write Cycle)
1. All write timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going
low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning
of write to the end of write.
3. tCW is measured from the later of CE going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change.
6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should
not be applied.
11. For test conditions, see AC Test Condition, Figure A.
SD116U128 / SD116U128L
9
Notes (Write Cycle)
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is High for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
Data Retention Mode
V
DR
>
1.0V
Vcc_typ
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Characteristics (L Version Only)(1)
Parameter Symbol Test Condition Min Max Unit
VCC for Data Retention VDR CE > VCC - 0.2V 1.0 -V
Data Retention Current ICCDR -1µA
Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0- ns
Operation Recovery Time(2) tRVIN < 0.2V tRC - ns
SD116U128/SD116U128L
Ordering Information
Device Type* Speed Package
SD116U128H-70 70 ns 44-pin TSOP Type 2
SD116U128H-85 85 ns
SD116U128H-100 100 ns
SD116U128H-120 120 ns
SD116U128LH-70 70 ns
SD116U128LH-85 85 ns
SD116U128LH-100 100 ns
SD116U128LH-120 120 ns
SD116U128FG-70 70 ns 48-fpBGA
SD116U128FG-85 85 ns
SD116U128FG-100 100 ns
SD116U128FG-120 120 ns
SD116U128µG-70 70 ns 48-µBGA
SD116U128µG-85 85 ns
SD116U128µG-100 100 ns
SD116U128µG-120 120 ns
Note: Soft Device reserves the right to make changes to its products and to this data sheet at any time, without notice, to improve design or performance.
Soft Device makes no representation that circuits shown are free from patent infringments. Circuitry and other examples shown are meant only to indicate
the performance and characteristics of our products. Soft Device products are not authorized for use as critical components in life support systems without
written permission of the appropriate officer of Soft Device.
10
* For Induatrial temperature tested devices, an “I” designator will be added to the end of the device number.
