CS5361-KZZ - Cirrus Logic, Inc.

http://www.cirrus.com

CS5361

114 dB, 192 kHz, Multi-Bit Audio A/D Converter

Features

zAdvanced Multi-bit Delta-sigma Architecture

z24-bit Conversion

z114 dB Dynamic Range

z-105 dB THD+N

zSystem Sampling Rates up to 192 kHz

z135 mW Power Consumption

zHigh-pass Filter and DC Offset Calibration

zSupports Logic Levels Between 5 and 2.5 V

zDifferential Analog Architecture

zOverflow Detection

zPin-compatible with the CS5381

General Description

The CS5361 is a complete analog-to-digital converte r for

digital audio systems. It performs sampling, analog-to-

digital conversion, and anti-alias filtering. The CS5361

generates 24-bit values for both left and right inputs in

serial form at sample rates up to 192 kHz per channel.

The CS5361 uses a 5th-order, multi-bit, delta-sigma

modulator followed by digital filtering and decimation.

This removes the need for an external anti-alias filter.

The ADC us es a d iff er en tia l ar chitecture which pr ov ide s

excellent noise rejection.

The CS5361 is ideal for audio systems requiring wide dy-

namic range, negligible distortion, and low noise. These

applications include A/V receivers, DVD-R, CD-R, digital

mixing consoles, and effects processors.

ORDERING INFORMATION

CS5361-KSZ -10° to 70°C 24-pin SOIC Lead Free

CS5361-KZZ -10° to 70°C 24-pin TSSOP Lead Free

CS5361-DZZ -40° to 85°C 24-pi n TSSOP Lead Fr ee

CDB5361 Evaluation Board

Voltage Reference Serial Output Interface

Digital

Filter

High

Pass

Filter

High

Pass

Filter

Decimation

Digital

Filter

Decimation

DAC

S/H

DAC

S/H

AINR+

SCLK SDOUT MCLK

RST

VQ LRCK

AINR-

AINL+

AINL-

FILT+ I

S/LJ

M/S

HPF

MODE0

MODE1

REFGND V

MDIV

LP Filter

∆Σ

OVFL

FEB ‘05

DS467F2

CS5361
2DS467F2
TABLE OF CONTENTS
1.0  CHARACTERISTICS AND SPECIFICATIONS ......................................................................4
Specified Operating Conditions ................................................................................................4
Absolute Maximum Ratings......................................................................................................4
Analog Characteristics (CS5361-KSZ/KZZ)...... ........................................................................5
Analog Characteristics (CS5361-DZZ) ................ .....................................................................6
Digital Filter Characteristics......................................................................................................7
DC Electrical Characterist ics ............ ... ... ... .............................................................................10
Digital Characteristics.............................................................................................................10
Switching Characteristics - Serial Audio Port..........................................................................11
2.0  PIN DESCRIPTIONS  ............................................................................................................14
3.0  TYPICAL CONNECTION DIAGRAM ....................................................................................15
4.0  APPLICATIONS ............. ................. ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... ...................16
4.1 Operational Mode/Sample Rate Range Select ................................................................16
4.2 System Clocking .... ... .... ... ... ... ................................. ... ... ... .... ... ... ... ... ................. ... ... ... ......16
4.2.1 Slave Mode ......... ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... ............16
4.2.2 Master Mode ............. .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ................ ... ... ...17
4.3 Power-up Sequence  ..................... ... ... ... .... ... ... ... .... ... ... ...................................................18
4.4 Analog Connections ............... .... ... ...................................................................................18
4.5  High-pass Filter and DC Offset Calibration .....................................................................19
4.6 Overflow Detection ...........................................................................................................19
4.6.1 OVFL Output Timing ...........................................................................................19
4.7 Grounding and Power Supply Decoupling .......................................................................19
4.8 Synchronization of Multiple Devices ................................................................................19
5.0  PARAMETER DEFINITIONS ................................................................................................20
6.0  PACKAGE DIMENSIONS    ..................................................................................................21
7.0  REVISION HISTORY  ............................................................................................................23

CS5361
DS467F2 3
LIST OF FIGURES
Figure 1. Single Speed Mode Stopband Rejection .......... ... ... .... ... ... ... ... .... ... ... ... .... ... . 8
Figure 2. Single Speed Mode Transition Band ........................................................... 8
Figure 3. Single Speed Mode Transition Band (Detail)  .............................................. 8
Figure 4. Single Speed Mode Passband Ripple .............. ... ... .... ... ... ... ... .... ... ... ... .... ... . 8
Figure 5. Double Speed Mode Stopband Rejection ................................................... 8
Figure 6. Double Speed Mode Transition Band ......................................................... 8
Figure 7. Double Speed Mode Transition Band (Detail) ............................................. 9
Figure 8. Double Speed Mode Passband Ripple ....................................................... 9
Figure 9. Quad Speed Mode Stopband Rejection ...................................................... 9
Figure 10. Quad Speed Mode Transition Band .......................................................... 9
Figure 11. Quad Speed Mode Transition Band (Detail)  ..... ... .... ... ... ... ... .... ... ... ... ........ 9
Figure 12. Quad Speed Mode Passband Ripple ........................................................ 9
Figure 13. Master Mode, Left Justified SAI .............................................................. 12
Figure 14. Slave Mode, Left Justified SAI  ................................................................ 12
Figure 15. Master Mod e, I2S SAI . .... ... ... ... ... .... ... ................................ ... .... ... ... ... .... .. 12
Figure 16. Slave Mode, I2S SAI ................................................................................ 12
Figure 17. OVFL Output Timing  ............................................................................... 12
Figure 18. Left Justified Serial Audio Interface ......................................................... 13
Figure 19. I2S Serial Audio Interface ........................................................................ 13
Figure 20. OVFL Output Timing, I2S Format ................ ......................... ................... 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................. 13
Figure 22. Typical Connection Diagram  ................................................................... 15
Figure 23. CS5361 Master Mode Clocking ............................................................... 17
Figure 24. CS5361 Recommended Analog Input Buffer .......................................... 18
LIST OF TABLES
Table 1. CS5361 Mode Control .............................................................................. 16
Table 2. CS5361 Slave Mode Clock Ratios  ........................................................... 16
Table 3. CS5361 Common Master Clock Frequencies .......................................... 17
Table 4. Revision History  ....................... .................... ................... ... .................... .. 23

CS5361

4DS467F2

1.0 CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical per-

formance characteristics an d specifications are derived from measurements taken at typical supply voltages and

TA = 25°C.

SPECIFIED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to GND.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V, All voltages with respect to GND. (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR

latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Unit

DC Power Supplies: Positive Analog

Positive Digital

Positive Logic

4.75

3.1

2.37

5.0

3.3

5.25

Ambient Operating Temperature Commercial (-KSZ/-KZZ)

Automotive (-DZZ) TAC

TAA

-10

-40 -

-70

85 °C

°C

Parameter Symbol Min Max Units

DC Power Supplies: Analog

Logic

Digital

-0.3

+6.0

Input Current (Note 2) Iin -10 +10 mA

Analog Input Voltage (Note 3) VIN - 0.7 VA + 0.7 V

Digital Input Voltage (Note 3) VIND -0.7 VL + 0.7 V

Ambient Operating Temperature (Power Applied) TA-50 +95 °C

Storage Temperature Tstg -65 +150 °C

CS5361

DS467F2 5

ANALOG CHARACTERISTICS (CS5361-KSZ/KZZ)

Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz.

Notes: 4. Referred to the typical full-scale input voltage.

5. Measured between AIN+ and AIN-

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 108

105 114

111 -

-dB

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N -

-105

-91

-51

-99

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-99

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-99

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0 .1 - dB

Gain Error -2 - 2 %

Gain Drift -100 - 100 ppm/°C

Offset Error HPF enabled

HPF disabled -

-0

100 LSB

LSB

Analog Input Characteristics

Full-scale Input Voltage 1.10*VA 1.13*VA 1.15*VA Vpp

Input Impedance (Differential) (Note 5) 7.5 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS5361

6DS467F2

ANALOG CHARACTERISTICS (CS5361-DZZ)

Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz.

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted 106

103 114

111 -

-dB

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N -

-105

-91

-51

-95

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz band width unwe ig ht ed

106

103

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-95

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz band width unwe ig ht ed

106

103

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-105

-91

-51

-102

-95

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -5 - 5 %

Gain Drift -100 - 100 ppm/°C

Offset Error HPF enabled

HPF disabled -

-0

100 LSB

LSB

Analog Input Characteristics

Full-scale Input Voltage 1.07*VA 1.13*VA 1.18*VA Vpp

Input Impedance (Differential) (Note 5) 7.5 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS5361

DS467F2 7

DIGITAL FILTER CHARACTERISTICS

Notes: 6. The filter frequency response scales precisely with Fs.

7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

Parameter Symbol Min Typ Max Unit

Single Speed Mode (2 kHz to 51 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.47 Fs

Passband Ripple -0.1 - 0.035 dB

St op ba nd (Note 6) 0.58 - - Fs

Stopband Attenuation -95 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs- s

Interchannel Phase Deviation - 0.0001 - Deg

Double Speed Mode (50 kHz to 102 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.45 Fs

Passband Ripple -0.1 - 0.035 dB

St op ba nd (Note 6) 0.68 - - Fs

Stopband Attenuation -92 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs- s

Interchannel Phase Deviation - 0.0001 - Deg

Quad Speed Mode (100 kHz to 204 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.24 Fs

Passband Ripple -0.1 - 0.035 dB

St op ba nd (Note 6) 0.78 - - Fs

Stopband Attenuation -92 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs- s

Interchannel Phase Deviation - 0.0001 - Deg

High-pas s Fi lt er Cha r ac te ris ti cs

Frequency Response -3.0 dB

-0.13 dB (Note 7) -1

20 -

-Hz

Phase Deviation @ 20 Hz (Note 7) - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time 105/Fs s

CS5361

8DS467F2

Figure 1. Single Speed Mode Stopband Rejection Figure 2. Single Speed Mode Tran sition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (d B)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 3. Single Speed Mode Transition Band (Detail) Figure 4. Single Speed Mode Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (normalize d to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency ( normalized to Fs )

Amplitude (dB)

Figure 5. Double Speed Mode Stopband Rejection Figure 6. Double Speed Mode Transition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

CS5361

DS467F2 9

Figure 7. Double Speed Mode Transition Band (Detail) Figure 8. Double Speed Mode Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency ( nor m alized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 9. Quad Speed Mode Stopband Rejection Figure 10. Quad Speed Mode Transition B and

Amplitude (dB)

Frequency (normalized to Fs)

Amplitude (dB)

Frequency (normalized to Fs)

Figure 11. Quad Speed Mode Tran sition Band (Detail) Figure 12. Quad Speed Mode Passband Ripple

Frequency (no rmalized to Fs)

Amplitude (dB)

Frequency (normalized to Fs)

CS5361

10 DS467F2

DC ELECTRICAL CHARACTERISTICS

GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode.

Notes: 8. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V

(Normal Operation) VL,VD = 5 V

VL,VD = 3.3 V

17.5

14.5

21.5

27.5

Power Supply Current VA = 5 V

(Power-Down Mode) (Note 8) VL,VD = 5 V IA

-100

100 -

-µA

µA

Power Consumption

(Normal Operation) VA, VD, VL = 5 V

VA = 5 V, VL, VD = 3.3 V

(Power-Down Mode)

198

135

243

161

Power Supply Rejection Ratio (1 kHz) (Note 9) PSRR - 65 - dB

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

2.5

0.01

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

0.01

kΩ

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VL) VIH 70% - - V

Low-Level Input Voltage (% of VL) VIL --30%V

High-Level Output Voltage at Io = 100 µA(% of VL)V

OH 70% - - V

Low-Level Output Voltage at Io = 100 µA(% of VL)V

OL --15%V

OVFL Current Sink Iovfl --4.0mA

Input Leakage Current (all pins except SCLK and LRCK) Iin -10 - 10 µA

Input Leakage Current (SCLK and LRCK) Iin -25 - 25 µA

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature - - 135 °C

Junction to Ambient Thermal Impedance

(Multi-layer PCB) TSSOP

(Multi-layer PCB) SOIC

(Single-layer PCB) TSSOP

(Single-layer PCB) SOIC

θJA-TM

θJA-SM

θJA-TS

θJA-SS

105

°C/W

CS5361

DS467F2 11

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT

Logic “0” = GND = 0 V; Logic “1” = VL, CL = 20 pF

Parameter Symbol Min Typ Max Unit

Output Sample Rate Single S peed Mode

Double Speed Mode

Quad Speed Mode

100

102

204

kHz

OVFL to LRCK edge setup time tsetup 16/fsclk --s

OVFL to LRCK edge hold time thold 1/fsclk --s

OVFL time-out on overrange condition

Fs = 44.1, 88.2, 176.4 kHz

Fs = 48, 96, 192 kHz -

-740

680 -

-ms

MCLK Specifications

MCLK Period tclkw 38 - 1953 ns

MCLK Pulse Duty Cycle 40 50 60 %

Master Mode

SCLK falling to LRCK tmslr -20 - 20 ns

SCLK falling to SDOUT valid tsdo 0 - 32 ns

SCLK Duty Cycle - 50 - %

Slave Mode

Single Speed

Output Sample Rate Fs 2 - 51 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 153 - - ns

SCLK Duty Cycle 45 50 55 %

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Double Speed

Output Sample Rate Fs 50 - 102 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 153 - - ns

SCLK Duty Cycle 45 50 55 %

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Quad Speed

Output Sample Rate Fs 100 - 204 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 77 - - ns

SCLK Duty Cycle 45 50 55 %

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -8 - 3 ns

CS5361

12 DS467F2

Figure 13. Master Mode, Left Justified SAI Figure 14. Slave Mode, Left Justified SAI

SC LK output

tmslr

SDOUT

tsdo

LRCK

output

MSB MSB-1

CLK input

LRCK input

dss

MSB MSB-1 MSB-2

tsclkw

SDOUT

srdl

Figure 15. Master Mode, I2S SAI Figure 16. Slave Mode, I2S SAI

SCLK input

LRCK input

MSB MSB-1

tsclkw

SDOUT

srdl

dss

SCLK input

LRCK input

MSB MSB-1

tsclkw

SDOUT

srdl

dss

OVFL

tsetup

LRCK

thold

Figure 17. OVFL Output Timing

CS5361

DS467F2 13

Figure 18. Left Justified Serial Audio Inter fa ce

SDATA 23 22 7 623 22

SCLK

LRCK

23 2254321087654321089 9

Left Channel Right Channel

Figure 19. I2S Serial Audio Interface

SDATA 23 22 8 723 22

SCLK

LRCK

23 2265432108765432109 9

Left Channel Right Channel

Figure 20. OVFL Output Timing, I2S Format

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

Figure 21. OVFL Output Timing, Left-Justified Format

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

CS5361

14 DS467F2

2.0 PIN DESCRIPTIONS

RST 124FILT+

M/S 223REFGND

LRCK 322VQ

SCLK 421AINR+

MCLK 520AINR-

VD 619VA

GND 718GND

VL 817AINL-

SDOUT 916AINL+

MDIV 10 15 OVFL

HPF 11 14 M1

I2S/LJ 12 13 M0

Pin Name #Pin Description

RST 1Reset (Input) - The device enters a low power mo de when low.

M/S 2Master/Slave Mode (Input) - Selects operation as either clock master or slave.

LRCK 3Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

MCLK 5Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VD 6Digital Power (Input) - Positive power supply for the digital section.

GND 7,18 Ground (Input) - Ground reference. Must be connected to anal og ground.

VL 8Logic Power (Input) - Positive power for the digital input/output.

SDOUT 9Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MDIV 10 MCLK Divider (Input) - Enables a master clock divide by two function.

HPF 11 High-pass Filter Enab le (Input) - Enables the Digital High-Pass Filter.

I2S/LJ 12 Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.

M1 13,

14 Mode Selection (Input) - Determines the operational mode of the device.

OVFL 15 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.

AINL+

AINL- 16,

17 Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma

modulators via the AINL+/- pins.

VA 19 Analog Power (Input) - Positive power supply for the analog section.

AINR-

AINR+ 20,

21 Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma

modulators via the AINR+/- pins.

VQ 22 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

REF_GND 23 Reference Ground (Input) - Ground reference for the internal sampling circui ts.

FILT+ 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

CS5361

DS467F2 15

FILT+

AINL+

AINL-

0.01µ

A/D CONVERTER

SCLK

CS5361

M/S

MCLK

AINR+

AINR-

**47 µ

F+

RST

VA V L

+5V

1µ

F+ 5Vto2.5 V

5.1 Ω

1µ

+ +

SDOUT

GND

I2S/LJ

LRCK

GND

Power Down

and M ode

Settings

Audio Data

Processor

TimingLogic

andClock

0.01µ

F0.01 µF

HPF

REFGND

MDIV

+ 5 V to 3 .3 V 1µ

F0.01µF

1µ

Analog

Input

Buffer

(Figure 24)

Analog

Input

Buffer

(Figure 24)

OVFL

10 k

0.01µ

* Resistor m ay only

be used if VD is

derived from V A. If

used, do not drive any

other logic from V D.

3.0 TYPICAL CONNECTION DIAGRAM

Figure 22. Typical Connection Diagram

CS5361

16 DS467F2

4.0 APPLICATIONS

4.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5361 must be set to the proper speed

mode via the mode pins, M1 and M0. Refer to Table 1.

4.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously gen-

erated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The d evice also

includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other

internal circuitry when MDIV is enabled, se t to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic

4.2.1 Slave Mode

LRCK and SCLK opera te as inputs in Slave mode. The left/right clock must be synchrono usly derived from the mas-

ter clock and be equal to F s. It is also recommend ed that the serial clock be synchro nously derived fr om the master

clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios.

Table 2. CS5361 Slave Mode Clock Ratios

M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)

0 0 Single Speed Mode 2 kHz - 51 kHz

0 1 Double Speed Mode 50 kHz - 102 kHz

1 0 Quad Speed Mode 100 kHz - 204 kHz

11 Reserved

Table 1. CS5361 Mode Control

Single Speed Mode

Fs = 2 kHz to 51 kHz Double Speed Mode

Fs = 50 kHz to 102 kHz Quad Speed Mode

Fs = 100 kHz to 204 kHz

MCLK/LRCK Ratio 256x, 512x 128x, 256x 128x

SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 32x, 64x

CS5361

DS467F2 17

4.2.2 Master Mode

In Master mode, LRCK an d SCLK operate as outputs. T he left/rig ht and serial clocks are in ternally derived from the

master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer

to Table 3 for common master clock frequencies.

÷ 128

÷ 256

÷ 64

M0M1

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 4

÷ 1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 1 0

MCLK

MDIV

Figure 23. CS5361 Master Mode Clocking

SAMPLE RATE (kHz) MDIV = 0

MCLK (MHz) MDIV = 1

MCLK (MHz)

32 8.192 16.384

44.1 11.2896 22.5792

48 12.288 24.576

64 8.192 16.384

88.2 11.2896 22.5792

96 12.288 24.576

176.4 11.2896 22.5792

192 12.288 24.576

Table 3. CS5361 Common Mast er Clock Frequencies

CS5361

18 DS467F2

4.3 Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and config-

uration pins are stable. It is also recommended that rese t be enabled if the analog or digital sup plies drop below the

minimum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay be-

tween the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the

presence of the external capacitance.

4.4 Analog Connections

The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the

filter. However, there is no rejection for input signals which are (n ×6.144 MHz) the digital passband frequency,

where n=0,1,2,...Refer to Figure 24 which shows the suggested filter that will attenuate any noise energy at

6.144 MHz, in addition to providing the optimum sou rce impedance fo r the modulators. The u se of capacitors wh ich

have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal

linearity.

Figure 24. CS5361 Recommended Analog Input Buffer

634 Ω

91 Ω

2700 pF

470 pF

COG

10 uF

ADC AIN+

ADC AIN-

AIN+

AIN-

COG

100kΩ

10 kΩ

100kΩ

CS5361

DS467F2 19

4.5 High-pass Filter and DC Offset Calibration

The operational amplifie rs in the input circuitry driving the CS5361 may generate a small DC offset into the A/D con-

verter. The CS5361 includ es a high-pass filter afte r the de cimator to re move any DC offset which could resu lt in re-

cording a DC level, possibly yielding “clicks” when switching between devices in a multichannel system.

The high-pass filter continuously subtracts a measure of the DC offset fro m the ou tput of the de cimation filter. If the

HPF pin is taken high during normal op eration, the current value of the DC offset register is frozen and this DC offset

will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC

offset calibration by:

1) Running the CS5361 with the high- pass filter enabled until the filter settles. See the Digital Filter Char acter-

istics for filter settling time.

2) Disabling the high-pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration

point and the CS5361.

4.6 Overflow Detection

The CS5361 includes overflow detection on both the left and right channels. This time multiplexed information is

presented as open dr ain, active low on pin 15, OVFL. The OVFL_L and OVFL_R da ta will go to a logical low as soon

as an overrange condition in either chan nel is detected. The data will remain low as specified in the Switching Char-

acteristics - Serial Audio Port section. This ensures sufficient time to detect an overra nge condition regardless of the

speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any

other overrange condition detected. Please note that an overrange condition on either channel will restart the time-

out period for both channels.

4.6.1 OVFL Output Timing

In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format, the OVFL

pin is updated two SCLK peri ods after an LRCK transition. Refer to Figures 23 and 2 4. In both cases the OVFL data

can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK

would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow

status. In I2S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of

LRCK would latch the left channel overflow status.

4.7 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5361 requires careful attention to power supply and grounding arrange-

ments if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with

VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply

or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from

VD. Decoupling c apacitors should be as near to the AD C as possible, with the low value ceramic capacitor being

the nearest. All signals, especially clocks, sh ould be kept away from the FILT+ and VQ pins in order to avoid un-

wanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 µF, must be

positioned to minimize the electrical path from FILT+ and REFGND. The CDB5361 evaluation board demonstr ates

the optimum layout and power supply ar rangements. To minimize digital noise, con nect the ADC digital outputs only

to CMOS inputs.

4.8 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure

synchronous sampling, the MCLK and LRCK must be the same for all of the CS5361’s in the system. If on ly one

master clock source is needed, one solution is to place one CS5361 in Master mode, and slave all of the other

CS5361’s to the one master. If multiple master clock so urces are needed, a possible solution would be to supply all

clocks from the same external source and time the CS53 61 reset with the inactive edge of MCLK. This will ensure

that all converters begin sampling on the same clock edge.

CS5361

20 DS467F2

5.0 PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is added to resulting me asureme nt to refer th e measurement to full-scale.

This technique ensures that th e distortion components are below the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society,

AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response

at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decib els.

Gain Error

The deviation from the nominal full-scale analog output for a full-scal e digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.

CS5361

DS467F2 21

6.0 PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51

C 0.009 0.013 0.23 0.32

D 0.598 0.614 15.20 15.60

E 0.291 0.299 7.40 7.60

e 0.040 0.060 1.02 1.52

H 0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27

∝0° 8° 0° 8°

24L SOIC (300 MIL BODY) PACKAGE DRAWING

∝

SEATING

PLANE

CS5361

22 DS467F2

Notes: 1.“D” and “E1” are refere nce datums and do no t in cluded mold flash or protrusions, but do include mold

mismatch and are measure d at the parting line, mold flash or pr otrusions shall not exceed 0.20 mm per

side.

2.Dimension “b” does n ot include d ambar protru sion/intrusion. Allowable dambar protrusion shall b e

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOT

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.303 0.307 0.311 7.70 7.80 7.90 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

CS5361

DS467F2 23

7.0 REVISION HISTORY

Release Date Changes

PP3 Mar 2003 Preliminary datasheet.

PP4 Sept 2004 Include lead-free device ordering info.

F1 Jan 2005 Improve Gain Error specification under Analog Characteri stics.

Specify Full-scale Input Voltage in terms of VA under Analog Characteristics.

Update Differential Input Impedance under Analog Characteristics.

Increase maximum THD+N rating for automotive grade devices.

Increase maxim u m Pow er -Su p ply Curr en t, I A, un de r DC Electric al Ch ar ac ter ist ics.

Reduce maximum Power Consumption under DC Electrical Characteristics.

Update FILT+ Output Impedance specification under DC Electrical Characteristics.

Extend maximum Fs in Single-Speed Mode to 51 kHz.

Extend maximum Fs in Double-Speed Mode to 102 kHz.

Extend maximum Fs in Quad-Speed Mode to 204 kHz.

Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode.

Replace min im um MC LK hig h/ l ow timin g spe c ifications with duty cycle specification.

Replace minimum SCLK high/low timing specifications with duty cycle specification.

F2 Feb 2005 Correct Recommended Analog Input Circuit.

Table 4. Revision History

Contacting Cirrus Lo gic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to www.cirrus.com

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