A
S12
28 PIN SSOP PACKAGE
FEATURES
APPLICATIONS
ARA2000S12
CATV Reverse Amplifier with Step Attenuator
Advanced Product Information
Rev. 0
·Low cost integrated monolithic GaAs
amplifier with step attenuator.
·Attenuation Range: 0 56 dB, variable in
1 dB steps via serial input.
·Meets DOCSIS distortion requirements at
+60 dBmV
·Low distortion & Low noise figure
·Frequency range: 5 100 MHz
·5 Volt operation
·MCNS/DOCSIS Compliant Cable Modems
·CATV Interactive Set-Top Box
·Telephony over Cable Systems
DESCRIPTION
The ARA2000S12 is a GaAs IC designed to perform the reverse path amplification and output level control
functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step
attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver
amplifier. It is capable of meeting the MCNS/DOCSIS harmonic distortion specifications while only requiring
a single polarity +5V supply. This
part is a balanced design that
meets or exceeds the MCNS/
DOCSIS requirement for
harmonic performance
@ +60dBmV output levels. Both
the input and output are matched
to 75 ohms. The precision
attenuator provides up to 56 dB
of attenuation in 1 dB
increments. The ARA2000S12 is
supplied in a 28-pin SSOP
package featuring a thermal heat
slug on the bottom of package.
Soldering this heat slug to the
ground plane of the PC board
ensures the lowest possible
thermal resistance for the device
resulting in a long MTF.
V
DD
)42,12,9,4,2SNIP(9CDV
V
NIFR
)8,5SNIP(3-ot0CDV
TTA
NI
TTA)01,3(
TUO
V)62,91(5CDV
I
TES
)22,7SNIP( 2CDV
SNIP(egatloVtupnIFR
8,5
*)
06+VmBd
erutarepmeTegarotS002+ot55-C°
erutarepmeTgniredloS062C°
emiTgniredloS5ceS
erutarepmeTesaCgnitarepO58+ot0C°
ABSOLUTE MAXIMUM RATINGS
PARAMETER PARAMETER
A2
ARA2000S12
Notes:
1. As measured in ANADIGICS test fixture
2. At +60 dBmV output level into 75 ohm load
RETEMARAPNIMPYTXAMTINUSTNEMMOC
niaG
1
92BdnoitaunettaBd0tA
gnittes
ssentalFniaG
1
-57.0-BdzHM001ot5
pmeTrevOnoitairaVniaG-600.0--c°/Bd
spetSnoitaunettA
1
Bd1
Bd2
Bd4
Bd8
Bd61
Bd23
1
2
9.3
0.8
7.51
5.13
Bd
2
dn
leveLnoitrotsiDcinomraH
2
zHM01-75-cBdVmBd06+ta
3
dr
leveLnoitrotsiDcinomraH
2
zHM01-46-cBdVmBd06+ta
3
dr
tnioPtpecretnItuptuOredrO87-- VmBd
tnioPnoisserpmoCniaGBd107- VmBd
erugiFesioN-7.15.2Bd
rewoPesioNtupuO
gnitteS.nttAniM/langiSoN/evitcA
gnitteS.nttAxaM/langiSoN/evitcA
-
-
-
-
6.42-
6.14-
VmBd
zHK0023ynA
morfhtdiwdnab
zHM24-5
zHM54tanoitalosIhctiwS-5303Bd
tuptuoniecnereffiD
neewteblevellangis
ybdnatsdnaevitca
ecnadepmItupnI
1
-57-mho
ssoLnruteRtupnI
1
-02-51-Bd
ecnadepmItuptuO
1
-57-mho
ssoLnruteRtuptuO
1
-02-51-BddelbanexT
ssoLnruteRtuptuO
1
-21-01-BddelbasidxT
cigoLlortnoChctiwStuptuOLIV
HIV
0
8.2
-
-
1
V
DD
V
V
ecnadepmIlortnoChctiwStuptuO-K01-mho
V
1DD
V,
2DD
-57V
V
DD
latigiD-5-V
nwodtuhSV-0-V
I
1DD
-06-Am
I
2DD
-09-Am
I
DD
latigiD-2102Am
noitpmusnoCrewoP-57.0-W
cigoLlortnoCrotaunettA
4
LIV
HIV
0
7.2
-
-
5.0
5.6 stloV
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 °C)
3
A
ARA2000S12
Attenuation @ 20 MHz
Pou t = + 62 dBm V @ 0 dB Attn . Setting
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
0 2 4 6 8 10121416182022242628303234363840424446485052545658606264
Attenuator Setting
Measured Attenuation
Attenuation @ 65 MHz
Pou t = +62 dBmV @ 0 dB Att n. Setting
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
A ttenuator Sett ing (dB)
Measured Attenuatio n (d B)
ARA2000 Harmo nic Perf o rm ance ov er Frequency
Pout = +62 dBmV
-72
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50 0 5 10 15 20 25 30 35 40
Frequency (MHz)
Harmonic Level (dBc)
2nd Harmonic 3r d Harmonic
A4
ARA2000S12
Figure 1: Cable Modem or Interactive Set-Top Box Block Diagram
Figure 2
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
EFET
EFET
GaAs IC
Attn In
Amp Out
Amp In
ISET 1
Shut Down 1
Amp Out
Amp In
Attn In
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
Attn Out
Amp In
Amp Out
Shut Down 2
ISET 2
Amp Out
Amp In
Attn Out
CMOS IC (Serial to Parallel Inter face)
2-Bit Shift
Register/
Address
Buffer Buffer
Contr ol Latch Data Latch
2-Bit Shift
Regis t er / Di e I D 4-Bit Shift
Register/ Chip Sel 8-Bit Shi ft Regist er
P5 P4 P3 P2 P1 P0
8
2
8
8
2
Data
Die
Address 0
Die
Address 1
Clock
Data
Enable
Unive r sal Reverse Amp
PA
MAC
QAM
Receiver
w/FEC
SAW
Double
Conversion
Tuner
Microcontroller
w/Enet MAC RAM
ROM
10Base-T
Tranceiver
Balun
ARA
2000
Reverse Amp
54-860 MHz
Gain Control
Clock
Clock
Data
Data
RJ45
Connector
45 MHz IF
Tx Enable/Disable
CLK
DAT
EN
CMOS IC
PA
PA
"Shutdown"
~
Low Pass
Filter
Diplexer
Filter
Coax Input
ATTN
1/2/4/8/16/32 dB
PA
~
"Shutdown"
Low Pass
Filter
Upstream
QPSK/
16-QAM
Modulator
5
A
ARA2000S12
TEST CIRCUIT
gnd
1
+5V
2
3Attn In +
4Out A1 +
gnd
Attn Out +
In A2 +
28
27
26
25
In A1 +
5
Vg1
6
7SB1
8In A1 -
Out A2 +
Vg2
SB2
Out A2 -
24
23
22
21
Data
13 C1 16
Enable
14 C0 15
Out A1 -
9
Attn In -
10
11
Vdd CMOS
12 Clock
In A2 -
Attn Out -
Gnd CMOS
nc
20
19
18
17
+5V +5V
+5VVg1 Vg2
RF Output
Vdd CMOS
CLOCK
DATA
ENABLE
C0
C1
n/c
2:12:1
RF Input (75 ohm)
1
µ
F
.1µF
10
µ
F
1
µ
F1
µ
F
1.2K
470 pF
470 pF
2K
1
µ
F
1K 3.9
1
µ
F1
µ
F
1.2K
10
µ
F
1
µ
F
.1µF
1
µ
F
.1µF
470 pF
1K
2K
1
µ
F
0
.1
µ
F
1µF
**
*
Balun: Toko part # 616PT-1030
A6
ARA2000S12
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
A0 A1 C0 C1 CS0 CS1 CS2 CS3
D
0P0/D0 P1/D1 P2 P3 P4 P5 P6 P7
A0 A1 REGISTER
0
1
0
0
0
1
1
1
Data Port
Parallel Port
N/A
N/A
Register Addr ess
CS0 CS1 APPLICATION
0001 Serial-Parallel Interface
N/A
Chip Sele ct
CS2 CS3
All Other Combinations
C0 C1
00
11
01
10
Die Address
Serial Data
Input
00 01 10 11
External Die
Connection
Indicates Device is
Selected
SERIAL
DATA FUNCTION
P0/D0 1 dB Attenuator Bit / External Data Port 0
Data Port Description
P7
P6
P5
P4
P3
P2
P1/D1 2 dB Attenuator Bit / External Data Port 1
4 dB Attenuator Bit
8 dB Attenuator Bit
16 dB Attenuator Bit
32 dB Attenuator Bit
N/A
N/A
DATA
CLOCK
ENABLE
ENABLE
OR
D
15
: MSB D
14
D
8
D
7
D
1
D
0
: LSB
SERIAL DATA INPUT TIMING
Programming Word
Figure 3
Figure 4
7
A
ARA2000S12
niPnoitcnuFnoitpircseD
1dnuorG
2cdV5+
3TTA
NI
)+()+(tupnIrotaunettA
4)+(1A
TUO
tuoptuO)+(1reifilpmA
5)+(1A
NI
tupnI)+(1reifilpmA
61gVnwodtuhS)-/+(1AreifilpmA
7I
1TES
tsujdAtnerruC)-/+(1AreifilpmA
8)-(1A
NI
tupnI)-(1AreifilpmA
9)-(1A
TUO
tuptuO)-(1AreifilpmA
01TTA
)-(NI
)-(tupnIrotaunettA
11ylppuSlatigiDddVtiucriClatigiDroFylppuS
21KLCkcolC
31TADataD
41nEelbanE
510C)6egapees(sserddAeiD
611C)6egapees(sserddAeiD
71C/NnoitcennocoN
81dng.giDdnuorglatigiD
91TTA
)-(TUO
)-(tuptuOrotaunettA
022A
)-(TUPNI
tupnI)-(2AreifilpmA
122A
)-(TUPTUO
tuptuO)-(2AreifilpmA
22 I
2TES
tsujdAtnerruC)-/+(2AreifilpmA
322gVnwodtuhS)-/+(2AreifilpmA
422A
)+(TUPTUO
tuptuO)+(2AreifilpmA
522A
)+(TUPNI
tupnI)+(2AreifilpmA
62TTA
)+(TUO
)+(tuptuOrotaunettA
72C/NnoitcennoCoN
82DNGdnuorG
PIN DESCRIPTION
A8
ARA2000S12
PACKAGE DIAGRAM
9
A
ARA2000S12
NOTES
A10
ARA2000S12
NOTES
11
A
ARA2000S12
NOTES
NOTES
A12
ARA2000S12
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice.
The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to
a products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable.
However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the
information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
A
ANADIGICS, Inc.
35 Technology Drive
Warren, New Jersey 07059
Tel: (908) 668-5000
Fax: (908) 668-5132
http://www.anadigics.com
Mktg@anadigics.com
