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AS1374
Dual 200mA, Low-Noise, High-PSRR, Low Dropout Regulators
Datasheet
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 1 - 18
1 General Description
The AS1374 is a low-noise, low-dropout linear regulator with two
separated outputs. Designed to deliver 200mA continuous output
current at each output pin, the LDOs can achieve a low 120mV
dropout for 200mA load current and are designed and optimized to
work with low-cost, small-capacitance ceramic capacitors.
An integrated P-channel MOSFET pass transistor allows the devices
to maintain extremely low quiescent current (30µA).
The AS1374 uses an advanced architecture to achieve ultra-low
output voltage noise of 20µVRMS and a power-supply rejection-ratio
of better than 85dB (@ 1kHz).
Two active-High enable pins allows to switch on or off each output
independently from each other.
The AS1374 requires only 1µF output capacitor for stability at any
load.
The device is available in a 6-bump WLP package.
Figure 1. AS1374 - Typical Application Circuit
2 Key Features
Preset Output Voltages: 1.2V to 3.6V (in 50mV steps)
Output Noise: 20µVRMS @ 100Hz to 100kHz
Power-Supply Rejection Ratio: 85dB @ 1kHz
Low Dropout: 120mV @ 200mA Load
Stable with 1µF Ceramic Capacitor for any Load
Guaranteed 200mA output
Pull-Down Option in Shutdown (factory set)
Extremely-Low Quiescent Current: 30µA
Excellent Load/Line Transient
Overcurrent and Thermal Protection
6-bump WLP Package
3 Applications
The devices are ideal for mobile phones, wireless phones, PDAs,
handheld computers, mobile phone base stations, Bluetooth portable
radios and accessories, wireless LANs, digital cameras, personal
audio devices, and any other portable, battery-powered application.
AS1374
5
GND
4
EN 2
2
VDD
3
OUT 1
6
EN 1
C1
1µF
Input
2V to 5.5V Output1
1.2V to 3.6V
1
OUT 2
C2
1µF
C3
1µF
Output2
1.2V to 3.6V
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AS1374
Datasheet - Pin Assignments
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 2 - 18
4 Pin Assignments
Figure 2. Pin Assignments (Top Vie w)
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number Pin Name Description
1OUT 2
Regulated Output Voltage 2. Bypass this pin with a capacitor to GND. See Application
Information for capacitor selection.
2VDD
Input Supply
3OUT 1 Regulated Output Voltage 1. Bypass this pin with a capacitor to GND. See Application
Information for capacitor selection.
4EN 2
Enable 2. Pull this pin to logic low to disable Regulated Output 2 voltage.
5GND
Ground
6EN 1 Enable 1. Pull this pin to logic low to disable Regulated Output 1 voltage.
AS1374
4
13
6
5
2
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AS1374
Datasheet - Absolute Maximum Ratings
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 3 - 18
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Min Max Units Comments
Electrical Parameters
VDD to GND -0.3 7 V
All other pins to GND -0.3 VDD + 0.3 V
Output Short-Circuit Duration Infinite
Input Current (latch-up immunity) -100 100 mA Norm: JEDEC 78
Electrostatic Discharge
Electrostatic Discharge HBM 2 kV Norm: MIL 883 E method 3015
Temperature Ranges and Storage Conditions
Thermal Resistance JA 201.7 ºC/W
Junction-to-ambient thermal resistance is very
dependent on application and board-layout. In
situations where high maximum power dissipation
exists, special attention must be paid to thermal
dissipation during board design.
Junction Temperature +125 ºC
Storage Temperature Range -55 +150 ºC
Package Body Temperature +260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
Humidity non-condensing 5 85 %
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AS1374
Datasheet - Electrical Characteristics
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 4 - 18
6 Electrical Characteristics
VIN = VOUT + 0.5V, VOUT = 2.85V, CIN = COUT = 1µF, Typical values are at TAMB = +25ºC (unless otherwise specified). All limits are
guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
TAMB Operating Temperature Range -40 +85 °C
VIN Input Voltage Range 2 5.5 V
VOUT Output Voltage Accuracy IOUT = 1mA, TAMB = +25ºC -1 +1 %IOUT = 100µA to 200mA, TAMB = +25ºC -1.5 +1.5
IOUT = 100µA to 200mA -2.5 +2.5
IOUT Maximum Output Current Each channel 200 mA
IGND Ground Current One channel on, IOUT = 50µA 25 50 µA
One channel on, IOUT = 200mA 30 55 µA
ILIMIT Current Limit OUT = short 210 300 400 mA
Dropout Voltage 1
1. Dropout is defined as VIN - VOUT when VOUT is 100mV below the value of VOUT for VIN = VOUT + 0.5V.
2V VOUT 2.5V, IOUT = 100mA 80 150 mV
IQQuiescent Current Both channels on, IOUT = 0.05mA 30 90 µA
Both channels ON,
VIN = VOUTNOM - 0.1V, IOUT = 0mA 50
VLNR Line Regulation VIN = (VOUT +0.5V) to 5.5V, IOUT = 1mA 0.02 %/V
VLDR Load Regulation IOUT = 1 to 200mA 0.0005 %/mA
ISHDN Shutdown Current OUT 1 and OUT 2 disable 0.01 2 µA
PSRR R ip ple Re jec tion f = 1kHz, IOUT = 10mA 85 dBf = 10kHz, IOUT = 10mA 65
f = 100kHz, IOUT = 10mA 50
Output Noise Voltage (RMS) f = 100Hz to 100kHz, ILOAD = 20mA 20 µV
Enable
Enable Inpu t Bias Current 0.01 µA
Enable Exit Delay 2
2. Time needed for VOUT to reach 90% of final value.
Both channels initially OFF 150 µs
One channel initially OFF 200
Enable Logic Low Level 0.4 V
Enable Logic High Level 1.4 V
Thermal Protection
TSHDN Thermal Shutdown Temperature 160 ºC
TSHDN Thermal Shutdown Hysteresis 15 ºC
COUT Output Capacitor Load Capacitor Range 0.47 10 µF
Maximum ESR Load 500 m
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AS1374
Datasheet - Typical Operating Characteristics
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 5 - 18
7 Typical Operating Characteristics
VIN = VOUT + 0.5V, VOUT = 2.85V, CIN = COUT = 1µF, TAMB = 25°C (unless otherwise specified).
Figure 3. Output Voltage vs. Temperature Figure 4. Output Voltage vs. Input Voltage
2.82
2.83
2.84
2.85
2.86
2.87
2.88
-45 -30 -15 0 15 30 45 60 75 90
T emperatur e (°C)
Output V oltage (V )
CH1
CH2
2.82
2.83
2.84
2.85
2.86
2.87
2.88
3.35 3.85 4.35 4.85 5.35
Input Volt age ( V)
Output V oltage (V )
Iload = 1m A
Iload = 10mA
Iload = 100mA
Iload = 200mA
Figure 5. Output Voltage vs. Load Current Figure 6. Output Voltage vs. Input Voltage - Dropout
2.8
2.81
2.82
2.83
2.84
2.85
2.86
2.87
2.88
0 25 50 75 100 125 150 175 200
Load Current (mA)
O utput v oltage (V )
-40°C
+25°C
+85°C
2.72
2.74
2.76
2.78
2.8
2.82
2.84
2.86
2.75 2.8 2.85 2.9 2.95 3 3.05
Input Volt age ( V)
Output V oltage (V )
Il oad = 100mA
Il oad = 200mA
Figure 7. Dropout Voltage vs. Load Current Figure 8. PSRR vs. Frequency
0
25
50
75
100
125
150
25 50 75 100 125 150 175 200
Load Current (mA)
Dropout Voltage (V )
-40°C
+25°C
+85°C
20
30
40
50
60
70
80
90
100
100 1000 10000 100000
F r equency (Hz)
PSRR (dB)
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AS1374
Datasheet - Typical Operating Characteristics
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 6 - 18
Figure 9. Ground Pin Current vs. Load Current Figure 10. Ground Pin Current vs. Temperature
23
24
25
26
27
28
29
30
31
32
33
0 25 50 75 100 125 150 175 200
Load Current ( mA)
Gr ound P in Cur r ent (µA )
-40°C
+25°C
+85°C
25
26
27
28
29
30
-45 -30 -15 0 15 30 45 60 75 90
Temper atur e ( ° C)
Gr ound P in Cur r ent (µA )
Figure 11. Ground Pin Current vs. Input Voltage; one Channel
on, no Load Figure 12. Ground Pin Current vs. Input Voltage; one Channel
on, ILOAD = 200mA
0
10
20
30
40
50
60
012345
I nput Voltage ( V)
Gr ound P in Cur r ent (µA )
-40°C
+25°C
+85°C
0
10
20
30
40
50
60
3.35 3.85 4.35 4.85 5.35
Input Voltage (V)
Gr ound P in Cur r ent (µA )
-40°C
+25°C
+85°C
Figure 13. Ground Pin Current vs. Input Voltage; both Channels
on, no Load Figure 14. Ground Pin Current vs. Input Voltage; both Channels
on, ILOAD = 200mA
0
10
20
30
40
50
60
70
80
90
100
012345
Input Volt age ( V)
Gr ound P in Cur r ent (µA )
-40°C
+25°C
+85°C
0
10
20
30
40
50
60
70
80
90
100
3.35 3.85 4.35 4.85 5.35
I nput Voltage ( V)
Gr ound P in Cur r ent (µA )
-40°C
+25°C
+85°C
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AS1374
Datasheet - Typical Operating Characteristics
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 7 - 18
Figure 15. Shutdown Current vs. Input Voltage Figure 16. Load Regulation vs. Temperature
0
10
20
30
40
50
60
0.511.522.533.544.555.5
I nput Voltage ( V)
S hutdown Cur r e nt ( nA )
-40°C
+25°C
+85°C
-0.0012
-0.001
-0.0008
-0.0006
-0.0004
-0.0002
0
-45 -30 -15 0 15 30 45 60 75 90
Temper atur e ( ° C)
Load Re gulation (% / m A )
CH1
CH2
Figure 17. Line Regulation vs. Load Current Figure 18. Line Regulation vs. Temperature
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 25 50 75 100 125 150 175 200
Load Cur r ent ( mA)
Line Regulation (% / V )
-40°C
+25°C
+85°C
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
-45 -30 -15 0 15 30 45 60 75 90
Temper atur e ( ° C)
Line Regulation (% / V )
Iload = 1m A
Iload = 10mA
Iload = 100mA
Iload = 200mA
Figure 19. Load Transient Response, Crosstalk, between CH1
and CH2, IOUT = 200mA Figure 20. Load Transient Response near Dropout,
IOUT = 200mA
20µs/Div
VOUT2
10mV/Div 10mV/Div 100mA/Div
VOUT1IOUT1
20µs/Div
20mV/Div
100mA/Div
VOUT1IOUT1
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AS1374
Datasheet - Typical Operating Characteristics
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 8 - 18
Figure 21. Line Transient Response Figure 22. Shu tdown
100µs/Div
10mV/Div 500mV/Div
VOUT1VIN
100µs/Div
VOUT1
1V/Div 2V/Div 50mA/Div
EN1IOUT1
Figure 23. Startup of CH1 when CH2 is Off Figure 24. Startup of CH1 when CH2 is On
20µs/Div
VOUT1
1V/Div 2V/Div 100mA/Div
EN1IIN
20µs/Div
VOUT1
1V/Div 2V/Div 100mA/Div
EN1IIN
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AS1374
Datasheet - Detailed Description
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 9 - 18
8 Detailed Description
Figure 25 shows the block diagram of the AS1374. It identifies the basics of a series linear regulator employing a P-Channel MOSFET as the
control element. A stable voltage reference (REF in Figure 25) is compared with an attenuated sample of the output voltage. Any difference
between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control element to reduce the
difference to a minimum. The error amplifier incorporates additional buffering to drive the relatively large gate capacitance of the series pass P-
channel MOSFET, when additional drive current is required under transient conditions. Input supply variations are absorbed by the series
element, and output voltage variations with loading are absorbed by the low output impedance of the regulator.
8.1 Output Voltage
The AS1374 deliver preset output voltages from 1.2V to 3.6V, in 50mV increments (see Ordering Information on page 17).
8.2 Enable
The AS1374 feature an active high enable mode to shutdown each output independently. Driving EN 1 low disables Output 1, driving EN 2 low
disables Output 2. The disabled Output enters a high-impedance state.
Figure 25. AS1374 Block Diagram
8.3 Current Limit
The AS1374 include a current limiting circuitry to monitor and control the P-channel MOSFET pass transistor’s gate voltage, thus limiting the
device output current to 300mA.
Note: See Table 3 on page 4 for the recommended min and max current limits. The output can be shorted to ground indefinitely without
causing damage to the device.
8.4 Thermal Protection
Integrated thermal protection circuitry limits total power dissipation in the AS1374. When the junction temperature (TJ) exceeds +160ºC, the
thermal sensor signals the shutdown logic, turning off the P-channel MOSFET pass transistor and allowing the device to cool down. The thermal
sensor turns the pass transistor on again after the device’s junction temperature drops by 15ºC, resulting in a pulsed output during continuous
thermal-overload conditions.
Note: Thermal protection is designed to protect the devices in the event of fault conditions. For continuous operation, do not exceed the
absolute maximum junction temperature rating of +150ºC.
Trimmable
Reference
Bandgap
+
-
+
-
Enable Logic
CH1
Thermal
Protection Common
Logic
Enable Logic
CH2
EN1
VIN
EN2
O
U
T
1
G
N
D
O
U
T
2
AS1374
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2
ams AG
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AS1374
Datasheet - Application Information
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 10 - 18
9 Application Information
9.1 Dropout Voltage
Dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. At this point, the output voltage change
follows the input voltage change. Dropout voltage may be measured at different load currents, but is usually specified at maximum output. As a
result, the MOSFET maximum series resistance over temperature is obtained. More generally:
VDROPOUT = ILOAD x RSERIES (EQ 1)
Dropout is probably the most important specification when the regulator is used in a battery application. The dropout performance of the
regulator defines the useful “end of life” of the battery before replacement or re-charge is required.
Figure 26. Graphical Representation of Dropout Voltage
Figure 26 shows the variation of VOUT as VIN is varied for a certain load current. The practical value of dropout is the differential voltage (VOUT-
VIN) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal
regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential.
9.2 Efficiency
Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is
directly related to quiescent current and dropout voltage. Efficiency is given by:
Efficiency = % (EQ 2)
Where:
IQ = quiescent current of LDO
Dropout
Voltage
100mV
VIN
VOUT
VOUT VIN
VOUT VIN=VOUT(TYP)+0.5V
VIN
VLOAD ILOAD
VIN IQILOAD
+
----------------------------------------- 100
ams AG
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AS1374
Datasheet - Application Information
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 11 - 18
9.3 Power Dissipation
Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current
required to bias the internal voltage reference and the internal error amplifier, and is calculated as:
Watts (EQ 3)
Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as:
Watts (EQ 4)
Total LDO power dissipation is calculated as:
Watts (EQ 5)
9.4 Junction Temperature
Under all operating conditions, the maximum junction temperature should not be allowed to exceed 125°C (unless otherwise specified in the
datasheet). Limiting the maximum junction temperature requires knowledge of the heat path from junction to case (JC°C/W fixed by the IC
manufacturer), and adjustment of the case to ambient heat path (CA°C/W) by manipulation of the PCB copper area adjacent to the IC position.
Figure 27. Package Physical Arrangements
PD MAX
SeriespassILOAD MAX
=VIN MAX
VOUT MIN
–
PD MAX
BiasVIN MAX
IQ
=
PD MAX
TotalPD MAX
SeriespassPD MAX
+Bias=
Chip
PCB
Package Transfer Layer
CS-WLP Package
Solder Balls
ams AG
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AS1374
Datasheet - Application Information
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 12 - 18
Figure 28. Steady State Heat Flow Equivalent Circuit
Total Thermal Path Resistance: R
JA = R
JC + R
CS + R
SA (EQ 6)
Junction Temperature (TJ ºC) is determined by: TJ = (PD(MAX) x R
JA) + TAMB ºC (EQ 7)
9.5 Explanation of Steady State Specifications
9.5.1 Line Regulation
Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the
regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain
of the error amplifier. More generally:
Line Regulation = and is a pure number (EQ 8)
In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is
available with numerous output voltage trim options.
Line Regulation = % / V (EQ 9)
9.5.2 Load Regulation
Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the
regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output
resistance of the regulator. More generally:
Load Regulation = and is units of ohms ()(EQ 10)
In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is
available with numerous output voltage trim options.
Load Regulation = % / mA (EQ 11)
Junction
TJ°C Package
TC°C PCB/Heatsink
TS°C Ambient
TA°C
Chip
Power
RJC RCS RSA
VOUT
VIN
-----------------
VOUT
VIN
----------------- 100
VOUT
-------------
VOUT
IOUT
-----------------
VOUT
IOUT
----------------- 100
VOUT
-------------
ams AG
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AS1374
Datasheet - Application Information
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 13 - 18
9.5.3 Setting Accuracy
Accuracy of the final output voltage is determined by the accuracy of the ratio of R1 and R2, the reference accuracy and the input offset voltage
of the error amplifier. When the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification.
When the regulator has a SET terminal, the output voltage may be adjusted externally. In this case, the tolerance of the external resistor network
must be incorporated into the final accuracy calculation. Generally:
(EQ 12)
The reference tolerance is given both at 25°C and over the full operating temperature range.
9.5.4 Total Accuracy
Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally:
Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % (EQ 13)
9.6 Explanation of Dynamic Specifications
9.6.1 Power Supply Rejection Ratio (PSRR)
Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a
summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in
the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low
quiescent current conditions. Generally:
PSRR = dB using lower case to indicate AC values (EQ 14)
Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally. The AS1374 is
designed to deliver low noise and high PSRR, with low quiescent currents in battery-powered systems. The power-supply rejection is 85dB at
1kHz and 50dB at 100kHz. When operating from sources other than batteries, improved supply-noise rejection and transient response are
achieved by increasing the values of the input and output capacitors. Additional passive LC filtering at the input can provide enhanced rejection
at high frequencies.
9.6.2 Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to
cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause
instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown
either by a plot of stable ESR versus load current, or a maximum value in the datasheet.
Some ceramic capacitors exhibit large capacitance and ESR variations with variations in temperature. Z5U and Y5V capacitors may be required
to ensure stability at temperatures below TAMB = -10°C. With X7R or X5R capacitors, a 1µF capacitor should be sufficient at all operating
temperatures.
Larger output capacitor values (10µF) help to reduce noise and improve load transient-response, stability and power-supply rejection.
9.6.3 Input Capacitor
An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1369 power supply
input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance
of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used
at the input.
9.6.4 Noise
The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error
amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will
produce system problems.
VOUT VSET VSET
1R1R1
R2R2
---------------------
+
=
20LogVOUT
VIN
-----------------
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AS1374
Datasheet
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 14 - 18
9.6.5 Transient Response
The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error
loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output
capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally:
Units are Volts, Amps, Ohms. (EQ 15)
Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Do remember to keep the ESR within
stability recommendations when reducing ESR by adding multiple parallel output capacitors.
After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change.
This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of:
Units are Volts, Seconds, Farads, Ohms. (EQ 16)
Where:
CLOAD is output capacitor
T= Propagation Delay of the LDO
This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for
t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load
current step produces 50mV output drop if the LDO response is 1µsec and the load cap is 1µF.
There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specifi cat ion
discussed above.
9.6.6 Turn On Time
This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the
time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator min and max limits.
Shutdown reduces the quiescent curren t to very low, mostly leakage values (<1µA).
9.6.7 Thermal Protection
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device.
Die temperature is measured, and when a 160°C threshold is reached, the device enters shutdown. When the die cools sufficiently, the device
will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15°C prevents low frequency oscillation between start-up and
shutdown around the temperature thresho ld.
VTRANSIENT IOUTPUT RESR
=
VTRANSIENT IOUTPUT RESR T
CLOAD
-----------------
+
=
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AS1374
Datasheet - Package Drawings and Markings
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 15 - 18
10 Package Drawings and Markings
The AS1374 is available in a 6-bump WLP package.
Figure 29. 6-bump WLP Package
Notes:
1. ccc – Coplanarity
2. All dimensions are in µm.
Top through view Bottom view (ball side)
ASSH
XXXX
ams AG
Technical content still valid
AS1374
Datasheet - Package Drawings and Markings
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 16 - 18
Revision History
Note: Typos may not be explicitly mentioned under revision history.
Revision Date Owner Description
Initial revisions
1.7 11 Oct, 2011 afe Changes made across the document
1.8 12 Dec, 2011 Updated equations in Power Dissipation section
ams AG
Technical content still valid
AS1374
Datasheet - Orderin g Info rmation
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 17 - 18
11 Ordering Information
The devices are available as the standard products shown in Table 4.
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Table 4. Ordering Information
Ordering Code Marking Output Voltage 1 Output Voltage 2 Delivery Form Package
AS1374-BWLT-285 ASSH 2.85V 2.85V Tape and Reel 6-bump WLP
AS1374-BWLT1833 ASSJ 1.8V 3.3V Tape and Reel 6-bump WLP
AS1374-BWLT1818 ASSP 1.8V 1.8V Tape and Reel 6-bump WLP
AS1374-BWLT1218 ASSK 1.2V 1.8V Tape and Reel 6-bump WLP
AS1374-BWLT1214 ASSY 1.2V 1.4V Tape and Reel 6-bump WLP
AS1374-BWLT18285 ASSZ 1.8V 2.85V Tape and Reel 6-bump WLP
AS1374-BWLT1212 ASSW 1.2V 1.2V Tape and Reel 6-bump WLP
AS1374-BWLT1827 ASTB 1.8V 2.7V Tape and Reel 6-bump WLP
AS1374-BWLT15331
1. On request
ASTF 1.5V 3.3V Tape and Reel 6-bump WLP
AS1374-BWLT18201ASTG 1.8V 2.0V Tape and Reel 6-bump WLP
AS1374-BWLT18211ASTH 1.8V 2.1V Tape and Reel 6-bump WLP
AS1374-BWLT25331ASTI 2.5V 3.3V Tape and Reel 6-bump WLP
AS1374-BWLT2
2. Non-standard devices from 1.2V to 3.6V are available in 50mV steps.
For more information and inquiries contact http://www.austriamicrosystems.com/contact
____ tbd tbd Tape and Reel 6-bump WLP
ams AG
Technical content still valid
AS1374
Datasheet - Orderin g Info rmation
www.austriamicrosystems.com/LDOs/AS1374 Revision 1.8 18 - 18
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
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