ANALOG DEVICES Octal Sample-and-Hold with Multiplexed Input SMP-08 FEATURES Internai Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatibie With CD4051 Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for A.T.E. Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control ORDERING INFORMATION ' PACKAGE: 16-PIN DIP/SO OPERATING CERDIP PLASTIC TEMPERATURE 16-PIN 16-PIN RANGE TBA - MIL SMPO8FQ SMPO8FP XIND - SMPO8FS XIND Consult factory for 883 data sheet. + Burn-in is available on industrial temperature range parts in CerDIP and plas- tic DIP packages. PIN CONNECTIONS 16-PIN CERDIP (Q-Suffix) 16-PIN EPOXY DIP (P-Suffix) 16-PIN SO (S-Suffix) GENERAL DESCRIPTION The SMP-08 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and Manufactured under the following U.S. patent: 4,739,281 REV. B fast acquisition time. The SMP-08 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to +1/2 LSB in less than seven microseconds. The SMP-08's out- put swing includes the negative supply in both single and dual supply operation. The SMP-08 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration makes the SMP-08 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. The SMP-08 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or VCA gain ad- justments. One or more SMP-O8s can be used with single or multiple DACs ta provide multiple set points within a system. The SMP-08 offers significant cost and size reduction over discrete designs. It is available in a 16-pin hermetic or plastic DIP, or surface mount SOIC package. FUNCTIONAL DIAGRAM INPUT ow B wee) INH a }___* vano 1 OF 8 DECODER 16 p__ 65, ony | > CHo OUT ew > CH, OUT cys im > CH, OUT Sewl a CHg OUT he wi CH, OUT CHs OUT CH, OUT a Sw CH, OUT HOLDCAPS Lu (INTERNAL) T" Tr } t Fk 1 b L Fk 1 t t a PY YY & SAMPLE/TRACK-HOLD AMPLIFIERS 4-101SMP-08 ABSOLUTE MAXIMUM RATINGS (Note 1) IN . Voyr to DGND... Analog Output Current 0.0.0... eee (Not short-circuit protected) Operating Temperature Range FR, FS oe sesesceesesnscnecneessensee Junction Temperature.. Storage Temperature .. 2. 1. . 40C to +85C sesteseasteess +150C 65C to +150C 2. Lead Temperature (Soldering, 60 sec).. +300C PACKAGE TYPE @,, (Note 2) %& UNITS a. 16-Pin Hermetic DIP (Q) 94 12 C/W 16-Pin Plastic DIP (P) 76 33 C/W 16-Pin SO (S) 92 27 C/W NOTES: 1. Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. @,, is specified for worst case mounting conditions, i.e.,@, ,is specified for device in socket for CerDIP and P-DIP packages; @,, is specified for device soldered to printed circuit board for SO package. CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper anti- Static handling procedures. Remove power before inserting or removing units from their sockets. ELECTRICAL CHARACTERISTICS at V,,, = +5V, V., = -5V, DGND = OV, R, = No Load, T, = 40C to +85C for SMP-08F, unless otherwise noted. SMP-08F PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Linearity Error 3V $ Vins +3V _ 0.01 - % Buffer Offset Voltage Vos ts oot, < 285C ~ ae 60 mv Hold Step Vus Vin =0V _ 1 4 mv Droop Rate AVG, /At T, = +25C, V, = 0V _ 2 20 mV/s Output Source Current \source Viy = OV (Note 1) 1.2 _ _ mA Output Sink Current donk Viy = OV (Note 1) 0.5 _ _ mA Output Voltage Range R, = 20kQ -3.0 +3.0 Vv LOGIC CHARACTERISTICS Logic Input High Voltage INH 2.4 _ _ v Logic Input Low voltage Vine _ 0.8 v Logic Input Current I Vin =2.4V _ 05 1 pA DYNAMIC PERFORMANCE (Note 2) Acquisition Time bo Ty, = +25C, -3V to +3V 10 0.1% _ 7 - ps Hold Mode Settling Time ty To + tmV of Final Value 1 _- ps Channel Select Time low _ 90 _ ns Channel Deselect Time les _- 45 _ ns Inhibit Recovery Time te _ 90 - ns Slew Rate SR _- 3 _- Vins Capacitive Load Stability <30% Overshoot - 500 - pF Analog Crosstalk -3V to +3V Step -72 _ dB 4-102 SAMPLE/TRACK-HOLD AMPLIFIERS REV. BSMP-08 ELECTRICAL CHARACTERISTICS at V,,, = +5V, Vag =-5V, DGND = OV, R, = No Load, T, = 40C to +85C for SMP-O8F, unless otherwise noted. Continued SMP-08F PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR Vy = +5V to +6V 60 75 - dB NOTES: 1. Outputs are capable of sinking and sourcing over 20mA but offset is guaran- teed at specified load levels. 2. Allinput control signals are specified with Leh= 5ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. ELECTRICAL CHARACTERISTICS at Vpp = +12V, Veg =0V, DGND = OV, R, =NoLoad, T, =-40C to+85C for SMP-O8F, unless otherwise noted. SMP-08F PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Linearity Error 6OMV $ Vins 10V _ 0.01 - % Buffer Offset Voltage Vos " on gat, 6 485C 0 mv Hoid Step Vus Vin =6V _ 1 4 mV Droop Rate AVo,,/At T A= 425C, Vin =6V _ 2 20 mV/s Output Source Current IeouRCE Vin = 6V (Note 1) 1.2 _ _ mA Output Sink Current eink Viy = 8V (Note 1) 0.5 _- - mA Output Voltage Range rt - aa pee ~ Oe v LOGIC CHARACTERISTICS Logic Input High Voltage Vind 2.4 _ - v Logic Input Low voltage Vine _ 0.8 v Logic Input Current by Viya2.4av _ 05 1 pA DYNAMIC PERFORMANCE (Note 2) Acquisition Time ha yh =+26C, 010 10V 100.1% _ 9 _ us Hold Mode Settling Time ly To + 1mvV of Final Value - 1 _ Bs Channel Select Time tow - 90 _ ns Channel Deselect Time loos - 45 - ns Inhibit Recovery Time ta - 90 - ns Slew Rate SR R_ = 20k (Note 3) 3 4 - Vips Capacitive Load Stability <30% Overshoot - 500 _ pF Analog Crosstalk 0 to 10V Step ~72 dB SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8V <V,, 8 13.2V 60 75 - dB Supply Current loo vte e 1 <+85C _ 20 100 ma NOTES: 1, Outputs are capable of sinking and sourcing over 20mA but offset is guaran- teed at specified load levels. 2. Allinputcontrol signals are specified with t, = t= Sns (10% to 90% of +5V) and timed from a voltage level of 1.6V. 3. Slew rate is measured in the sample mode with a 0 to 10V step from 20% to 80%. REV. B SAMPLE/TRACK-HOLD AMPLIFIERS 4-103SMP-08 DICE CHARACTERISTICS 1. CH, OUT 9. CCONTROL 2. CH, OUT 10, BCONTROL 3. INPUT 11. ACONTROL 4, CH, OUT 12. CH, OUT 5. CH, OUT 13. CH, OUT 6. INH 14, CH, OUT 7. Veg 45, CH, OUT 8. DGND 16. Voo DIE SIZE 0.080 x 0.120 Inch, 9,600 sq. mils (2.032 x 3.048 mm, 6.193 sq. mm) WAFER TEST LIMITS at Vop = +12V, Veg = DGND = OV, R, = No Load, T, = +25C, unless otherwise specified. SMP-08GBC PARAMETER SYMBOL CONDITIONS LIMITS UNITS Buffer Offset Voltage Vos Viy = +6V 20 mV MAX Droop Rate AVQ,/dt Vin = +6V 20 mV/s MAX Output Source Current lsounce Vin = t6V 1.2 mA MIN Output Sink Current leink Vw = +6V 0.5 mA MIN Output Voltage Range et - on ones V MAX/MIN LOGIC CHARACTERISTICS Logic Input High Voltage Vin 2.4 VMIN Logic Input Low Voltage Vine 0.8 V MAX Logic Input Current Ww Viy=2-4V 1 pA MAX SUPPLY CHARCTERISTICS Power Supply Rejection Ratio PSRR 10.8V $V5) $13.2 60 dB MIN Supply Current loo 8.0 mA MAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 4-104 SAMPLE/TRACK-HOLD AMPLIFIERS REV. BSMP-08 TYPICAL PERFORMANCE CHARACTERISTICS DROOP RATE (mV/s) DROOP RATE vs TEMPERATURE 10000 T T Vop = +12V Vss = 0V Vin = +5V Rp = 10k g 8 ~ 3 / J 4 -55-35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) HOLD STEP vs INPUT VOLTAGE Ta= +25C Vop = +12V Vgg = OV NO LOAD HOLD STEP (mV) o -2 23 4 5 6 7 8 10 INPUT VOLTAGE (VOLTS) Oo o1 OFFSET VOLTAGE vs INPUT VOLTAGE Ta = 425C Vop = +12V Vss = OV NO LOAD = 20k0 OFFSET VOLTAGE (mv) o 1 2 3 INPUT VOLTAGE (VOLTS) 4 5 6 7 8 8 10 REV. B HOLD STEP (mv) DROOP RATE (mV/s) OFFSET VOLTAGE (mv) Ta= DROOP RATE vs INPUT VOLTAGE 425C Voo = +12 Vgg = OV NO LOAD Qo .1 23 4 5 6 7 8 INPUT VOLTAGE (VOLTS) HOLD STEP vs TEMPERATURE Vop = +12V Vss = OV Vin = +5V NO LOAD oo1 3 -5 -35 -15 5 25 45 65 TEMPERATURE (C) OFFSET VOLTAGE vs INPUT VOLTAGE 9 10 85 Th = 485C Vop = +1 Vgg = OV 2Vv NO LOAD 23 4 5 6 7 8 INPUT VOLTAGE (VOLTS) 9 10 DROOP RATE (mVss) OFFSET VOLTAGE (mv) SLEW RATE (Vius) DROOP RATE vs INPUT VOLTAGE Ta= 4125C Vpp = +12 Vsg = OV NO LOAD 600 09 12 3 4 5 6 7 8 9 10 INPUT VOLTAGE (VOLTS) SLEW RATE vs Vpp T T Ta = 425C Vsg = OV NO LOAD \ yo Z| | y Ye 10 11412 #13 14 #15 #16 17 18 Voo (VOLTS) OFFSET VOLTAGE vs INPUT VOLTAGE Ta = -40C Vop = +12V Veg = OV NO LOAD Ry = 20k o 12 3 4 6 7 8 10 INPUT VOLTAGE (VOLTS) SAMPLE/TRACK-HOLD AMPLIFIERS 4-105SMP-08 TYPICAL PERFORMANCE CHARACTERISTICS Continued OFFSET VOLTAGE vs SAMPLE MODE 0 TEMPERATURE 14 SUPPLY CURRENT vs Vpp 0 POWER SUPPLY REJECTION Vpp = +12V Vsg = OV 80 -1 Veg = OV 12 NO LOAD = Vin = +5V = 70 LIN a + P= Kn Z g we E 10 o 60 f SH : Z ott | NING ill Bs a, 8 so Hl HE TN Cis 5s 2 2 LMT UIT a n 4 6 -~8 55-35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Vop (VOLTS) GAIN, PHASE SHIFT vs FREQUENCY Vg =0V | NO LOAD PHASE SHIFT (DEG) OUTPUT IMPEDANCE (2) 100 1k 10k 100k.s tM~s 10M FREQUENCY (Hz) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Ta= Vopp = +8V Vss = -6V NO LOAD REJECTION RATIO (dB) PEAK-TO-PEAK OUTPUT (VOLTS) 100k FREQUENCY (Hz) 1M 4-106 SAMPLE/TRACK-HOLD AMPLIFIERS 8 10 12 #14 #+16 #18 0 10 ST o LUM UIE UU TE LTH (0100 *~CKS**NOK:S*Ok aM FREQUENCY (Hz) OUTPUT IMPEDANCE vs FREQUENCY Ta = 425C Vop = +12V Vss = OV NO LOAD 100 1k 10k 1M FREQUENCY (Hz) 100k HOLD MODE POWER SUPPLY REJECTION +PSRR Ta = 425C Vop = +12V. Vss = OV NO LOAD HOLD CAPACITORS REFERENCED TO Vss Vititl -PSAR a T 1 1k 10k-s100k)s 1M FREQUENCY (Hz) 10 100 REV. BSMP-08 BURN-IN CIRCUIT QIN [O/H/aloln |= Voc +15V 10kQ APPLICATIONS INFORMATION The SMP-08, a multiplexed octal S/H, minimizes board space in systems requiring cycled calibration or an array of control voltages. When used in conjunction with a low cost 10-bit D/A, the SMP-08 can easily be integrated into microprocessor based systems. Since the SMP-08 features break-before-make switching and an internal decoder, no external logic is required. The SMP-08 has an internally regulated TTL supply so that TTL/ CMOS compatibility is maintained over the full supply range. See Figure 1 for channel decode address information. POWER SUPPLIES The SMP-08 is capable of operating with either single or dual supplies, over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, Vpp and Vgg establish the input andoutput voltage range, which is: (Vgg + 9.06V) < Voutn $ (Vpp -2V) Note that several specifications, including acquisition time, offset and output voltage compliance will degrade for supply voltages of less than 7V. If split supplies are used, the negative supply should be bypassed with a 0.1pF capacitor in parallel with a 10uF to ground. The internal hold capacitors are connected to this supply pin and any noise will appear at the outputs. In single supply applications, it is extremely important that the Vg (negative supply) pin is connected to a clean ground. The hold capacitors are internally tied to the V... (negative) rail. Any ground noise or disturbance will directly couple to the output of the sample-and-hold, degrading the signal-to-noise perfor- mance. The analog and digital ground traces on the circuit board should be physically separated to reduce digital switching noise from entering the analog circuitry. POWER SUPPLY SEQUENCING Vop Should be applied to the SMP-08 before the logic input signals. The SMP-08 has been designed to be immune to latch- up, but standard precautions should still be taken. REV. B OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15) The buffer offset specification is 10mV; this is less than 1/2 LSB of an 8-bit DAC with 10V full scale. The hold step (magnitude of step caused in the output voltage when switching from sampie- to-hold mode, also referred to as the pedestal error or sample- to-hold offset), is about 2mV with little variation over the full output voltage range. The droop rate of a held channel is 2mV/s typical and 20mV/s maximum. The buffers are designed to drive loads connected to ground. The outputs can source more than 20mA, over the full voltage range, but have limited current sinking capability near V.,.. In split supply operation, symmetrical output swings can be obtained by restricting the output range to 2V from either supply. On-chip SMP-08 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capacitive loads upto 500pF. However, since the SMP-08s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pin 3) The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP-08's acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (Vs, < V,,, < Vpp) to avoid the possibility of fatch- up. If single supply operation is desired, op amps such as the OP-21, OP-80, or OP-90 that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as +7.5V, can be used with the SMP-08. APPLICATION TIPS All unused digital inputs should be connected to logic LOW and unused analog inputs connected to analog ground. For connector-driven analog inputs that may become temporarily disconnected, aresistorto Vop Veg or analog ground should be used with a value ranging from 200kQ to 1MQ. SAMPLE/TRACK-HOLD AMPLIFIERS 4-107SMP-08 +12V 5V REF-02 = +12V 4 17 VaerA Von! WAR CS Gnd 2 Pe toe 14 ce, DIGITAL ) 3 7 Ve INPUTS DAC-8228 OA / Ves boo. 15 acu, ADDRESS ADDRESS waa 16 1 BUS DECODE WT, Ves iol, poy Pt 00 CHANNEL DECODING PINS PIN1O PIN11 PING Cc B A INH CH PIN 0 0 0 0 0 43 0 0 1 0 1 14 0 1 0 0 2 15 0 1 1 0 3 12 1 0 oO 0 4 1 1 0 1 0 5 5 1 1 0 0 6 2 1 1 4 0 7 4 x x x 1 NONE - ! boo 2 oo 1 CHy Ves Tt CHs 8 DGND t O CHg Cc Loo. t 4 _ocu, FIGURE 1: 8-Channel Multiplexed D/A Converter Do not apply signals to the SMP-08 with power off unless the input current is limited to less than 10mA. TYPICAL APPLICATIONS AN 8-CHANNEL MULTIPLEXED D/A CONVERTER Figure 1 illustrates a typical multiplexing function of the SMP- 08. itis used to sample-and-hold eight different output voltages 4-108 SAMPLE/TRACK-HOLD AMPLIFIERS corresponding to eight different digital codes from a D/A con- verter. The SMP-08's droop rate of 20mV/s requires a refresh once every 500ms, before the voltage drifts beyond 1/2 LSB ac- curacy (1 LSB of an 8-bit DAC is equivalent to 19.5mV, out of a full-scale voltage of 5V). For a 10-bit DAC, the refresh rate must be less than 120ms, and, for a 12-bit system, 31ms. This im- plementation is very cost-effective compared to using multiple DACs as the number of output channels increases. REV. B